CN116612795A - Resistive memory device - Google Patents

Abstract

The invention provides a resistive memory device, which comprises a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of selection circuits and a switch circuit. The plurality of word lines cross the plurality of bit lines, respectively. The memory array includes a plurality of memory components. One end of each memory element is coupled to a corresponding word line, and the other end of each memory element is coupled between a first end point and a second end point on a corresponding bit line. Each bypass path is connected in parallel with a corresponding bit line between the first and second end points. Each selection circuit is coupled to a corresponding bit line and bypass path, and is configured to select the coupled bit line or bypass path. The switch circuit is coupled to the plurality of word lines and configured to select one of the plurality of word lines.

Description

resistive memory device

technical field

The present invention relates to a memory device, in particular to a resistive memory device.

Background technique

Resistive random access memory (resistive random access memory, RRAM) is a kind of non-volatile memory actively developed in the industry. In a 1-transistor-1-resistor (1T1R) architecture, the transistor controls the current passing through the resistive memory unit. In this type of architecture, the area of the transistors used to control the current is relatively large. Attempts to shrink transistors complicate the process and reduce the available current. Therefore, a 1-selector-1-resistor (1S1R) architecture in which a transistor is replaced by a selector is gradually being used in the industry.

However, in the current 1-selector-1-resistor architecture, even the unselected memory elements will generate sneak current, which not only easily causes errors in the read operation, but also sometimes causes adjacent memory elements to Component transitions inappropriately. For example, FIG. 1A and FIG. 1B show a schematic diagram of sneak current on a conventional resistive memory device. Please refer to FIG. 1A and FIG. 1B , in FIG. 1A , since the memory element MT is selected to operate, the switch element SW is turned on to write data into or read data from the memory element MT. However, as shown in FIG. 1A , the unselected memory element MN1 may also generate a sneak current SC1 along the path P1 , thereby affecting the operation. Similarly, as shown in FIG. 1B , the unselected memory elements MN2 and MN3 may also generate a sneak current SC2 along the path P2, thereby affecting the operation.

The more cells connected in the manner shown in FIG. 1A and FIG. 1B , the greater the impact of the sneak current. Therefore, how to manage the sneak current is a major issue for designers in the field.

Contents of the invention

The invention provides a resistive memory device, which can manage the sneak current and reduce the influence caused by the sneak current.

The resistive memory device of the present invention includes a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of selection circuits and a switch circuit. The plurality of word lines respectively cross the plurality of bit lines. A storage array includes multiple storage components. One end of each storage element is coupled to a corresponding word line, and the other end of each storage element is coupled between a first terminal and a second terminal on a corresponding bit line. Each bypass path is connected in parallel with the corresponding bit line between the first terminal and the second terminal. Each selection circuit is coupled to a corresponding bit line and a bypass path, configured to select the coupled bit line or the bypass path. The switch circuit is coupled to a plurality of word lines and is configured to select one of the plurality of word lines.

In an embodiment of the present invention, when one of the above-mentioned plurality of storage elements is selected as the selected storage element, the selection circuit coupled to the selected storage element through the bit line selects the coupled bit line, and the other The selection circuit selects the coupled bypass path.

Based on the above, in the resistive memory device of the present invention, when one of the plurality of memory elements is selected, except for the bit line required to operate the selected memory element, the conduction paths of other bit lines Can be replaced by a bypass path. Therefore, the resistive memory device of the present invention can reduce the paths that generate sneak current, and even in a structure with a larger area, it can indeed reduce the influence caused by the sneak current.

Description of drawings

1A and 1B show a schematic diagram of a sneak current on a conventional resistive memory device;

2 is a schematic block diagram of a resistive memory device according to an embodiment of the present invention;

3 is a schematic circuit diagram of a resistive memory device according to an embodiment of the present invention;

4 is a schematic block diagram of a storage component according to an embodiment of the present invention;

5A and 5B are examples of the operation method of the selection circuit according to an embodiment of the present invention.

Explanation of reference signs

100: resistive memory device

110: storage array

120_0～120_3: selection circuit

130: switch circuit

200: resistive memory cell

210: selector

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts.

FIG. 2 is a schematic block diagram of a resistive memory device according to an embodiment of the invention. FIG. 3 is a schematic circuit diagram of a resistive memory device according to an embodiment of the invention. Please refer to FIG. 2 and FIG. 3 at the same time. The resistive memory device 100 includes bit lines BL0 ˜ BL3 , word lines WL0 ˜ WL3 , bypass paths BP0 ˜ BP3 , a memory array 110 , selection circuits 120_0 ˜ 120_3 and a switch circuit 130 . As shown in FIG. 3 , the word lines WL0 - WL3 are respectively arranged to intersect with the bit lines BL0 - BL3 , and the intersecting angle is, for example, about 90 degrees, but the present invention is not limited thereto. The resistive memory device 100 is, for example, a subset of a larger memory array.

The storage array 110 includes storage elements M00-M33, one end of the storage elements M00-M03 is coupled to the word line WL0, one end of the storage elements M10-M13 is coupled to the word line WL1, and one end of the storage elements M20-M23 is coupled to the word line WL2, one end of the memory elements M30-M33 are coupled to the word line WL3. The other ends of the storage elements M00 , M10 , M20 , M30 are coupled between the first terminal ND1_0 and the second terminal ND2_0 on the bit line BL0 . The other ends of the memory elements M01 , M11 , M21 , M31 are coupled between the first terminal ND1_1 and the second terminal ND2_1 on the bit line BL1 . The other ends of the memory elements M02 , M12 , M22 , M32 are coupled between the first terminal ND1_2 and the second terminal ND2_2 on the bit line BL2 . The other ends of the storage elements M03 , M13 , M23 , M33 are coupled between the first terminal ND1_3 and the second terminal ND2_3 on the bit line BL3 .

The following uses the storage module M00 as an example to describe the internal structure of the storage module in this embodiment, and the internal structures of the other storage modules M01-M33 are the same as the storage module M00. FIG. 4 is a schematic block diagram of a storage device according to an embodiment of the invention. Referring to FIG. 4 , the memory module M00 includes a resistive memory unit 200 and a selector 210 . The resistive memory cell 200 can provide a single bit of stored data. The selector 210 can be a bidirectional threshold switch (ovonic threshold switch, OTS), which is a two-terminal symmetrical voltage sensitive switching device. For example, when an applied voltage less than the threshold voltage is applied on the selector 210, the selector 210 remains in an off state (eg, a non-conductive state). On the other hand, when an applied voltage greater than the threshold voltage is applied in either direction of the selector 210 , the selector 210 becomes a conducting state (eg, a conducting state). That is to say, the selector 210 can allow bidirectional switching, and since there is no need to control whether to conduct a terminal (such as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) gate or bipolar The base of a bipolar junction transistor (BJT)) has the advantage of a small area. Also, the selector 210 may be based on field-enhanced emission or tunneling.

It should be noted that, in the present invention, there is no need to limit the arrangement order of the resistive memory unit 200 and the selector 210 in the memory module M00, as long as one memory module M00 is configured with one resistive memory unit 200 and one selector 210 The configuration method can be. In an embodiment, the selector 210 may also be integrated into the resistive memory unit 200 .

Returning to FIG. 2 and FIG. 3 , the bypass paths BP0 - BP3 are respectively connected in parallel with the bit lines BL0 - BL3 . As shown in FIG. 3 , the bypass path BP0 is connected in parallel with the bit line BL0 between the first terminal ND1_0 and the second terminal ND2_0 . The bypass path BP1 is connected in parallel with the bit line BL1 between the first terminal ND1_1 and the second terminal ND2_1 . The bypass path BP2 is connected in parallel with the bit line BL2 between the first terminal ND1_2 and the second terminal ND2_2 . The bypass path BP3 is connected in parallel with the bit line BL3 between the first terminal ND1_3 and the second terminal ND2_3 .

The selection circuits 120_0 - 120_3 are respectively coupled to the bit lines BL0 - BL3 and the bypass paths BP0 - BP3 . The selection circuit 120_0 is coupled to the bit line BL0 and the bypass path BP0, and is configured to select the coupled bit line BL0 or the bypass path BP0 to conduct voltage or current. The selection circuit 120_1 is coupled to the bit line BL1 and the bypass path BP1, and is configured to select the coupled bit line BL1 or the bypass path BP1 to conduct voltage or current. The selection circuit 120_2 is coupled to the bit line BL2 and the bypass path BP2, and is configured to select the coupled bit line BL2 or the bypass path BP2 to conduct voltage or current. The selection circuit 120_3 is coupled to the bit line BL3 and the bypass path BP3, and is configured to select the coupled bit line BL3 or the bypass path BP3 to conduct voltage or current.

The switch circuit 130 is coupled to the word lines WL0˜WL3. The switch circuit 130 is configured to select one of the word lines WL0 - WL3 to conduct voltage or current.

In this embodiment, all the selection circuits 120_0 - 120_3 and the switch circuit 130 can realize the selection operation by operating the switch components. The switching components may for example consist of transistors. As shown in FIG. 3 , the selection circuit 120_0 includes a first switch component SW1_0 and a second switch component SW2_0, the selection circuit 120_1 includes a first switch component SW1_1 and a second switch component SW2_1, and the selection circuit 120_2 includes a first switch component SW1_2 and a second switch component SW2_1. The switch component SW2_2 and the selection circuit 120_3 include a first switch component SW1_3 and a second switch component SW2_3. The switch circuit 130 includes third switch components SW3_0 - SW3_3 .

The first switch elements SW1_0 - SW1_3 are respectively controlled by the control signals SBL0 - SBL3 to be turned on or off. The second switch components SW2_0 - SW2_3 are respectively controlled by the control signals SBP0 - SBP3 to be turned on or off. The third switch elements SW3_0 - SW3_3 are respectively controlled by the control signals SWL0 - SWL3 to be turned on or off. The control signals SBL0 ˜ SBL3 , SBP0 ˜ SBP3 and SWL0 ˜ SWL3 may come from a memory controller outside the resistive memory device 100 , for example.

The internal circuits of the selection circuits 120_0-120_3 are configured in a similar manner. Taking the selection circuit 120_0 as an example, the first switch component SW1_0 is configured on the bit line BL0, the second switch component SW2_0 is configured on the bypass path BP0, and the first switch component One end of SW1_0 and one end of the second switch element SW2_0 are commonly coupled to ND2_0 on the bit line BL0. In the switch circuit 130 , one ends of the third switch components SW3_0 ˜ SW3_3 are respectively coupled to the word lines WL0 ˜ WL3 , and the other ends of the third switch components SW3_0 ˜ SW3_3 are coupled to the source line SL.

In this embodiment, when one of the memory elements M00-M33 is selected as the selected memory element MS, the selection circuit coupled to the selected memory element MS through the bit line will select the coupled bit line for voltage or For current conduction, other selection circuits will select the coupled bypass path for voltage or current conduction. The storage component MS is selected, for example, for a write operation or a read operation. The following takes when the storage component M10 is selected as an example to describe the operation mode when the storage component M10 is selected as the storage component MS.

Specifically, FIG. 5A and FIG. 5B are examples of the operation method of the selection circuit according to an embodiment of the present invention. When the selected storage element MS (storage element M10 ) is selected, the selection circuit 120_0 selects the bit line BL0 to conduct voltage or current. As shown in FIG. 5A , the first switch element SW1_0 disposed on the bit line BL0 corresponding to the selected memory element MS is turned on based on the control signal SBL0 of the turn-on level VP to generate the current I1 . The second switch element SW2_0 disposed on the bypass path BP0 parallel to the bit line BL0 is turned off based on the control signal SBP0 of the turn-off level V0.

On the other hand, when the selected memory element MS (memory element M10 ) is selected, the selection circuits 120_1 - 120_3 respectively select the bypass paths BP1 - BP3 to conduct voltage or current. The first switch components SW1_1-SW1_3 provided on the bit lines BL1-BL3 corresponding to other storage components are turned off, and are provided on bypass paths BP1-BP3 parallel to the bit lines BL1-BL3 corresponding to other storage components. The second switch components SW2_1˜SW2_3 on the top will be turned on. Taking the selection circuit 120_1 as an example, as shown in FIG. 5B, the first switch element SW1_1 disposed on the bit line BL1 will be turned off based on the control signal SBL1 of the off level V0, and is disposed in a bypass connected in parallel with the bit line BL1. The second switch element SW2_1 on the path BP1 is turned on based on the control signal SBP1 of the turn-on level VP to generate the current I2.

Moreover, when the selected memory element MS (storage element M10) is selected, the third switch element SW3_1 coupled to the word line WL1 corresponding to the selected memory element MS is also turned on based on the control signal SWL1 of the conduction level VP .

Through the above method, when the selected storage element MS is selected to perform a write operation or a read operation, only the bit line coupled to the selected storage element MS will remain conductive, and the conduction paths of other bit lines will be bypassed. path instead. In this way, by limiting to a sufficiently small subset of the memory array, the amount of possible sneak current is reduced, thereby reducing the impact of the sneak current.

It should be noted that, in the embodiment of the present invention, a 4x4 storage array 110 including 16 storage modules M00-M33 is used for illustration, but the present invention is not limited thereto, as long as the bypass path taught by the present invention is consistent with For the circuit structure, those skilled in the art can analogize the number of storage components used to more according to the actual needs according to the teaching of the present invention. In addition, those skilled in the art can properly arrange a plurality of resistive memory devices taught by the present invention, for example, in the extending direction of the bit lines, to expand into a larger memory array.

To sum up, in the resistive memory device of the present invention, multiple bypass paths are configured. When one of the plurality of storage elements is selected, except for the bit line required to operate the selected memory element, the conduction paths of other bit lines can be replaced by bypass paths. Therefore, the resistive memory device of the present invention can reduce the paths that generate sneak current, and even in a structure with a larger area, it can indeed reduce the influence caused by the sneak current.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (12)

1. A resistive memory device, comprising:

a plurality of bit lines;

a plurality of word lines intersecting the plurality of bit lines, respectively;

a memory array including a plurality of memory elements, one end of each of the plurality of memory elements being coupled to a corresponding one of the word lines, and the other end of each of the plurality of memory elements being coupled between a first end and a second end on a corresponding one of the bit lines;

a plurality of bypass paths, each of the plurality of bypass paths being connected in parallel with a corresponding bit line between the first and second endpoints;

a plurality of selection circuits, each of the plurality of selection circuits coupled to a corresponding one of the bit line and the bypass path, configured to select the bit line or the bypass path to which it is coupled; and

a switching circuit is coupled to the plurality of word lines and configured to select one of the plurality of word lines.

2. The resistive memory device of claim 1, wherein when one of the plurality of memory components is selected as a select memory component, the bit line coupled is selected by the select circuit of the bit line coupled to the select memory component, and the other select circuits select the bypass path coupled.

3. The resistive memory device of claim 2, wherein each of the plurality of selection circuits comprises a first switch element disposed on the corresponding bit line and a second switch element disposed on the corresponding bypass path, one end of the first switch element and one end of the second switch element being commonly coupled to the second end point on the corresponding bit line.

4. The resistive memory device according to claim 3, wherein when the selection memory element is selected, the first switching element provided on the bit line corresponding to the selection memory element is turned on, and the second switching element provided on the bypass path parallel to the bit line corresponding to the selection memory element is turned off.

5. The resistive memory device according to claim 3, wherein when the selected memory element is selected, the first switching element provided on the bit line corresponding to the other memory element is turned off, and the second switching element provided on the bypass path parallel to the bit line corresponding to the other memory element is turned on.

6. The resistive memory device of claim 2, wherein the switching circuit comprises a plurality of third switching elements, one ends of the third switching elements are respectively coupled to the plurality of word lines, the other ends of the third switching elements are coupled to source lines,

when the selection memory component is selected, the third switch component coupled to the word line corresponding to the selection memory component is conducted.

7. The resistive memory device of claim 1, wherein each of the plurality of memory components comprises a resistive memory cell and a selector.

8. The resistive memory device of claim 7 wherein the selector is an ovonic threshold switch that is a two-terminal symmetric voltage-sensitive switching component.

9. The resistive memory device of claim 7, wherein the selector is based on field enhanced emission or tunneling.

10. The resistive memory device of claim 7, wherein the selector is integrated into the resistive memory cell.

11. The resistive memory device according to claim 7, wherein the selector is maintained in an off state when an applied voltage smaller than a threshold voltage is applied to the selector, and the selector becomes an on state when an applied voltage larger than the threshold voltage is applied in either direction of the selector.

12. The resistive memory device of claim 7 wherein the selector allows for bi-directional switching.