CN116612795A

CN116612795A - Resistive memory device

Info

Publication number: CN116612795A
Application number: CN202210122907.XA
Authority: CN
Inventors: 陈达; 廖修汉; 许博砚; 林纪舜
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2022-02-09
Filing date: 2022-02-09
Publication date: 2023-08-18

Abstract

The invention provides a resistive memory device, which comprises a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of selection circuits and a switch circuit. The plurality of word lines cross the plurality of bit lines, respectively. The memory array includes a plurality of memory components. One end of each memory element is coupled to a corresponding word line, and the other end of each memory element is coupled between a first end point and a second end point on a corresponding bit line. Each bypass path is connected in parallel with a corresponding bit line between the first and second end points. Each selection circuit is coupled to a corresponding bit line and bypass path, and is configured to select the coupled bit line or bypass path. The switch circuit is coupled to the plurality of word lines and configured to select one of the plurality of word lines.

Description

Resistive memory device

Technical Field

The present invention relates to a memory device, and more particularly, to a resistive memory device.

Background

Resistive random access memory (resistive random access memory, RRAM) is a non-volatile memory that is actively developed in the industry. In a 1-transistor 1 resistor (1-transistor-1-resistor, 1T 1R) architecture, the current through the resistive memory cell is controlled by a transistor. In this type of architecture, the area of the transistor for controlling the current is large. Attempts to shrink the transistor may result in complex processes and reduced current supplied. Therefore, the architecture of 1-selector-1-resistor (1S 1R) in which transistors are replaced with selectors is increasingly used in the industry.

However, in the current 1-selector 1 resistor architecture, even the unselected memory devices generate sneak current (sneak current), which is not only prone to error in the read operation, but also sometimes causes the neighboring memory devices to transition improperly. For example, fig. 1A and 1B show schematic diagrams of sneak currents on a conventional resistive memory device. Referring to fig. 1A and 1B, in fig. 1A, since the memory element MT is selected to operate, the switch element SW is turned on to write data into the memory element MT or read data from the memory element MT. However, as shown in fig. 1A, the unselected memory element MN1 may generate sneak current SC1 along the path P1, thereby affecting the operation. Similarly, as shown in fig. 1B, the unselected memory elements MN2 and MN3 may generate sneak current SC2 along the path P2, which may affect the operation.

The more cells (cells) connected in the manner of fig. 1A and 1B, the greater the impact of sneak currents, and therefore how to manage the sneak currents is a great issue for the designers in the art.

Disclosure of Invention

The invention provides a resistive memory device capable of managing sneak current and reducing influence caused by the sneak current.

The resistive memory device of the present invention includes a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of selection circuits, and a switching circuit. The plurality of word lines cross the plurality of bit lines, respectively. The memory array includes a plurality of memory components. One end of each memory element is coupled to a corresponding word line, and the other end of each memory element is coupled between a first end point and a second end point on a corresponding bit line. Each bypass path is connected in parallel with a corresponding bit line between the first and second end points. Each selection circuit is coupled to a corresponding bit line and bypass path, and is configured to select the coupled bit line or bypass path. The switch circuit is coupled to the plurality of word lines and configured to select one of the plurality of word lines.

In an embodiment of the present invention, when one of the plurality of memory devices is selected as a selected memory device, the bit line is selected by a selection circuit coupled to the selected memory device, and the other selection circuit selects the bypass path coupled thereto.

Based on the above, in the resistive memory device of the present invention, when one of the plurality of memory elements is selected, the conductive path of the bit line other than the bit line required for operating the selected memory element can be replaced by the bypass path. Thus, the resistive memory device of the present invention can reduce the path of the sneak current, and can reliably reduce the influence caused by the sneak current even in a large-area architecture.

Drawings

FIGS. 1A and 1B are schematic diagrams illustrating sneak currents in a conventional resistive memory device;

FIG. 2 is a block diagram of a resistive memory device according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a resistive memory device according to an embodiment of the present invention;

FIG. 4 is a block diagram of a memory component according to one embodiment of the invention;

fig. 5A and 5B are examples of an operation method of the selection circuit according to an embodiment of the invention.

Description of the reference numerals

100 resistance memory device

110 memory array

120_0 to 120_3 selection circuit

130 switch circuit

200 resistive memory cell

210 selector

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 2 is a block diagram of a resistive memory device according to an embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a resistive memory device according to an embodiment of the present invention. Referring to fig. 2 and 3, the resistive memory device 100 includes bit lines BL0 to BL3, word lines WL0 to WL3, bypass paths BP0 to BP3, a memory array 110, selection circuits 120_0 to 120_3, and a switch circuit 130. As shown in fig. 3, the word lines WL0 to WL3 are arranged to intersect the bit lines BL0 to BL3, respectively, and the intersecting angle is, for example, about 90 degrees, but the invention is not limited thereto. The resistive memory device 100 is, for example, a subset (subset) of a large memory array (larger memory array).

The memory array 110 includes memory elements M00-M33, one ends of the memory elements M00-M03 are coupled to the word line WL0, one ends of the memory elements M10-M13 are coupled to the word line WL1, one ends of the memory elements M20-M23 are coupled to the word line WL2, and one ends of the memory elements M30-M33 are coupled to the word line WL3. The other ends of the memory elements M00, M10, M20, M30 are coupled between the first node ND1_0 and the second node ND2_0 on the bit line BL 0. The other ends of the memory elements M01, M11, M21, M31 are coupled between the first node ND1_1 and the second node ND2_1 on the bit line BL 1. The other ends of the memory elements M02, M12, M22, M32 are coupled between the first node ND1_2 and the second node ND2_2 on the bit line BL 2. The other ends of the memory elements M03, M13, M23, M33 are coupled between the first node ND1_3 and the second node ND2_3 on the bit line BL 3.

The internal structure of the memory module of the present embodiment will be described below using the memory module M00 as an example, and the internal structures of the other memory modules M01 to M33 are the same as the memory module M00. FIG. 4 is a block diagram of a memory device according to an embodiment of the invention. Referring to fig. 4, the memory module M00 includes a resistive memory cell 200 and a selector 210. Resistive memory cell 200 may provide a single bit of stored data. The selector 210 may be a bidirectional threshold switch (ovonic threshold switch, OTS), which is a two-terminal symmetric voltage-sensitive switching component. For example, when an applied voltage less than a threshold voltage is applied across the selector 210, the selector 210 remains in an off state (e.g., a non-conductive state). On the other hand, when an applied voltage greater than the threshold voltage is applied in either direction of the selector 210, the selector 210 may become an on state (e.g., conductive state). That is, the selector 210 may allow bi-directional switching, and has an advantage of small area because it is not required to control whether to turn on or not the terminal (e.g., gate of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or base of bipolar junction transistor (bipolar junction transistor, BJT)). Also, the selector 210 may be based on field-enhanced emission (field-enhanced emission) or tunneling (tunneling).

In the present invention, the arrangement order of the resistive memory cells 200 and the selectors 210 in the memory module M00 is not limited, and the arrangement manner of one resistive memory cell 200 and one selector 210 in one memory module M00 may be adopted. In one embodiment, the selector 210 may also be integrated into the resistive memory cell 200.

Returning to fig. 2 and 3, bypass paths BP 0-BP 3 are respectively connected in parallel with bit lines BL 0-BL 3. As shown in fig. 3, the bypass path BP0 is connected in parallel with the bit line BL0 between the first end point nd1_0 and the second end point nd2_0. The bypass path BP1 is connected in parallel with the bit line BL1 between the first end point nd1_1 and the second end point nd2_1. The bypass path BP2 is connected in parallel with the bit line BL2 between the first end point nd1_2 and the second end point nd2_2. The bypass path BP3 is connected in parallel with the bit line BL3 between the first end point nd1_3 and the second end point nd2_3.

The selection circuits 120_0 to 120_3 are coupled to the bit lines BL0 to BL3 and the bypass paths BP0 to BP3, respectively. The selection circuit 120_0 is coupled to the bit line BL0 and the bypass path BP0, and is configured to select the coupled bit line BL0 or bypass path BP0 for conducting voltage or current. The selection circuit 120_1 is coupled to the bit line BL1 and the bypass path BP1, and is configured to select the coupled bit line BL1 or bypass path BP1 for conducting voltage or current. The selection circuit 120_2 is coupled to the bit line BL2 and the bypass path BP2, and is configured to select the coupled bit line BL2 or bypass path BP2 for conducting voltage or current. The selection circuit 120_3 is coupled to the bit line BL3 and the bypass path BP3, and is configured to select the coupled bit line BL3 or bypass path BP3 for conducting voltage or current.

The switch circuit 130 is coupled to the word lines WL 0-WL 3. The switching circuit 130 is configured to select one of the word lines WL0 to WL3 for conducting a voltage or current.

In the present embodiment, the selection circuits 120_0 to 120_3 and the switch circuit 130 can realize the selection operation by the operation of the switch components. The switching assembly may be constituted, for example, by a transistor. As shown in fig. 3, the selection circuit 120_0 includes a first switch component sw1_0 and a second switch component sw2_0, the selection circuit 120_1 includes a first switch component sw1_1 and a second switch component sw2_1, the selection circuit 120_2 includes a first switch component sw1_2 and a second switch component sw2_2, and the selection circuit 120_3 includes a first switch component sw1_3 and a second switch component sw2_3. The switch circuit 130 includes third switch components Sw3_0 to Sw3_3.

The first switch components Sk1_0 to Sk1_3 can be respectively controlled by the control signals SBL0 to SBL3 to be turned on or turned off. The second switch elements Sw2_0 to Sw2_3 can be turned on or off by the control signals SBP0 to SBP3, respectively. The third switch components Sw3_0 to Sw3_3 can be respectively controlled by the control signals SWL0 to SWL3 to be turned on or turned off. The control signals SBL 0-SBL 3, SBP 0-SBP 3, and SWL 0-SWL 3 may be, for example, from memory controllers external to the resistive memory device 100.

The internal circuits of the selection circuits 120_0 to 120_3 are configured in a similar manner, taking the selection circuit 120_0 as an example, the first switch element sw1_0 is configured on the bit line BL0, the second switch element sw2_0 is configured on the bypass path BP0, and one end of the first switch element sw1_0 and one end of the second switch element sw2_0 are coupled together to the nd2_0 on the bit line BL 0. In the switch circuit 130, one ends of the third switch elements Sw3_0 to Sw3_3 are coupled to the word lines WL0 to WL3, respectively, and the other ends of the third switch elements Sw3_0 to Sw3_3 are coupled to the source line SL.

In this embodiment, when one of the memory elements M00-M33 is selected as the selected memory element MS, the bit line is selected by the selection circuit coupled to the selected memory element MS to conduct voltage or current, and the other selection circuit is selected by the bypass path coupled to conduct voltage or current. The selection memory component MS is selected, for example, for a write operation or a read operation. The following describes an operation mode when the storage component M10 is selected as the storage component MS, taking the storage component M10 as an example.

Specifically, fig. 5A and 5B are examples of an operation method of the selection circuit according to an embodiment of the invention. When the selected memory cell MS (memory cell M10) is selected, the selection circuit 120_0 selects the bit line BL0 for conducting voltage or current. As shown in fig. 5A, the first switch device sw1_0 disposed on the bit line BL0 corresponding to the selected memory device MS is turned on based on the control signal SBL0 of the on level VP to generate the current I1. The second switching element sw2_0 disposed on the bypass path BP0 in parallel with the bit line BL0 is turned off based on the control signal SBP0 of the turn-off level V0.

On the other hand, when the memory cell MS (memory cell M10) is selected, the selection circuits 120_1 to 120_3 select the bypass paths BP1 to BP3, respectively, to conduct the voltage or the current. The first switching elements sw1_1 to sw1_3 provided on the bit lines BL1 to BL3 corresponding to the other memory elements are turned off, and the second switching elements sw2_1 to sw2_3 provided on the bypass paths BP1 to BP3 connected in parallel to the bit lines BL1 to BL3 corresponding to the other memory elements are turned on. Taking the selection circuit 120_1 as an example, as shown in fig. 5B, the first switch device sw1_1 on the bit line BL1 is turned off based on the control signal SBL1 at the turn-off level V0, and the second switch device sw2_1 on the bypass path BP1 parallel to the bit line BL1 is turned on based on the control signal SBP1 at the turn-on level VP to generate the current I2.

When the selected memory cell MS (memory cell M10) is selected, the third switch device sw3_1 coupled to the word line WL1 corresponding to the selected memory cell MS is turned on based on the control signal SWL1 of the turn-on level VP.

In this way, when the selected memory device MS is selected for writing or reading, only the bit line coupled to the selected memory device MS remains conductive, and the conductive paths of the other bit lines are replaced by the bypass paths. In this way, by limiting to a sufficiently small subset of the memory array, the amount of sneak current that may occur is reduced, thereby reducing the impact of sneak current.

It should be noted that, in the embodiment of the present invention, the 4×4 memory array 110 including 16 memory elements M00-M33 is used for illustration, but the present invention is not limited thereto, and those skilled in the art can analogize the number of memory elements used to more according to the actual requirements according to the teachings of the present invention, so long as the circuit structure of the bypass path taught by the present invention is satisfied. In addition, a person skilled in the art can also extend a plurality of resistive memory devices taught by the present invention, for example, to a larger memory array by arranging them appropriately in the extending direction of the bit lines.

In summary, in the resistive memory device of the present invention, a plurality of bypass paths are arranged. When one of the plurality of memory components is selected, the conductive path of the other bit lines may be replaced with the bypass path in addition to the bit lines required for operating the selected memory component. Thus, the resistive memory device of the present invention can reduce the path of the sneak current, and can reliably reduce the influence caused by the sneak current even in a large-area architecture.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A resistive memory device, comprising:

a plurality of bit lines;

a plurality of word lines intersecting the plurality of bit lines, respectively;

a memory array including a plurality of memory elements, one end of each of the plurality of memory elements being coupled to a corresponding one of the word lines, and the other end of each of the plurality of memory elements being coupled between a first end and a second end on a corresponding one of the bit lines;

a plurality of bypass paths, each of the plurality of bypass paths being connected in parallel with a corresponding bit line between the first and second endpoints;

a plurality of selection circuits, each of the plurality of selection circuits coupled to a corresponding one of the bit line and the bypass path, configured to select the bit line or the bypass path to which it is coupled; and

a switching circuit is coupled to the plurality of word lines and configured to select one of the plurality of word lines.

2. The resistive memory device of claim 1, wherein when one of the plurality of memory components is selected as a select memory component, the bit line coupled is selected by the select circuit of the bit line coupled to the select memory component, and the other select circuits select the bypass path coupled.

3. The resistive memory device of claim 2, wherein each of the plurality of selection circuits comprises a first switch element disposed on the corresponding bit line and a second switch element disposed on the corresponding bypass path, one end of the first switch element and one end of the second switch element being commonly coupled to the second end point on the corresponding bit line.

4. The resistive memory device according to claim 3, wherein when the selection memory element is selected, the first switching element provided on the bit line corresponding to the selection memory element is turned on, and the second switching element provided on the bypass path parallel to the bit line corresponding to the selection memory element is turned off.

5. The resistive memory device according to claim 3, wherein when the selected memory element is selected, the first switching element provided on the bit line corresponding to the other memory element is turned off, and the second switching element provided on the bypass path parallel to the bit line corresponding to the other memory element is turned on.

6. The resistive memory device of claim 2, wherein the switching circuit comprises a plurality of third switching elements, one ends of the third switching elements are respectively coupled to the plurality of word lines, the other ends of the third switching elements are coupled to source lines,

when the selection memory component is selected, the third switch component coupled to the word line corresponding to the selection memory component is conducted.

7. The resistive memory device of claim 1, wherein each of the plurality of memory components comprises a resistive memory cell and a selector.

8. The resistive memory device of claim 7 wherein the selector is an ovonic threshold switch that is a two-terminal symmetric voltage-sensitive switching component.

9. The resistive memory device of claim 7, wherein the selector is based on field enhanced emission or tunneling.

10. The resistive memory device of claim 7, wherein the selector is integrated into the resistive memory cell.

11. The resistive memory device according to claim 7, wherein the selector is maintained in an off state when an applied voltage smaller than a threshold voltage is applied to the selector, and the selector becomes an on state when an applied voltage larger than the threshold voltage is applied in either direction of the selector.

12. The resistive memory device of claim 7 wherein the selector allows for bi-directional switching.