JP6721205B1 - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an anti-fuse memory and a semiconductor memory device capable of suppressing a leak current at the time of writing data. A plurality of anti-fuse memories M are arranged in a matrix in a semiconductor memory device 1. The anti-fuse memory M has a memory capacitor 10 and a MOS transistor 20. In the memory capacitor 10, the memory gate electrode 10a is connected to the source region 20b of the MOS transistor 20, and the diffusion region 10b is connected to the source line SL for each column. The gate electrode 20a of the MOS transistor 20 is connected to the word line WL for each column, and the drain region 20c is connected to the bit line BL for each row, and the voltage applied independently is controlled. [Selection diagram] Figure 1

Description

The present invention relates to an antifuse memory and a semiconductor memory device.

There is known an anti-fuse memory in which data can be written only once (for example, see Patent Document 1). In the anti-fuse memory, data is written by electrically breaking down the memory gate insulating film that is the insulating film of the memory capacitor.

Patent Document 1 describes a semiconductor memory device in which a plurality of anti-fuse memories each composed of a diode-connected N-type MOS transistor (rectifying element) and a memory capacitor are arranged in a matrix. The memory capacitor has a structure in which a memory gate insulating film, which is dielectrically broken down by a voltage difference between a word line and a bit line, and a memory gate electrode are stacked on an active region. A word line is provided corresponding to each row of the anti-fuse memory, and a bit line is provided corresponding to each column. In the memory capacitor of each anti-fuse memory, the bit line is connected to the diffusion region provided at one end of the active region, and the source region of the MOS transistor is connected to the memory gate electrode. In the MOS transistor, the gate electrode and the drain region are connected to each other to form a diode connection, and the gate electrode and the drain region are connected to the word line.

In the above semiconductor memory device, when writing data to a specific antifuse memory among the antifuse memories arranged in a matrix, a voltage of 0 V is applied to the bit line connected to the antifuse memory for writing the data. A voltage of 5V is applied to the word line. Voltages of 3V and 0V are applied to the other bit lines and word lines, respectively. As a result, in an anti-fuse memory that writes data, a voltage difference that causes dielectric breakdown of the memory gate insulating film is generated between the memory gate electrode and the diffusion region, and in other anti-fuse memories, a voltage that does not cause dielectric breakdown of the memory gate insulating film. The difference is.

International Publication No. 2016/136604

In the antifuse memory configured as described above, an antifuse memory (hereinafter, referred to as a selected antifuse memory) that is connected to the same word line as an antifuse memory to which data is written (hereinafter, referred to as a selected antifuse memory) In the memory), similar to the selective anti-fuse memory, a voltage of 5 V for writing is applied from the word line to the gate electrode and the drain region of the MOS transistor. As a result, even in the non-selected anti-fuse memory, the MOS transistor is turned on and a voltage of 5V is applied to the memory gate electrode of the memory capacitor. A voltage of 3V is applied to the bit line connected to the non-selected anti-fuse memory so that the memory gate insulating film is not broken down, but a voltage difference of about 2V is applied between the memory gate electrode and the diffusion region. Occurs. As a result, when the memory gate insulating film of the non-selected anti-fuse memory is already broken down, there is a problem that a leak current flows from the word line to the bit line through the non-selected anti-fuse memory.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an anti-fuse memory and a semiconductor memory device capable of suppressing a leak current at the time of writing data.

An anti-fuse memory according to the present invention includes a memory capacitor having an active region, a memory gate insulating film formed on the active region, and a memory gate electrode formed on the memory gate insulating film, and a gate electrode, A memory transistor having a source region and a drain region, wherein the gate electrode is connected to a word line, and the drain region is connected to a bit line provided separately from the word line; And the source region are connected to each other.

According to another aspect of the present invention, there is provided a semiconductor memory device including a memory array in which the antifuse memories are arranged in a matrix, and the bit lines provided for each row of the antifuse memories and connected to the antifuse memories in a corresponding row. And the word line provided for each column of the anti-fuse memory and connected to the anti-fuse memory in the corresponding column, respectively.

According to the present invention, the word line is connected to the gate electrode of the MOS transistor, the drain region is connected to the bit line provided separately from the word line, and the voltages applied to the gate electrode and the drain region are independently controlled. Therefore, when writing data, it is possible to turn off the MOS transistor of the anti-fuse memory that is not the target of writing, and suppress the leak current of the anti-fuse memory in which the memory gate insulating film has already been dielectrically broken down. be able to.

1 is a schematic diagram showing a circuit configuration of a semiconductor memory device according to an embodiment. It is sectional drawing which shows the structure of an anti-fuse memory. FIG. 9 is an explanatory diagram showing a planar layout of each active region, source line, word line, and bit line in the memory array. FIG. 9 is an explanatory diagram showing an example of a voltage application state to each source line, each word line, and each bit line during a write operation. FIG. 6 is an explanatory diagram showing an example of a voltage application state to each source line, each word line, and each bit line during a read operation. FIG. 6 is a schematic diagram showing a circuit configuration of a semiconductor memory device of an example in which diffusion regions of each memory capacitor are electrically connected to each other so as to be equipotential.

In FIG. 1, the semiconductor memory device 1 includes a memory array CA, a bit line BL, a word line WL, and a source line SL. In the memory array CA, a plurality of anti-fuse memories (memory cells) M are arranged in a matrix. The bit line BL is provided corresponding to each row of the anti-fuse memory M, and the word line WL and the source line SL are provided corresponding to each column of the anti-fuse memory M. That is, the anti-fuse memories M arranged in the row direction share one bit line BL, and the anti-fuse memories M arranged in the column direction share one word line WL and one source line SL. ..

In the following, when distinguishing the individual anti-fuse memories M, i and j will be described as 1, 2, 3,... And the one in the i-th column and the j-th row will be described as the anti-fuse memory Mij. Further, when distinguishing the word line WL and the source line SL into a specific column, the i-th column will be described as a word line WLi and a source line SLi. Similarly, for the bit line BL, when the bit line BL is classified into a particular row, the j-th row is described as the bit line BLj.

Furthermore, when distinguishing the anti-fuse memory M that is the target of data writing and reading from the anti-fuse memory M that is not the target, the former is called the selected anti-fuse memory M and the latter is called the non-selected anti-fuse memory M. Explain.

The anti-fuse memories M have the same structure and each have a memory capacitor 10 and a MOS transistor 20. Each word line WL and each source line SL are connected to each antifuse memory M in the corresponding column. Each bit line BL is connected to each antifuse memory M in the corresponding row. Therefore, the anti-fuse memory Mij in the i-th column and the j-th row is connected to the word line WLi, the source line SLi, and the bit line BLj, respectively. As will be described later, the bit lines BL extend in the row direction, and the word lines WL and the source lines SL extend in the column direction and are orthogonal to each other.

The semiconductor memory device 1 also includes a column selection circuit 25, a row selection circuit 26, and a sense amplifier 27. The bit line BL is connected to the row selection circuit 26 and the sense amplifier 27, respectively, and the word line WL and the source line SL are connected to the column selection circuit 25, respectively.

In the anti-fuse memory M, the gate electrode 20a of the MOS transistor 20 is connected to the word line WL, the source region 20b is connected to the memory gate electrode 10a of the memory capacitor 10, and the drain region 20c is connected to the bit line BL. Further, the diffusion region 10b of the memory capacitor 10 is connected to the source line SL. In the anti-fuse memory M, the column selection circuit 25 and the row selection circuit 26 control the voltages of the connected bit line BL, source line SL, and word line WL, thereby writing and reading data.

The memory capacitor 10 has a memory gate electrode 10a, a diffusion region 10b, and a memory gate insulating film 10c (see FIG. 2), and 1-bit data is non-volatile depending on the presence or absence of dielectric breakdown of the memory gate insulating film 10c. Hold. That is, in the memory capacitor 10, the memory gate insulating film 10c is not dielectrically broken and the memory gate electrode 10a and the diffusion region 10b are electrically insulated, and the memory gate insulating film 10c is dielectrically broken. The short-circuited state in which the memory gate electrode 10a and the diffusion region 10b are electrically short-circuited corresponds to "0" or "1" of 1-bit data. Note that, in this example, dielectric breakdown of the memory gate insulating film 10c to bring it into a short-circuit state is referred to as writing of data in the anti-fuse memory M. Further, the data reading means to detect whether the memory capacitor 10 is in the insulated state or the short-circuited state.

At the time of writing and reading data, the column selection circuit 25 applies a voltage to the word line WL and the source line SL, and the row selection circuit 26 applies a voltage to the bit line BL. The voltage applied to the word line WL includes a first selected column voltage and a first unselected column voltage at the time of writing, and a second selected column voltage and a second unselected column voltage at the time of reading. The voltage applied to the source line SL includes a first source line voltage at the time of writing and a second source line voltage at the time of reading. The voltage applied to the bit line BL includes a first selected row voltage and a first unselected row voltage at the time of writing, and a second selected row voltage and a second unselected row voltage at the time of reading. Details of these voltages will be described later.

A precharge method is used for reading data. The sense amplifier 27 acquires the 1-bit data written in the anti-fuse memory M based on the change in the potential of the bit line BL precharged to the second selected row voltage. For example, the sense amplifier 27 detects whether the potential of the bit line BL falls below a predetermined threshold potential within a fixed time. In this example, the precharge method is used for reading data, but the method for reading data is not particularly limited.

FIG. 2 shows an example of a sectional structure of the anti-fuse memory M. The antifuse memories M adjacent in the row direction are arranged line-symmetrically with respect to the column direction. Therefore, the anti-fuse memory M has an arrangement shown in FIG. 2 and an arrangement symmetrical with respect to this. The anti-fuse memory M is formed in the P-type well S2 on the semiconductor substrate S1. The P-type well S2 is provided with a first active region 31 and a second active region 32, which are separated in the row direction by an element isolation film IL formed of an insulating material.

The memory capacitor 10 is formed in the first active region 31. In the first active region 31, a diffusion region 10b that is heavily doped with an N-type dopant is formed at a predetermined distance from the element isolation film IL. As will be described later, the diffusion region 10b functions as the source line SL. A memory gate insulating film 10c is formed on the first active region 31 between the element isolation film IL and the diffusion region 10b. The memory gate electrode 10a is provided over the respective upper surfaces of the memory gate insulating film 10c and the element isolation film IL. Sidewalls SW1 made of an insulating material are provided on both side walls of the memory gate electrode 10a.

The MOS transistor 20 is formed in the second active region 32. In the second active region 32, a source region 20b heavily doped with an N-type dopant is formed so as to be adjacent to the element isolation film IL. Further, in the second active region 32, a drain region 20c which is heavily doped with an N-type dopant is formed at a predetermined distance from the source region 20b. A gate insulating film 20d is formed on the second active region 32 between the source region 20b and the drain region 20c, and a gate electrode 20a is formed on the gate insulating film 20d. As will be described later, the gate electrode 20a functions as the word line WL. Sidewalls SW2 made of an insulating material are provided on both side walls of the gate electrode 20a. The thickness of the gate insulating film 20d is determined according to the first selected column voltage and is made larger than that of the memory gate insulating film 10c so as not to cause dielectric breakdown when writing data.

A contact C1 is provided across the source region 20b of the MOS transistor 20 and the memory gate electrode 10a of the memory capacitor 10. The contact C1 connects the memory gate electrode 10a of the memory capacitor 10 and the source region 20b of the MOS transistor 20. Instead of connecting the memory gate electrode 10a and the source region 20b by the contact C1, contacts may be provided on the memory gate electrode 10a and the source region 20b, and the contacts may be connected by wiring.

A contact C2 is provided in the drain region 20c, and the contact C2 is connected to the bit line BL formed of a metal wiring provided in a metal wiring layer above the gate electrode 20a. In this example, the contact C2 includes a contact C2a formed in the same layer as the contact C1 and a contact C2b formed on the contact C2a. The contact C2 may be formed as one contact. The bit line BL extends in the row direction. The memory gate electrode 10a, the gate electrode 20a, the contact C1, the contact C2, and the bit line BL are covered with an interlayer insulating film. The memory gate electrode 10a of the memory capacitor 10 and the gate electrode 20a of the MOS transistor 20 are wirings in the same wiring layer (same layer) formed in the same process.

FIG. 3 shows an example of a plane layout of the anti-fuse memory M. A plurality of anti-fuse memories M are arranged in a matrix to form a memory array CA. The arrangement of each element of the anti-fuse memory M adjacent in the row direction is line-symmetric with respect to the column direction as described above. The arrangement of each element of the anti-fuse memory M in each row is the same.

A plurality of first active regions 31 extending in the column direction are formed in the well S2. The first active region 31 is heavily doped with an N-type dopant to form the source line SL. A contact C3 is formed on the first active region 31 at the end of the memory array, the source line SL is connected to the column selection circuit 25 via the contact C3, a metal wiring (not shown), and the like. Two source line voltages are provided. The source line SL extends in the column direction and is shared by the anti-fuse memories M adjacent in the row direction.

In the well S2 between the first active regions 31 adjacent to each other, a plurality of rectangular second active regions 32 elongated in the row direction are arranged in the column direction at predetermined intervals. The second active region 32 is integrated with that of the anti-fuse memory M adjacent in the row direction.

The memory gate electrode 10a of the memory capacitor 10 is formed in a rectangular shape elongated in the row direction, and one end of the memory gate electrode 10a extends into the first active region 31. The other end is between the first active region 31 and the second active region 32, but may extend into the second active region 32. The contact C1 is formed across the memory gate electrode 10a and the second active region 32, and the memory gate electrode 10a and the source region 20b of the MOS transistor 20 provided in the second active region 32 are electrically connected. ..

A word line WL extending in the column direction is provided for each column as a wiring shared by the anti-fuse memories M arranged in the column direction. Each word line WL is arranged so as to cross the second active region 32 in the column direction. The portion of the word line WL on the second active region 32 becomes the gate electrode 20a of the MOS transistor 20. A contact C4 is formed on the word line WL at the end of the memory array, and the word line WL is connected to the column selection circuit 25 via the contact C4, a metal wiring (not shown), etc., and the first selected column voltage and the first non-selected voltage are applied. The selected column voltage, the second selected column voltage, and the second unselected column voltage are applied.

A contact C2 is formed in the center of the second active region 32 in the row direction. The contact C2 is shared by the anti-fuse memories M adjacent in the row direction. Bit lines BL are provided for each row as wirings shared by the anti-fuse memories M arranged in the row direction. Each bit line BL extends in the row direction and is orthogonal to the word line WL and the source line SL. The bit line BL is connected to the drain region 20c of the MOS transistor 20 provided in the second active region 32 by the contact C2. The bit line BL is connected to the row selection circuit 26, and is supplied with a first selected row voltage, a first unselected row voltage, a second selected row voltage, and a second unselected row voltage.

The writing and reading of the data having the above configuration will be described below. When one antifuse memory M is selected and data is written to the antifuse memory M, the first selected column voltage is applied to the word line WL which is the selected word line connected to the selected antifuse memory M. Then, the first non-selected column voltage is applied to the word line WL which becomes the other non-selected word line. Further, the first selected row voltage is applied to the bit line BL which is the selected bit line connected to the selected anti-fuse memory M, and the first unselected row voltage is applied to the bit lines BL which are the other unselected bits. .. Further, the first source line voltage is applied to both the source line SL that is the selected source line and the other source line SL that is the non-selected source line connected to the selected anti-fuse memory M.

The first selected column voltage is a gate voltage that can turn on the MOS transistor 20 to which the first selected row voltage is applied as the drain voltage, and is set to be equal to or higher than the threshold voltage of the MOS transistor 20. The first non-selected column voltage is a gate voltage that turns off the MOS transistor 20.

The first selected row voltage and the first non-selected row voltage are applied as the drain voltage of the MOS transistor 20. The first selected row voltage causes dielectric breakdown of the memory gate insulating film 10c between the memory gate electrode 10a to which this voltage is applied via the MOS transistor 20 and the diffusion region 10b to which the first source line voltage is applied. It is set as a voltage that causes a voltage difference. The first selected row voltage is set higher than the first source line voltage.

The first non-selected row voltage is the first to prevent the dielectric breakdown of the memory gate insulating film 10c and to prevent the leak current from flowing from the bit line BL to the source line SL via the non-selected anti-fuse memory M. It is set to the same as the source line voltage.

In this example, the first selected row voltage is 5V and the first selected column voltage is 6V. The first non-selected column voltage, the first non-selected row voltage, and the first source line voltage are 0V, which is the same as the well voltage (potential).

In the selected anti-fuse memory M, the first selected column voltage from the word line WL is applied to the gate electrode 20a, and the first selected row voltage from the bit line BL is applied to the drain region 20c. As a result, the MOS transistor 20 is turned on, and the first selected row voltage of the bit line BL is applied to the memory gate electrode 10a via the MOS transistor 20. Further, the first source line voltage is applied from the source line SL to the diffusion region 10b of the memory capacitor 10.

As described above, in the selected anti-fuse memory M, the first selected row voltage (=5V) is applied to the memory gate electrode 10a of the memory capacitor 10, and the first source line voltage (=0V) is applied to the diffusion region 10b. Therefore, a channel (not shown) is formed on the surface of the first active region 31 just below the memory gate electrode 10a, and the channel is turned on, and the channel potential becomes the same potential as the potential of the source line SL. As a result, in the selected anti-fuse memory M, the potential difference between the channel and the memory gate electrode 10a becomes 5 V, so that the memory gate insulating film 10c below the memory gate electrode 10a is dielectrically broken down. In this way, the memory gate electrode 10a and the diffusion region 10b are brought into a low resistance conductive state through the channel, and a state in which data is written is obtained.

For example, when writing data to the anti-fuse memory M11, as shown in FIG. 4, the word line WL1 is set to the first selected column voltage (=6V), and the word lines WL2, WL3... Are set to the first unselected column. The voltage (=0 V) is set, the bit line BL1 is set to the first selected row voltage (=5 V), and the bit lines BL2, BL3... Are set to the first non-selected row voltage (=0 V).

The word lines WL1 to 6V are applied to the gate electrode 20a of the MOS transistor 20 of the anti-fuse memory M11, and the bit lines BL1 to 5V are applied to the drain region 20c. As a result, the MOS transistor 20 is turned on, and 5V applied to the drain region 20c is applied to the memory gate electrode 10a via the source region 20b of the MOS transistor 20.

In the anti-fuse memory M11, the diffusion region 10b of the memory capacitor 10 is set to the first source line voltage (=0V) of the source line SL1. As a result, in the anti-fuse memory M11, the memory gate insulating film 10c is dielectrically broken between the memory gate electrode 10a and the channel formed in the first active region 31 immediately below the memory gate electrode 10a as described above. A voltage difference of 5V occurs. As a result, the memory gate insulating film 10c is broken down, the memory capacitor 10 is short-circuited, and data is written in the anti-fuse memory M11.

On the other hand, in the non-selected anti-fuse memory M, the first non-selected column voltage is applied from the word line WL to the gate electrode 20a to turn off the MOS transistor 20, or the bit line BL to the drain region 20c of the MOS transistor 20. Either or both of the first unselected column voltages are applied.

In the former case, the voltage from the bit line BL is not applied to the memory gate electrode 10a via the MOS transistor 20, and in the latter case, the voltage is applied to the memory gate electrode 10a via the MOS transistor 20. The non-selection voltage becomes the same as the first source line voltage applied from the source line SL to the diffusion region 10b. Therefore, in either case, in the non-selected anti-fuse memory M, there is no voltage difference between the memory gate electrode 10a and the first active region 31 immediately below the memory gate electrode 10a due to dielectric breakdown. The memory gate insulating film 10c remains in the insulating state without being broken down, and the state in which no data is written is maintained. Further, a leak current is prevented from flowing from the bit line BL to the source line SL via the non-selected anti-fuse memory M.

In the following, (A) unselected antifuse memory M in the same row as selected antifuse memory M, (B) different unselected antifuse memory M in the same column as selected antifuse memory M, and (C) different selected antifuse memory M. The row and column non-selected anti-fuse memory M will be described.

(A) In the non-selected anti-fuse memory M in the same row as the selected anti-fuse memory M, that is, in the anti-fuse memories M21, M31,... Connected to the same bit line BL1 as the anti-fuse memory M11, those MOS transistors 20 are connected. The first selected row voltage (=5V) is applied to the drain region 20c of the memory cell from the bit line BL1, but the first unselected column voltage (=0V) is applied to the memory gate electrode 10a from the word lines WL2, WL3. Is applied. As a result, the MOS transistors 20 of the antifuse memories M21, M31,... Are turned off. As a result, in the anti-fuse memories M21, M31,..., Memory gate insulation is performed between the memory gate electrode 10a of the memory capacitor 10 and the diffusion region 10b to which the first source line voltage (=0 V) is applied. There is no voltage difference that causes dielectric breakdown of the film 10c. Therefore, no data is written to the anti-fuse memories M21, M31....

In some or all of the anti-fuse memories M21, M31,..., Data may already be written and the memory capacitor 10 may be in a short circuit state. As described above, in the conventional semiconductor memory device including the conventional anti-fuse memory in which the gate electrode and the drain region of the MOS transistor are connected, the unselected anti-fuse memory in the same row as the selected anti-fuse memory sharing the word line is used. Since the MOS transistor of the fuse memory is turned on, there is a problem that a leak current flows from the word line to the bit line through the short-circuited memory capacitor. In the semiconductor memory device 1 as well, when the MOS transistors 20 of the anti-fuse memories M21, M31,... Are turned on, the bit lines BL1 are transferred to the source lines SL2, SL3,. Leak current flows. However, in this semiconductor memory device 1, a voltage can be independently applied to the bit line BL and the word line WL, and the first non-selected gate electrode 20a of the MOS transistor 20 of the anti-fuse memories M21, M31. Since the column voltage is applied to turn it off, such a leak current does not occur.

By the way, when data is written to the selective anti-fuse memory M, if an excessive voltage difference is generated between the memory gate electrode 10a and the diffusion region 10b or an excessive current flows, the range of destruction of the memory capacitor 10 becomes the well. It may extend to the inside of S2. In that case, in addition to the normal leakage current path flowing to the source line SL via the memory gate electrode 10a, the memory gate insulating film 10c, and the surface of the well S2, the well is also provided from the memory gate electrode 10a through the memory gate insulating film 10c. A leak path flowing to S2 is formed. The leak current flowing in the source line SL can be blocked by adjusting the voltage of the source line SL, but the leak current flowing in the well S2 cannot be blocked because the well potential needs to be 0V.

As described above, in the conventional semiconductor memory device, the MOS transistor of the non-selected anti-fuse memory in the same row as the selected anti-fuse memory is turned on. Therefore, when there is a leak path flowing to the well, the short-circuited memory capacitor is present. There is a problem that a leak current flows from the word line to the well through the. Therefore, in the conventional semiconductor memory device, precise adjustment and control of the applied voltage and the like for data writing are indispensable so as to avoid excessive breakdown in the memory capacitor and perform appropriate dielectric breakdown.

On the other hand, in the semiconductor memory device 1, a voltage can be independently applied to the bit line BL and the word line WL, and the gate electrode 20a of the MOS transistor 20 of the anti-fuse memories M21, M31,. Since the non-selected column voltage is applied to turn it off, the leak current does not flow through the leak path even if there is a leak path flowing through the well S2. This means that the formation of a leak path to the well S2 is allowed at the time of writing data, and the data writing conditions such as the first selected column voltage and the first selected row voltage can be easily determined. In addition to being able to do so, it is advantageous for reliable dielectric breakdown.

Further, since the leak current to the source lines SL2, SL3,... Through a part or all of the anti-fuse memories M21, M31,... Is suppressed by the MOS transistor 20 in the off state as described above, It is not necessary to suppress the leak current by setting the voltage set for the lines SL2, SL3... to higher than 0V. Therefore, the potential of the diffusion regions 10b of the anti-fuse memories M22, M32,..., M23, M33, etc., which are the non-selected anti-fuse memories M connected to the source lines SL2, SL3,. Therefore, it is possible to prevent erroneous writing to other anti-fuse memories M22, M32,..., M23, M33, etc. connected to the source lines SL2, SL3.

(B) In the unselected anti-fuse memories M in the same column as the selected anti-fuse memory M, that is, in the anti-fuse memories M12, M13,... Which are connected to the same word line WL1 and source line SL1 as the anti-fuse memory M11, The first selected column voltage is applied to the gate electrode 20a of the MOS transistor 20 from the word line WL1 to be turned on. However, in these anti-fuse memories M12, M13,..., The first non-selected row voltage (=0 V) from the bit lines BL2, BL3... Is applied to the drain region 20c of the MOS transistor 20. Further, the first source line voltage (=0 V) is applied from the source line SL1 to the diffusion region 10b of the memory capacitor 10. Therefore, the memory gate insulating film 10c is insulated between the memory gate electrode 10a to which the first non-selected row voltage is applied via the MOS transistor 20 and the diffusion region 10b to which the first source line voltage is applied. There is no voltage difference to destroy. Therefore, no data is written to the anti-fuse memories M12, M13,.... Further, since the bit lines BL2, BL3... And the source line SL1 have the same voltage, the source line SL1 and the bit lines BL2, BL3... Are passed through the anti-fuse memories M12, M13.・Leak current does not flow between and.

A first selected column voltage (=6V) higher than the voltage that causes dielectric breakdown of the memory gate insulating film 10c is applied to the gate insulating film 20d of the MOS transistor 20 of the anti-fuse memories M12, M13. Since the gate insulating film 20d is made thicker than the memory gate insulating film 10c according to the first selected column voltage, the gate insulating film 20d is not dielectrically broken down.

(C) An anti-fuse memory M of a row and a column different from that of the selected anti-fuse memory M, that is, an anti-fuse whose connected bit line BL, word line WL, and source line SL are different from the anti-fuse memory M11. In the memories M22, M32..., M23, M33, etc., the first non-selected column voltage (=0 V) from the word lines WL2, WL3,... Is applied to the gate electrodes 20a of the MOS transistors 20 thereof. ing. Therefore, since the MOS transistor 20 is maintained in the off state, the antifuse memories M22, M32,..., M23, M33,. No data is written.

Also, between the source lines SL2, SL3... And the bit lines BL2, BL3... Through the anti-fuse memories M22, M32..., M23, M33... In which the memory capacitors 10 are short-circuited. There is no leakage current flowing in. Since the first non-selected row voltage (=0 V) is applied to the bit lines BL2, BL3,... To which the anti-fuse memories M22, M32..., M23, M33... , No data is written due to the voltages of the bit lines BL2, BL3... And no leak current flows.

Next, the data read operation will be described. When reading data, first, the second source line voltage is set to each source line SL. With the second source line voltage set in this way, the second selected row voltage is applied to the bit line BL to which the selected anti-fuse memory M is connected, and the bit line BL is preset to the second selected row voltage. To charge. The other bit lines BL are not precharged as the second non-selected row voltage.

After the precharge is completed, the bit line BL is electrically disconnected from the row selection circuit 26. After that, the second selected column voltage is set to the word line WL to which the selected anti-fuse memory M is connected, and the second unselected column voltage is set to the other word lines WL. Then, the change in the potential of the bit line BL at this time is detected by the sense amplifier 27.

The second selected column voltage is determined as a gate voltage that turns on the MOS transistor 20, and is set to be equal to or higher than the threshold voltage of the MOS transistor 20. In this example, the second selected column voltage is set lower than the first selected column voltage. The second non-selected row voltage is a gate voltage that turns off the MOS transistor 20. The second non-selected row voltage is set to the same voltage as the second source line voltage. In this example, the second selected row voltage and the second selected column voltage are 3V, and the second unselected row voltage, the second unselected column voltage, and the second source line voltage are 0V, which is the same as the well voltage.

For example, when reading the data of the anti-fuse memory M11, as shown in FIG. 5, with the source lines SL1, SL2, SL3,... Set to the second source line voltage (=0 V), the bit line BL1 is changed to the first line. 2 Precharge up to the selected row voltage (=3V). After completion of the precharge, the word line WL1 is set to the second selected column voltage (=3V), and the other word lines WL2, WL3... Are set to the second non-selected column voltage (=0V).

The MOS transistor 20 of the anti-fuse memory M11 is turned on by applying 3V from the word lines WL1 to the gate electrode 20a thereof. As a result, the voltage of the bit line BL1 is applied to the memory gate electrode 10a via the MOS transistor 20.

When no data is written in the anti-fuse memory M11, that is, when the memory capacitor 10 is in an insulated state, no current flows from the memory capacitor 10 toward the source line SL1. Therefore, the bit line BL1 holds the precharged 3V as it is. On the other hand, when data is already written in the anti-fuse memory M11, that is, when the memory capacitor 10 is in a short-circuited state, a current flows from the bit line BL1 through the MOS transistor 20 and the memory capacitor 10 in the direction of the source line SL1 and the bit The potential of the line drops.

In the other anti-fuse memories M21, M31,... Connected to the bit line BL1, 0V is applied to the memory gate electrodes 10a of the MOS transistors 20 from the word lines WL2, WL3. As a result, the MOS transistors 20 of the antifuse memories M21, M31,... Are maintained in the off state. Therefore, no current flows from the bit line BL1 through the anti-fuse memories M21, M31....

As described above, the potential of the bit line BL1 is determined depending on whether or not the memory capacitor 10 of the antifuse memory M11 which is the selected antifuse memory M is in the short circuit state. When the memory capacitor 10 of the anti-fuse memory M11 is in the short-circuited state, the potential of the bit line BL1 drops with the lapse of time from the time when the second selected row voltage is applied.

By detecting the change in the potential of the bit line BL1 by the sense amplifier 27, it is possible to determine whether or not the anti-fuse memory M11 is written, that is, the 1-bit data held in the anti-fuse memory M11. ..

As described above, when writing data to the selective anti-fuse memory M, the range of destruction of the memory capacitor 10 extends to the inside of the well S2, and the leakage of current flowing from the memory gate electrode 10a to the well S2 through the memory gate insulating film 10c. A route may be formed.

In a conventional semiconductor memory device, a potential of a bit line connected to a diffusion region of a memory capacitor is detected by a sense amplifier and read. Specifically, when the memory capacitor is in a short circuit state, the voltage applied to the word line is applied to the memory gate electrode of the memory capacitor through the MOS transistor (rectifying element), a current flows through the memory capacitor, and the potential of the bit line is increased. Rises. If the memory capacitor is in the insulated state, no current flows through the memory capacitor even if the voltage applied to the word line is applied to the memory gate electrode of the memory capacitor through the MOS transistor (rectifying element), and the potential of the bit line does not change. ..

When a leak path for the current flowing from the memory gate electrode to the well is formed in the memory capacitor through the memory gate insulating film, the current flows from the memory gate electrode to the well and does not flow to the diffusion region of the memory capacitor. Then, in the conventional semiconductor memory device, even if the memory capacitor is short-circuited, the potential of the bit line does not rise and reading cannot be performed.

On the other hand, in the semiconductor memory device 1, when the memory capacitor 10 is in the short-circuited state, there is a leakage path of the current flowing from the memory gate electrode 10a to the well S2 through the memory gate insulating film 10c, and the bit line BL1 to the MOS. Even if current does not flow in the direction of the source line SL1 through the transistor 20 and the memory capacitor 10 and flows in the well S2, the potential of the bit line BL1 drops. Therefore, when data is written to the selected anti-fuse memory M, the range of destruction of the memory capacitor 10 extends to the inside of the well S2, and a leak path for a current flowing from the memory gate electrode 10a to the well S2 through the memory gate insulating film 10c is formed. Even if it is, it is possible to determine whether or not the anti-fuse memory M11 is written by detecting the change in the potential of the bit line BL1 with the sense amplifier 27.

In the above example, in the data write operation, the first non-selected row voltage is the same as the well voltage (=0 V), but it may be an intermediate voltage between the well voltage and the first selected row voltage. For example, when the first source line voltage and the well voltage are 0V and the first selected row voltage is 6V, the first non-selected row voltage can be about 3V. Thus, by setting the first non-selected row voltage to the intermediate voltage, the voltage applied to the gate insulating film 20d can be reduced. That is, it is formed on the surface of the gate electrode 20a to which the first selected column voltage is applied from the word line WL and the second active region 32 immediately below the gate electrode 20a, and the first non-contact from the bit line BL via the drain region 20c. The voltage difference from the channel to which the selected row voltage (intermediate voltage) is applied can be made smaller than in the above example. Therefore, the thickness of the gate insulating film 20d can be reduced, and for example, the memory gate insulating film 10c and the gate insulating film 20d can have the same thickness. When the first non-selected row voltage is set to the intermediate voltage as described above, the intermediate voltage is set so that the voltage difference from the well voltage is lower than the voltage that causes the dielectric breakdown of the memory gate insulating film 10c. ..

Further, in the above example, in the data write operation, 0 V is set as the first source line voltage to each source line SL, but the voltage of each source line SL not connected to the selected anti-fuse memory M is , But is not limited to this. For example, the voltage of each source line SL not connected to the selected anti-fuse memory M may be an intermediate voltage higher than 0V and lower than the first selected row voltage. In this case, the first selected row voltage can be set to 5V, and the voltage of each source line SL not connected to the selected anti-fuse memory M can be set to, for example, about 3V. In this case, for example, even when the off characteristic of the MOS transistor 20 is insufficient and a part of the first selected column voltage of the bit line BL is applied to the memory gate electrode 10a of the memory capacitor 10, Since the voltage difference between the memory gate electrode 10a and the source line SL becomes small, the leak current flowing through the memory capacitor 10 in the short-circuited state can be reduced.

When setting the voltage of each source line SL not connected to the selected anti-fuse memory M to the intermediate voltage as described above, the first non-selected column voltage is set to a voltage higher than 0V and lower than the first selected column voltage. However, the voltage applied to the memory gate electrode 10a from the bit line BL to which the first selected column voltage is applied to the memory gate electrode 10a via the MOS transistor 20 becomes equal to or lower than the intermediate voltage. The selected column voltage may be set. For example, the first selected column voltage may be 6V, the first selected row voltage may be 5V, the intermediate voltage may be 3V, and the first non-selected column voltage may be set to 3V or less. In this case, as in the conventional semiconductor memory device, the MOS transistor 20 of the unselected antifuse memory M on the same row as the selected antifuse memory M is turned on, but the voltage applied to the memory gate electrode 10a and the source Since the voltage difference from the intermediate voltage of the line SL is small, the leak current in the non-selected anti-fuse memory M connected to the same bit line BL as the selected anti-fuse memory M can be suppressed.

Further, in the data read operation, the second selected column voltage and the second selected row voltage are the same, but the present invention is not limited to this, and they may be different voltages. For example, the second selected column voltage may be set higher than the second selected row voltage, and the second selected row voltage can be set to 3V and the second selected column voltage can be set to 5V. By setting the second selected column voltage to be high, the on-current of the MOS transistor 20 can be increased, the voltage drop rate of the bit line BL when the memory capacitor 10 is in the short-circuited state can be increased, and the data read operation can be performed at high speed. Can be converted.

As described above, in the semiconductor memory device 1, data can be written and read even when the voltage of all the source lines SL is 0V. Therefore, as in the semiconductor memory device 1A whose circuit configuration is shown in FIG. 6, the diffusion region 10b of the memory capacitor 10 may have the same potential as the well S2. In this case, for example, the diffusion region 10b of the memory capacitor 10 may be replaced with a diffusion region heavily doped with a P-type dopant. Alternatively, the diffusion region may not be formed in the first active region 31. In writing data with such a configuration, the memory gate insulating film 10c is destroyed by the voltage difference between the memory gate electrode 10a and the first active region 31 (well S2), and in reading, the memory gate electrode 10a is insulated from the memory gate electrode 10a. A current from the bit line BL1 is passed through the first active region 31 through the destroyed memory gate insulating film 10c. According to such a semiconductor memory device 1A, the source line SL can be eliminated and the circuit scale can be reduced.

In the above example, the N-type memory capacitor in which the memory gate insulating film and the memory gate electrode are stacked on the P-type well (first active region) and the gate insulating film on the P-type well (second active region) The anti-fuse memory is composed of the N-type MOS transistor and the gate electrode stacked, but the present invention is not limited to this, and the anti-fuse memory is composed of a P-type memory capacitor and a P-type MOS transistor. You may. In this case, in the P-type memory capacitor, the memory gate insulating film and the memory gate electrode are stacked on the first active region provided in the N-type well, and the P-type dopant is highly doped in the first active region. The diffusion region may be formed by forming the diffusion region. As for the diffusion region of this P-type memory capacitor, similarly to the above-described example, the diffusion region is not formed even if the N-type dopant is highly doped in addition to the P-type dopant being highly doped. It may be configured. In the P-type MOS transistor, a gate insulating film and a gate electrode may be stacked in an N-type well to form a drain region and a source region that are heavily doped with a P-type dopant.

Further, in the above example, the plurality of anti-fuse memories are arranged in a matrix of a plurality of rows and a plurality of columns, but the number of rows and the number of columns may be one or more, for example, a matrix of one row and a plurality of columns It may be in a matrix of a plurality of rows and one column.

1, 1A Semiconductor memory device 10 Memory capacitor 10a Memory gate electrode 10b Diffusion region 10c Memory gate insulating film 20 MOS transistor 20a Gate electrode 20b Source region 20c Drain region 20d Gate insulating film 27 Sense amplifier 31, 32 Active region BL bit line SL source Line WL Word line M Anti-fuse memory

Claims (4)

Bit lines extending in the row direction,
A word line extending in the column direction,
Source lines extending in the column direction,
A plurality of anti-fuse memories and a memory array arranged in a matrix,
Each antifuse memory of the plurality of antifuse memories is
A memory capacitor having an active region, a memory gate insulating film formed on the active region, a memory gate electrode formed on the memory gate insulating film, and a diffusion region formed in the active region,
A MOS transistor having a gate electrode, a source region, and a drain region,
The word line is connected to the gate electrode,
The bit line is connected to the drain region,
The source line is connected to the diffusion region,
The memory gate electrode and the source region are connected,
A first selected row voltage, which is a voltage that causes a dielectric breakdown of the memory gate insulating film, is applied to a selected bit line that is the bit line connected to the anti-fuse memory that is a write target,
A first selected column voltage, which is a voltage for turning on the MOS transistor, is applied to a selected word line that is the word line connected to the anti-fuse memory that is the target of writing,
The same voltage as the voltage of the well in which the active region is formed is applied to the selected source line that is the source line to which the anti-fuse memory that is the target of writing is connected,
A semiconductor memory device, wherein a voltage higher than 0V and lower than the first selected row voltage is applied to a non-selected source line which is the source line to which the anti-fuse memory which is a write target is not connected. .. 2. A voltage higher than 0 V and lower than the first selected column voltage is applied to an unselected word line which is the word line to which the anti-fuse memory which is a write target is not connected. The semiconductor memory device according to 1. Applying a second selected row voltage to the selected bit line which is the bit line to which the anti-fuse memory that is the target of reading is connected,
A second selected column voltage which is a voltage for turning on the MOS transistor and higher than the second selected row voltage is applied to a selected word line which is the word line connected to the anti-fuse memory which is a read target. The semiconductor memory device according to claim 1, wherein the voltage is applied. 4. The semiconductor memory device according to claim 1, further comprising a sense amplifier connected to the bit line and detecting a change in the potential of the bit line.

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