TW202329623A - Glitch-free low-pass filter circuit and system circuit using the same - Google Patents

Abstract

A glitch-free low-pass filter circuit and a system circuit using the same are illustrated. The glitch-free low-pass filter circuit has a first low-pass filter unit and a second low-pass filter unit. The first low-pass filter unit is used to generate a first signal corresponding to an integration result of an input signal, perform hysteresis processing on the first signal to generate a second signal, and reset a voltage of the first signal to be a first reset voltage or a second reset voltage according to the first signal and the second signal, wherein the first reset voltage is greater than the second reset voltage. The second low-pass filter unit is used to generate a third signal corresponding to an integration result of the second signal, perform hysteresis processing on the third signal to generate a fourth signal, and reset a voltage of the third signal to be the first reset voltage or the second reset voltage according to the fourth signal.

Description

Low-pass filter circuit without short-time pulse wave and system circuit using it

The present invention relates to a low-pass filter circuit, and in particular to a glitch-free low-pass filter circuit and a system circuit using it. The pulse width of the input signal is close to that of the low-pass filter circuit When the preset filter pulse width is selected, the output signal will not have a short-term pulse wave (glitch).

The power glitch attack is the most common attack method, which is used to make a chip with security protection go through such an attack, so that the security protection mode of the chip has been disarmed, and then steal the internal information of the chip. important information. Usually the power glitch can be filtered out by a low-pass filter, so that the chip is protected from the above-mentioned attacks. In addition, in order to avoid the short-time pulse wave generated by the clock signal due to noise, the low-pass filter circuit can also be used to filter out the short-time pulse wave in the clock signal, so as to avoid the back-end circuit due to receiving short-time pulse wave The clock signal of the pulse wave may cause operation errors.

One of the low-pass filter circuits in the prior art is shown in Figure 1. The low-pass filter circuit 1 includes an integrating circuit (composed of a resistor R1 and a capacitor C1) and a Schmitt trigger SCHTRG, wherein one end of the resistor R1 receives an input signal, the other end of the resistor R1 is electrically connected to the input end of the Schmitt trigger SCHTRG and one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected to a low voltage, such as the ground voltage GND. When the input signal VIN has a short-time pulse wave or other interference, the low-pass filter circuit 1 can filter the input signal VIN to a certain extent through the low-pass filter characteristic of the integrating circuit and cooperate with the hysteresis characteristic of the Schmitt trigger SCHTRG. The short-time pulse wave or other interference is eliminated, and thereby the output signal VOUT is generated.

However, the low-pass filter circuit 1 lacks the charge removal mechanism of the integrating capacitor (i.e. capacitor C1), so the result of the low-pass filter still has considerable dependence on the waveform or pattern of the input signal VIN. The discharge time constant (associated with the resistance value of resistor R1 and the capacitance value of capacitor C1) does not match the pattern of the input signal VIN, and may not be able to filter out short-term pulse waves or other interference in the input signal VIN, resulting in output Signal VOUT transitions erroneously.

In order to improve the above problems, a logic control circuit can be added under the structure of the above low-pass filter circuit to periodically clear the charge of the integrating capacitor. The low-pass filter circuit can filter out signals whose pulse width is smaller than the preset filter pulse width. It’s just that when the pulse width of the signal is very close to the preset filter pulse width, due to the lack of a proper arbitration mechanism, the capacitor is not discharged correctly, so the edge of the output signal instead forms a short-term pulse wave with a smaller pulse width.

As shown in Figure 2, the pulse width of the input signal VIN gradually decreases from being greater than but close to the preset filtered pulse width PW over time, and is closer to the preset filtered pulse width PW, while the edge of the output signal VOUT will be due to the capacitor is not properly adjusted. Discharge with short-term pulse wave SP. When the pulse width is closer to the preset filter pulse width PW, the short-time pulse wave SP is more obviously generated at the edge of the output signal VOUT, and this short-time pulse wave SP will cause the load circuit at the end of the low-pass filter circuit to be damaged. Operation error.

An embodiment of the present invention provides a short-time pulse-free low-pass filter circuit, which includes a first low-pass filter unit and a second low-pass filter unit. The first low-pass filter unit is electrically connected to the input signal, and includes a first integration circuit, a first logic circuit and a first Schmitt trigger, wherein the first integration circuit is electrically connected to the first logic circuit and the first Schmitt trigger. flip-flop, the first logic circuit is electrically connected to the first Schmitt trigger, the first integration circuit is used to generate the first signal corresponding to the integration result of the input signal to the first Schmitt trigger, the first Schmitt trigger The flip-flop is used to generate a second signal according to the first signal, and the first logic circuit resets the voltage of the first signal to a first reset voltage or a second reset voltage according to the input signal and the second signal, wherein the first reset The voltage is greater than the second reset voltage. The second low-pass filter unit is electrically connected to the first low-pass filter unit, and includes a second integration circuit, a second logic circuit and a second Schmitt trigger, wherein the second integration circuit is electrically connected to the second logic circuit and the second logic circuit. Two Schmitt triggers, the second logic circuit is electrically connected to the second Schmitt trigger, the second integration circuit is used to generate a third signal corresponding to the integration result of the second signal to the second Schmitt trigger, The second Schmitt trigger is used to generate a fourth signal according to the third signal, and the second logic circuit resets the voltage of the third signal to the first reset voltage or the second reset voltage according to the fourth signal.

An embodiment of the present invention also provides a low-pass filter circuit without glitches, which includes a first low-pass filter unit and a second low-pass filter unit. The first low-pass filter unit is used to generate a first signal corresponding to the integration result of the input signal, perform hysteresis processing on the first signal to generate a second signal, and convert the voltage of the first signal according to the input signal and the second signal Reset to a first reset voltage or a second reset voltage, wherein the first reset voltage is greater than the second reset voltage. The second low-pass filter unit is electrically connected to the first low-pass filter unit, and is used for generating a third signal corresponding to the integration result of the second signal, performing hysteresis processing on the third signal to generate a fourth signal, and according to the first low-pass filter unit The four signals reset the voltage of the third signal to the first reset voltage or the second reset voltage.

An embodiment of the present invention further provides a system circuit, which includes the aforementioned low-pass filter circuit without short-time pulse wave and a load circuit, and the load circuit is electrically connected to the output signal generated by the low-pass filter circuit according to the fourth signal for operation.

To sum up, the low-pass filter circuit without short-term pulse wave provided by the embodiment of the present invention can not let the pulse width of the input signal close to the preset filter pulse width that the low-pass filter circuit can filter out. The output signal produces a short-time pulse wave.

In order to further understand the techniques, means and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and drawings are only for reference and illustration of the implementation of the present invention, and are not intended to limit the present invention.

Reference will now be made in detail to the exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts. In addition, the practice of the exemplary embodiment is only one of the implementations of the design concept of the present invention, and the following demonstrations are not intended to limit the present invention.

Embodiments of the present invention provide a short-time pulse-free low-pass filter circuit and a system circuit using the same. This low-pass filter circuit solves the technical problem that when the pulse width of the input signal shown in Figure 2 is close to the preset filter pulse width corresponding to the low-pass filter circuit, the output signal will have a short-term pulse wave. In other words, when the pulse width of the input signal is close to the preset filter pulse width corresponding to the low-pass filter circuit, the output signal generated by the low-pass filter circuit without short-term pulse wave in the embodiment of the present invention will not have a short-time pulse wave , so it can ensure that the load circuit of the output signal generated by the low-pass filter circuit at the back end can operate correctly.

The present invention uses two series-connected low-pass filter units to realize the above-mentioned low-pass filter circuit, and the low-pass filter unit has a mechanism for clearing the charge of the integrating capacitor. When the pulse width of the input signal is close to the preset filter pulse width corresponding to the low-pass filter circuit, although the low-pass filter unit of the first stage will still have a short-term pulse wave after the low-pass filter processing of the input signal, but Because the second-stage low-pass filter unit will perform low-pass filtering again, the short-term pulse wave in the signal output by the first-stage low-pass filter unit will be filtered out, so that the output signal output by the second-stage low-pass filter unit No longer has glitches.

Further, the low-pass filtering unit of the first stage is used to generate a first signal corresponding to the integration result of the input signal, and perform hysteresis processing on the first signal through a Schmitt trigger to generate a second signal. The low-pass filtering unit of the first stage can reset the voltage of the first signal to the first reset voltage (usually the system voltage) or the second reset voltage (less than the first reset voltage) according to the input signal and the second signal. Voltage, usually ground voltage) to achieve the mechanism of clearing the charge of the integrating capacitor.

The low-pass filtering unit of the second stage is used to generate a third signal corresponding to the integration result of the second signal, and performs hysteresis processing on the third signal through a Schmitt trigger to generate a fourth signal. The low-pass filter unit of the second stage can further reset the voltage of the third signal to the first reset voltage or the second reset voltage according to the fourth signal, so as to achieve the mechanism of clearing the charge of the integrating capacitor. The fourth signal of the second-stage low-pass filter unit will not generate a short-time pulse wave because the pulse width of the input signal is close to the preset filter pulse width corresponding to the low-pass filter circuit, and the fourth signal can be directly used as a low-pass filter. The output signal of the pass filter circuit, or the output signal of the low pass filter circuit after delay and/or inversion processing.

The system circuit of the embodiment of the present invention includes the above-mentioned low-pass filter circuit and a load circuit. The load circuit is electrically connected to the low-pass filter circuit, and obtains an output signal of the low-pass filter circuit for operation. For example, the input signal is a clock signal, and the fourth signal of the second-stage low-pass filter unit is delayed as an output signal to the load circuit, and the output signal is a clock signal without a short-term pulse wave. , so the load circuit can directly use this output signal as a clean clock signal to operate. The load circuit can be a different type of load circuit, for example, a microcontroller, a memory controller, or a front-end communication circuit, etc., and the present invention is not limited thereto. In addition, the input signal is not limited to be a clock signal, and may also be other types of signals, and the present invention is not limited by the type of the input signal.

Please refer to FIG. 3 . FIG. 3 is a circuit diagram of a low-pass filter circuit according to an embodiment of the present invention. The low-pass filter circuit 3 includes two low-pass filter units 31 and 32 electrically connected in series. The low-pass filter units 31 and 32 have a mechanism for clearing the charge of the integrating capacitor. After the input signal VIN is low-pass filtered by the two low-pass filter units 31 and 32, the low-pass filter circuit 3 will generate an output signal VOUT, and the output signal VOUT is close to the pulse width of the input signal obtained by the low-pass filter circuit 3. When the corresponding preset filter pulse width is used, there will be no short-term pulse wave.

The low-pass filter unit 31 is electrically connected to the input signal VIN, and includes an integrating circuit 311, a logic circuit 312 and a Schmitt trigger U5, wherein the integrating circuit 311 is electrically connected to the logic circuit 312 and the Schmitt trigger U5, and the logic circuit 312 Electrically connect the Schmitt trigger U5. The integration circuit 311 is used to generate the first signal corresponding to the integration result of the input signal VIN (in this embodiment, the input signal VIN is integrated by the integration circuit 311 after passing through two inverters U1, U2) to Schmitt Trigger U5. The Schmitt trigger U5 generates the second signal according to the first signal based on its own hysteresis specificity. The logic circuit 312 resets the voltage of the first signal (that is, the voltage at the connection point of the resistor R2 and the Schmitt trigger U5) to the system voltage VDD or the ground voltage GND according to the input signal VIN and the second signal, for example, according to the input signal VIN The voltage of the first signal is reset by the inverted signal generated to U1 through the inverter and the inverted signal generated by the second signal through the inverter U6.

The low-pass filter unit 32 is electrically connected to the low-pass filter unit 31, and includes an integrating circuit 321, a logic circuit 322 and a Schmitt trigger U8, wherein the integrating circuit 321 is electrically connected to the logic circuit 322 and the Schmitt trigger U8, and the logic The circuit 322 is electrically connected to the Schmitt trigger U8. The integration circuit 321 is used to generate the third signal VRC corresponding to the integration result of the second signal to the Schmitt trigger U8 (in this embodiment, after the second signal passes through two inverters U6, U7, it is integrated by the integration circuit 321 for integration). The Schmitt trigger U8 is used to generate the fourth signal according to the third signal VRC based on its own hysteresis specificity. The logic circuit 322 resets the voltage of the third signal VRC to the system voltage VDD or the ground voltage GND according to the fourth signal, for example, according to the fourth signal, the inverted signal and the fourth signal are passed through the inverter U9, The delayed signal generated by U12 resets the voltage of the third signal VRC.

In this embodiment, the integration circuit 311 includes two capacitors and a resistor R1, one of which is implemented by a P-type MOS transistor MC1, and the other capacitor is implemented by an N-type MOS transistor MC2, that is, a P-type MOS transistor MC1 and N-type MOS transistor MC2 are used as capacitor transistors, but the present invention is not limited by the way of capacitor implementation. The source and drain of the P-type MOS transistor MC1 are electrically connected to the system voltage VDD, the gate of the P-type MOS transistor MC1 is electrically connected to the gate of the N-type MOS transistor MC2, and the source of the N-type MOS transistor MC2 The pole and the drain are electrically connected to the ground voltage GND. One end of the resistor R2 is electrically connected to the input signal VIN, and the other end of the resistor R2 is electrically connected to the gate of the P-type MOS transistor MC1, the gate of the N-type MOS transistor MC2, and the Schmitt trigger U5 to output the first A signal to the Schmitt trigger U5.

The logic circuit 312 includes logic gates and switches. The logic gates of the logic circuit 312 are implemented with the OR gate U3 and the AND gate U4 in this embodiment, and the switches of the logic circuit 312 are implemented with P-type MOS transistors P1 and N in this embodiment. Type MOS transistor N1 is implemented, but the present invention is not limited to the above implementation.

The OR gate U3 is electrically connected to the input signal VIN (the inverting signal generated by the input signal VIN through the inverter U1 is input to the OR gate U3) and the Schmitt trigger U5 (the Schmitt trigger U5 is electrically connected through the inverter U6 connected to the OR gate U3), and generate the first control signal according to the input signal VIN and the second signal, for example, according to the inversion signal of the input signal VIN through the inverter U1 and the inversion signal generated by the second signal through the inverter U6 Generate a first control signal. The gate of the P-type MOS transistor P1 receives the first control signal, the source of the P-type MOS transistor P1 receives the system voltage VDD, and the drain of the P-type MOS transistor P1 is electrically connected to the Schmitt trigger U5 and the other end of resistor R2. The P-type MOS transistor P1 can reset the voltage of the second signal to the system voltage VDD according to the first control signal.

The AND gate U4 is electrically connected to the input signal VIN (the inverting signal generated by the input signal VIN through the inverter U1 is input to the AND gate U4 and the Schmitt trigger U5 (the Schmitt trigger U5 is electrically connected through the inverter U6 And gate U4), and generate the second control signal according to the input signal VIN and the second signal, for example, according to the inverted signal of the input signal VIN through the inverter U1 and the inverted signal generated by the second signal through the inverter U6 The second control signal. The gate of the N-type MOS transistor N1 receives the second control signal, the source of the N-type MOS transistor N1 receives the ground voltage GND, and the drain of the N-type MOS transistor N1 is electrically connected to the Smith The other end of the special trigger U5 and the resistor R2. The N-type MOS transistor N1 can reset the voltage of the second signal to the ground voltage GND according to the second control signal.

In the embodiment of the present invention, the low-pass filter unit 31 may further include a plurality of inverters U1 , U2 and U6 . The input terminal of the inverter U1 is electrically connected to the input signal VIN, the output terminal of the inverter U1 is electrically connected to the OR gate U3, and the gate U4 and the input terminal of the inverter U2, and the output terminal of the inverter U2 is electrically connected One end of the resistor R2 of the first integration circuit 311, the input end of the inverter U6 is electrically connected to the Schmitt trigger U5, and the output end of the inverter U6 is electrically connected to the OR gate U3, the gate U4 and the low-pass filter unit 32.

Please note here that the existence of the inverters U1, U2 and U6 may be unnecessary, and they are only provided for the specific design of the logic circuit 312. When the types and connection methods of the logic gates and switches of the logic circuit 312 are different As a modification, at least one of the inverters U1 , U2 and U6 may be removed, or more inverters may be disposed in the low-pass filter unit 31 .

In this embodiment, the integration circuit 321 includes two capacitors and a resistor R3, one of which is implemented by a P-type MOS transistor MC3, and the other capacitor is implemented by an N-type MOS transistor MC4, that is, a P-type MOS transistor MC3 and N-type MOS transistor MC4 are used as capacitor transistors, but the present invention is not limited by the way of capacitor implementation. The source and drain of the P-type MOS transistor MC3 are electrically connected to the system voltage VDD, the gate of the P-type MOS transistor MC3 is electrically connected to the gate of the N-type MOS transistor MC4, and the source of the N-type MOS transistor MC4 The pole and the drain are electrically connected to the ground voltage GND. One end of the resistor R3 is electrically connected to the second signal (the second signal is transmitted to one end of the resistor R3 through the inverters U6 and U7), and the other end of the resistor R3 is electrically connected to the gate of the P-type MOS transistor MC3, the N-type The gate of the MOS transistor MC4 and the Schmitt trigger U8 are used to output the third signal VRC to the Schmitt trigger U5.

The logic circuit 322 includes logic gates and switches. The logic gates of the logic circuit 322 are implemented with the OR gate U10 and the AND gate U11 in this embodiment, and the switches of the logic circuit 322 are implemented with P-type MOS transistors P2 and N in this embodiment. Type MOS transistor N2 is implemented, but the present invention is not limited to the above implementation.

The OR gate U10 is electrically connected to the Schmitt trigger U8 (the Schmitt trigger U8 is electrically connected to the OR gate U10 through the inverter U9, and is electrically connected to the OR gate U10 through the inverters U9 and U12), and the root The four signals generate the third control signal VP, for example, the third control signal VP is generated according to the inverted signal of the fourth signal passed through the inverter U9 and the delayed signal generated by the fourth signal passed through the inverters U9 and U12. The gate of the P-type MOS transistor P2 receives the third control signal VP, the source of the P-type MOS transistor P2 receives the system voltage VDD, and the drain of the P-type MOS transistor P2 is electrically connected to the Schmitt trigger U8 with the other end of resistor R3. The P-type MOS transistor P2 can reset the voltage of the third signal VRC to the system voltage VDD according to the third control signal VP.

And the gate U11 is electrically connected to the Schmitt trigger U8 (the Schmitt trigger U8 is electrically connected to the gate U11 through the inverter U9, and is electrically connected to the gate U11 through the inverters U9 and U12), and the root The four signals generate the fourth control signal VN, for example, the fourth control signal VN is generated according to the inverted signal of the fourth signal passed through the inverter U9 and the delayed signal generated by the fourth signal passed through the inverters U9 and U12. The gate of the N-type MOS transistor N2 receives the fourth control signal VN, the source of the N-type MOS transistor N2 receives the ground voltage GND, and the drain of the N-type MOS transistor N2 is electrically connected to the Schmitt trigger U8 with the other end of resistor R3. The N-type MOS transistor N2 can reset the voltage of the third signal VRC to the ground voltage GND according to the fourth control signal VN.

In the embodiment of the present invention, the low-pass filtering unit 32 may further include a plurality of inverters U7 , U9 and U12 . The input end of the inverter U7 is electrically connected to the low-pass filter unit 31 (electrically connected to the output end of the inverter U6), the output end of the inverter U7 is electrically connected to one end of the resistor R3, and the input end of the inverter U9 The Schmitt trigger U8 is electrically connected, the output terminal of the inverter U9 is electrically connected to the OR gate U10, and the gate U11 is connected to the input terminal of the inverter U12, and the output terminal of the inverter U12 is electrically connected to the OR gate U10 and the input terminal of the inverter U12. And gate U11. The output signal VOUT is generated by the four signals passing through the inverters U9 and U12.

Please note here that the existence of the inverters U7, U9 and U12 may be unnecessary, and they are only provided for the specific design method of the logic circuit 322. When the types and connection methods of the logic gates and switches of the logic circuit 312 are different As a modification, at least one of the inverters U7 , U9 and U12 may be removed, or more inverters may be disposed in the low-pass filter unit 32 .

Please refer to FIG. 3 and FIG. 4 of the present invention. FIG. 4 is a waveform diagram of signals in the low-pass filter circuit of the embodiment of the present invention. When the pulse width of the input signal VIN is close to the preset filtered pulse width, the second signal output by the Schmitt trigger U5 may have a short-term pulse wave, but after low-pass filtering by the low-pass filtering unit 32 again, the output The signal VOUT and the inverted fourth signal VF output by the inverter U9 do not have a short-time pulse wave. The reason is that when the second signal has a short-time pulse wave, the third signal VRC will be pulled low or pulled down suddenly. High, at this time, the third control signal VP generated by the OR gate U10 or the fourth control signal VN generated by the AND gate U11 will control the switch to reset the voltage of the third signal VRC to the system voltage VDD or the ground voltage GND, through this arbitration mechanism It can solve the technical problem of the low-pass filter circuit in the prior art that when the pulse width of the input signal is close to the preset filter pulse width, the short-time pulse wave will obviously be generated at the edge of the output signal.

Based on the above, the low-pass filter circuit without short-term pulse wave provided by the embodiment of the present invention can achieve the following technical effects: (1) Even if the pulse width of the input signal is close to the preset filter pulse width corresponding to the low-pass filter circuit , the output signal will not have a short-time pulse wave; (2) It can be used as the front-end circuit of the load circuit in the system circuit, which can more effectively solve the hacker's power supply or clock short-time pulse wave attack, and can also Stably provide output power or output clock without short-term pulse waves to the load circuit to ensure the load circuit can operate correctly.

It should be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes in view thereof will be suggested to those skilled in the art, and will be included within the spirit and scope of the application and the scope of the appended claims. within range.

1, 3: Low-pass filter circuit 31, 32: low-pass filter unit 311, 321: integrating circuit 312, 322: logic circuit R1, R2, R3: Resistors C1: capacitance SCHTRG, U5, U8: Schmitt Trigger VIN: input signal VOUT: output signal PW: preset filter pulse width SP: short duration pulse wave VF: Inverted fourth signal VP: The third control signal VN: The fourth control signal VRC: Third Signal U1, U2, U6, U7, U9, U12: Inverters U4, U11: and gate U3, U10: OR gate P1, P2, MC1, MC3: P-type MOS transistors N1, N2, MC2, MC4: N-type MOS transistors

The accompanying drawings are provided to enable those skilled in the art to which the present invention pertains to further understand the present invention, and are incorporated in and constitute a part of the specification of the present invention. The drawings illustrate exemplary embodiments of the invention and together with the description serve to explain principles of the invention.

FIG. 1 is a circuit diagram of a prior art low-pass filter circuit.

FIG. 2 is a waveform diagram of signals in a low-pass filter circuit with a charge removal mechanism of an integrating capacitor in the prior art.

FIG. 3 is a circuit diagram of a low-pass filter circuit according to an embodiment of the present invention.

FIG. 4 is a waveform diagram of signals in the low-pass filter circuit of the embodiment of the present invention.

3: Low-pass filter circuit

31, 32: low-pass filter unit

311, 321: integrating circuit

312, 322: logic circuit

R2, R3: resistance

U5, U8: Schmitt trigger

VIN: input signal

VOUT: output signal

VF: Inverted fourth signal

VP: The third control signal

VN: The fourth control signal

VRC: Third Signal

U1, U2, U6, U7, U9, U12: Inverters

U4, U11: and gate

U3, U10: OR gate

P1, P2, MC1, MC3: P-type MOS transistors

N1, N2, MC2, MC4: N-type MOS transistors

Claims (10)

A low-pass filter circuit without short-term pulse waves, including: A first low-pass filter unit is electrically connected to an input signal, and includes a first integration circuit, a first logic circuit and a first Schmitt trigger, wherein the first integration circuit is electrically connected to the first The logic circuit and the first Schmitt trigger, the first logic circuit is electrically connected to the first Schmitt trigger, and the first integration circuit is used to generate a first integral result corresponding to the input signal. signal to the first Schmitt trigger, the first Schmitt trigger is used to generate a second signal according to the first signal, and the first logic circuit generates the first signal according to the input signal and the second signal a voltage of the signal is reset to a first reset voltage or a second reset voltage, wherein the first reset voltage is greater than the second reset voltage; and A second low-pass filter unit, electrically connected to the first low-pass filter unit, and includes a second integration circuit, a second logic circuit and a second Schmitt trigger, wherein the second integration circuit is electrically The second logic circuit is connected to the second Schmitt trigger, the second logic circuit is electrically connected to the second Schmitt trigger, and the second integrating circuit is used to generate an integral corresponding to the second signal A third signal of the result is given to the second Schmitt trigger, and the second Schmitt trigger is used to generate a fourth signal according to the third signal, and the second logic circuit generates the first signal according to the fourth signal. A voltage of the three signals is reset to the first reset voltage or the second reset voltage. The short-time pulse-free low-pass filter circuit as described in claim 1, wherein each of the first integrating circuit and the second integrating circuit includes: a first capacitor, one end of which is electrically connected to the first reset voltage; a second capacitor, one end of which is electrically connected to the other end of the first capacitor, and the other end of which is electrically connected to the second reset voltage; and a resistor, one end of which is electrically connected to the other end of the first capacitor and the one end of the second capacitor, and one end of which is electrically connected to the input signal; The other end of the resistor of the first integrating circuit is electrically connected to the input signal, and the one end of the resistor of the first integrating circuit is electrically connected to the first Schmitt trigger to output the first signal to The first Schmitt trigger, the other end of the resistor of the second integrating circuit is electrically connected to the second signal, and the one end of the resistor of the second integrating circuit is electrically connected to the second Schmitt trigger flip-flop to output the third signal to the second Schmitt trigger. The low-pass filter circuit without short-term pulse wave as described in claim 1, wherein the first logic circuit includes: a first logic gate, electrically connected to the input signal and the first Schmitt trigger, and generates a first control signal according to the input signal and the second signal; a second logic gate electrically connected to the input signal and the first Schmitt trigger, and generates a second control signal according to the input signal and the second signal; a first switch electrically connected to the first reset voltage, the first integration circuit and the first logic gate, and resets the voltage of the second signal to the first reset voltage according to the first control signal ;as well as a second switch electrically connected to the second reset voltage, the first integrating circuit and the second logic gate, and resets the voltage of the second signal to the second reset voltage according to the second control signal . The low-pass filter circuit without short-term pulse waves as described in claim 3, wherein the first logic gate is an OR gate, the second logic gate is an AND gate, and the first switch is a P-type MOS transistor , the second switch is an N-type MOS transistor, and the first low-pass filter unit further includes a first inverter, a second inverter and a third inverter, wherein the first inverter An input end of the inverter is electrically connected to the input signal, and an output end of the first inverter is electrically connected to the first logic gate, the second logic gate and the second inverter of the first logic circuit. an input end, an output end of the second inverter is electrically connected to the first integration circuit, an input end of the third inverter is electrically connected to the first Schmitt trigger, and the third inverter An output terminal of the device is electrically connected to the first logic gate, the second logic gate and the second low-pass filter unit of the first logic circuit. The low-pass filter circuit without short-term pulse wave as described in claim 1, wherein the second logic circuit includes: A third logic gate, electrically connected to the second Schmitt trigger, generates a third control signal according to the fourth signal; A fourth logic gate, electrically connected to the second Schmitt trigger, generates a fourth control signal according to the fourth signal; a third switch electrically connected to the first reset voltage, the second integrating circuit and the third logic gate, and resets the voltage of the third signal to the first reset voltage according to the third control signal ;as well as a fourth switch electrically connected to the second reset voltage, the second integrating circuit and the fourth logic gate, and resets the voltage of the third signal to the second reset voltage according to the fourth control signal . The low-pass filter circuit without short-term pulse wave as described in claim 5, wherein the third logic gate is an OR gate, the fourth logic gate is an AND gate, and the third switch is a P-type MOS transistor , the fourth switch is an N-type MOS transistor, and the first low-pass filter unit further includes a fourth inverter, a fifth inverter and a sixth inverter, the fourth inverter An input end of the fourth inverter is electrically connected to the first low-pass filter unit, an output end of the fourth inverter is electrically connected to the second integration circuit, and an input end of the fifth inverter is electrically connected to the second Schmitt trigger, an output end of the fifth inverter is electrically connected to the third logic gate, the fourth logic gate and an input end of the sixth inverter of the second logic circuit, the first An output terminal of the six inverters is electrically connected to the third logic gate and the fourth logic gate of the second logic circuit. The low-pass filter circuit without short-time pulse wave as described in claim 2, wherein the first capacitor is a first capacitor transistor, and the second capacitor is a second capacitor transistor, and the first capacitor transistor A source and a drain of the first capacitive transistor are electrically connected to the first reset voltage, a gate of the first capacitive transistor is electrically connected to a gate of the second capacitive transistor, and a gate of the second capacitive transistor A source and a drain are electrically connected to the second reset voltage, wherein the first capacitor transistor is a P-type MOS transistor, and the second capacitor transistor is an N-type MOS transistor. The low-pass filter circuit without short-term pulse waves as described in claim 1, wherein the input signal is a first clock signal, an output signal of the low-pass filter circuit is a second clock signal, and the first The reset voltage is a system voltage, and the second reset voltage is a ground voltage. A low-pass filter circuit without short-term pulse waves, including: A first low-pass filtering unit is used for generating a first signal corresponding to an integration result of an input signal, performing hysteresis processing on the first signal to generate a second signal, and according to the input signal and the the second signal resets a voltage of the first signal to a first reset voltage or a second reset voltage, wherein the first reset voltage is greater than the second reset voltage; and A second low-pass filter unit, electrically connected to the first low-pass filter unit, for generating a third signal corresponding to an integration result of the second signal, and performing hysteresis processing on the third signal to generate a fourth signal, and reset a voltage of the third signal to the first reset voltage or the second reset voltage according to the fourth signal. A system circuit comprising: The low-pass filter circuit without glitches as described in one of claims 1-9, wherein the low-pass filter circuit is used to generate an output signal according to the fourth signal; and A load circuit is electrically connected to the output signal for operation.