TW202329371A - Dram device with embedded chip and fabrication method thereof - Google Patents

Abstract

A DRAM (dynamic random access memory) device with an embedded chip includes a semiconductor chip and a logic chip. The semiconductor chip includes a first substrate, a dynamic random access memory, and an embedded area. The dynamic random access memory is formed on the first substrate and has a bit line and a capacitor disposed on the bit line. The embedded area is defined in the semiconductor chip apart from the dynamic random access memory, and a bottom of the embedded area is on or below a surface of the first substrate. The logic chip is embedded in the embedded area, wherein the logic chip includes a second substrate and a logic device formed on the second substrate, and a bottom of the second substrate is disposed on or below the surface of the first substrate.

Description

Dynamic random access memory device with embedded chip and manufacturing method thereof

The present invention relates to a method of integrating DRAM and logic chip, and in particular to a DRAM device with embedded chip and its manufacturing method.

In the current semiconductor technology, if it is necessary to integrate dynamic random access memory (DRAM) and logic chips, there are mainly two ways.

One is to use a redistribution carrier (RDL interposer) in the packaging process to bond the DRAM chip and the logic chip to the redistribution carrier respectively, and then bond the redistribution carrier to the printed circuit board.

The other is to use WoW (Wafer on Wafer) technology to bond DRAM chips and logic chips at the wafer level, and then use through-silicon via (TSV) and redistribution (RDL) processes to complete the internal interconnection.

The invention provides a dynamic random access memory (DRAM) device with an embedded chip, which can directly embed a thin logic chip into a semiconductor chip with a dynamic random access memory, so that the dynamic random access memory and the logic chip are integrated to the same semiconductor wafer.

The present invention also provides a method for manufacturing a DRAM device with an embedded chip, which can integrate logic elements and DRAM in the front-end process without requiring complex back-end process or packaging technology.

The DRAM device with embedded chip of the present invention includes a semiconductor chip and a logic chip. The semiconductor chip includes a first substrate, a DRAM and an embedding area. The DRAM is formed on the first substrate, and has bit lines and capacitors arranged on the bit lines. The embedded area is defined in the semiconductor chip other than the DRAM, and the bottom of the embedded area is on or below the surface of the first substrate. A logic chip is embedded in the embedding area, wherein the logic chip includes a second substrate and logic elements formed on the second substrate, and the bottom of the second substrate is located on or below the surface of the first substrate.

In an embodiment of the present invention, the thickness of the logic chip is less than or equal to the thickness of the dynamic random access memory.

In an embodiment of the present invention, the second substrate of the logic chip includes a silicon substrate or an SOI substrate.

In an embodiment of the present invention, the semiconductor wafer includes a first inner dielectric layer covering capacitors, the logic wafer includes a second inner dielectric layer covering logic elements, and the first inner dielectric layer The top surface is coplanar with the top surface of the second interlayer dielectric layer.

In an embodiment of the present invention, the above-mentioned DRAM device may further include a first metal layer formed on the first ILD layer and the second ILD layer.

In an embodiment of the present invention, the dynamic random access memory device may further include an insulating material interposed between the logic chip and the semiconductor chip, so that the logic chip is fixed on the first substrate of the semiconductor chip.

In an embodiment of the present invention, the embedding region includes a groove formed in the first substrate, and the bottom surface of the second substrate contacts the bottom surface of the groove.

In an embodiment of the present invention, the surface of the second substrate is located between the bottom surface and the top surface of the capacitor.

The method for manufacturing a DRAM device with an embedded chip of the present invention includes providing a semiconductor chip with a DRAM, the semiconductor chip comprising a first substrate and a DRAM formed on the first substrate. An access memory, wherein the dynamic random access memory includes bit lines and capacitors disposed on the bit lines. Then, an embedding area is defined in the semiconductor wafer other than the DRAM, and the bottom of the embedding area is located on the surface of the first substrate or below the surface. A logic chip is embedded in the embedding area, wherein the logic chip includes a second substrate and logic elements formed on the second substrate. An insulating material is deposited on the semiconductor wafer and the logic wafer, so that the logic wafer is fixed on the first substrate of the semiconductor wafer. Afterwards, a plurality of conductive plugs are formed, respectively connected to the capacitor and the logic element, and then a first metal layer is formed on the semiconductor wafer and the logic wafer, so as to be electrically connected to the capacitor and the logic element through the conductive plugs, respectively. line.

In another embodiment of the present invention, the semiconductor chip further includes at least one first interlayer dielectric layer formed on the first substrate and the capacitor.

In another embodiment of the present invention, the method for defining the embedded region includes etching and removing the first interlayer dielectric layer.

In another embodiment of the present invention, the method for defining the embedding region includes etching and removing the first interlayer dielectric layer to expose the surface of the first substrate, and then etching and removing part of the exposed first substrate to form a concave groove.

In another embodiment of the present invention, the step of forming the plurality of conductive plugs includes forming a plurality of first conductive plugs connected to the capacitors and forming peripheral circuits respectively connected to logic elements and dynamic random access memory A plurality of second conductive plugs are connected, wherein the height of the second conductive plugs is greater than the height of the capacitor.

In another embodiment of the present invention, before forming the plurality of conductive plugs, grinding the insulating material by chemical mechanical planarization may be further included.

In another embodiment of the present invention, the above-mentioned logic chip further includes a second interlayer dielectric layer covering the logic element, and after depositing the above-mentioned insulating material, it may further include etching back the insulating material, so as to reduce the contact between the semiconductor chip and the semiconductor chip. The surface height difference of the logic wafer is divided by a chemical mechanical planarization method, and then ground to the required height of the plurality of conductive plugs.

In another embodiment of the present invention, before etching back the insulating material, it may further include forming a mask layer to cover the insulating material on the dynamic random access memory and exposing the insulating material on the second inner layer dielectric layer. .

Based on the above, the present invention uses a thin logic chip and directly embeds it in the semiconductor chip. Since the semiconductor chip has been formed with a DRAM, and the capacitor of the DRAM generally has a capacitor with a height of about 2 μm, Therefore, as long as the thickness of the logic chip is controlled to be slightly larger than or close to the height of the capacitor, the logic chip can be installed in it without complicated back-end process or packaging technology. Even if the thickness of the logic chip is much larger than the height of the capacitor, the logic chip can be embedded in the groove by forming a groove in the substrate, and then using methods such as etching back and chemical mechanical planarization, etc., can be used in the front-end process. Integrating logic components and DRAM does not require complicated back-end process or packaging technology.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

The following presents a number of different implementations, or examples, for implementing different features of the invention. Moreover, these embodiments are only examples, and are not intended to limit the scope and application of the present invention. Furthermore, for the sake of clarity, the relative size (such as length, thickness, pitch, etc.) and relative position of various regions or structural elements may be reduced or enlarged. In addition, similar or identical reference numerals are used in each drawing to indicate similar or identical elements or features.

1A to 1D are schematic cross-sectional views of a manufacturing process of a DRAM device with an embedded chip according to a first embodiment of the present invention.

1A, a semiconductor chip 100 is provided, which includes a first substrate 102 and a DRAM 104 formed on the first substrate 102, wherein the DRAM 104 includes a bit line BL and a set The capacitor 106 on the bit line BL belongs to COB (capacitor over bitline) DRAM. The first substrate 102 is, for example, a silicon substrate or other semiconductor substrates, and may have an element isolation structure STI. The semiconductor chip 100 further includes first interlayer dielectric layers 108 ₁ , 108 ₂ and 108 ₃ formed on the first substrate 102 and the capacitor 106 . The DRAM 104 generally further includes embedded word lines WL formed in the first substrate 102, an insulating layer 110 covering the word lines WL, conductive doped regions 112 between the word lines WL, A bit line contact 114 and a storage node contact 116 are formed on the first substrate 102 . The capacitor 106 may include a lower electrode layer 118, a dielectric layer 120 and an upper electrode layer 122, wherein the lower electrode layer 118 is such as a Ti/TiN layer, the dielectric layer 120 is such as a high dielectric constant material layer, and the upper electrode layer 122 is such as a polysilicon layer 124 and metal layer 126 in combination. However, the present invention is not limited thereto, and the structure of the capacitor 106 can also have other deformations according to requirements.

Then, referring to FIG. 1B, an embedding region EM is defined in the semiconductor wafer 100 other than the dynamic random access memory 104, and the bottom of the embedding region EM is located on the surface 102a of the first substrate 102, wherein the method for defining the embedding region EM For example, the first ILD layers 108 ₁ and 108 ₃ are removed by etching.

Next, referring to FIG. 1C, a logic chip 130 is embedded in the embedding region EM, wherein the logic chip 130 includes a second substrate 132 and logic elements 134 formed on the second substrate 132, wherein the second substrate 132 is for example a silicon substrate or an SOI substrate , the logic element 134 is, for example, a MOS transistor, and a second interlayer dielectric layer 136 is formed on the logic element 134 . In the first embodiment, the total thickness of the logic chip 130 is not greater than 2.5 µm, for example, the thickness of the second substrate 132 is about 2 µm, the thickness of the second interlayer dielectric layer 136 is about 0.5 µm, and the insulating material in the logic chip 130 The STI depth is about 0.3 µm. Then, an insulating material 138 is deposited on the semiconductor wafer 100 and the logic wafer 130 to fix the logic wafer 130 on the first substrate 102 of the semiconductor wafer 100 . The insulating material 138 is not only located above the first ILD layer ₁₀₈₃ and the second ILD layer 136 , but also fills the gap between the logic chip 130 and the DRAM 104 in the embedding region EM.

Afterwards, please refer to FIG. 1D , the insulating material 136 may be ground by using a chemical mechanical planarization method to remove the level difference on the surface of the structure. Although the figure shows that there is no insulating material 138 above the first ILD layer ₁₀₈₃ and the second ILD layer 136, the invention is not limited thereto. In another embodiment, part of the insulating material 138 may still remain above the first ILD layer ₁₀₈₃ and the second ILD layer 136 . Next, a plurality of conductive plugs 140 a and 140 b are formed, wherein the conductive plug 140 a is connected to the capacitor 106 (metal layer 126 ), and the conductive plug 140 b is connected to the logic element 134 (source/drain S/D). The conductive plugs 140a, 140b can be formed by the same process. For example, a photoresist layer (not shown) is first formed on the first interlayer dielectric layer ₁₀₈₃ and the second interlayer dielectric layer 136, and then the photoresist layer is exposed and developed by using the same photomask to obtain The patterned photoresist layer, and then use the patterned photoresist layer as a mask to etch and remove the first interlayer dielectric layer ₁₀₈₃ and the second interlayer dielectric layer 136 to form the opening O1 exposing the metal layer 126 and The opening O2 of the source/drain S/D is exposed, and then a metal layer (such as tungsten) is formed to fill the opening O1 and O2, and then the metal other than the opening O1 and O2 is removed to obtain the conductive plugs 140a and 140b. Then, a first metal layer M1 is formed on the semiconductor chip 100 and the logic chip 130 to form lines electrically connected to the capacitor 104 and the logic element 134 through the conductive plugs 140 a and 140 b respectively. The above-mentioned first metal layer M1 can also be formed by using the same process. In other words, after embedding the logic chip 130 , the back end of line (BEOL) of the DRAM 104 and the logic element 134 can be performed at the same time, which saves time and cost.

In the DRAM device with embedded chips in FIG. 1D , the logic chip 130 is embedded in the embedding region EM of the semiconductor chip 100, and the thickness t1 of the logic chip 130 is less than or equal to the thickness of the DRAM 104. t2. The semiconductor wafer 100 includes a first ILD layer 108 ₃ covering the capacitor 106 , the logic wafer 130 includes a second ILD layer 136 covering the logic elements 134 , and the top surface of the first ILD layer 108 ₃ is in contact with The top surface of the second ILD layer 136 is coplanar. The first metal layer M1 is formed on the first ILD layer 108 ₃ and the second ILD layer 136 . In addition, an insulating material (not shown) is interposed between the logic chip 130 and the semiconductor chip 100 so that the logic chip 130 is fixed on the first substrate 102 of the semiconductor chip 100 . The surface 132 a of the second substrate 132 is located between the bottom surface 106 b and the top surface 106 a of the capacitor 106 .

2A to 2D are schematic cross-sectional views of a manufacturing process of a DRAM device with an embedded chip according to a second embodiment of the present invention, wherein the same element symbols as those in the first embodiment are used to denote the same or Similar parts and components, and related content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be described again.

After performing the steps of FIG. 1A to FIG. 1B in the first embodiment, referring to FIG. 2A, a logic chip 200 is embedded in the embedding region EM, wherein the logic chip 200 includes a second substrate 202 and is formed on the second substrate The logic element 204 on the 202, wherein the second substrate 200 is for example a silicon substrate or an SOI substrate, and the logic element 204 is for example a MOS transistor. The logic die 200 also includes a second ILD layer 206 covering the logic elements 204 . The bottom of the embedding region EM is located on the surface 102 a of the first substrate 102 . In the second embodiment, the total thickness of the logic chip 200 is greater than 2.5 μm, including the second ILD layer 206 whose thickness is much greater than 0.5 μm, so the semiconductor chip 100 and the logic chip 200 have a large surface level difference.

Next, please refer to FIG. 2B , in order to eliminate or reduce the above-mentioned surface height difference, an insulating material 208 can be deposited on the semiconductor wafer 100 and the logic wafer 200 , and the logic wafer 200 is fixed on the first substrate 102 of the semiconductor wafer 100 at the same time. The insulating material 208 is not only located above the first ILD layer ₁₀₈₃ and the second ILD layer 206 , but also fills the gap between the logic chip 200 and the DRAM 104 in the embedding region EM. The insulating material 208 can be the same material as the second ILD layer 206, such as silicon oxide, and if a fluid material is used to form the insulating material 208, it is beneficial to reduce the thickness of the first ILD layer 108 of the semiconductor wafer 100. ₃ and the surface level difference of the second ILD layer 206 of the logic chip 200 .

Then, referring to FIG. 2C, the insulating material 208 in FIG. 2B can be etched back first to reduce the surface height difference between the semiconductor wafer 100 and the logic wafer 200, and then the surface height difference is divided by a chemical mechanical planarization method, such as oxidation Silicon CMP to remove the insulating material 208 and part of the second ILD layer 206 on the logic chip 200 to obtain the second ILD layer 206 ′ and the insulating material 208 ′ as shown in FIG. 2C . In addition, if the surface level difference is too large, before etching back the insulating material 208 in FIG. The insulating material 208 on the second ILD layer 206, and wait until the surface of the second ILD layer 206' after etching back is close to the insulating material 208 on the DRAM 104, and then remove the above-mentioned mask layer .

Afterwards, please refer to FIG. 2D , the chemical mechanical planarization method can be continued, and the grinding is stopped until the height required by the conductive plug is stopped, and then a plurality of conductive plugs 140a, 140b are formed, respectively connected to the capacitor 106 and the logic element 204, and then The first metal layer M1 is formed on the semiconductor chip 100 and the logic chip 200 ′ to form lines electrically connected to the capacitor 106 and the logic element 204 through the conductive plugs 140 a and 140 b respectively. The method of forming the conductive plugs 140a, 140b and the method of forming the first metal layer M1 can refer to the first embodiment.

In the DRAM device with embedded chips in FIG. 2D , the logic chip 200 ′ is embedded in the embedding region EM of the semiconductor chip 100 . The semiconductor wafer 100 includes a first ILD layer 108 ₃ covering the capacitors 106 , the logic wafer 200 ′ includes a second ILD layer 206 ′ covering the logic elements 204 , and the top of the first ILD layer 108 ₃ The surface is coplanar with the top surface of the second ILD layer 206'. The first metal layer M1 is formed on the first ILD layer ₁₀₈₃ and the second ILD layer 206'. In addition, an insulating material (not shown) is interposed between the logic chip 200 ′ and the semiconductor chip 100 , so that the logic chip 200 ′ is fixed on the first substrate 102 of the semiconductor chip 100 . The surface 202a of the second substrate 202 is close to the top surface 106a of the capacitor 106 .

3A to 3E are schematic cross-sectional views of a manufacturing process of a DRAM device with an embedded chip according to a third embodiment of the present invention, wherein the same element symbols as those in the first embodiment are used to denote the same or Similar parts and components, and related content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be described again.

Referring to FIG. 3A , a semiconductor chip 100 is provided, which includes a first substrate 102 and a DRAM 104 formed on the first substrate 102 . In addition, the DRAM 104 usually has a peripheral circuit 300 disposed in the peripheral circuit region. The peripheral circuit 300 has, for example, a multi-time programmable memory (MTP) and is formed in The zeroth metal layer M0 on the first ILD layer 108 ₁ is interconnected. That is to say, the first embodiment and the second embodiment may also include the above-mentioned peripheral circuit 300 .

Then, referring to FIG. 3B , in order to embed a logic chip with a total thickness much greater than 2.5 μm, the method of defining the embedding region EM in the semiconductor wafer 100 other than the dynamic random access memory 104, except etching to remove the first interlayer dielectric layer 108 ₁ and 108 ₃ , the part of the exposed first substrate 102 will be further etched away to form the groove 302 , so the bottom of the embedding region EM is below the surface 102 a of the first substrate 102 .

After that, referring to FIG. 3C , a logic chip 304 is embedded in the embedding region EM, wherein the logic chip 304 includes a second substrate 306 and a logic element 308 formed on the second substrate 306 . The logic die 304 also includes a second ILD layer 310 covering the logic elements 308 . An insulating material (not shown) is deposited on the semiconductor chip 100 and the logic chip 304 to fix the logic chip 304 in the groove 302 of the first substrate 102 of the semiconductor chip 100 . In addition to being located above the first ILD layer ₁₀₈₃ and the second ILD layer 310 , the insulating material also fills the gap S between the logic chip 304 and the DRAM 104 in the embedding region EM. In addition, if the structure has a surface level difference, the above-mentioned insulating material can be ground by chemical mechanical planarization.

Next, referring to FIG. 3D, a first conductive plug 312 connected to the capacitor 106 and a plurality of second conductive plugs 314 connected to the logic element 308 and the peripheral circuit 300 of the DRAM are formed, wherein the first The height of the two conductive plugs 314 is greater than the height of the capacitor 106 , for example. Therefore, the first conductive plug 312 and the second conductive plug 314 can be formed by different processes, for example, the first conductive plug 312 is formed first and then the second conductive plug 314 is formed; or, the second conductive plug 314 is formed first A first conductive plug 312 is then formed. Moreover, since the second conductive plugs 314 in the logic chip 304 can be fabricated together with the second conductive plugs 314 in the peripheral circuit area, there is no increase in steps or cost of the manufacturing process.

Then, referring to FIG. 3E , a first metal layer M1 is formed on the semiconductor wafer 100 and the logic wafer 304 to form electrical connections to the capacitor 106 and the logic element 308 via the first conductive plug 312 and the second conductive plug 314 respectively. At the same time, a circuit electrically connected to the peripheral circuit 300 via the second conductive plug 314 can be formed. The method of forming the first metal layer M1 can refer to the first embodiment.

In the DRAM device with embedded die in FIG. 3E , the logic die 304 is embedded in the embedding region EM of the semiconductor die 100 . The embedding area EM includes a groove 302 formed in the first substrate 102 , so the bottom surface of the second substrate 306 contacts the bottom surface of the groove 302 . The semiconductor wafer 100 includes a first ILD layer 108 ₃ covering the capacitor 106 , the logic wafer 304 includes a second ILD layer 310 covering the logic elements 308 , and the top surface of the first ILD layer 108 ₃ is in contact with The top surface of the second ILD layer 310 is coplanar. The first metal layer M1 is formed on the first ILD layer 108 ₃ and the second ILD layer 310 . In addition, an insulating material (not shown) is interposed between the logic chip 304 and the semiconductor chip 100 , so that the logic chip 304 is fixed on the first substrate 102 of the semiconductor chip 100 . In this embodiment, the surface 306 a of the second substrate 306 is close to the bottom surface 106 b of the capacitor 106 .

In summary, the present invention utilizes the height occupied by the capacitor in the DRAM in the semiconductor chip to directly embed the thin logic chip in the semiconductor chip, so that the position of the logic chip matches the height of the above-mentioned capacitor, without the need for Complicated back-end process or packaging technology completes the combination of logic chip and dynamic random access memory. If the thickness of the logic chip is much greater than the height of the capacitor, it is also possible to form a groove in the substrate, embed the logic chip in the groove, and then use the planarization method to achieve the integration of logic elements and dynamic random access in the front-end process. memory results.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: semiconductor wafer 102: first substrate 102a: surface 104: DRAM 106: capacitor 106a: top surface 106b: bottom surface 108 ₁ , 108 ₂ , 108 ₃ : first inner dielectric layer 110: insulating layer 112: conductive doped region 114: bit line contact window 116: storage node contact window 118: lower electrode layer 120: dielectric layer 122: upper electrode layer 124: polysilicon layer 126: metal layer 130, 200, 200', 304 : logic chip 132, 202, 306: second substrate 134, 204, 308: logic element 136, 206, 206', 310: second inner dielectric layer 138, 208, 208': insulating material 140a, 140b: conductive Plug 300: Peripheral circuit 302: Groove 312: First conductive plug 314: Second conductive plug BL: Bit line EM: Embedded area M0: Zeroth metal layer M1: First metal layer O1, O2: Opening S: gap S/D: source/drain STI: component isolation structure t1, t2: thickness WL: word line

1A to 1D are schematic cross-sectional views of a manufacturing process of a DRAM device with an embedded chip according to a first embodiment of the present invention. 2A to 2D are schematic cross-sectional views of a manufacturing process of a DRAM device with an embedded chip according to a second embodiment of the present invention. 3A to 3E are schematic cross-sectional views of a manufacturing process of a DRAM device with an embedded chip according to a third embodiment of the present invention.

100: semiconductor wafer

102: The first substrate

104: Dynamic Random Access Memory

106: Capacitor

106a: top surface

106b: bottom surface

108 ₃ : the first inner dielectric layer

126: metal layer

130: logic chip

132: Second substrate

134: logic element

136: second inner dielectric layer

140a, 140b: conductive plugs

EM: embedded area

M1: first metal layer

O1, O2: opening

S/D: source/drain

t1, t2: Thickness

Claims (16)

A dynamic random access memory device with an embedded chip, comprising: Semiconductor wafers, including: first substrate; a dynamic random access memory formed on the first substrate, wherein the dynamic random access memory includes a bit line and a capacitor disposed on the bit line; and an embedded region defined in the semiconductor wafer other than the DRAM, and the bottom of the embedded region is at or below the surface of the first substrate; and a logic chip embedded in the embedding region, wherein the logic chip includes a second substrate and logic elements formed on the second substrate, and the bottom of the second substrate is located on the surface of the first substrate or below the surface. The dynamic random access memory device with embedded chip as claimed in claim 1, wherein the thickness of the logic chip is less than or equal to the thickness of the dynamic random access memory. The DRAM device with an embedded chip as claimed in claim 1, wherein the second substrate of the logic chip comprises a silicon substrate or an SOI substrate. The DRAM device with an embedded chip as claimed in claim 1, wherein the semiconductor chip includes a first interlayer dielectric layer covering the capacitor, and the logic chip includes a layer covering the logic element. a second inner dielectric layer, and the top surface of the first inner dielectric layer is coplanar with the top surface of the second inner dielectric layer. The DRAM device with embedded chips as claimed in claim 4 further includes a first metal layer formed on the first ILD layer and the second ILD layer. The dynamic random access memory device with embedded chips as claimed in claim 1, further comprising an insulating material interposed between the logic chip and the semiconductor chip, so that the logic chip is fixed on the semiconductor chip on the first substrate of the wafer. The DRAM device with an embedded chip as claimed in claim 1, wherein the embedded region includes a groove formed in the first substrate, and the bottom surface of the second substrate contacts the groove bottom of the groove. The DRAM device with embedded chip as claimed in claim 7, wherein the surface of the second substrate is located between the bottom surface and the top surface of the capacitor. A method of manufacturing a dynamic random access memory device with an embedded chip, comprising: Provided is a semiconductor wafer having a dynamic random access memory, the semiconductor wafer comprising a first substrate and the dynamic random access memory formed on the first substrate, wherein the dynamic random access memory comprises bit a bit line and a capacitor disposed on the bit line; defining an embedded region in the semiconductor wafer other than the dynamic random access memory, the bottom of the embedded region being at or below the surface of the first substrate; embedding a logic die in the embedding region, wherein the logic die includes a second substrate and logic elements formed on the second substrate; depositing an insulating material on the semiconductor wafer and the logic wafer, so that the logic wafer is fixed on the first substrate of the semiconductor wafer; forming a plurality of conductive plugs respectively connected to the capacitor and the logic element; and A first metal layer is formed on the semiconductor chip and the logic chip to form lines electrically connected to the capacitor and the logic element respectively via the plurality of conductive plugs. The method for manufacturing a dynamic random access memory device with an embedded chip as described in claim 9, wherein the semiconductor chip further includes at least one first interlayer dielectric layer formed between the first substrate and the on the capacitor. The method for manufacturing a DRAM device with an embedded chip as claimed in claim 10, wherein the method for defining the embedded region includes etching and removing the first interlayer dielectric layer. The method for manufacturing a DRAM device with an embedded chip as described in claim 10, wherein the method for defining the embedded area includes: etching away the first ILD layer to expose the surface of the first substrate; and Etching and removing part of the exposed first substrate to form a groove. The method for manufacturing a DRAM device with an embedded chip as described in claim 12, wherein the step of forming a plurality of conductive plugs includes: forming a plurality of first conductive plugs connected to the capacitor; and A plurality of second conductive plugs are formed, respectively connected to the logic element and the peripheral circuit of the DRAM, wherein the height of the plurality of second conductive plugs is greater than that of the capacitor. The method of manufacturing a dynamic random access memory device with an embedded chip as claimed in claim 9, further comprising polishing the insulating material by chemical mechanical planarization before forming the plurality of conductive plugs. The method for manufacturing a dynamic random access memory device with an embedded chip as described in claim 9, wherein the logic chip further includes a second interlayer dielectric layer covering the logic element, and depositing the insulating material Later it includes: Etching back the insulating material to reduce the surface level difference between the semiconductor wafer and the logic wafer; and After the surface height difference is divided by a chemical mechanical planarization method, grinding is performed until the required height of the plurality of conductive plugs is reached. The manufacturing method of a dynamic random access memory device with an embedded chip as described in claim 15, wherein before etching back the insulating material, it further includes forming a mask layer to cover all the parts on the dynamic random access memory and exposing the insulating material on the second interlayer dielectric layer.

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