TW202326493A - Processing circuit, control system and control method - Google Patents

Abstract

A processing circuit including an attribute set circuit, a control circuit and a combination circuit is provided. The attribute set circuit sets the security attribute of a first peripheral circuit according to a first access attribute, sets the security attribute of a second peripheral circuit according to a second access attribute, and generates a third access attribute. The control circuit determines the security attribute of an input output port according to an output. In response to the operation mode of the input output port being a general purposed input output (GPIO) mode, the combination circuit generates the output according to the third access attribute. In response to the operation mode of the input output port not being the GPIO mode, the combination circuit generates the output according to the first or second access attribute.

Description

Processing circuit, control system and control method

The present invention relates to a processing circuit, in particular to a processing circuit for setting the security level of input and output ports.

In today's computer system or control system, in order to improve data security, the security level of the peripheral circuits inside the system is usually set. When a peripheral circuit has a high security level, only legitimate devices can communicate with the high security level peripheral circuit. The peripheral circuit may use at least one input and output port to communicate with external circuits. When the security level of the input and output ports is different from that of the peripheral circuit, the peripheral circuit may not be able to communicate with the external circuit normally.

An embodiment of the present invention provides a processing circuit coupled between a first peripheral circuit, a second peripheral circuit and an input/output port, and includes a property setting circuit, a control circuit and a combination circuit. The attribute setting circuit provides a first access attribute to the first peripheral circuit according to a first peripheral setting for setting the security level of the first peripheral circuit, and provides a second access attribute to the first peripheral circuit according to a second peripheral setting The second peripheral circuit is used to set the security level of the second peripheral circuit. The attribute setting circuit generates a third access attribute according to an input and output setting. The control circuit generates a control command according to a control setting, and determines the security level of the input and output ports according to an output. The combinational circuit decodes the control command to know whether the operation mode of the I/O port is a general-purpose I/O mode. When the operation mode of the I/O port is the general-purpose I/O mode, the combinational circuit generates an output according to the third access attribute. When the operation mode of the I/O port is not the general-purpose I/O mode, the combinational circuit generates an output according to the first or the second access attribute.

The present invention further provides a control system, which includes a first peripheral circuit, a second peripheral circuit, a first input and output port and a processing circuit. The first peripheral circuit receives a first access attribute. The second peripheral circuit receives a second access attribute. The processing circuit is used for determining the security level of the first input and output port. When the processing circuit sets the operation mode of the first I/O port to a general-purpose I/O mode according to a first control setting, the processing circuit determines the security level of the first I/O port according to a third access attribute. When the processing circuit sets the operation mode of the first I/O port to be other than general-purpose I/O mode according to the first control setting, the processing circuit determines the security level of the first I/O port according to the first or second access attribute.

The present invention further provides a control method for controlling the security level of an input and output port. The control method includes: setting the security level of a first peripheral circuit according to a first access attribute; according to a second access attribute, Set the security level of a second peripheral circuit; determine the operation mode of the input and output ports according to a control setting. When the operation mode of the I/O port is set as a general I/O mode, the security level of the I/O port is set according to a default access attribute. When the operation mode of the I/O port is not set to the general I/O mode, the security level of the I/O port is set according to the first or second access attribute.

The control method of the present invention can be implemented through the processing circuit or control system of the present invention, which is hardware or firmware capable of executing specific functions, and can also be recorded in a recording medium through program code and combined with specific hardware to practice. When the program code is loaded and executed by the electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a processing circuit or a control system for implementing the present invention.

In order to make the purpose, features and advantages of the present invention more comprehensible, the following specifically cites the embodiments, together with the accompanying drawings, for a detailed description. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the arrangement of each element in the embodiment is for illustration, not for limiting the present invention. In addition, the partial repetition of the symbols in the figures in the embodiments is for the purpose of simplifying the description, and does not imply the relationship between different embodiments.

Fig. 1 is a schematic diagram of the control system of the present invention. As shown in the figure, the control system 100 includes at least peripheral circuits 102 , 104 , a processing circuit 106 and an input/output port 108 . For convenience of description, FIG. 1 only shows two peripheral circuits, but it is not intended to limit the present invention. In other embodiments, the control system 100 may have more or fewer peripheral circuits. In a possible embodiment, the control system 100 is a microcontroller system.

The peripheral circuit 102 is coupled to the processing circuit 106 and receives an access attribute Peri1_SA. In this embodiment, the access attribute Peri1_SA is used to set the security level of the peripheral circuit 102 . In a possible embodiment, when the access attribute Peri1_SA is a specific potential, the peripheral circuit 102 enters a security mode. In the secure mode, the peripheral circuit 102 has a high security level. At this time, only active devices (or legitimate devices) that also have a high security level can access the peripheral circuit 102 . When the access attribute Peri1_SA is not at a specific potential, the peripheral circuit 102 operates in a non-secure mode. In the non-secure mode, the peripheral circuit 102 does not have a high security level, so any active device can access the peripheral circuit 102 .

The present invention does not limit how the peripheral circuit 102 with a high security level determines the security level of the active device. For example, when an active device 114 sends an access command to the peripheral circuit 102 through a system bus 112 and the bus 116, the peripheral circuit 102 judges whether a specific pin of the bus 116 is at a specific level (such as high level). If a specific pin of the bus bar 116 is at a specific level, it indicates that the active device 114 has a high security level. Therefore, the peripheral circuit 102 executes the access command issued by the active device 114 . However, if a specific pin of the bus 116 is not at a specific level (eg, a specific pin is at a low level), it means that the active device 114 does not have a high security level. Therefore, the peripheral circuit 102 does not execute the access command issued by the active device 114 .

The peripheral circuit 104 is coupled to the processing circuit 106 and receives an access attribute Peri2_SA. The access attribute Peri2_SA is used to set the security level of the peripheral circuit 104 . Since the characteristics of the peripheral circuit 104 are the same as those of the peripheral circuit 102 , details are not repeated here. The invention does not limit the types of the peripheral circuits 102 and 104 . In a possible embodiment, at least one of the peripheral circuits 102 and 104 is a serial peripheral interface (SPI) circuit or a pulse width modulation (PWM) circuit.

The processing circuit 106 is coupled to the peripheral circuits 102 , 104 and the I/O port 108 . In this embodiment, the processing circuit 106 accesses the peripheral circuits 102 , 104 and the input/output port 108 through the bus bars BS1 - BS3 . Taking the bus BS1 as an example, the processing circuit 106 may receive data and/or signals from the peripheral circuit 102 or provide data and/or signals to the peripheral circuit 102 through the bus BS1 . In other embodiments, the processing circuit 106 may receive data and/or signals from the input and output ports 108 through the bus BS3, and then provide the data and/or signals from the input and output ports 108 to peripheral circuits through the bus BS1. 102. In one embodiment, the processing circuit 106 may provide data and/or signals from the peripheral circuit 102 to the I/O port 108 through the bus BS3.

In this embodiment, the processing circuit 106 generates and provides the access attributes Peri1_SA and Peri2_SA to the peripheral circuits 102 and 104 for setting the security levels of the peripheral circuits 102 and 104 . The present invention does not limit how the processing circuit 106 provides the access attributes Peri1_SA and Peri2_SA to the peripheral circuits 102 and 104 . In a possible embodiment, the processing circuit 106 transmits the access attributes Peri1_SA and Peri2_SA to the peripheral circuits 102 and 104 by using two transmission lines (not shown) other than the buses BS1 and BS2 .

The present invention does not limit how the processing circuit 106 generates the access attributes Peri1_SA and Peri2_SA. In a possible embodiment, the active device 114 writes a first peripheral setting and a second peripheral setting into the processing circuit 106 through the system bus 112 and the bus 120 . In this example, the processing circuit 106 generates the access attribute Peri1_SA according to the first perimeter setting, and generates the access attribute Peri2_SA according to the second perimeter setting. The invention does not limit the type of the active device 114 . In one possible embodiment, the active device 114 is a central processing unit (CPU).

In other embodiments, the active device 114 writes a first control setting into the processing circuit 106 through the system bus 112 and the bus 120 . The processing circuit 106 sets the operation mode of the I/O port 108 according to the first control setting. In this example, the processing circuit 106 decodes the first control setting to generate a control signal SET1. The I/O port 108 operates in a general-purpose input/output (hereinafter referred to as GPIO) mode or a multi-function pin (hereinafter referred to as MFP) mode according to the control signal SET1 .

In GPIO mode, the I/O port 108 may be directly operated by the active device 114 . The active device 114 directly controls related functions of the I/O port 108 through the processing circuit 106 . For example, the active device 114 may output a high level or a low level by setting the I/O port 108 in an output mode, or read an input in an input mode. The output level of port 108.

When the I/O port 108 is set to the GPIO mode, the processing circuit 106 may determine the security level of the I/O port 108 according to an I/O setting provided by the active device 114 . When the processing circuit 106 knows that the I/O port 108 has a high security level according to the I/O setting, the processing circuit 106 identifies whether the access from the system bus 112 is a legitimate access. At this time, only legitimate devices (with a high security level) can access the I/O port 108 . When the I/O port 108 does not have a high security level, any active device can access the I/O port 108 .

When the I/O port 108 operates in the MFP mode, the processing circuit 106 may determine the security attribute of the I/O port 108 according to the access attribute Peri1_SA or Peri2_SA. For example, when the processing circuit 106 learns that the active device 114 allocates the I/O port 108 to the peripheral circuit 102 , the processing circuit 106 determines the security level of the I/O port 108 according to the access attribute Peri1_SA. At this time, the security level of the I/O port 108 is the same as that of the peripheral circuit 102 . When the active device 114 allocates the I/O port 108 to the peripheral circuit 104 , the processing circuit 106 determines the security level of the I/O port 108 according to the access attribute Peri2_SA. In this example, the security level of the I/O port 108 is the same as that of the peripheral circuit 104 .

The I/O port 108 serves as an interface for the active device 114 to communicate with an external circuit (eg, 122 ). In this embodiment, the processing circuit 106 communicates with the I/O port 108 through the bus BS3. In this example, the processing circuit 106 may provide signals from the peripheral circuits 102, 104 or the active device 114 to the I/O port 108, or transmit signals from the I/O port 108 to the peripheral circuits 102, 104 or the active device 108. Formula device 114. The present invention does not limit the circuit structure of the I/O port 108 . In a possible embodiment, the I/O port 108 includes many circuits, such as a pull-high circuit and/or a pull-low circuit. In some embodiments, the I/O port 108 has a pin for coupling to an external circuit (such as 122 ).

The present invention does not limit the number of input and output ports of the control system 100 . In this embodiment, the control system 100 further includes input and output ports 109 - 111 . The input and output ports 109 - 111 are coupled to the processing circuit 106 . The processing circuit 106 generates control signals SET2 - SET4 according to a second control setting, a third control setting, and a fourth control setting provided by the active device 114 . The input and output ports 109-111 operate in GPIO mode or MFP mode according to the control signals SET2-SET4. Since the characteristics of the input and output ports 109 ˜ 111 are the same as those of the input and output port 108 , details are not repeated here. In some embodiments, the processing circuit 106 communicates with the input and output ports 109 - 111 through the bus bars BS4 - BS6 . In other embodiments, the active device 114 communicates with external circuits (such as 124 and 126 ) through the input and output ports 109 - 111 .

In other embodiments, the input and output ports 108 - 111 may be divided into the same or different groups. For example, assume that the input and output ports 108˜111 are divided into the same group. In this example, the processing circuit 106 determines the security levels of the input and output ports 108 - 111 according to the same input and output settings. In another embodiment, if the input and output ports 108-111 belong to four groups, the processing circuit 106 determines the security level of the input and output ports 108-111 according to different input and output settings. The present invention does not limit the number of input and output ports of each group. In a possible embodiment, each group has sixteen sets of input and output ports.

In other embodiments, when an I/O port operates in the MFP mode, the processing circuit 106 learns the function of the I/O port according to a multi-function setting notified by the active device 114 . The present invention does not limit the number of functions of the input and output ports. For the convenience of description, it is assumed that each I/O port may provide an input function, an output function, a pull-up function and a pull-down function. Taking the I/O port 108 as an example, the I/O port 108 may provide at least one of an input function, an output function, a pull-up function, and a pull-down function. When the active device 114 commands the I/O port 108 to provide an input function, the I/O port 108 receives signals and/or data from the external circuit 122 . When the active device 114 commands the I/O port 108 to provide an output function, the I/O port 108 outputs signals and/or data to the external circuit 122 . When the active device 114 commands the I/O port 108 to provide a pull-up function, a pull-up circuit (not shown) in the I/O port 108 is enabled to output a high level. When the active device 114 commands the I/O port 108 to provide a pull-down function, a pull-down circuit (not shown) in the I/O port 108 is enabled to output a low level.

Figure 2 shows a possible embodiment of the processing circuit of the present invention. In this embodiment, the processing circuit 200 includes a property setting circuit 210 , a combination circuit 220 and a control circuit 230 . The attribute setting circuit 210 receives and stores the peripheral settings S1˜SM. The peripheral settings S1~SM may be provided by an active device (such as 114). The attribute setting circuit 210 generates access attributes Peri1_SA~PeriM_SA according to the peripheral settings S1~SM, for setting the security levels of M peripheral circuits, wherein M is a positive integer. In a possible embodiment, the attribute setting circuit 210 outputs the access attributes Peri1_SA˜PeriM_SA to the combining circuit 220 in parallel. The present invention does not limit the architecture of the property setting circuit 210 . In a possible embodiment, the attribute setting circuit 210 is a security attribute unit (SAU).

In this embodiment, the attribute setting circuit 210 further receives and stores the input and output settings IOG1˜IOGX. The input and output settings IOG1~IOGX may be provided by an active device (such as 114). The attribute setting circuit 210 sets IOG1˜IOGX according to the input and output to generate access attributes IOG1_SA˜IOGX_SA for setting the security levels of the input and output ports of X groups, where X is a positive integer.

Take Figure 1 as an example, when the input and output ports 108~111 are set to GPIO mode, and the input and output ports 108~111 are divided into the same group. In this example, the attribute setting circuit 210 may generate the access attribute IOG1_SA according to the input and output setting IOG1. In this example, the input and output ports 108-111 have the same security level. In other embodiments, it is assumed that the input and output ports 108 - 111 are set to the GPIO mode, and the input and output ports 108 - 111 respectively belong to four groups. In this example, the attribute setting circuit 210 may generate the access attributes IOG1_SA˜IOG4_SA according to the input and output settings IOG1˜IOG4.

The control circuit 230 has register groups 231 - 23N. In this embodiment, the register groups 231˜23N correspond to N input and output ports, where N is a positive integer. The register groups 231˜23N respectively store the control settings IO1˜ION. In a possible embodiment, the control settings IO1˜ION are provided by an active device (such as 114).

In addition, the control circuit 230 generates control commands SET1 ˜ SETN according to the control settings IO1 ˜ ION for setting the operation modes of the N input and output ports and the functions of the input and output ports. The input and output ports enter GPIO mode or MFP mode according to corresponding control commands. In the MFP mode, the input and output ports provide corresponding functions according to corresponding control commands, such as at least one of a pull-up function, a pull-down function, an input function and an output function.

In some embodiments, the control circuit 230 generates a control command IOM1-IOMN according to the control settings IO1-ION. In this example, the control commands IOM1-IOMN include the MFP setting value IO[1...N]MFP[1...K] and the IO mode setting value IO[1...N]GPIO. The MFP setting value IO[1...N]MFP[1...K] is used to indicate the corresponding relationship between the input and output ports and peripheral circuits and the functions of the input and output ports. The IO mode setting value IO[1...N]GPIO is used to indicate the operation mode of the input and output ports, GPIO mode or MFP mode.

The combination circuit 220 generates outputs IO1_SA˜ION_SA according to the MFP setting value IO[1…N]MFP[1…K] and the IO mode setting value IO[1…N]GPIO. The control circuit 230 learns the security levels of the N input and output ports according to the outputs IO1_SA˜ION_SA. For example, when the combinational circuit 220 knows that an input and output port (such as the input and output port 108 in FIG. 1 ) is set to the MFP mode according to the IO mode setting value IO[1...N]GPIO, and knows that the input and output port When the port is assigned to a peripheral circuit (such as the peripheral circuit 102 in FIG. 1 ), the combining circuit 220 may set the output IO1_SA according to the access attribute of the peripheral circuit (such as Peri1_SA in FIG. 1 ). When an I/O port (such as the I/O port 108 in FIG. 1 ) is set to the GPIO mode, the combination circuit 220 generates an output IO1_SA according to one of the IOG1-IOGX set.

The control circuit 230 defines the security levels of the N input and output ports according to the outputs IO1_SA˜ION_SA. In some embodiments, the control circuit 230 has N pins for respectively receiving the outputs IO1_SA˜ION_SA. In this example, the control circuit 230 judges the voltage levels of the N pins to determine the security level of the input and output ports 108 - 111 . For example, when the output IO1_SA is equal to a specific level, the control circuit 230 defines an I/O port with a high security level. When the output IO1_SA is not equal to a specific level, the control circuit 230 defines that the I/O port does not have a high security level.

In other embodiments, the combining circuit 220 is more responsible for the data transmission between each peripheral circuit and the corresponding input and output ports. Taking FIG. 1 as an example, the combined circuit 220 may serve as a bridge between the peripheral circuit 102 and the input/output port 108 .

Fig. 3 is another schematic diagram of the processing circuit of the present invention. As shown in the figure, the processing circuit 300 includes a property setting circuit 310 , a combination circuit 320 and a control circuit 330 . In this embodiment, the attribute setting circuit 310 stores the peripheral settings S1˜SM and the input and output settings IOG1˜IOGX. Since the characteristics of the attribute setting circuit 310 are similar to those of the attribute setting circuit 210 in FIG. 2 , details are omitted here.

The control circuit 330 decodes the control settings IO1~ION to generate the control commands SET1~SETN, the IO mode setting value IO[1...N]GPIO and the MFP setting value IO[1...N]MFP[1...K] to the combination circuit 320 . Since the characteristics of the control circuit 330 are similar to those of the control circuit 230 in FIG. 2 , details are omitted here.

The combining circuit 320 includes a decoding circuit 321 and a control circuit 322 . The control circuit 322 knows the function of each input and output port operating in the MFP mode according to the MFP setting value IO[1...N]MFP[1...K]. In some embodiments, the control circuit 322 decodes the MFP setting value IO[1...N]MFP[1...K] to generate another setting value IO[1...N]_Peri[1...K] for the decoding circuit 321. The control circuit 322 can serve as a bridge between peripheral circuits and input/output ports.

The decoding circuit 321 knows the corresponding relationship between the input and output ports and peripheral circuits according to the set value IO[1...N]_Peri[1...K], and generates the output IOA_SA~ION_SA to the control circuit 330, so that the security of the input and output ports The level is the same as the security level of the corresponding peripheral circuit. In this embodiment, the decoding circuit 321 is an input output security attribute decoder (input output security attribute decoder). The input and output attribute decoder receives and decodes the access attribute IOG1_SA~IOGX_SA, the access attribute Peri1_SA~PeriM_SA, the setting value IO[1…N]_Peri[1…K] and the IO mode setting value IO[1…N]GPIO, using to generate output IOA_SA~ION_SA.

In some embodiments, the decoding rule of the input-output attribute decoder is that when an input-output port is set to GPIO mode, the access attribute of the input-output port is the same as the access attribute of the group to which the input-output port belongs (that is, one of the access attributes IOG1_SA~IOGX_SA). When an I/O port is set to the MFP mode, the access attribute of the I/O port is the same as that of a corresponding peripheral circuit.

In Figure 1 as an example, assume that the control system 100 has two peripheral circuits 102 and 104 (ie M=2), four input and output ports 108~111 (ie N=4), and each input and output port can provide four different MFP function (ie K=4). In this example, the attribute setting circuit 321 generates the access attributes Peri1_SA and Peri2_SA according to the surrounding settings S1 and S2. The attribute setting circuit 321 generates access attributes Peri1_SA and Peri2_SA according to the peripheral settings S1 and S2. The attribute setting circuit 321 also sets the IOG1 according to the input and output to generate the access attribute IOG1_SA.

The control circuit 330 generates the MFP set value IO[1...4]MFP[1...K] and the IO mode set value IO[1...4]GPIO according to the control settings IO1-IO4. Suppose, the control circuit 330 sets the input and output ports 108 to 110 as the MFP mode according to the control settings IO1 to IO4 , and sets the input and output port 111 as the GPIO mode. In this example, the control circuit 330 knows that the input and output port 108 is assigned to the peripheral circuit 102 according to the control settings IO1˜IO3, and the input and output ports 109 and 110 are assigned to the peripheral circuit 102, wherein the input and output port 108 is assigned to the peripheral circuit 102. It is required to provide a pull-up function, the I/O port 109 is required to provide an input function, and the I/O port 110 is required to provide an output function.

Therefore, the control circuit 330 sets the I/O port 108 to enter the MFP mode through the control command SET1 and provides a pull-up function. In this example, the control circuit 330 sets the I/O port 109 to enter the MFP mode through the control command SET2 and provides an input function. The control circuit 330 sets the input and output ports 110 to enter the MFP mode through the control command SET3 and provides an output function. In addition, the control circuit 330 further sets the input/output port 111 to enter the GPIO mode through the control command SET4. In other embodiments, at least one of the I/O ports 108-110 is required to provide multiple functions, such as a pull-up function and an input function.

In some embodiments, since the I/O port 108 is allocated to the peripheral circuit 102 , the decoding circuit 321 generates the output IO1_SA according to the access attribute Peri1_SA of the peripheral circuit 102 . The control circuit 330 defines the security level of the I/O port 108 according to the output IO1_SA. Therefore, the security level of the I/O port 108 is the same as that of the peripheral circuit 102 . In addition, since the input and output ports 109 and 110 are allocated to the peripheral circuit 104 , the decoding circuit 321 generates outputs IO2_SA and IO3_SA according to the access attribute Peri2_SA of the peripheral circuit 104 . The control circuit 330 defines the security levels of the input and output ports 109 and 110 according to the outputs IO2_SA and IO3_SA. Therefore, the security level of the input and output ports 109 and 110 is the same as that of the peripheral circuit 104 . In addition, since the input/output port 111 enters the GPIO mode, the decoding circuit 321 generates the output IO4_SA according to the access attribute IOG1_SA. The control circuit 330 defines the security level of the I/O port 111 according to the output IO4_SA.

Fig. 4 is a schematic diagram of the decoding circuit of the present invention. In this embodiment, the decoding circuit 400 includes decoding units DU1˜DUN. Each of the decoding units DU1˜DUN is used for setting the access attribute of an input and output port. Taking FIG. 1 as an example, the decoding unit DU1 is used to set the access attribute of the I/O port 108 , and the decoding unit DU2 is used to set the access attribute of the I/O port 109 . The present invention does not limit the number of decoding units. In a possible embodiment, the number of decoding units is the same as the number of input and output ports. Since the decoding units DU1˜DUN have the same characteristics, only the characteristics of the decoding unit DU1 will be described below.

The decoding unit DU1 includes multiplexers 411 and 412 . The multiplexer 411 selects one of the access attributes Peri1_SA, Peri3_SA, Peri5_SA and Peri7_SA as the output OUT according to the MFP setting value MFP[K]. In this embodiment, the MFP setting value MFP[K] is used to represent the number of functions of the input and output ports 108 . For example, when K=4, it means that the I/O port 108 provides four functions.

In some embodiments, since the input and output ports 108 may be assigned to four peripheral circuits, such as the first peripheral circuit, the third peripheral circuit, the fifth peripheral circuit and the seventh peripheral circuit, the multiplexer 411 receives the first and the second peripheral circuits. 3. Access attributes of the fifth and seventh peripheral circuits, such as Peri1_SA, Peri3_SA, Peri5_SA and Peri7_SA. In this example, when K=1, the multiplexer will access attribute Peri1_SA as output OUT. When K=2, the multiplexer will access attribute Peri3_SA as output OUT. When K=3, the multiplexer will access attribute Peri5_SA as output OUT. When K=4, the multiplexer will access attribute Peri7_SA as output OUT.

The multiplexer 412 receives the access attribute IOG1_SA and the output OUT, and uses one of the access attribute IOG1_SA and the output OUT as the output IO1_SA according to the mode information IO[1] GPIO. In this embodiment, the mode information IO[1] GPIO is used to indicate whether the pin of the I/O port 108 is set as a general-purpose I/O pin. In this example, when the value of the mode information IO[1] GPIO is 1, it means that the pin of the input/output port 108 is set as a general-purpose input/output pin. Therefore, the multiplexer 412 will access the attribute IOG1_SA as the output IO1_SA. When the mode information IO[1] GPIO is 0, it means that the pin of the I/O port 108 is not used as a general-purpose I/O pin, and the multiplexer 412 outputs OUT as the output IO1_SA.

Fig. 5 is a schematic flow chart of the control method of the present invention. The control method of the present invention is applied in a control system, and the control system has a plurality of peripheral circuits and at least one input and output port. First, the security levels of all peripheral circuits are set (step S511). In a possible embodiment, a central processing unit determines the security level of each peripheral circuit according to a security attribute code. When the peripheral circuit receives a specific level, the peripheral circuit enters into a safe mode. In secure mode, only legitimate external circuits can access peripheral devices. When the peripheral circuit does not receive a specific level, the peripheral circuit does not enter a safe mode. At this point, any external circuit can access the peripheral device.

According to a control setting, an operation mode of an input and output port is set (step S512). In a possible embodiment, the control setting is provided by a central processing unit. The CPU predetermines the operation mode of the I/O port, such as a GPIO mode or an MFP mode.

Determine whether the operation mode of the I/O port is set to a GPIO mode (step S513). When the operation mode of the I/O port is set as a GPIO mode, the security level of the I/O port is determined according to a default access attribute (step S514). In a possible embodiment, step S514 sets security levels of different input and output ports in the same group according to the same default access attribute. In another possible embodiment, step S514 determines the security levels of the input and output ports in different groups according to different preset access attributes.

However, when the operation mode of the I/O port is not set as the GPIO mode, the security level of the I/O port is set according to the access attribute of the corresponding peripheral circuit (step S515 ). In a possible embodiment, step 515 determines whether the I/O port corresponds to the first or the second peripheral circuit. When the input and output ports correspond to the first peripheral circuit, step S515 determines the security level of the input and output ports according to the access attribute of the first peripheral circuit. At this time, the security level of the input and output ports is the same as the security level of the first peripheral circuit. When the input and output ports correspond to the second peripheral circuit, step S515 determines the security level of the input and output ports according to the access attribute of the second peripheral circuit. At this time, the security level of the input and output ports is the same as that of the second peripheral circuit. In this embodiment, when the input and output ports operate in the MFP mode, the security levels of the input and output ports are consistent with those of the peripheral circuits, thus improving the security of the peripheral circuits.

The control method of the present invention, or specific forms or parts thereof, may exist in the form of program codes. The code may be stored on a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (such as a computer-readable) storage medium, or a computer program product without limitation in an external form, wherein, When the program code is loaded and executed by a machine, such as a computer, the machine becomes a control system or processing circuit for participating in the present invention. Code may also be sent via some transmission medium, such as wire or cable, optical fiber, or any type of transmission in which, when the code is received, loaded, and executed by a machine, such as a computer, the machine becomes the one used to participate in this Invented control system or processing circuit. When implemented on a general-purpose processing unit, the code combines with the processing unit to provide a unique device that operates similarly to application-specific logic circuits.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood by those of ordinary skill in the art to which this invention belongs. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice. Although terms such as 'first' and 'second' may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device or method described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100: Control system 102, 104: Peripheral circuits 106, 200, 300: processing circuit 108~111: Input and output ports Peri1_SA~PeriM_SA, IOG1_SA~IOGX_SA: access attribute IO1_SA~ION_SA: output BS1~BS6, 116, 118, 120: busbar S1~SM: Peripheral settings IOG1~IOGX: Input and output settings 112: System bus 114: Active device IO1~ION: Control setting 122, 124, 126: external circuit IOM1~IOMN: Control command IO[1…N]GPIO: IO mode setting value IO[1…N]MFP[1…K], IO[1…N]_Peri[1…K]: MFP setting value SET1~SETN: control signal 210, 310: attribute setting circuit 220, 320: combination circuit 321: decoding circuit 230, 322, 340: control circuit 231~23N: Register group 400: decoding circuit DU1~DUN: decoding unit 411, 412: multiplexer S511~S515: steps

Fig. 1 is a schematic diagram of the control system of the present invention. Figure 2 shows a possible embodiment of the processing circuit of the present invention. Fig. 3 is another schematic diagram of the processing circuit of the present invention. Fig. 4 is a schematic diagram of the decoding circuit of the present invention. Fig. 5 is a schematic flow chart of the control method of the present invention.

200: processing circuit

Peri1_SA~PeriM_SA, IOG1_SA~IOGX_SA, IO1_SA~ION_SA: access attribute

S1~SM: Peripheral settings

IOG1~IOGX: Input and output settings

IOM1~IOMN: Control command

IO[1...N]GPIO: mode information

IO[1...N]MFP[1...K]: pairing information

210: attribute setting circuit

220: combination circuit

230: control circuit

231~23N: Register group

SET1~SETN: control signal

IO1~ION: Control setting

Claims (10)

A processing circuit coupled between a first peripheral circuit, a second peripheral circuit and a first input/output port, and includes: An attribute setting circuit, according to a first peripheral setting, provides a first access attribute to the first peripheral circuit for setting the security level of the first peripheral circuit, and provides a second storage according to a second peripheral setting acquiring an attribute to the second peripheral circuit for setting the security level of the second peripheral circuit, and generating a third access attribute according to a first input and output setting; A first control circuit generates a first control command according to a control setting, and determines the security level of the first input and output port according to a first output; and A combined circuit, decoding the first control command, to know whether the operation mode of the first input-output port is a general-purpose input-output mode; in: When the operation mode of the first I/O port is the general-purpose I/O mode, the combination circuit generates the first output according to the third access attribute; When the operation mode of the first I/O port is not the general-purpose I/O mode, the combination circuit generates the first output according to the first or second access attribute. The processing circuit of claim 1, wherein when the operation mode of the first I/O port is the general-purpose I/O mode, the combined circuit sets the level of a pin according to the third access attribute, and the first control The circuit determines the security level of the first input and output port according to the level of the pin. Such as the processing circuit of claim 1, wherein: When the operation mode of the first I/O port is not the general-purpose I/O mode, the combination circuit decodes the first control command to know whether the first I/O port corresponds to the first peripheral circuit or the second Peripheral circuits; When the first I/O port corresponds to the first peripheral circuit, the combining circuit takes the first access attribute as the first output; and When the first I/O port corresponds to the second peripheral circuit, the combining circuit takes the second access attribute as the first output. Such as the processing circuit of claim 3, wherein: When the first I/O port corresponds to the first peripheral circuit, the security level of the first I/O port is the same as the security level of the first peripheral circuit; When the first I/O port corresponds to the second peripheral circuit, the security level of the first I/O port is the same as that of the second peripheral circuit. The processing circuit according to claim 1, wherein the combined circuit includes: a second control circuit, decoding the first control command to generate a set value; and A decoding circuit, receiving the set value; Wherein, the second control circuit serves as a bridge between the first peripheral circuit and the first I/O port, and the first control circuit serves as a bridge between the first I/O port and an active device. The processing circuit according to claim 5, wherein the decoding circuit decodes the first control command to know whether the operation mode of the first I/O port is the general-purpose I/O mode. A control system comprising: a first peripheral circuit, receiving a first access attribute; a second peripheral circuit, receiving a second access attribute; a first input and output port; and a processing circuit for determining the security level of the first input and output port; in: When the processing circuit sets the operation mode of the first I/O port to a general-purpose I/O mode according to a first control setting, the processing circuit determines the security level of the first I/O port according to a third access attribute ; When the processing circuit sets the operation mode of the first I/O port to be other than the general-purpose I/O mode according to the first control setting, the processing circuit determines the first I/O port according to the first or second access attribute The security level of the port. As the control system of claim 7, wherein the processing circuit includes: An attribute setting circuit, which provides the first access attribute to the first peripheral circuit according to the first peripheral setting to set the security level of the first peripheral circuit, and provides the second storage according to the second peripheral setting. Acquiring attributes to the second peripheral circuit; used to set the security level of the second peripheral circuit, and generate the third access attribute according to the first input and output setting; A first control circuit, according to the first control setting, generates a control signal for setting the operation mode of the input and output port; and A combination circuit decodes the control command to know whether the operation mode of the I/O port is the general-purpose I/O mode. As the control system of claim 8, wherein the combined circuit includes: A second control circuit decodes the control command to obtain a set value, and according to the set value, establishes a transmission path between the first peripheral circuit and the first input-output port, or establishes a transmission path between the first peripheral circuit and the first input-output port, or establishes a transmission path between the second The transmission path is established between the peripheral circuit and the first I/O port. A control method for controlling the security level of an input and output port, the control method comprising: setting a security level of a first peripheral circuit according to a first access attribute; setting a security level of a second peripheral circuit according to a second access attribute; Determine the operation mode of the input and output port according to a control setting; When the operation mode of the I/O port is set as a general-purpose I/O mode, setting the security level of the I/O port according to a default access attribute; and When the operation mode of the I/O port is not set as the general-purpose I/O mode; according to the first or second access attribute, the security level of the I/O port is set.

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