TW202324693A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

Description

Semiconductor element and its manufacturing method

This application claims priority to U.S. Patent Application Nos. 17/541,817 and 17/544,410 (i.e., with priority dates of "December 3, 2021" and "December 7, 2021"), the content of which is It is incorporated herein by reference in its entirety.

The present disclosure relates to a semiconductor device and a manufacturing method thereof. In particular, it relates to a semiconductor device with buried word lines and a method of manufacturing the same.

In a dynamic random access memory (DRAM) device, multiple word lines are used to find the addresses of multiple memory cells. Interference between wordlines in different memory cells should be avoided to reduce storage node leakage (such as junction leakage and sub-threshold leakage) and preserve writes to cell capacitors charge.

As DRAM devices become highly integrated, it becomes more difficult to connect a word line (which can be denoted as an active word line) in a memory cell with another word line in an adjacent memory cell. The line (which can be represented as a passing word line) is insulated. When a pass word line is turned on, the junction leakage current can be accelerated by trap-assisted tunneling, which is generated by an internal electric field.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element includes a base with a surface; and a first dielectric layer extending from the surface of the base into the base. The semiconductor element also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and extending through the substrate The first dielectric layer and the second dielectric layer are separated from the substrate.

Another embodiment of the disclosure provides a semiconductor device. The semiconductor element includes a substrate with a surface; a first dielectric layer extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and passing through the first dielectric layer. layer is separated from the substrate. The semiconductor element also includes a second dielectric layer extending from the surface of the base into the base; and a second conductive layer disposed in the base and separated from the base by the second dielectric layer separated. The first dielectric layer and the second dielectric layer have different thicknesses.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes forming a first recess in a first dielectric layer in a substrate; and forming a second recess spaced apart from the first recess and in the substrate. The preparation method also includes disposing a protective layer on the base to cover the second recess; and disposing a second dielectric layer on the first dielectric layer.

By forming two dielectric layers between the conductive layer and the substrate, the effective electric field can be reduced and thus the junction leakage current can be reduced. Therefore, interference between word lines in different memory cells can be avoided and the charge written to the cell capacitor can be preserved.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

The various embodiments (or examples) of the disclosure depicted in the drawings are now described using specific language. It should be understood that no limitation of the scope of the present disclosure is meant here. Any changes or modifications of the described embodiments, and any further application of the principles described in this document, are considered to be within the ordinary skill of the art to which this disclosure pertains. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same element number.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 1 may include a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell). As shown in FIG. 1 , in some embodiments, a semiconductor device 1 may include a substrate 10 , diffusion regions 10 a , 10 b , dielectric layers 11 , 13 , conductive layers 12 , 14 and an isolation layer 15 .

In some embodiments, conductive layers 12 and 14 may serve as word lines. For example, conductive layers 12 and 14 may be used with multiple bit lines, such as bit line 16 shown in FIG. 1, to address multiple memory cells. For example, the conductive layer 14 can be used as a gate electrode of a transistor in a memory cell. The diffusion region 10a and the diffusion region 10b can be regarded as a drain region and a source region of the transistor. Diffusion region 10a may be coupled to a capacitor (eg, capacitor 23 shown in FIG. 1 ), and diffusion region 10b may be coupled to a bit line (eg, bit line 16 shown in FIG. 1 ). The transistor retains charge in the capacitor. Similarly, conductive layer 12 can be used as a gate electrode of a transistor in another memory cell, and the transistor can hold charge in another capacitor (not shown).

In some embodiments, the conductive layer 12 and the conductive layer 14 can be configured to find addresses of different memory cells. In some embodiments, conductive layer 12 may include a pass word line, and conductive layer 14 may include an active word line. As used herein, the term "active wordline" means a wordline configured to receive a voltage to seek the address of a memory cell; and the term "passing wordline" " denotes a word line configured to receive a voltage to find the address of a neighboring memory cell.

In some embodiments, conductive layer 12 may be a pass wordline in one memory cell, but become an active wordline in another memory cell. In some embodiments, conductive layer 14 can be an active word line in a memory cell, but becomes a pass word line in yet another memory cell.

In some embodiments, conductive layer 12 and conductive layer 14 may be configured to receive different voltages. For example, conductive layer 12 may be configured to receive a negative voltage, and conductive layer 14 may be configured to receive a positive voltage, or vice versa.

In some embodiments, the semiconductor device 1 may further include a bit line 16 , isolation layers 17 , 18 , 20 , 22 , a capacitor contact plug 19 , a capacitor contact pad 21 and a capacitor 23 .

In some embodiments, the substrate 10 may include a surface 101 and a surface 102 , and the surface 102 is disposed opposite to the surface 101 . In some embodiments, the surface 101 may be an active surface of the substrate 10 , and the surface 102 may be a rear surface of the substrate 10 .

In some embodiments, substrate 10 may include, for example, Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, In, InAs, InP, or other Group IV-IV, III-V, or II-VI semiconductors Material. In some other embodiments, the substrate 10 may include a layered semiconductor, such as silicon/silicon germanium, silicon-on-insulator, or silicon-germanium-on-insulator.

In some embodiments, the diffusion region 10 a and the diffusion region 10 b can be disposed on or in the substrate 10 . In some embodiments, the diffusion region 10 a and the diffusion region 10 b can be disposed on or close to the surface 101 of the substrate 10 . In some embodiments, the diffusion region 10 a and the diffusion region 10 b may be disposed at opposite sides of the conductive layer 14 .

In some embodiments, the diffusion region 10 a and the diffusion region 10 b can be doped with an N-type dopant, such as P, As or Sb. In some other embodiments, the diffusion region 10a and the diffusion region 10b may be doped with a P-type dopant, such as B or In.

In some embodiments, the diffusion region 10a and the diffusion region 10b may be doped with a dopant having the same conductivity type or a plurality of impurity ions. In some embodiments, the diffusion region 10 a and the diffusion region 10 b may be doped with dopants having different conductivity types or a plurality of impurity ions.

In some embodiments, a dielectric layer 11 may be disposed in the substrate 10 . In some embodiments, the dielectric layer 11 may be a part of an insulating structure, such as a shallow trench isolation (STI) structure. In some embodiments, the dielectric layer 11 may be disposed in an STI trench of the substrate 10 .

In some embodiments, the dielectric layer 11 may include a double-layer structure. For example, the dielectric layer 11 may include a sub-layer 11a and a sub-layer 11b. For example, an interface or a boundary between sub-layer 11a and sub-layer 11b can be seen.

In some embodiments, the sub-layer 11a may include a dielectric layer, such as an oxide film. The sub-layer 11a may extend from the surface 101 of the substrate 10 into the substrate 10 . The sub-layer 11a may partially pass through the substrate 10 . In some embodiments, the sub-layer 11a may have a surface (eg, an upper surface) 11a1 substantially coplanar with the surface 101 of the substrate 10 .

In some embodiments, the sub-layer 11b includes a dielectric layer, such as an oxide film. The sub-layer 11b may extend from the surface 101 of the substrate 10 into the substrate 10 . The sub-layer 11b may partially pass through the substrate 10 . In some embodiments, the sub-layer 11b may have a surface (eg, an upper surface) 11b1 substantially coplanar with the surface 101 of the substrate 10 . In some embodiments, the surface 11b1 of the sub-layer 11b may be substantially coplanar with the surface 11a1 of the sub-layer 11a.

In some embodiments, the sub-layer 11a is disposed between the sub-layer 11a and the substrate 10 . In some embodiments, sub-layer 11 b is disposed between sub-layer 11 a and conductive layer 12 . In some embodiments, the sub-layer 11a may define a recess, and the sub-layer 11b may be disposed in the recess.

In some embodiments, each of sub-layer 11a and sub-layer 11b may include a low dielectric constant material, such as a fluorine-doped silicon dioxide (FSG), organosilicate glass (OSG), carbon-doped oxide (CDO ), porous silica, etc. In some embodiments, each of sub-layer 11a and sub-layer 11b may be a dielectric material having a dielectric constant lower than that of silicon dioxide, or having a dielectric constant lower than about 4.0. A dielectric constant of a dielectric material.

In some embodiments, the sub-layer 11a and the sub-layer 11b may have different materials. In some embodiments, the sub-layer 11a and the sub-layer 11b may have the same material, and their fabrication techniques include different steps. For example, the fabrication technique of the sub-layer 11a may include a chemical vapor deposition (CVD) process, and the fabrication technique of the sub-layer 11b may include an atomic layer deposition (ALD) process. For example, sub-layer 11a and sub-layer 11b may comprise different steps.

In some embodiments, the sub-layer 11a and the sub-layer 11b may have different densities, such as different particle densities. For example, a density of the sub-layer 11a may be lower than a density of the sub-layer 11b. A density of the sub-layer 11b may be higher than a density of the sub-layer 11a. For example, sub-layer 11b may be denser than sub-layer 11a. For example, the surface 11b1 of the sub-layer 11b may be denser than the surface 11a1 of the sub-layer 11a.

In some embodiments, a conductive layer 12 may be disposed in the substrate 10 . In some embodiments, the conductive layer 12 may be disposed in the dielectric layer 11 . In some embodiments, the dielectric layer 11 (including the sub-layer 11 a and the sub-layer 11 b ) may define a recess, and the conductive layer 12 may be disposed in the recess. In some embodiments, conductive layer 12 may be surrounded by sub-layer 11b, and further surrounded by sub-layer 11a. In some embodiments, the conductive layer 12 may be separated from the substrate 10 by the sub-layer 10a and the sub-layer 10b. In some embodiments, the conductive layer 12 may have a surface (eg, an upper surface) 121 separated from the surface 101 of the substrate 10 . For example, the surface 121 of the conductive layer 12 may not be coplanar with the surface 101 of the substrate 10 . In some embodiments, the surface 121 of the conductive layer 12 may be separated from the surface 11b1 of the sub-layer 11b and the surface 11a1 of the sub-layer 11a. For example, the surface 121 of the conductive layer 12 may not be coplanar with the surface 11b1 of the sub-layer 11b and the surface 11a1 of the sub-layer 11a.

In some embodiments, the conductive layer 12 may include a single layer of metal, a metal composite, or multiple layers of conductive materials. In some embodiments, the conductive layer 12 may include polysilicon (poly-Si), TiN, WN, or the like.

In some embodiments, a dielectric layer 13 may be disposed in the substrate 10 . In some embodiments, the dielectric layer 13 may include an oxide film. The dielectric layer 13 may extend from the surface 101 of the substrate 10 into the substrate 10 . The dielectric layer 13 may pass through the substrate 10 . In some embodiments, the dielectric layer 13 may have a surface 131 (eg, an upper surface), which is substantially coplanar with the surface 101 of the substrate 10 .

In some embodiments, the dielectric layer 13 may include a low dielectric constant material, such as a fluorine-doped silicon dioxide (FSG), organosilicate glass (OSG), carbon-doped oxide (CDO), porous dioxide Silicon etc. In some embodiments, dielectric layer 13 may include a dielectric material having a dielectric constant lower than that of silicon dioxide, or having a dielectric constant lower than about 4.0 of a dielectric material.

In some embodiments, the dielectric layer 13 may have a material that is different from the material of the sub-layer 11a and the sub-layer 11b. In some embodiments, the dielectric layer 13 , the sub-layer 11a and the sub-layer 11b may have the same material, and their fabrication techniques include different steps. For example, the fabrication technique of the dielectric layer 13 may include a thermal oxidation step. In some embodiments, the dielectric layer 13 is formed after the sub-layer 11a is formed and the sub-layer 11b is formed.

In some embodiments, the dielectric layer 13 , the sub-layer 11 a and the sub-layer 11 b may have different densities, such as different particle densities. For example, a density of the dielectric layer 13 may be higher than a density of the sub-layer 11a and lower than a density of the sub-layer 11b. For example, the dielectric layer 13 (or the surface 131 ) may be denser than the sub-layer 11a (or the surface 11a1 ). For example, the sub-layer 11b (or surface 11b1 ) may be denser than the dielectric layer (or surface 131 ).

In some embodiments, a conductive layer 14 may be disposed in the substrate 10 . In some embodiments, conductive layer 14 may be disposed in dielectric layer 13 . In some embodiments, the dielectric layer 13 may define a recess, and the conductive layer 14 may be disposed in the recess. In some embodiments, the conductive layer 14 may be surrounded by the dielectric layer 13 . In some embodiments, the conductive layer 14 can be separated from the substrate 10 by the dielectric layer 13 . In some embodiments, a dielectric layer 13 may be disposed between the conductive layer 14 and the substrate 10 .

In some embodiments, the conductive layer 14 may have a surface (eg, an upper surface) 141 separated from the surface 101 of the substrate 10 . For example, the surface 141 of the conductive layer 14 may not be coplanar with the surface 101 of the substrate 10 . In some embodiments, the surface 141 of the conductive layer 14 may be separated from the surface 131 of the dielectric layer 13 . For example, the surface 141 of the conductive layer 14 may not be coplanar with the surface 131 of the dielectric layer 13 .

In some embodiments, conductive layer 14 may include a single layer of metal, a metal composite, or multiple layers of conductive material. In some embodiments, conductive layer 14 may include polysilicon, TiN, WN, or the like.

In some embodiments, the dielectric layer 11 (including the sub-layer 11a and the sub-layer 11b ) and the dielectric layer 13 may have different thicknesses. For example, the thickness (eg, maximum thickness or average thickness) of the dielectric layer 11 may be greater than the thickness (eg, maximum thickness or average thickness) of the dielectric layer 13 . For example, the distance between the conductive layer 12 and the substrate 10 may be greater than the distance between the conductive layer 14 and the substrate 10 .

In some embodiments, a dielectric constant of the dielectric layer 11 (including the sub-layer 11 a and the sub-layer 11 b ) may be lower than that of the substrate 10 . In some embodiments, a dielectric constant of the dielectric layer 13 may be lower than that of the substrate 10 .

In some embodiments, the low dielectric constant characteristics of the dielectric layer 11 and the dielectric layer 13 can help the insulation between the conductive layer 12 and the conductive layer 14 . For example, the first dielectric constant characteristic of the dielectric layer 11 and the dielectric layer 13 can help reduce the effective electric field generated when the conductive layer 12 is turned on or activated (eg, through a word line) and avoid interference therebetween.

In some embodiments, isolation layer 15 may be disposed on surface 121 of conductive layer 12 and on surface 141 of conductive layer 14 . In some embodiments, a portion of the isolation layer 15 on the conductive layer 12 may be separated from the substrate 10 by the dielectric layer 11 (including the sub-layer 11 a and the sub-layer 11 b ). In some embodiments, a portion of the isolation layer 15 on the conductive layer 12 may cover the surface 11a1 of the sub-layer 11a and the surface 11b1 of the sub-layer 11b. In some embodiments, a portion of the isolation layer 15 on the conductive layer 12 may contact the surface 11a1 of the sub-layer 11a and the surface 11b1 of the sub-layer 11b.

In some embodiments, a portion of the isolation layer 15 on the conductive layer 14 may be separated from the substrate 10 by the dielectric layer 13 . In some embodiments, a portion of the isolation layer 15 on the conductive layer 14 may cover the surface 131 of the dielectric layer 13 . In some embodiments, a portion of the isolation layer 15 on the conductive layer 14 may contact the surface 131 of the dielectric layer 13 .

In some embodiments, at least a portion of isolation layer 15 may be buried in substrate 10 . For example, at least a portion of the isolation layer 15 may be buried in a recess defined by the sub-layer 11 b and the surface 121 of the conductive layer 12 . For example, at least a portion of the isolation layer 15 may be embedded in a recess defined by the dielectric layer 13 and the surface 141 of the conductive layer 14 .

In some embodiments, the isolation layer 15 may include SiO ₂ , Si ₃ N ₄ , N ₂ OSi ₂ , N ₂ OSi _{2 ,} etc., but not limited thereto. In some embodiments, the isolation layer 15 can cover and protect the surface 121 of the conductive layer 12 and the surface 141 of the conductive layer 14 .

In some embodiments, bit line 16 may be disposed on diffusion region 10b. In some embodiments, the bit line 16 can be electrically connected to the diffusion region 10b. In some embodiments, the bit line 16 may include, but not limited to, a polysilicon 16a and a lamination 16b, and the lamination 16b includes a _WNx film, a W film, and so on.

In some embodiments, the isolation layer 17 can be disposed on the isolation layer 15 and the bit line 16 . In some embodiments, the isolation layer 17 may include SiO ₂ , Si ₃ N ₄ , N ₂ OSi ₂ , N ₂ OSi _{2 ,} etc., but not limited thereto.

In some embodiments, isolation layer 18 may be disposed on isolation layer 17 . In some embodiments, an upper surface of the isolation layer 18 may be substantially coplanar with an upper surface of the capacitor contact pad plug 19 . In some embodiments, the isolation layer 18 may include SiO ₂ , Si ₃ N ₄ , N ₂ OSi ₂ , N ₂ OSi _{2 ,} etc., but not limited thereto.

In some embodiments, capacitor contact plug 19 may extend through isolation layer 17 as well as isolation layer 18 . In some embodiments, a capacitor contact plug 19 may be disposed on the diffusion region 10a. In some embodiments, the capacitor contact plug 19 can be electrically connected to the diffusion region 10a.

In some embodiments, capacitor contact plug 19 may comprise a suitable conductive material. For example, the capacitor contact plug 19 may include W, Cu, Al, Ag, alloys thereof, or combinations thereof.

In some embodiments, an isolation layer 20 may be disposed on the isolation layer 18 and the capacitor contact plug 19 . In some embodiments, isolation layer 22 may be disposed on isolation layer 20 . In some embodiments, the isolation layer 20 may surround the capacitor contact pad 21 . In some embodiments, isolation layer 22 and isolation layer 20 may surround capacitor 23 . In some embodiments, each of the isolation layer 20 and the isolation layer 22 may include SiO ₂ , Si ₃ N ₄ , N ₂ OSi ₂ , N ₂ OSi _{2 ,} etc., but not limited thereto.

In some embodiments, the capacitor 23 can be electrically connected to the diffusion region 10 a (eg, a source junction or a drain junction of a corresponding transistor) via the capacitor contact plug 19 . In some embodiments, the capacitor 23 may include a lower electrode 23a, an isolation layer 23b and an upper electrode 23c.

In some embodiments, the lower electrode 23a and the upper electrode 23c may include doped polysilicon or metal. In some embodiments, the isolation layer 23b includes Ta ₂ O ₅ , Al ₂ O ₃ , SrBi ₂ Ta ₂ O ₉ (SBT), BaSrTiO ₃ (BST), a dielectric material having a dielectric constant higher than that of SiO ₂ material, or a dielectric material having a dielectric constant of about 4.0 or greater.

In a comparative embodiment, the sub-layer 11b can be omitted, and the conductive layer 12 can be separated from the substrate 10 only by the sub-layer 11a.

As DRAM devices become more highly integrated, connecting an active word line (such as conductive layer 14) in a memory cell with a pass word line (such as conductive layer 12) in an adjacent memory cell Insulation becomes more difficult. For example, when a pass word line (such as the conductive layer 12) is turned on, an inversion layer can be created and the source/drain junction can be extended to generate an internal electric field. The junction leakage current can be accelerated by trap-assisted tunneling, which is generated by the internal electric field.

By forming two dielectric layers (such as sub-layer 11a and sub-layer 11b) between conductive layer 12 and substrate 10, the dielectric material with a low dielectric constant between conductive layer 12 and substrate 10 is thicker; The internal electric field is reduced and therefore the junction leakage current can be reduced. Therefore, interference between word lines (eg, conductive layer 12 and conductive layer 14 ) in different memory cells of the present disclosure can be avoided, and charges written to cell capacitors can be preserved. In some embodiments, the sub-layer 11b having a higher density than the sub-layer 11a can also enhance the insulation between word lines (such as conductive layer 12 and conductive layer 14) in different memory cells of the present disclosure. .

Figure 2A, Figure 2B, Figure 2C, Figure 2D, Figure 2E, Figure 2F, Figure 2G, Figure 2H, Figure 2I, Figure 2J, Figure 2K, Figure 2L, Figure 2M, Figure 2N, Figure 2O, Figure 2P, Figure 2Q , FIG. 2R , FIG. 2S , and FIG. 2T are schematic cross-sectional views illustrating multiple stages of the manufacturing method of the semiconductor device according to some embodiments of the present disclosure. At least some of the drawings have been simplified in order to better understand aspects of the present disclosure. In some embodiments, the semiconductor device 1 in FIG. 1 can be performed through the following steps and correspond to FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I. , FIG. 2J, FIG. 2K, FIG. 2L, FIG. 2M, FIG. 2N, FIG. 2O, FIG. 2P, FIG. 2Q, FIG. 2R, FIG. 2S, and FIG. 2T are manufactured.

Referring to FIG. 2A , a substrate 10 may be provided. The sublayer 11 a may be disposed in the substrate 10 . In some embodiments, the fabrication technique of the sub-layer 11a may include trench etching followed by filling the trench with a dielectric material. In some embodiments, the fabrication technique of the sub-layer 11a may include a chemical vapor deposition (CVD) process. In some embodiments, the sub-layer 11a may include a low-k dielectric material, such as FSG, OSG, CDO, porous silicon dioxide, and the like. In some embodiments, the sub-layer 11a may be a dielectric material having a dielectric constant lower than SiO ₂ or a dielectric material having a dielectric constant lower than about 4.0.

Referring to FIG. 2B , a recess 11 r may be formed in the sub-layer 11 a, and a recess 13 r may be formed in the substrate 10 . In some embodiments, the recessed portion 11r and the recessed portion 13r may be separated from each other. In some embodiments, the recessed portion 11r and the recessed portion 13r may be formed sequentially or simultaneously.

In some embodiments, the fabrication techniques of the recessed portion 11r and the recessed portion 13r may include lithography and etching techniques. In some embodiments, the sub-layer 11a and the substrate 10 have different etch rates with respect to an etchant. For example, relative to an etchant, the etch rate of the sub-layer 11a may be greater than the etch rate of the substrate 10 . In some embodiments, a depth of the recessed portion 11r may be deeper than a depth of the recessed portion 13r.

Referring to FIG. 2C , a protection layer 24 may be disposed on the surface 101 of the substrate 10 . The protective layer 24 may be provided in the recessed part 11r as well as the recessed part 13r. The protective layer 24 can fill up the recessed portion 11r and the recessed portion 13r. In some embodiments, the passivation layer 24 and the substrate 10 have different etch rates with respect to an etchant. In some embodiments, the passivation layer 24 may exhibit an etch characteristic different from that of the substrate 10 . For example, the passivation layer 24 may include nitride or photoresist.

Referring to FIG. 2D , a photoresist 25 and a hard mask (not shown in the drawing) can be provided on the passivation layer 24 . In some embodiments, photoresist 25 may be patterned. In some embodiments, the photoresist 25 may be disposed on the concave portion 13r. In some embodiments, the photoresist 25 may not cover the recess 11r. In some embodiments, the photoresist 25 may not overlap the recess 11r.

Referring to FIG. 2E , the passivation layer 24 can be patterned. In some embodiments, since the passivation layer 24 and the substrate 10 have different etch rates or exhibit different etching characteristics corresponding to an etchant, the substrate 10 may remain unchanged when the passivation layer 24 is patterned. After removing a portion of the protective layer 24, the sublayer 11a may be exposed and the surface 11a1 may be exposed.

Referring to FIG. 2F, the sub-layer 11b may be disposed in the recess 11r and on the sub-layer 11a. In some embodiments, the fabrication technique of the sub-layer 11b may include a process different from that of the sub-layer 11a. In some embodiments, the fabrication technique of the sub-layer 11b may include an atomic layer deposition (ALD) process. In some embodiments, a density of the sub-layer 11b may be higher than a density of the sub-layer 11a. In some embodiments, the sub-layer 11b may include a low-k dielectric material, such as FSG, OSG, CDO, porous silicon dioxide, and the like. In some embodiments, the sub-layer 11b may be a dielectric material having a dielectric constant lower than SiO ₂ , or a dielectric material having a dielectric constant lower than about 4.0. In some embodiments, the sub-layer 11b and the sub-layer 11a may have the same material.

Referring to FIG. 2G , the photoresist 25 can be removed from the passivation layer 24 .

Referring to FIG. 2H , for example, the protection layer 24 may be removed from the substrate 10 by a wet etching process or other suitable processes. After the protective layer 24 is removed, the recessed portion 13r may be exposed. In other words, the recess 13r may be removed after the sub-layer 11b is disposed in the recess 11r and on the sub-layer 11a.

Referring to FIG. 2I, the dielectric layer 13 may be disposed in the recessed portion 13r. In some embodiments, the fabrication technique of the dielectric layer 13 may include a process different from that of the sub-layer 11a or the sub-layer 11b. In some embodiments, the fabrication technique of the dielectric layer 13 may include a thermal oxidation step. In some embodiments, the density of the dielectric layer 13 may be higher than that of the sub-layer 13a and lower than that of the sub-layer 11b. In some embodiments, the dielectric layer 13 may include a low-k dielectric material, such as FSG, OSG, CDO, porous silicon dioxide, and the like. In some embodiments, the dielectric layer 13 may be a dielectric material having a dielectric constant lower than SiO ₂ , or a dielectric material having a dielectric constant lower than about 4.0. In some embodiments, the dielectric layer 13 , the sub-layer 11b and the sub-layer 11a may have the same material.

In some embodiments, the surface 11a1 of the sub-layer 11a, the surface 11b1 of the sub-layer 11b and/or the surface 131 of the dielectric layer 13 may be formed after a chemical mechanical polishing (CMP) process. In some embodiments, the surface 101 of the substrate 10 , the surface 11a1 of the sub-layer 11a , the surface 11b1 of the sub-layer 11b and/or the surface 131 of the dielectric layer 13 may be substantially coplanar.

Please refer to FIG. 2J , the manufacturing technique of the diffusion regions 10 a and 10 b may include doping a plurality of impurities through ion implantation or thermal diffusion. In some embodiments, the diffusion regions 10 a and 10 b may be formed on or close to the surface 101 of the substrate 10 . In some embodiments, diffusion regions 10a and 10b may be formed after the other steps described. For example, the diffusion regions 10a and 10b may be formed after one of FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G, and FIG. 2H.

Referring to FIG. 2K, a conductive material 12m may be disposed on the substrate 10 to fill up the recessed portion 11r and the recessed portion 13r. In some embodiments, for example, the fabrication techniques of the conductive material 12m may include plating, electroless plating, printing, CVD, or other suitable steps.

Referring to FIG. 2L, a portion of the conductive material 12m may be removed by an etch-back process, such as a dry etch process using a silicon nitride film (not shown) as a mask. In some embodiments, after the etch-back process, the conductive layer 12 may be formed in the recessed portion 11r, and the conductive layer 14 may be formed in the recessed portion 13r. In some embodiments, after the etch-back process, the surface 121 of the conductive layer 12 may be separated from the surface 101 of the substrate 10 . In some embodiments, after the etch-back process, the surface 141 of the conductive layer 14 may be separated from the surface 101 of the substrate 10 .

Referring to FIG. 2M , the isolation layer 15 may be disposed on the surface 121 of the conductive layer 12 and on the surface 141 of the conductive layer 14 . In some embodiments, for example, the fabrication techniques of the isolation layer 15 may include ALD, CVD, physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), coating, etc. .

Referring to FIG. 2N, the isolation layer 15 can be patterned to define the position of the bit lines formed in the next steps.

Referring to FIG. 2O, the bit line 16 may be disposed on the diffusion region 10b. For example, a laminate 16b of W/WN film and polysilicon 16a may be patterned, thereby forming bit lines 16 . In some embodiments, bit line 16 may contact diffusion region 10b. In some embodiments, the bit line 16 can be electrically connected to the diffusion region 10b.

Referring to FIG. 2P , the isolation layer 17 can be disposed on the isolation layer 15 and the bit line 16 . In some embodiments, for example, the fabrication techniques of the isolation layer 17 may include ALD, CVD, PVD, RPCVD, PECVD, coating, and the like.

Referring to FIG. 2Q , the isolation layer 18 may be disposed on the isolation layer 17 . In some embodiments, for example, the fabrication techniques of the isolation layer 18 may include ALD, CVD, PVD, RPCVD, PECVD, coating, and the like.

Referring to FIG. 2R, an opening 18r can be formed in the isolation layer 17 and the isolation layer 18 by lithography and etching techniques. The diffusion region 10a may be exposed through the opening 18r.

Referring to FIG. 2S, a conductive material of the capacitor contact plug 19 may be formed in the opening 18r. The capacitor contact plug 19 can pass through the isolation layer 17 and the isolation layer 18 . The fabrication techniques of the conductive material may include suitable techniques such as electroplating or an electroless plating process, CVD, PVD, and the like.

Referring to FIG. 2T , similar steps can be repeated to form capacitor contact pads 21 and other conductive elements (if any) on the capacitor contact plug 19 . Isolation layer 20 and isolation layer 22 may be disposed on isolation layer 18 . An opening can be formed in the isolation layer 20 and the isolation layer 22 .

The capacitor 23 can be disposed in the opening defined by the isolation layer 20 and the isolation layer 22 . For example, the electrode material of the lower electrode 23a can be disposed in the opening by, for example, plating, electroless plating, printing, CVD, or other suitable steps. The isolation material of the isolation layer 23b may be provided on the inner side of the lower electrode 23a by, for example, CVD. The electrode material of the upper electrode 23c can be disposed in the opening by, for example, plating, electroless plating, printing, CVD, or other suitable steps.

In some embodiments, a wiring layer (not shown) may be formed on the capacitor 23 after the capacitor 23 is formed. For example, the wiring layer may have a multilayer wiring structure including a plurality of wiring layers and interlayer isolation films.

FIG. 3 is a schematic flowchart illustrating a method 30 for fabricating a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the manufacturing method 30 may include a step S31 of forming a first recess in a first dielectric layer in a substrate. For example, as shown in FIG. 2B , the recess 11 r may be formed in the sub-layer 11 a in the substrate 10 .

In some embodiments, the manufacturing method 30 may include a step S32 of forming a second recessed portion spaced from the first recessed portion and in the substrate. For example, as shown in FIG. 2B , a recess 13 r may be formed in the substrate 10 . The depressed portion 13r is spaced apart from the depressed portion 11r.

In some embodiments, the manufacturing method 30 may include a step S33 of disposing a protection layer on the substrate to cover the second depression. For example, as shown in FIG. 2C , a protective layer 24 may be disposed on the substrate 10 to cover the recessed portion 13r.

In some embodiments, the manufacturing method 30 may include a step S34 of disposing a second dielectric layer on the first dielectric layer. For example, as shown in FIG. 2F, sub-layer 11b may be disposed on sub-layer 11a.

In some embodiments, the manufacturing method 30 may include a step S35 of removing the protective layer to expose the second recessed portion. For example, as shown in FIG. 2H , the protection layer 24 may be removed from the substrate 10 and the recess 13r may be exposed.

In some embodiments, the manufacturing method 30 may include a step S36 of disposing a third dielectric layer in the second recess. For example, as shown in FIG. 2I , the dielectric layer 13 may be disposed in the recessed portion 13r.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element includes a base with a surface; and a first dielectric layer extending from the surface of the base into the base. The semiconductor element also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and extending through the substrate The first dielectric layer and the second dielectric layer are separated from the substrate.

Another embodiment of the disclosure provides a semiconductor device. The semiconductor element includes a substrate with a surface; a first dielectric layer extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and passing through the first dielectric layer. layer is separated from the substrate. The semiconductor element also includes a second dielectric layer extending from the surface of the base into the base; and a second conductive layer disposed in the base and separated from the base by the second dielectric layer separated. The first dielectric layer and the second dielectric layer have different thicknesses.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes forming a first recess in a first dielectric layer in a substrate; and forming a second recess spaced apart from the first recess and in the substrate. The preparation method also includes disposing a protective layer on the base to cover the second recess; and disposing a second dielectric layer on the first dielectric layer.

By forming two dielectric layers between the conductive layer and the substrate, the effective electric field can be reduced and thus the junction leakage current can be reduced. Therefore, interference between word lines in different memory cells can be avoided and the charge written to the cell capacitor can be preserved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

1: Semiconductor components 10: Base 101: surface 102: surface 10a: Diffusion zone 10b: Diffusion zone 11: Dielectric layer 11a: Sublayer 11a1: Surface 11b: sublayer 11b1: surface 11r: depression 12: Conductive layer 121: surface 12m: conductive material 13: Dielectric layer 131: surface 13r: depression 14: Conductive layer 141: surface 15: isolation layer 16: bit line 16a: Polysilicon 16b: Laminate 17: isolation layer 18: isolation layer 18r: opening 19: Capacitor contact plugging 20: isolation layer 21: Capacitor Contact Pad 22: isolation layer 23: Capacitor 23a: Lower electrode 23b: isolation layer 23c: Upper electrode 24: protective layer 25: photoresist 30: Preparation method S31: step S32: step S33: step S34: step S35: step S36: step

The disclosure content of the present application can be understood more fully when the drawings are considered together with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2A is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 2B is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2C is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2D is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2E is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2F is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2G is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2H is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2I is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2J is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 2K is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2L is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 2M is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2N is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2O is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 2P is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2Q is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. 2R is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2S is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 2T is a schematic cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

1: Semiconductor components

10: Base

101: surface

102: surface

10a: Diffusion zone

10b: Diffusion zone

11: Dielectric layer

11a: Sublayer

11a1: Surface

11b: sublayer

11b1: surface

12: Conductive layer

121: surface

13: Dielectric layer

131: surface

14: Conductive layer

141: surface

15: isolation layer

16: bit line

16a: Polysilicon

16b: Laminate

17: isolation layer

18: isolation layer

19: Capacitor contact plugging

20: isolation layer

21: Capacitor Contact Pad

22: isolation layer

23: Capacitor

23a: Lower electrode

23b: isolation layer

23c: Upper electrode

Claims (37)

A semiconductor element comprising: a base having a surface; a first dielectric layer extending from the surface of the substrate into the substrate; a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate; and A first conductive layer is arranged in the base and separated from the base by the first dielectric layer and the second dielectric layer. The semiconductor device as claimed in claim 1, wherein the second dielectric layer is disposed between the first dielectric layer and the first conductive layer. The semiconductor device as claimed in claim 1, wherein a density of the second dielectric layer is different from a density of the first dielectric layer. The semiconductor device as claimed in claim 3, wherein the density of the second dielectric layer is higher than the density of the first dielectric layer. The semiconductor device as claimed in claim 3, further comprising a second conductive layer disposed in the substrate and separated from the substrate by a third dielectric layer. The semiconductor device as claimed in claim 5, wherein a density of the third dielectric layer is different from the density of the second dielectric layer and the density of the first dielectric layer. The semiconductor device as claimed in claim 6, wherein the density of the third dielectric layer is lower than the density of the second dielectric layer and higher than the density of the first dielectric layer. The semiconductor device according to claim 5, wherein the first conductive layer includes a pass word line, and the second conductive layer includes an active word line, and the first conductive layer and the second conductive layer are configured to Find addresses of different memory cells. The semiconductor device as claimed in claim 5, wherein the first conductive layer and the second conductive layer are configured to receive different voltages. The semiconductor device as claimed in claim 1, wherein the first dielectric layer includes a first upper surface substantially coplanar with the surface of the substrate. The semiconductor device as claimed in claim 1, wherein the second dielectric layer includes a second upper surface substantially coplanar with the surface of the substrate. The semiconductor device as claimed in claim 1, wherein the first conductive layer includes a surface separated from the surface of the substrate. The semiconductor device as claimed in claim 12, further comprising an isolation layer disposed on the surface of the first conductive layer, wherein the isolation layer is connected to the first dielectric layer and the second dielectric layer The substrates are separated, and the isolation layer contacts the first dielectric layer and the second dielectric layer. A semiconductor element comprising: a base having a surface; a first dielectric layer extending from the surface of the substrate into the substrate; a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer; a second dielectric layer extending from the surface of the substrate into the substrate; and a second conductive layer disposed in the substrate and separated from the substrate by the second dielectric layer; Wherein the first dielectric layer and the second dielectric layer have different thicknesses. The semiconductor device as claimed in claim 14, wherein a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. The semiconductor device as claimed in claim 14, wherein the first dielectric layer includes a first sublayer and a second sublayer, and the second sublayer is disposed between the first sublayer and the first conductive layer . The semiconductor device as claimed in claim 16, wherein a density of the second sublayer is different from a density of the first sublayer, and the density of the second sublayer is greater than the density of the first sublayer. The semiconductor device as claimed in claim 15, wherein a density of the second dielectric layer is lower than the density of the second sublayer and higher than the density of the first sublayer, and a density of the first sublayer is The upper surface and an upper surface of the second sub-layer are substantially coplanar. The semiconductor device according to claim 14, wherein the first conductive layer includes a pass word line and the second conductive layer includes an active word line, and the first conductive layer and the second conductive layer are configured to Find addresses of different memory cells. The semiconductor device as claimed in claim 14, wherein the first conductive layer and the second conductive layer are configured to receive different voltages. A method for preparing a semiconductor element, comprising: forming a first recess in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion in the base; disposing a protection layer on the base to cover the second recess; and A second dielectric layer is disposed on the first dielectric layer. The preparation method according to claim 21, wherein the first depression is deeper than the second depression. The preparation method as claimed in claim 21, wherein the first dielectric layer is formed by a chemical vapor deposition process. The preparation method as claimed in claim 21, wherein the second dielectric layer is formed by an atomic layer deposition process. The preparation method as described in claim item 21, further comprising: removing the protection layer to expose the second recess; and A third dielectric layer is disposed in the second recess. The manufacturing method as claimed in claim 25, wherein the third dielectric layer is formed by a thermal oxidation process. The preparation method as claimed in claim 25, further comprising forming a first conductive layer on the second dielectric layer, wherein the first conductive layer is connected with the first dielectric layer and the second dielectric layer The base is separated. The manufacturing method as claimed in claim 27, further comprising forming a second conductive layer on the third dielectric layer, wherein the second conductive layer is separated from the substrate by the third dielectric layer. The method of claim 28, wherein the first conductive layer and the second conductive layer include a plurality of word lines and are configured to find addresses of different memory cells. The manufacturing method as claimed in claim 21, wherein a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. The preparation method according to claim 21, wherein the first dielectric layer includes a first sublayer and a second sublayer, and the second sublayer is disposed between the first sublayer and the first conductive layer . The method of claim 31, wherein a density of the second sublayer is different from a density of the first sublayer. The method of claim 31, wherein the density of the second sublayer is greater than the density of the first sublayer. The method of claim 31, wherein a density of the second dielectric layer is lower than the density of the second sublayer and higher than the density of the first sublayer. The preparation method according to claim 31, wherein an upper surface of the first sublayer and an upper surface of the second sublayer are substantially coplanar. The method of claim 31, wherein the first conductive layer includes a pass word line, and the second conductive layer includes an active word line. The manufacturing method as claimed in claim 31, wherein the first conductive layer and the second conductive layer are configured to receive different voltages.

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