TW202324390A - Data receiving circuit - Google Patents
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- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
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- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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Abstract
Description
本申請案主張美國第17/541,801號及第17/544,574號專利申請案之優先權(即優先權日為「2021年12月3日」及「2021年12月7日」),其內容以全文引用之方式併入本文中。This application claims priority from U.S. Patent Application Nos. 17/541,801 and 17/544,574 (i.e., with priority dates of "December 3, 2021" and "December 7, 2021"), the content of which is It is incorporated herein by reference in its entirety.
本揭露關於一種資料接收電路,特別是關於一種具有感應放大器的資料接收電路。The present disclosure relates to a data receiving circuit, in particular to a data receiving circuit with an inductive amplifier.
在記憶體元件中,輸入接收器被廣泛用於接收輸入訊號。然而,隨著對記憶體元件操作速度的要求越來越高,輸入接收器的性能可能無法跟上,導致對輸入資料做正確判斷的餘量更小。在輸入資料被錯誤解釋的情況下,記憶體元件可能因此而崩潰或操作異常。In memory devices, input receivers are widely used to receive input signals. However, as the operating speed of the memory device is required to be higher and higher, the performance of the input receiver may not be able to keep up, resulting in a smaller margin for making correct judgments on the input data. In cases where input data is misinterpreted, memory components may crash or operate abnormally as a result.
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.
本揭露的一個實施例提供一種資料接收電路。該資料接收電路包括一資料輸入電路、一鎖存電路以及一電流源。該資料輸入電路經配置以接收一輸入訊號。該鎖存電路經配置以因應於該輸入訊號來輸出一輸出訊號。該電流源經配置以向該鎖存電路提供一電流。該電流源與該資料輸入電路不同。An embodiment of the disclosure provides a data receiving circuit. The data receiving circuit includes a data input circuit, a latch circuit and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide a current to the latch circuit. The current source is distinct from the data input circuit.
本揭露的另一個實施例提供一種資料接收電路。該資料接收電路包括一第一電晶體、一第二電晶體、一第三電晶體以及一鎖存電路。該第一電晶體其一閘極經配置以接收一輸入訊號。該鎖存電路經配置以因應於輸入訊號來輸出一輸出訊號。該第二電晶體具有一閘極和一極,該閘極經配置以接收一第一訊號,該汲極與該鎖存電路相連。該第三電晶體具有一閘極和一汲極,該閘極經配置以接收該第一訊號,該汲極連接到該鎖存電路。該第二電晶體和該第三電晶體經配置以因應於該第一訊號來向鎖存電路提供一電流。Another embodiment of the disclosure provides a data receiving circuit. The data receiving circuit includes a first transistor, a second transistor, a third transistor and a latch circuit. A gate of the first transistor is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate and a pole, the gate is configured to receive a first signal, and the drain is connected to the latch circuit. The third transistor has a gate and a drain, the gate is configured to receive the first signal, and the drain is connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.
現在用具體的語言來描述附圖中說明的本揭露的實施例,或實例。應理解的是,在此不打算限制本揭露的範圍。對所描述的實施例的任何改變或修改,以及對本文所描述的原理的任何進一步應用,都應被認為是與本揭露內容有關的本領域普通技術人員通常會做的。參考符號可以在整個實施例中重複,但這並不一意旨一個實施例的特徵適用於另一個實施例,即使它們共用相同的參考符號。Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference signs may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference signs.
應理解的是,儘管用語第一、第二、第三等可用於描述各種元素、元件、區域、層或部分。可用於描述各種元素、部件、區域、層或部分,但這些元素、部件、區域、層或部分不受這些用語的限制。相反,這些用語僅用來區分一個元素、元件、區域、層或部分與另一個區域、層或部分。因此,下面討論的第一元素、元件、區域、層或部分可以稱為第二元素、元件、區域、層或部分而不偏離本發明概念的教導。It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections, but these elements, components, regions, layers or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.
本文使用的用語僅用於描述特定的實施例,並不打算局限于本發明的概念。正如本文所使用的,單數形式的”一"、"一個”和”該”旨在包括複數形式,除非上下文特別指出。應進一步理解,用語”包括”和”包含”在本說明書中使用時,指出了所述特徵、整數、步驟、操作、元素或元件的存在,但不排除存在或增加一個或多個其他特徵、整數、步驟、操作、元素、元件或其組。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms unless the context specifically dictates otherwise. It should be further understood that when the words "comprise" and "comprising" are used in this specification, they point out the existence of said features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.
圖1A是電路圖,例示本揭露一些實施例之資料接收電路100(或資料接收器)。資料接收電路100包括輸入電路110、鎖存電路120,和等化器130。在一些實施例中,資料接收電路100可以是或可以包括一感應放大器。在一些實施例中,輸入電路110和鎖存電路120可統稱為感應放大器。FIG. 1A is a circuit diagram illustrating a data receiving circuit 100 (or data receiver) of some embodiments of the present disclosure. The
輸入電路110包括電晶體T11、T12和T13。在一些實施例中,電晶體T11、T12和T13是P型金屬氧化物半導體(PMOS)電晶體。電晶體T11的源極經連接以接收電源電壓Vdd。電晶體T11的閘極經連接以接收時脈訊號V1。在部分實施例中,時脈訊號V1與等化訊號Veq是相同的。例如,時脈訊號V1與等化訊號Veq具有相同的時脈。電晶體T11的汲極連接到電晶體T12的源極和電晶體T13的源極。電晶體T12的閘極經連接以接收參考訊號V2。電晶體T12的汲極與鎖存電路120相連(例如,與電晶體T21的源極相連)。電晶體T13的閘極經連接以接收輸入訊號Vin。電晶體T13的汲極連接到鎖存電路120(例如,連接到電晶體T23的源極)。在一些實施例中,參考訊號V2的一電壓電平在約0.1Vdd至約0.42Vdd的範圍內。在其他實施例中,參考訊號V2可根據設計要求以具有其他電壓電平。在一些實施例中,輸入訊號Vin的一電壓電平在大約-0.2V至大約Vdd+0.2V的範圍內。在其他實施例中,輸入訊號Vin可根據設計要求以具有其他電壓電平。The
鎖存電路120可以包括兩個反相器,其中一個反相器的輸出端與另一個反相器的輸入端相連。如圖1A所示,鎖存電路120包括電晶體T21、T22、T23和T24。電晶體T21和T22定義一反相器,而電晶體T23和T24定義另一反相器。電晶體T21和T23是PMOS電晶體,電晶體T22和T24是N型金屬氧化物半導體(N-type metal-oxide-semiconductor,NMOS)電晶體。The
電晶體T21的源極與電晶體T12的汲極相連。電晶體T21的閘極與電晶體T22的閘極、電晶體T23的汲極和電晶體T24的汲極相連。電晶體T21的汲極連接到電晶體T22的汲極。電晶體T22的源極與公共電壓(例如,地)相連。電晶體T21的汲極和電晶體T22的汲極可以做為資料接收電路100的輸出端Vout1。The source of the transistor T21 is connected to the drain of the transistor T12. The gate of the transistor T21 is connected with the gate of the transistor T22, the drain of the transistor T23 and the drain of the transistor T24. The drain of transistor T21 is connected to the drain of transistor T22. The source of transistor T22 is connected to a common voltage (eg, ground). The drains of the transistor T21 and the transistor T22 can be used as the output terminal Vout1 of the
電晶體T23的源極與電晶體T13的汲極相連。電晶體T23的汲極與電晶體T24的汲極相連。電晶體T24的源極與公共電壓(例如,地)相連。電晶體T23的汲極和電晶體T24的汲極可以做為資料接收電路100的輸出端Vout2。The source of transistor T23 is connected to the drain of transistor T13. The drain of transistor T23 is connected to the drain of transistor T24. The source of transistor T24 is connected to a common voltage (eg, ground). The drains of the transistor T23 and the transistor T24 can be used as the output terminal Vout2 of the
等化器130包括電晶體T31、T32、T33、T34和T35。在一些實施例中,電晶體T31、T32、T33、T34和T35是NMOS電晶體。電晶體T31、T32、T33、T34和T35的閘極相互連接以接收等化訊號Veq。電晶體T31的源極與公共電壓(例如,地)相連。電晶體T33的源極連接到公共電壓(例如,連接到地)。電晶體T34的源極連接到公共電壓(例如,連接到地)。電晶體T35的源極與公共電壓(如地)相連。電晶體T32連接在電晶體T31和T33之間。The
圖1B是時序圖,例示本揭露一些實施例之圖1A的資料接收電路100在不同節點的時序波形。FIG. 1B is a timing diagram illustrating timing waveforms at different nodes of the
在一些實施例中,在時間T1之前,資料接收電路100經配置以操作在一等化階段。在這個階段,等化器130被致能。具有一高邏輯電平(例如,邏輯值"1")的等化訊號Veq(等於時脈訊號V1)經輸入到電晶體T31、T32、T33、T34和T35的閘極,以開啟(turn on)這些電晶體。因此,電晶體T12汲極的電壓Vcom1、電晶體T13汲極的電壓Vcom2、Vout1和Vout2將被拉低到公共電壓(例如,地),如圖1C所示,例示操作在等化階段的資料接收電路100的等效電路。In some embodiments, before the time T1, the
在時間T1之後,該等化階段完成,因此具有一低邏輯電平(例如邏輯值"0")的等化訊號Veq經輸入到電晶體T31、T32、T33、T34和T35的閘極,以關閉(turn off)這些電晶體。等化器130被關閉。圖1D例示本揭露一些實施例之資料接收電路100在此操作階段的等效電路。After time T1, the equalization phase is completed, so the equalization signal Veq having a low logic level (for example, logic value "0") is input to the gates of transistors T31, T32, T33, T34 and T35 to Turn off these transistors.
在T1的時候,等化器130關閉,此時時脈訊號V1等於等化訊號Veq,電晶體T11被打開,具有一高邏輯電平的輸入訊號Vin(例如,邏輯值"1")經輸入到電晶體T13的閘極。電晶體T11的汲極(或電晶體T12或T13的源極)的電壓Vtop開始上升。例如,電壓Vtop被拉高。電晶體T12的汲極(或電晶體T21的源極)的電壓Vcom1也開始上升。例如,電壓Vcom1被拉高。電晶體T13的汲極(或電晶體T23的源極)的電壓Vcom2也開始上升。例如,電壓Vcom2被拉高。At T1, the
由於電晶體T13閘極的電壓(如輸入訊號Vin)高於電晶體T12閘極的電壓(如參考訊號V2),流經電晶體T12的電流I11比流經電晶體T13的電流I12大。經過足夠長的時間,電晶體T21被完全開啟。由於在該等化階段,電晶體T21和T22閘極的電壓Vout2已經被拉低到公共電壓(例如,地),電晶體T21和T24被完全開啟,而電晶體T22和T23被完全關閉。因此,在電晶體T21和T22的汲極(或電晶體T23和T24的閘極)的電壓Vout1在時間T2開始上升。例如,電壓Vout1在時間T2被拉高。Since the gate voltage of the transistor T13 (such as the input signal Vin) is higher than the gate voltage of the transistor T12 (such as the reference signal V2), the current I11 flowing through the transistor T12 is larger than the current I12 flowing through the transistor T13. After a long enough time, transistor T21 is fully turned on. Since the gate voltage Vout2 of the transistors T21 and T22 has been pulled down to the common voltage (eg, ground) during the equalization phase, the transistors T21 and T24 are fully turned on, and the transistors T22 and T23 are completely turned off. Therefore, the voltage Vout1 at the drains of transistors T21 and T22 (or the gates of transistors T23 and T24 ) starts to rise at time T2. For example, voltage Vout1 is pulled high at time T2.
在一些實施例中,在時間T2,資料接收電路100經配置以操作在一資料開發階段。在時間T3,電晶體T21和T22的汲極(或電晶體T23和T24的閘極)的電壓Vout1已完全拉高到該高邏輯電平(例如,邏輯值"1")。在一些實施例中,在時間T3和時間T4期間,資料接收電路100經配置以操作在一資料鎖存階段。In some embodiments, at time T2, the
在資料輸入的時期(例如從時間T1到時間T4)完成後,資料接收電路100經配置以在時間T4階段再次操作在一等化階段。After the period of data input (eg, from time T1 to time T4 ) is completed, the
當在資料輸入期間(例如,從時間T1到時間T4)操作時,如果輸入訊號Vin的電壓高於參考訊號V2的電壓,則資料接收電路100經配置以輸出具有高邏輯電平(例如,邏輯值"1")的電壓Vout1;如果輸入訊號Vin的電壓低於參考訊號V2的電壓,則資料接收電路100經配置以輸出端有低邏輯電平(例如,邏輯值"0")的電壓Vout1。然而,由於存在於電晶體T12和T13的汲極的寄生元件(例如,電阻、電感和/或電容),電流I11和電流I12必須對這些寄生元件充電(或放電)以拉高(或拉低)電壓Vcom1和Vcom2。When operating during data input (for example, from time T1 to time T4), if the voltage of the input signal Vin is higher than the voltage of the reference signal V2, the
如圖1A和圖1D中所示,電流I11和電流I12分別由電晶體T12和T13確定。例如,電流I11(或電流I12)可以由電晶體T12(或電晶體T13)的源極和閘極之間的電壓差(例如Vsg)決定。然而,由於電晶體T12的閘極的電壓V2(例如,約0.1Vdd至約0.42Vdd)和和電晶體T13的閘極的電壓Vin(約Vdd+0.2V)相對較高,電流I11和電流I12將減少,這將使電壓Vout1的上升時間(或下降時間)相對延長。例如,如圖1B所示,與輸入訊號Vin相比,電壓Vout1上升緩慢。當資料接收電路100的操作速度增加時,這種情況變得嚴重。在某些情況下,電壓Vout1將不能正確反映輸入訊號Vin,導致資料接收電路100不正常。As shown in FIGS. 1A and 1D, current I11 and current I12 are determined by transistors T12 and T13, respectively. For example, the current I11 (or the current I12 ) can be determined by the voltage difference (eg, Vsg) between the source and the gate of the transistor T12 (or the transistor T13 ). However, since the voltage V2 (for example, about 0.1Vdd to about 0.42Vdd) of the gate of the transistor T12 and the voltage Vin (about Vdd+0.2V) of the gate of the transistor T13 are relatively high, the current I11 and the current I12 will decrease, which will relatively prolong the rising time (or falling time) of the voltage Vout1. For example, as shown in FIG. 1B , compared with the input signal Vin, the voltage Vout1 rises slowly. This situation becomes severe as the operating speed of the
圖2A是電路圖,例示本揭露一些實施例之資料接收電路200(或資料接收器)。資料接收電路200包括輸入電路410、鎖存電路420、等化器430、電流源(或電流汲取)440,和脈衝產生器450。在一些實施例中,資料接收電路200可以是或可以包括一感應放大器。FIG. 2A is a circuit diagram illustrating a data receiving circuit 200 (or data receiver) of some embodiments of the present disclosure. The
輸入電路包括410電晶體T41、T42和T43。在一些實施例中,電晶體T41、T42和T43是P型金屬氧化物半導體(PMOS)電晶體。電晶體T41的源極經連接以接收電源電壓Vdd。電晶體T41的閘極經連接以接收來自脈衝產生器450的訊號V3。電晶體T41的汲極與電晶體T42的源極和電晶體T43的源極相連。電晶體T42的閘極經相連以接收參考訊號V5。電晶體T42的汲極與鎖存電路420相連(例如,與電晶體T51的汲極、電晶體T52的汲極、電晶體T53的閘極和電晶體T54的閘極)。電晶體T42的汲極也連接到等化器430上。電晶體T43的閘極經連接以接收輸入訊號Vin1。電晶體T43的汲極連接到鎖存電路420(例如,連接到電晶體T53的汲極、電晶體T54的汲極、電晶體T51的閘極和電晶體T52的閘極)。電晶體T43的汲極也連接到等化器430。The input circuit includes 410 transistors T41, T42 and T43. In some embodiments, transistors T41 , T42 and T43 are P-type metal oxide semiconductor (PMOS) transistors. The source of the transistor T41 is connected to receive the power voltage Vdd. The gate of the transistor T41 is connected to receive the signal V3 from the
在一些實施例中,參考訊號V5的一電壓電平在大約0.1Vdd到大約0.42Vdd的範圍內。在其他實施例中,參考訊號V5可根據設計要求以具有其他電壓電平。在一些實施例中,輸入訊號Vin1的電壓電平範圍在大約-0.2V至大約Vdd+0.2V的範圍內。在其他實施例中,輸入訊號Vin1可根據設計要求以具有其他電壓電平。In some embodiments, a voltage level of the reference signal V5 is in a range of about 0.1Vdd to about 0.42Vdd. In other embodiments, the reference signal V5 can have other voltage levels according to design requirements. In some embodiments, the voltage level of the input signal Vin1 ranges from about −0.2V to about Vdd+0.2V. In other embodiments, the input signal Vin1 can have other voltage levels according to design requirements.
鎖存電路420可以包括兩個反相器(例如,如圖2D所示的反相器IN1和IN2),其中一個反相器的輸出端與另一個反相器的輸入端相連。如圖2A所示,鎖存電路420包括電晶體T51、T52、T53和T54。電晶體T51和T52定義一反相器,而電晶體T53和T54定義另一反相器。電晶體T51和T53是PMOS電晶體,電晶體T52和T54是N型金屬氧化物半導體(NMOS)電晶體。The
電晶體T51的源極與電流源440(例如,與電晶體T71的汲極)相連。電晶體T51的閘極與電晶體T52的閘極、電晶體T53的汲極和電晶體T54的汲極相連。電晶體T51的汲極與電晶體T52的汲極相連。電晶體T52的源極與公共電壓(例如,地)相連。電晶體T51的汲極和電晶體T52的汲極可以做為資料接收電路200的輸出端Vout3。The source of the transistor T51 is connected to the current source 440 (eg, to the drain of the transistor T71 ). The gate of transistor T51 is connected with the gate of transistor T52, the drain of transistor T53 and the drain of transistor T54. The drain of transistor T51 is connected to the drain of transistor T52. The source of transistor T52 is connected to a common voltage (eg, ground). The drains of the transistor T51 and the transistor T52 can be used as the output terminal Vout3 of the
電晶體T53的源極與電流源相連440(例如,與電晶體T72的汲極相連)。電晶體T53的汲極與電晶體T54的汲極相連。電晶體T54的源極連接到公共電壓(例如,連接到地)。電晶體T53的汲極和電晶體T54的汲極可以做為資料接收電路200的輸出端Vout4。The source of transistor T53 is connected 440 to a current source (eg, connected to the drain of transistor T72). The drain of transistor T53 is connected to the drain of transistor T54. The source of transistor T54 is connected to a common voltage (eg, to ground). The drains of the transistor T53 and the transistor T54 can be used as the output terminal Vout4 of the
等化器430包括電晶體T61、T62、T63、T64和T65。在一些實施例中,電晶體T61、T62、T63、T64和T65是NMOS電晶體。電晶體T61、T62、T63、T64和T65的閘極相互連接以接收等化訊號Veq1。電晶體T61的源極與公共電壓(如地)相連。電晶體T63的源極連接到公共電壓(例如,連接到地)。電晶體T64的源極連接到公共電壓(例如,連接到地)。電晶體T65的源極與公共電壓(例如,地)相連。電晶體T62連接在電晶體T61和T63之間。The
電流源440包括電晶體T71和T72。在一些實施例中,電晶體T71和T72是PMOS電晶體。電晶體T71的源極經連接以接收電源電壓Vdd。電晶體T71的閘極經連接以接收訊號V4。電晶體T71的汲極經連接到鎖存電路420。電晶體T72的源極經連接以接收電源電壓Vdd。電晶體T72的閘極經連接以接收訊號V4,電晶體T72的汲極經連接到鎖存電路420。The
脈衝產生器450可以包括反相器G1、延遲電路(或緩衝器)G2、和或閘(OR gate)G3。圖2B是時序圖,例示本揭露一些實施例之脈衝產生器450在不同節點的波形。The
在操作中,脈衝產生器450經配置以接收具有週期為P1的一第一邏輯值的輸入(例如,訊號V4)並產生具有週期為P2的一第二邏輯值的輸出(例如,訊號V3)。在一些實施例中,該第一邏輯值與該第二邏輯值相同。例如,如圖2B所示,該第一邏輯值為0,該第二邏輯值為0。在一些實施例中,週期P2小於週期P1。例如,P2等於n×P1,其中0<n<1。In operation,
在一些實施例中,n可以由延遲電路G2的延遲時間決定。如圖2B所示,在時間TG1,具有邏輯值"0”的訊號V4(等於等化訊號Veq)經輸入到脈衝產生器450。詳言之,具有邏輯值"0”的訊號V4輸入至延遲電路G2與或閘G3的一端點(即為訊號A)。延遲電路G2經配置以將經延遲的訊號輸入至反相器G1。反相器G1經配置以產生具有邏輯值"1”的輸出訊號B。時間TG2和時間TG1之間的差異是延遲電路G2的延遲時間。因此,在時間TG1到時間TG2的期間,或閘G3經配置以產生具有邏輯值”0”的訊號V3。In some embodiments, n can be determined by the delay time of the delay circuit G2. As shown in FIG. 2B , at time TG1 , a signal V4 (equal to the equalization signal Veq) having a logic value of “0” is input to the
圖2C是時序圖,例示本揭露一些實施例之圖2A的資料接收電路200在不同節點的波形。FIG. 2C is a timing diagram illustrating waveforms at different nodes of the
在一些實施例中,在時間T5之前,資料接收電路200經配置以操作在一等化階段。在這個階段,等化器430被致能。具有一高邏輯電平(例如,邏輯值"1")的等化訊號Veq1經輸入到電晶體T61、T62、T63、T64和T65的閘極,以開啟這些電晶體。因此,電壓Vcom3、Vcom4、Vout3和Vout4將被拉低到公共電壓(例如,地)。In some embodiments, before the time T5, the
在時間T5之後,該等化階段完成,因此具有一低邏輯電平(例如,邏輯值"0")的等化訊號Veq1經輸入到電晶體T61、T62、T63、T64和T65的閘極,以關閉這些電晶體。等化器430被關閉。圖2D例示本揭露一些實施例之資料接收電路200在此階段操作的等效電路。After time T5, the equalization phase is completed, so the equalization signal Veq1 having a low logic level (for example, logic value "0") is input to the gates of transistors T61, T62, T63, T64 and T65, to turn off these transistors.
在時間T5,具有一高邏輯電平的輸入訊號Vin1(例如,邏輯值"1")經輸入到電晶體T43的閘極。同時,具有邏輯值"0"的訊號V3和V4(例如,在圖2B中的時間TG1和時間TG2期間)經輸入到電晶體T41、T71和T72的閘極以開啟電晶體T41、T71和T72。電晶體T41的汲極(或電晶體T42或T43的源極)的電壓Vtop1開始上升。例如,電壓Vtop1被拉高。電晶體T71的汲極的電壓Vcom3也開始上升。例如,電壓Vcom3被拉高。電晶體T72的汲極的電壓Vcom4也開始上升。例如,電壓Vcom4被拉高。At time T5, the input signal Vin1 with a high logic level (for example, logic value “1”) is input to the gate of the transistor T43. Simultaneously, signals V3 and V4 having a logic value of "0" (for example, during time TG1 and time TG2 in FIG. 2B ) are input to the gates of transistors T41, T71 and T72 to turn on transistors T41, T71 and T72. . The voltage Vtop1 of the drain of the transistor T41 (or the source of the transistor T42 or T43 ) starts to rise. For example, the voltage Vtop1 is pulled high. The drain voltage Vcom3 of the transistor T71 also starts to rise. For example, voltage Vcom3 is pulled high. The drain voltage Vcom4 of the transistor T72 also starts to rise. For example, voltage Vcom4 is pulled high.
由於電晶體T43閘極的電壓(如輸入訊號Vin1)高於電晶體T42閘極的電壓(如參考訊號V5),電晶體T51和T52的汲極(或電晶體T53和T54的閘極)的電壓Vout3也開始上升。例如,電壓Vout3被拉高。在資料輸入的週期(例如從時間T5到時間T6)完成後,資料接收電路200經配置以在時間週期T6上再次操作在一等化階段。Since the gate voltage of the transistor T43 (such as the input signal Vin1) is higher than the voltage of the gate of the transistor T42 (such as the reference signal V5), the drains of the transistors T51 and T52 (or the gates of the transistors T53 and T54) The voltage Vout3 also starts to rise. For example, the voltage Vout3 is pulled high. After the period of data input (eg, from time T5 to time T6) is completed, the
當在資料輸入期間(例如,從時間T5到時間T6)操作時,如果輸入訊號Vin1的電壓高於參考訊號V5的電壓,則資料接收電路200經配置以輸出具有一高邏輯電平(例如,邏輯值"1")的電壓Vout3;如果輸入訊號Vin1的電壓低於參考訊號V5的電壓,則資料接收電路200經配置以輸出具有一低邏輯電平(例如,邏輯值"0")的電壓Vout3。在輸入訊號Vin1輸入到電晶體T43之後,在資料操作經鎖存電路420完成之前(例如,如圖2B所示的時間TG4之後),脈衝產生器450經配置以產生具有邏輯值"1”的訊號V3以關閉電晶體T41,因此防止電路因Vdd和地之間的短路而被損壞。When operating during the data input period (for example, from time T5 to time T6), if the voltage of the input signal Vin1 is higher than the voltage of the reference signal V5, the
根據一些實施例,如圖2A至圖2D所示,在資料輸入期間,電晶體T41、T71和T72的閘極經輸入具有邏輯值"0”的訊號。換句話說,在資料輸入期間,電晶體T41、T71和T72的閘極經連接到地。因此,電晶體T71(或電晶體T72)的源極和閘極之間的電壓差(例如Vsg)高於如圖1A所示的電晶體T12(或電晶體T13)的源極和閘極之間的電壓差(例如Vsg),這使得由電晶體T71和T72產生的電流I13和電流I14大於由電晶體T12和T13產生的電流I11和電流I12。與圖1A中的資料接收電路100相比,資料接收電路200可以用較大的電流I13和I14對寄生元件(例如,電阻、電感和/或電容)充電或放電,這可以增加資料接收電路200的輸出端(例如,電壓Vout3)的因應時間。換句話說,電壓Vout3的上升時間(或下降時間)可以減少。這可以增加資料接收電路200的容忍度和操作速度。According to some embodiments, as shown in FIG. 2A to FIG. 2D , during the data input period, the gates of the transistors T41 , T71 and T72 are input with a signal having a logic value of “0”. In other words, during data input, the gates of transistors T41, T71 and T72 are connected to ground. Therefore, the voltage difference (for example, Vsg) between the source and gate of transistor T71 (or transistor T72) is higher than that between the source and gate of transistor T12 (or transistor T13) as shown in FIG. 1A The voltage difference (such as Vsg) between them makes the current I13 and the current I14 generated by the transistors T71 and T72 larger than the current I11 and the current I12 generated by the transistors T12 and T13. Compared with the
雖然已詳述本揭露及其優點,然而應理解可以進行其他變化、取代與替代而不脫離揭露專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the patent claims disclosed. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.
再者,本揭露案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解以根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包括於本揭露案之揭露專利範圍內。Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.
100:資料接收電路 110:輸入電路 120:鎖存電路 130:等化器 200:資料接收電路 410:輸入電路 420:鎖存電路 430:等化器 440:電流源(或電流汲取) 450:脈衝產生器 A:訊號 B:輸出訊號 G1:反相器 G2:延遲電路 G3:或(OR)閘 I11:電流 I12:電流 I13:電流 I14:電流 IN1:反相器 IN2:反相器 P1:週期 P2:週期 T1:時間 T2:時間 T3:時間 T4:時間 T11:電晶體 T12:電晶體 T13:電晶體 T21:電晶體 T22:電晶體 T23:電晶體 T24:電晶體 T31:電晶體 T32:電晶體 T33:電晶體 T34:電晶體 T35:電晶體 T41:電晶體 T42:電晶體 T43:電晶體 T51:電晶體 T52:電晶體 T53:電晶體 T54:電晶體 T61:電晶體 T62:電晶體 T63:電晶體 T64:電晶體 T65:電晶體 T71:電晶體 T72:電晶體 TG1:時間 TG2:時間 V1:時脈訊號 V2:參考訊號 V3:訊號 V4:訊號 V5:參考訊號 Vcom1:電壓 Vcom2:電壓 Vcom3:電壓 Vcom4:電壓 Vdd:電源電壓 Veq:等化訊號 Veq1:等化訊號 Vin:輸入訊號 Vin1:輸入訊號 Vout1:輸出 Vout2:輸出 Vout3:輸出 Vout4:輸出 Vtop:電壓 Vtop1:電壓 100: data receiving circuit 110: input circuit 120: Latch circuit 130: equalizer 200: data receiving circuit 410: input circuit 420: Latch circuit 430: equalizer 440: current source (or current sink) 450: Pulse generator A: signal B: output signal G1: Inverter G2: delay circuit G3: Or (OR) gate I11: current I12: Current I13: current I14: current IN1: Inverter IN2: Inverter P1: period P2: Period T1: time T2: time T3: time T4: time T11: Transistor T12: Transistor T13: Transistor T21: Transistor T22: Transistor T23: Transistor T24: Transistor T31: Transistor T32: Transistor T33: Transistor T34: Transistor T35: Transistor T41: Transistor T42: Transistor T43: Transistor T51: Transistor T52: Transistor T53: Transistor T54: Transistor T61: Transistor T62: Transistor T63: Transistor T64: Transistor T65: Transistor T71: Transistor T72: Transistor TG1: time TG2: time V1: clock signal V2: Reference signal V3: Signal V4: signal V5: Reference signal Vcom1: voltage Vcom2: voltage Vcom3: voltage Vcom4: voltage Vdd: power supply voltage Veq: equalization signal Veq1: equalization signal Vin: input signal Vin1: input signal Vout1: output Vout2: output Vout3: output Vout4: output Vtop: voltage Vtop1: voltage
參閱實施方式與申請專利範圍合併考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。 圖1A是電路圖,例示本揭露一些實施例之資料接收電路。 圖1B是時序圖,例示本揭露一些實施例之圖1A的資料接收電路在不同節點的時序波形。 圖1C是電路圖,例示本揭露一些實施例之圖1A的資料接收電路的等效電路。 圖1D是電路圖,例示本揭露一些實施例之圖1A的資料接收電路的等效電路。 圖2A是電路圖,例示本揭露一些實施例之資料接收電路。 圖2B是時序圖,例示本揭露一些實施例之圖2A的資料接收電路在不同節點的波形。 圖2C是時序圖,例示本揭露一些實施例之圖2A的資料接收電路在不同節點的波形。 圖2D是電路圖,例示本揭露一些實施例之圖2A的資料接收電路的等效電路。 The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components. FIG. 1A is a circuit diagram illustrating a data receiving circuit of some embodiments of the present disclosure. FIG. 1B is a timing diagram illustrating timing waveforms at different nodes of the data receiving circuit of FIG. 1A according to some embodiments of the present disclosure. FIG. 1C is a circuit diagram illustrating an equivalent circuit of the data receiving circuit of FIG. 1A according to some embodiments of the present disclosure. FIG. 1D is a circuit diagram illustrating an equivalent circuit of the data receiving circuit of FIG. 1A according to some embodiments of the present disclosure. FIG. 2A is a circuit diagram illustrating a data receiving circuit of some embodiments of the present disclosure. FIG. 2B is a timing diagram illustrating waveforms at different nodes of the data receiving circuit of FIG. 2A according to some embodiments of the present disclosure. FIG. 2C is a timing diagram illustrating waveforms at different nodes of the data receiving circuit of FIG. 2A according to some embodiments of the present disclosure. FIG. 2D is a circuit diagram illustrating an equivalent circuit of the data receiving circuit of FIG. 2A according to some embodiments of the present disclosure.
200:資料接收電路 200: data receiving circuit
410:輸入電路 410: input circuit
420:鎖存電路 420: Latch circuit
430:等化器 430: equalizer
440:電流源 440: current source
450:脈衝產生器 450: Pulse generator
A:輸出訊號 A: output signal
B:輸出訊號 B: output signal
G1:反相器 G1: Inverter
G2:延遲電路 G2: delay circuit
G3:或(OR)閘 G3: Or (OR) gate
I13:電流 I13: Current
I14:電流 I14: current
T41:電晶體 T41: Transistor
T42:電晶體 T42: Transistor
T43:電晶體 T43: Transistor
T51:電晶體 T51: Transistor
T52:電晶體 T52: Transistor
T53:電晶體 T53: Transistor
T54:電晶體 T54: Transistor
T61:電晶體 T61: Transistor
T62:電晶體 T62: Transistor
T63:電晶體 T63: Transistor
T64:電晶體 T64: Transistor
T65:電晶體 T65: Transistor
T71:電晶體 T71: Transistor
T72:電晶體 T72: Transistor
V3:訊號 V3: Signal
V4:訊號 V4: signal
V5:參考訊號 V5: Reference signal
Vcom3:電壓 Vcom3: Voltage
Vcom4:電壓 Vcom4: voltage
Vdd:電源電壓 Vdd: power supply voltage
Veq1:等化訊號 Veq1: equalization signal
Vin1:輸入訊號 Vin1: input signal
Vout3:輸出 Vout3: output
Vout4:輸出 Vout4: output
Vtop1:電壓 Vtop1: Voltage
Claims (30)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US17/541,801 US11728794B2 (en) | 2021-12-03 | 2021-12-03 | Data receiving circuit |
US17/541,801 | 2021-12-03 | ||
US17/544,574 US11770117B2 (en) | 2021-12-07 | 2021-12-07 | Data receiving circuit |
US17/544,574 | 2021-12-07 |
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Publication Number | Publication Date |
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TW202324390A true TW202324390A (en) | 2023-06-16 |
TWI817362B TWI817362B (en) | 2023-10-01 |
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TW111106574A TWI817362B (en) | 2021-12-03 | 2022-02-23 | Data receiving circuit |
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JP4328596B2 (en) * | 2003-10-27 | 2009-09-09 | 日本電気株式会社 | Differential amplifier |
JP4596848B2 (en) * | 2004-08-04 | 2010-12-15 | 三洋電機株式会社 | Frequency correction circuit |
JP4502207B2 (en) * | 2005-12-28 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | Differential amplifier, data driver and display device |
JP5814542B2 (en) * | 2010-12-06 | 2015-11-17 | 株式会社東芝 | Oscillator circuit |
US10044354B2 (en) * | 2016-07-11 | 2018-08-07 | Ricoh Company, Ltd. | I/O cell |
EP3419168B1 (en) * | 2017-06-23 | 2020-12-02 | ams AG | Avalanche diode arrangement and method for controlling an avalanche diode arrangement |
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