TWI817362B - Data receiving circuit - Google Patents

Abstract

A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide a current to the latch circuit. The current source is different from the data input circuit.

Description

data receiving circuit

This application claims the priority of U.S. Patent Application Nos. 17/541,801 and 17/544,574 (i.e., the priority dates are "December 3, 2021" and "December 7, 2021"), and the contents are as follows The full text is incorporated into this article by reference.

The present disclosure relates to a data receiving circuit, and in particular to a data receiving circuit with a sense amplifier.

In memory devices, input receivers are widely used to receive input signals. However, as the requirements for the operating speed of memory components increase, the performance of the input receiver may not be able to keep up, resulting in less margin for making correct judgments on the input data. In the event that input data is misinterpreted, memory components may crash or operate abnormally as a result.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

An embodiment of the present disclosure provides a data receiving circuit. The data receiving circuit includes a data input circuit, a latch circuit and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide a current to the latch circuit. The current source is different from the data input circuit.

Another embodiment of the present disclosure provides a data receiving circuit. The data receiving circuit includes a first transistor, a second transistor, a third transistor and a latch circuit. A gate of the first transistor is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate configured to receive a first signal and a drain connected to the latch circuit. The third transistor has a gate configured to receive the first signal and a drain connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference signs may be repeated throughout the embodiments, but this does not necessarily imply that features of one embodiment apply to another embodiment even if they share the same reference signs.

It will be understood that the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections. May be used to describe various elements, components, regions, layers or sections but these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the words "comprises" and "includes", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

FIG. 1A is a circuit diagram illustrating a data receiving circuit 100 (or data receiver) according to some embodiments of the present disclosure. The data receiving circuit 100 includes an input circuit 110, a latch circuit 120, and an equalizer 130. In some embodiments, the data receiving circuit 100 may be or may include a sense amplifier. In some embodiments, input circuit 110 and latch circuit 120 may collectively be referred to as a sense amplifier.

Input circuit 110 includes transistors T11, T12 and T13. In some embodiments, transistors T11, T12, and T13 are P-type metal oxide semiconductor (PMOS) transistors. The source of transistor T11 is connected to receive the supply voltage Vdd. The gate of transistor T11 is connected to receive the clock signal V1. In some embodiments, the clock signal V1 and the equalization signal Veq are the same. For example, the clock signal V1 and the equalization signal Veq have the same clock. The drain of transistor T11 is connected to the source of transistor T12 and the source of transistor T13. The gate of transistor T12 is connected to receive reference signal V2. The drain of transistor T12 is connected to latch circuit 120 (eg, connected to the source of transistor T21). The gate of transistor T13 is connected to receive the input signal Vin. The drain of transistor T13 is connected to latch circuit 120 (eg, to the source of transistor T23). In some embodiments, the reference signal V2 has a voltage level in the range of about 0.1Vdd to about 0.42Vdd. In other embodiments, the reference signal V2 may have other voltage levels according to design requirements. In some embodiments, the input signal Vin has a voltage level in the range of approximately -0.2V to approximately Vdd+0.2V. In other embodiments, the input signal Vin may have other voltage levels according to design requirements.

The latch circuit 120 may include two inverters, where an output terminal of one inverter is connected to an input terminal of the other inverter. As shown in FIG. 1A, latch circuit 120 includes transistors T21, T22, T23, and T24. Transistors T21 and T22 define one inverter, and transistors T23 and T24 define another inverter. Transistors T21 and T23 are PMOS transistors, and transistors T22 and T24 are N-type metal-oxide-semiconductor (NMOS) transistors.

The source of transistor T21 is connected to the drain of transistor T12. The gate electrode of the transistor T21 is connected to the gate electrode of the transistor T22, the drain electrode of the transistor T23 and the drain electrode of the transistor T24. The drain terminal of transistor T21 is connected to the drain terminal of transistor T22. The source of transistor T22 is connected to a common voltage (eg ground). The drain terminal of the transistor T21 and the drain terminal of the transistor T22 can be used as the output terminal Vout1 of the data receiving circuit 100.

The source of transistor T23 is connected to the drain of transistor T13. The drain terminal of transistor T23 is connected to the drain terminal of transistor T24. The source of transistor T24 is connected to a common voltage (eg ground). The drain terminal of the transistor T23 and the drain terminal of the transistor T24 can be used as the output terminal Vout2 of the data receiving circuit 100.

Equalizer 130 includes transistors T31, T32, T33, T34 and T35. In some embodiments, transistors T31, T32, T33, T34, and T35 are NMOS transistors. The gates of transistors T31, T32, T33, T34 and T35 are connected to each other to receive the equalization signal Veq. The source of transistor T31 is connected to a common voltage (eg ground). The source of transistor T33 is connected to a common voltage (for example, to ground). The source of transistor T34 is connected to a common voltage (eg, to ground). The source of transistor T35 is connected to a common voltage (eg ground). Transistor T32 is connected between transistors T31 and T33.

FIG. 1B is a timing diagram illustrating timing waveforms at different nodes of the data receiving circuit 100 of FIG. 1A according to some embodiments of the present disclosure.

In some embodiments, before time T1, the data receiving circuit 100 is configured to operate in the equalization phase. At this stage, equalizer 130 is enabled. The equalization signal Veq (equal to the clock signal V1) having a high logic level (for example, logic value "1") is input to the gates of the transistors T31, T32, T33, T34 and T35 to turn on. ) these transistors. Therefore, the voltage Vcom1 at the drain of transistor T12, the voltages Vcom2, Vout1 and Vout2 at the drain of transistor T13 will be pulled down to the common voltage (for example, ground), as shown in Figure 1C, which illustrates the data of the equalization phase of the operation. Equivalent circuit of receiving circuit 100.

After time T1, the equalization phase is completed, so the equalization signal Veq having a low logic level (eg logic value "0") is input to the gates of transistors T31, T32, T33, T34 and T35 to Turn off these transistors. Equalizer 130 is turned off. FIG. 1D illustrates an equivalent circuit of the data receiving circuit 100 at this stage of operation according to some embodiments of the present disclosure.

At time T1, the equalizer 130 is turned off. At this time, the clock signal V1 is equal to the equalization signal Veq, the transistor T11 is turned on, and the input signal Vin with a high logic level (eg, logic value "1") is input to the gate of transistor T13. The voltage Vtop of the drain of transistor T11 (or the source of transistor T12 or T13) begins to rise. For example, voltage Vtop is pulled high. The voltage Vcom1 of the drain terminal of the transistor T12 (or the source terminal of the transistor T21) also begins to rise. For example, voltage Vcom1 is pulled high. The voltage Vcom2 of the drain terminal of the transistor T13 (or the source terminal of the transistor T23) also begins to rise. For example, voltage Vcom2 is pulled high.

Since the voltage at the gate of the transistor T13 (such as the input signal Vin) is higher than the voltage at the gate of the transistor T12 (such as the reference signal V2), the current I11 flowing through the transistor T12 is larger than the current I12 flowing through the transistor T13. After a sufficient period of time, transistor T21 is fully turned on. Since the gate voltage Vout2 of the transistors T21 and T22 has been pulled down to the common voltage (for example, ground) during the equalization stage, the transistors T21 and T24 are fully turned on, while the transistors T22 and T23 are completely turned off. Therefore, the voltage Vout1 at the drain terminals of transistors T21 and T22 (or the gate terminals of transistors T23 and T24) starts to rise at time T2. For example, voltage Vout1 is pulled high at time T2.

In some embodiments, at time T2, data receiving circuit 100 is configured to operate in a data development phase. At time T3, the voltage Vout1 of the drains of transistors T21 and T22 (or the gates of transistors T23 and T24) has been fully pulled up to the high logic level (eg, logic value "1"). In some embodiments, between time T3 and time T4, data receive circuit 100 is configured to operate in a data latch phase.

After the period of data input (eg, from time T1 to time T4) is completed, the data receiving circuit 100 is configured to operate in the equalization phase again at time T4.

When operating during the data input period (eg, from time T1 to time T4), if the voltage of the input signal Vin is higher than the voltage of the reference signal V2, the data receiving circuit 100 is configured to output an output having a high logic level (eg, logic value "1"); if the voltage of the input signal Vin is lower than the voltage of the reference signal V2, the data receiving circuit 100 is configured to output a voltage Vout1 with a low logic level (eg, a logic value "0") . However, due to the presence of parasitic elements (e.g., resistors, inductors, and/or capacitors) at the drains of transistors T12 and T13, current I11 and current I12 must charge (or discharge) these parasitic elements to pull high (or pull low). ) voltages Vcom1 and Vcom2.

As shown in Figures 1A and 1D, current I11 and current I12 are determined by transistors T12 and T13 respectively. For example, the current I11 (or the current I12) may be determined by the voltage difference (eg Vsg) between the source and gate of the transistor T12 (or the transistor T13). However, since the voltage V2 of the gate of the transistor T12 (for example, about 0.1Vdd to about 0.42Vdd) and the voltage Vin of the gate of the transistor T13 (about Vdd+0.2V) are relatively high, the current I11 and the current I12 will be reduced, which will make the rise time (or fall time) of voltage Vout1 relatively longer. For example, as shown in FIG. 1B , compared with the input signal Vin, the voltage Vout1 rises slowly. This situation becomes serious when the operating speed of the data receiving circuit 100 increases. In some cases, the voltage Vout1 will not correctly reflect the input signal Vin, causing the data receiving circuit 100 to be abnormal.

FIG. 2A is a circuit diagram illustrating a data receiving circuit 200 (or data receiver) according to some embodiments of the present disclosure. The data receiving circuit 200 includes an input circuit 410, a latch circuit 420, an equalizer 430, a current source (or current sink) 440, and a pulse generator 450. In some embodiments, the data receiving circuit 200 may be or may include a sense amplifier.

The input circuit includes 410 transistors T41, T42 and T43. In some embodiments, transistors T41, T42, and T43 are P-type metal oxide semiconductor (PMOS) transistors. The source of transistor T41 is connected to receive the supply voltage Vdd. The gate of transistor T41 is connected to receive signal V3 from pulse generator 450 . The drain of transistor T41 is connected to the source of transistor T42 and the source of transistor T43. The gate of transistor T42 is connected to receive the reference signal V5. The drain of transistor T42 is connected to the latch circuit 420 (eg, to the drain of transistor T51 , the drain of transistor T52 , the gate of transistor T53 , and the gate of transistor T54 ). The drain of transistor T42 is also connected to equalizer 430. The gate of transistor T43 is connected to receive the input signal Vin1. The drain of transistor T43 is connected to the latch circuit 420 (eg, to the drain of transistor T53, the drain of transistor T54, the gate of transistor T51, and the gate of transistor T52). The drain of transistor T43 is also connected to equalizer 430 .

In some embodiments, the reference signal V5 has a voltage level in the range of about 0.1Vdd to about 0.42Vdd. In other embodiments, the reference signal V5 may have other voltage levels according to design requirements. In some embodiments, the voltage level of the input signal Vin1 ranges from about -0.2V to about Vdd+0.2V. In other embodiments, the input signal Vin1 may have other voltage levels according to design requirements.

The latch circuit 420 may include two inverters (eg, inverters IN1 and IN2 as shown in FIG. 2D ), where an output terminal of one inverter is connected to an input terminal of the other inverter. As shown in FIG. 2A, latch circuit 420 includes transistors T51, T52, T53, and T54. Transistors T51 and T52 define one inverter, and transistors T53 and T54 define the other inverter. Transistors T51 and T53 are PMOS transistors, and transistors T52 and T54 are N-type metal oxide semiconductor (NMOS) transistors.

The source of transistor T51 is connected to current source 440 (eg, to the drain of transistor T71). The gate electrode of the transistor T51 is connected to the gate electrode of the transistor T52, the drain electrode of the transistor T53 and the drain electrode of the transistor T54. The drain terminal of transistor T51 is connected to the drain terminal of transistor T52. The source of transistor T52 is connected to a common voltage (eg ground). The drain terminal of the transistor T51 and the drain terminal of the transistor T52 can be used as the output terminal Vout3 of the data receiving circuit 200.

The source of transistor T53 is connected 440 to a current source (eg, to the drain of transistor T72). The drain terminal of transistor T53 is connected to the drain terminal of transistor T54. The source of transistor T54 is connected to a common voltage (eg, to ground). The drain terminal of the transistor T53 and the drain terminal of the transistor T54 can be used as the output terminal Vout4 of the data receiving circuit 200.

Equalizer 430 includes transistors T61, T62, T63, T64 and T65. In some embodiments, transistors T61, T62, T63, T64, and T65 are NMOS transistors. The gates of transistors T61, T62, T63, T64 and T65 are connected to each other to receive the equalization signal Veq1. The source of transistor T61 is connected to a common voltage (eg ground). The source of transistor T63 is connected to a common voltage (eg to ground). The source of transistor T64 is connected to a common voltage (eg, to ground). The source of transistor T65 is connected to a common voltage (eg ground). Transistor T62 is connected between transistors T61 and T63.

Current source 440 includes transistors T71 and T72. In some embodiments, transistors T71 and T72 are PMOS transistors. The source of transistor T71 is connected to receive the supply voltage Vdd. The gate of transistor T71 is connected to receive signal V4. The drain of transistor T71 is connected to latch circuit 420 . The source of transistor T72 is connected to receive the supply voltage Vdd. The gate of transistor T72 is connected to receive signal V4, and the drain of transistor T72 is connected to latch circuit 420.

The pulse generator 450 may include an inverter G1, a delay circuit (or buffer) G2, and an OR gate G3. FIG. 2B is a timing diagram illustrating the waveforms of the pulse generator 450 at different nodes according to some embodiments of the present disclosure.

In operation, pulse generator 450 is configured to receive an input having a first logic value (eg, signal V4) with period P1 and to generate an output having a second logic value (eg, signal V3) with period P2 . In some embodiments, the first logic value and the second logic value are the same. For example, as shown in FIG. 2B , the first logical value is 0 and the second logical value is 0. In some embodiments, period P2 is less than period P1. For example, P2 is equal to n×P1, where 0<n<1.

In some embodiments, n may be determined by the delay time of delay circuit G2. As shown in FIG. 2B , at time TG1 , the signal V4 having a logic value “0” (equal to the equalization signal Veq) is input to the pulse generator 450 . Specifically, the signal V4 with a logic value "0" is input to one end of the delay circuit G2 and the OR gate G3 (that is, the signal A). Delay circuit G2 is configured to input the delayed signal to inverter G1. Inverter G1 is configured to generate output signal B having a logic value of "1". The difference between time TG2 and time TG1 is the delay time of delay circuit G2. Therefore, during the period from time TG1 to time TG2, the OR gate G3 is configured to generate the signal V3 with a logic value of “0”.

FIG. 2C is a timing diagram illustrating waveforms at different nodes of the data receiving circuit 200 of FIG. 2A according to some embodiments of the present disclosure.

In some embodiments, before time T5, the data receiving circuit 200 is configured to operate in the equalization phase. At this stage, equalizer 430 is enabled. The equalization signal Veq1 having a high logic level (eg, logic value "1") is input to the gates of transistors T61, T62, T63, T64, and T65 to turn on these transistors. Therefore, voltages Vcom3, Vcom4, Vout3, and Vout4 will be pulled down to a common voltage (eg, ground).

After time T5, the equalization phase is completed, so the equalization signal Veq1 with a low logic level (eg, logic value "0") is input to the gates of transistors T61, T62, T63, T64, and T65, to turn off these transistors. Equalizer 430 is turned off. FIG. 2D illustrates an equivalent circuit of the data receiving circuit 200 operating at this stage according to some embodiments of the present disclosure.

At time T5, the input signal Vin1 having a high logic level (eg, logic value "1") is input to the gate of transistor T43. At the same time, signals V3 and V4 with logic values "0" (for example, during time TG1 and time TG2 in FIG. 2B ) are input to the gates of transistors T41 , T71 and T72 to turn on the transistors T41 , T71 and T72 . The voltage Vtop1 of the drain terminal of the transistor T41 (or the source terminal of the transistor T42 or T43) begins to rise. For example, voltage Vtop1 is pulled high. The drain voltage Vcom3 of the transistor T71 also begins to rise. For example, voltage Vcom3 is pulled high. The drain voltage Vcom4 of the transistor T72 also begins to rise. For example, voltage Vcom4 is pulled high.

Since the voltage of the gate of transistor T43 (such as input signal Vin1) is higher than the voltage of the gate of transistor T42 (such as reference signal V5), the drains of transistors T51 and T52 (or the gates of transistors T53 and T54) Voltage Vout3 also begins to rise. For example, voltage Vout3 is pulled high. After the period of data input (eg, from time T5 to time T6) is completed, the data receiving circuit 200 is configured to operate in the equalization phase again for time period T6.

When operating during the data input period (eg, from time T5 to time T6), if the voltage of the input signal Vin1 is higher than the voltage of the reference signal V5, the data receiving circuit 200 is configured to output a high logic level (eg, logic value "1"); if the voltage of the input signal Vin1 is lower than the voltage of the reference signal V5, the data receiving circuit 200 is configured to output a voltage with a low logic level (eg, logic value "0") Vout3. After the input signal Vin1 is input to the transistor T43 and before the data operation is completed through the latch circuit 420 (for example, after time TG4 as shown in FIG. 2B), the pulse generator 450 is configured to generate a pulse with a logic value "1". Signal V3 turns off transistor T41, thus preventing the circuit from being damaged by a short between Vdd and ground.

According to some embodiments, as shown in FIGS. 2A to 2D , during the data input period, the gates of the transistors T41 , T71 and T72 are inputted with signals having a logic value “0”. In other words, during data input, the gates of transistors T41, T71 and T72 are connected to ground. Therefore, the voltage difference (eg Vsg) between the source and gate of transistor T71 (or transistor T72) is higher than the voltage difference between the source and gate of transistor T12 (or transistor T13) as shown in FIG. 1A. The voltage difference between the two transistors (for example, Vsg) causes the currents I13 and I14 generated by the transistors T71 and T72 to be greater than the currents I11 and I12 generated by the transistors T12 and T13. Compared with the data receiving circuit 100 in FIG. 1A, the data receiving circuit 200 can use larger currents I13 and I14 to charge or discharge parasitic components (eg, resistors, inductors and/or capacitors), which can increase the number of data receiving circuits 200. The response time of the output terminal (for example, voltage Vout3). In other words, the rise time (or fall time) of voltage Vout3 can be reduced. This can increase the tolerance and operating speed of the data receiving circuit 200.

Although the disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the patent scope of the disclosure. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the process, machinery, manufacture, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that they can use existing or future processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein in accordance with the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of the present disclosure.

100: Data receiving circuit 110:Input circuit 120:Latch circuit 130: Equalizer 200: Data receiving circuit 410:Input circuit 420:Latch circuit 430: Equalizer 440: Current source (or current sink) 450:Pulse generator A:signal B: Output signal G1: Inverter G2: Delay circuit G3: OR gate I11: current I12: current I13: current I14: current IN1: inverter IN2: inverter P1:Period P2:Period T1: time T2: time T3: time T4: time T11: transistor T12: Transistor T13: Transistor T21: Transistor T22: transistor T23: Transistor T24: Transistor T31: transistor T32: transistor T33: transistor T34: Transistor T35: transistor T41: transistor T42: transistor T43: Transistor T51: transistor T52: transistor T53: transistor T54: transistor T61: transistor T62: transistor T63: transistor T64: transistor T65: transistor T71: transistor T72: Transistor TG1: time TG2: Time V1: Clock signal V2: Reference signal V3: signal V4: signal V5: Reference signal Vcom1: voltage Vcom2: voltage Vcom3: voltage Vcom4: voltage Vdd: power supply voltage Veq: equalized signal Veq1: equalized signal Vin: input signal Vin1: input signal Vout1: output Vout2: output Vout3: output Vout4: output Vtop: voltage Vtop1: voltage

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1A is a circuit diagram illustrating a data receiving circuit of some embodiments of the present disclosure. FIG. 1B is a timing diagram illustrating timing waveforms at different nodes of the data receiving circuit of FIG. 1A according to some embodiments of the present disclosure. FIG. 1C is a circuit diagram illustrating an equivalent circuit of the data receiving circuit of FIG. 1A according to some embodiments of the present disclosure. FIG. 1D is a circuit diagram illustrating an equivalent circuit of the data receiving circuit of FIG. 1A according to some embodiments of the present disclosure. FIG. 2A is a circuit diagram illustrating a data receiving circuit of some embodiments of the present disclosure. FIG. 2B is a timing diagram illustrating waveforms at different nodes of the data receiving circuit of FIG. 2A according to some embodiments of the present disclosure. FIG. 2C is a timing diagram illustrating waveforms at different nodes of the data receiving circuit of FIG. 2A according to some embodiments of the present disclosure. FIG. 2D is a circuit diagram illustrating an equivalent circuit of the data receiving circuit of FIG. 2A according to some embodiments of the present disclosure.

200: Data receiving circuit

410:Input circuit

420:Latch circuit

430: Equalizer

440:Current source

450:Pulse generator

A:Output signal

B: Output signal

G1: Inverter

G2: Delay circuit

G3: OR gate

I13: current

I14: current

T41: transistor

T42: transistor

T43: Transistor

T51: transistor

T52: transistor

T53: transistor

T54: transistor

T61: transistor

T62: Transistor

T63: transistor

T64: transistor

T65: transistor

T71: transistor

T72: Transistor

V3: signal

V4: signal

V5: Reference signal

Vcom3: voltage

Vcom4: voltage

Vdd: power supply voltage

Veq1: equalized signal

Vin1: input signal

Vout3: output

Vout4: output

Vtop1: voltage

Claims (24)

A data receiving circuit, including: a data input circuit configured to receive an input signal, wherein the data input circuit includes a first input terminal and a second input terminal, the first input terminal configured to receive a reference voltage , the second input terminal is configured to receive the input signal; a latch circuit is configured to output an output signal in response to the input signal, wherein the latch circuit is configured to when a voltage of the input signal is less than the When the reference voltage is used, the output signal having a low logic value is output; a current source configured to provide a current to the latch circuit, wherein the current source is different from the data input circuit; and a pulse generator electrically connected to the data input circuit and configured to receive a first signal and generate a second signal in response to the first signal, wherein a period of the first signal is greater than a period of the second signal, wherein when the data input When the circuit is configured to receive the input signal, the first signal is used to turn on the current source, the second signal is used to turn on the data input circuit, and before a latch operation of the latch circuit is completed. , the second signal is used to close the data input circuit. The data receiving circuit of claim 1, wherein the latch circuit is configured to output the output signal with a high logic value when a voltage of the input signal is greater than the reference voltage. The data receiving circuit as claimed in claim 1, wherein a logical value of the first signal is consistent with the third The two signals have different logical values. The data receiving circuit of claim 1, wherein the period of the second signal is approximately one-third of the period of the first signal. The data receiving circuit of claim 1, wherein the current source is configured to provide the current to the latch circuit without flowing through the data input circuit. The data receiving circuit of claim 1, further comprising an equalizer configured to connect an output terminal of the latch circuit and an output terminal of the current source to land. A data receiving circuit includes: a first transistor, a gate of which is configured to receive an input signal; a latch circuit configured to output an output signal in response to the input signal; a second transistor, There is a gate and a drain, the gate is configured to receive a first signal, the drain is connected to the latch circuit; and a third transistor has a gate and a drain, the gate Configured to receive the first signal, the drain is connected to the latch circuit; wherein the second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal. The data receiving circuit as described in claim 7 further includes a fourth transistor, a gate of which is Configured to receive a reference signal, wherein the latch circuit is configured to output the output signal having a high logic value when a voltage of the input signal is greater than a reference voltage. The data receiving circuit of claim 8, further comprising a fifth transistor having a gate and a drain, the gate being connected to receive a second signal, and the drain being connected to the first transistor and a source electrode of the fourth transistor. The data receiving circuit of claim 9, wherein a period of the second signal is approximately one-third of a period of the first signal. The data receiving circuit of claim 9 further includes a pulse generator configured to receive the first signal and generate the second signal. The data receiving circuit of claim 11, wherein the pulse generator includes: an inverter having an input terminal to receive the first signal; a delay circuit having an input terminal to receive the first signal; and An OR gate has a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to an output terminal of the inverter, and the second input terminal is connected to an output terminal of the delay circuit. An output terminal is connected, and the OR gate is configured to generate the second signal. The data receiving circuit of claim 12, wherein the input terminal of the inverter and the input terminal of the delay circuit are connected to the gate of the second transistor and the gate of the third transistor. The data receiving circuit as claimed in claim 13, wherein the output terminal of the OR gate is connected to the gate of the fifth transistor. The data receiving circuit of claim 9, wherein when the first transistor is configured to receive the input signal, the first signal is used to turn on the second transistor and the third transistor. The data receiving circuit of claim 15, wherein when the first transistor is configured to receive the input signal, the first signal is used to turn on the fifth transistor. The data receiving circuit of claim 16, wherein the first signal is used to turn off the fifth transistor before a latch operation of the latch circuit is completed. The data receiving circuit of claim 7, wherein the latch circuit includes: a sixth transistor, a source electrode of which is connected to the drain electrode of the second transistor; and a seventh transistor, a source electrode of which The drain electrode of the third transistor is connected; wherein a gate electrode of the sixth transistor is connected to a drain electrode of the first transistor. The data receiving circuit of claim 18, wherein the latch circuit includes: an eighth transistor having a drain and a gate, the drain being connected to the drain of the sixth transistor, and the gate The gate electrode of the sixth transistor is connected; and a ninth transistor has a drain electrode and a gate electrode, the drain electrode is connected to the drain electrode of the seventh transistor, and the gate electrode is connected to the seventh transistor. The gate is connected. The data receiving circuit of claim 19, wherein the drain of the sixth transistor and the drain of the eighth transistor are configured to output the output signal. The data receiving circuit of claim 7 further includes an equalizer configured to connect an output end of the latch circuit to ground when the equalizer is enabled. The data receiving circuit of claim 21, wherein the equalizer includes: a tenth transistor having a source and a drain, the source is connected to the ground, and the drain is connected to the second transistor. The drain electrode is connected; and an eleventh transistor has a source electrode and a drain electrode, the source electrode is connected to the ground, and the drain electrode is connected to the drain electrode of the third transistor. The data receiving circuit of claim 22, wherein the equalizer includes a twelfth transistor, the twelfth transistor has a gate, a source and a drain, and the gate is connected to the tenth transistor. A gate electrode of the transistor is connected to a gate electrode of the eleventh transistor, the source electrode is connected to the ground, and the drain electrode is connected to the drain electrode of the first transistor. The data receiving circuit of claim 7, wherein the first transistor is disconnected from the second transistor and the third transistor.