TW202312644A - Half-bridge flyback power converter and control method thereof - Google Patents

Abstract

A half-bridge flyback power converter: a first transistor, a second transistor and a third transistor which form a half-bridge circuit. The first transistor is turned on for generating a negative circulated current for achieving zero voltage switching of the second transistor. The second transistor is turned on for magnetizing a transformer. The third transistor is turned on during a demagnetized time period to generate an output voltage. The physical size of the first transistor is smaller than physical size of the third transistor.

Description

Half-bridge flyback converter and its control method

The invention relates to a half-bridge flyback converter, in particular to an asymmetrical half-bridge flyback converter. The present invention also relates to a control method for controlling an asymmetrical half-bridge flyback converter.

Please refer to FIG. 1. FIG. 1 shows an asymmetrical duty cycle flyback converter (Asymmetrical Duty Cycle Flyback Converter) of the prior art US Patent No. 5,959,850. This prior art discloses a zero voltage switching (ZVS) Half-bridge flyback converter to achieve higher power efficiency. ZVS can be defined as switching a transistor on when the voltage across the transistor (eg, drain-to-source voltage) is zero or close to zero. However, the disadvantage of the prior art is that the power conversion efficiency of the power converter is low in the light load state.

Another disadvantage of the above-mentioned prior art is that the output voltage of the power converter is not variable. Specifically, if the above-mentioned prior art is to be changed to a ZVS flyback converter with a variable output voltage, it must be changed by Detect the demagnetization period of the transformer and control the switching of the transformer.

Another prior art US patent US 7,151,681 is a multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer (Multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer). This prior art discloses a method for detecting the output voltage and discharge time of a transformer. The method of demagnetization period, however, cannot achieve ZVS of the power converter in the present prior art, which is used for discontinuous conduction mode (DCM) operation.

FIG. 2 shows a waveform diagram of a prior art half-bridge flyback converter operating in discontinuous conduction mode in a light load state. The driving signal SH is used to drive the upper switch of the half-bridge flyback converter to excite the transformer, and the driving signal SL is used to drive the lower switch of the half-bridge flyback converter. The signal waveform of the exciting current IM shows that the transformer operates at discontinuous conduction mode. When the output power of the half-bridge flyback converter decreases, the pulse width PW of the drive signal SH decreases due to the feedback control of the half-bridge flyback converter, and the pulse width of the drive signal SL also decreases accordingly. Therefore, the half-bridge As the switching frequency of the flyback converter increases, the switching losses also increase. After the driving signal SH turns to a low level (off), the first pulse of the driving signal SL is enabled during the demagnetization period of the transformer. The second pulse of the driving signal SL is enabled to generate a circulating current, thereby achieving zero-voltage switching of the high-side switch.

The disadvantage of the above-mentioned prior art is that when operating in the discontinuous conduction mode, the driving signal SL needs to be switched on/off twice in one switching cycle, so the average switching frequency of the driving signal SL is greatly increased, resulting in a large amount of switching loss and resulting in Energy dissipation in the lower side switch.

Compared with the prior art US Pat. No. 7,151,681, the present invention provides a resonant half-bridge flyback converter with omitted period to improve the power efficiency in the middle-load and light-load operation states.

Compared with the prior art U.S. Patent US 5,959,850, the present invention provides a method for generating a demagnetization signal and a switching control circuit, wherein the period of the demagnetization signal is equal to the demagnetization period of the transformer, and the present invention can be used for a zero voltage transformer with a programmable output voltage Voltage switching flyback converters such as USB PD power converters.

Compared with the prior art shown in FIG. 2, the present invention provides a control circuit for an asymmetrical half-bridge (AHB) flyback converter, which uses three transistors to improve the power in the operating states of medium load and light load. conversion efficiency.

Regarding one of the viewpoints, the present invention provides a half-bridge flyback converter, comprising: a first transistor controlled by a first signal; a second transistor controlled by a second signal; a third The transistor is controlled by a third signal, wherein the first transistor, the second transistor and the third transistor are used to form a half-bridge circuit; and a switching control circuit is used according to the half-bridge flyback The first signal is generated by an input voltage of the converter, the third signal is generated by an output voltage of the half-bridge flyback converter, and the second signal is generated by a feedback signal, wherein the feedback The signal is related to the output voltage of the half-bridge flyback converter; wherein in a discontinuous conduction mode (discontinuous conduction mode, DCM) operation, the switching control circuit operates in a first switching period to control the The first signal turns on the first transistor in a first period, wherein after the first period, the switching control circuit controls the first signal, the second signal and the third signal in a first non-conduction period , turn off the first transistor, the second transistor and the third transistor, wherein after the first non-conduction period, the switching control circuit controls the second signal to turn on the The second transistor, wherein after the second period, the switching control circuit controls the first signal, the second signal and the third signal to turn off the first transistor, the third signal in a second non-conduction period. The second transistor and the third transistor, wherein after the second non-conduction period, the switching control circuit controls the third signal to conduct the third transistor in a third period, wherein the third period passes Afterwards, the switching control circuit controls the first signal, the second signal and the third signal to turn off the first transistor, the second transistor and the third transistor in a third non-conducting period.

In a preferred embodiment, the first transistor is turned on to generate a circulating current, wherein the circulating current is used to achieve zero voltage switching (ZVS) of the second transistor in the discontinuous conduction mode of operation. ZVS).

In a preferred embodiment, the second transistor is turned on to energize a transformer of the half-bridge flyback converter.

In a preferred embodiment, the third transistor is turned on during a demagnetization period of the transformer.

In a preferred embodiment, the first transistor and the third transistor are configured as lower bridge transistors of the half-bridge flyback converter, and the second transistor is configured as the half-bridge flyback converter The bridge transistor above the device.

In a preferred embodiment, the half-bridge flyback converter further includes a timer, wherein the timer is used to time the third non-conduction period; wherein when the output power of the half-bridge flyback converter decreases, the third non-conduction period counted by the timer increases correspondingly.

In a preferred embodiment, the actual size of the first transistor is smaller than the actual size of the third transistor.

In a preferred embodiment, wherein: the amplitude of the first signal is lower than the amplitude of the third signal; and/or a maximum rating related to the gate of the first transistor is lower than A maximum rating associated with the gate of the third transistor.

From another point of view, the present invention also provides a control method for controlling a half-bridge flyback converter, wherein the half-bridge flyback converter includes a first transistor, a second transistor and a first Three transistors, the control method includes: generating a first signal to drive the first transistor according to an input voltage of the half-bridge flyback converter; generating a second signal to drive the first transistor according to a feedback signal driving the second transistor, wherein the feedback signal is related to an output voltage of the half-bridge flyback converter; and generating a third signal to drive the third transistor according to the output voltage; wherein driving the The steps of the first transistor, the second transistor and the third transistor include: in a discontinuous conduction mode of operation, controlling the first transistor to be turned on in a first period; after the first period , controlling the first transistor, the second transistor and the third transistor to be turned off in a first non-conducting period; after the first non-conducting period, controlling the second transistor to be in a second period conduction; after the second period, control the first transistor, the second transistor and the third transistor to be turned off in a second non-conduction period; after the second non-conduction period, control the The third transistor is turned on in a third period; and after the third period, the first transistor, the second transistor and the third transistor are controlled to be turned off in a third non-conduction period.

In a preferred embodiment, the control method further includes: generating a circulating current by turning on the first transistor to achieve zero voltage switching (Zero) of the second transistor in the discontinuous conduction mode of operation. Voltage Switching, ZVS).

In a preferred embodiment, a transformer of the half-bridge flyback converter is energized by turning on the second transistor.

In a preferred embodiment, the third transistor is turned on during a demagnetization period of the transformer.

In a preferred embodiment, the first transistor and the third transistor are lower bridge transistors of the half-bridge flyback converter, and the second transistor is a lower bridge transistor of the half-bridge flyback converter. Upper bridge transistor.

In a preferred embodiment, the control method further includes: when the output power of the half-bridge flyback converter decreases, correspondingly increasing the third non-conduction period.

In a preferred embodiment, the actual size of the first transistor is smaller than the actual size of the third transistor.

In a preferred embodiment, the amplitude of the first signal is lower than the amplitude of the third signal.

In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

The diagrams in the present invention are all schematic and mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. As for the circuits, signal waveforms and frequencies, they are not drawn to scale.

FIG. 3 shows a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-bridge flyback converter 300 includes: a first transistor 30 and a second transistor 40 for forming a half-bridge circuit. The transformer 10 and the resonant capacitor 20 are connected in series with each other and coupled to the switching node LX of the half-bridge circuit. The transformer 10 includes a primary winding NP, a secondary winding NS and an auxiliary winding NA, wherein the primary winding NP and the secondary winding NS have Turn ratio n, the secondary side winding NS and the auxiliary winding NA have a turn ratio m. The primary-side controller 200 generates the driving signal SH and the driving signal SL, and the driving signal SH and the driving signal SL switch the transformer 10 through the half-bridge circuit to generate the output voltage VO on the secondary side of the transformer 10 . The driving signal SH drives the first transistor 30 to excite the transformer 10 . The driving signal SL turns on the second transistor 40 during the demagnetization and resonance period of the transformer 10, and the driving signal SL is also used to turn on the second transistor 40 to generate a circulating current flowing through the transformer 10 to achieve the first transistor 30. Zero voltage switching. The resistor 60 generates a current sensing signal VCS by detecting the primary side switch current IP of the transformer 10 .

The driving signal SH and the driving signal SL are generated according to the feedback signal VFB, wherein the feedback signal VFB is generated according to the output power of the resonant half-bridge flyback converter 300 . The secondary side controller 100 is coupled to the output voltage VO to generate a feedback signal VFB, and the feedback signal VFB is coupled to the primary side controller 200 through the optocoupler 90 . The secondary-side controller 100 is also used to generate the driving signal SG to drive the secondary-side synchronous rectifier 70 during the demagnetization period TDS of the transformer 10 . The auxiliary winding NA generates an auxiliary winding signal VNA when the transformer 10 is switched. The resistors 51 and 52 are used to attenuate the auxiliary winding signal VNA to generate an auxiliary signal VAUX. The auxiliary signal VAUX is coupled to the primary side controller 200 . In one embodiment, the resistor 55 is coupled to the primary side controller 200 , and the demagnetization signal Sdmg is generated by setting parameters through the resistor 55 .

FIG. 4 shows an operation waveform corresponding to the embodiment of FIG. 3 . When the driving signal SH is turned on, the transformer 10 is excited and generates an excitation current IM. When the driving signal SH is not turned on, the transformer 10 is demagnetized. During the demagnetization period TDS, the transformer 10 generates a secondary side switching current IS, and the driving signal SL is related to the demagnetization period TDS of the transformer 10 . In one embodiment, the conduction period TSL (ie, the pulse width) of the driving signal SL is equal to or longer than the demagnetization period TDS of the transformer 10 , thereby preventing the transformer 10 from operating in a continuous conduction mode (CCM). During the demagnetization period TDS of the transformer 10 , a reflected voltage VX is generated on the resonant capacitor 20 , wherein the relationship between the reflected voltage VX and the output voltage VO is: VX=n*VO.

When the driving signal SH is off, the driving signal SL can be turned on, and when the driving signal SL is off, the driving signal SH can be turned on. Between the driving signal SH and the driving signal SL (that is, when the driving signal SH and the driving signal SL are both non-conductive) may include a dead time (eg, a period TRH, a period TRL).

Details of the operations in different periods of time in FIG. 4 are detailed in the following description.

The time period from time point t1 to time point t2 is the exciter transformer cycle. In this time period, the first transistor 30 is turned on and the second transistor 40 is turned off. The primary switching current IP flowing through the transformer 10 increases and the voltage of the resonant capacitor 20 also increases. , at this time the transformer 10 is excited and the resonant capacitor 20 is charged, the secondary side synchronous rectifier 70 is turned off and its body diode 75 is reverse biased, therefore, no energy is converted to the secondary side at this time.

The time period from time point t2 to time point t3 is the first circulating current period. In this period, both the first transistor 30 and the second transistor 40 are turned off, and the circulating current of the transformer 10 forces the switching node voltage VHB of the half-bridge circuit to drop until the second until the body diode 45 of the transistor 40 is turned on. The period from time t2 to time t3 corresponds to a quasi-resonant period to achieve zero-voltage switching of the second transistor 40 . At this time, the primary side voltage of the transformer 10 is the same as the voltage of the resonant capacitor 20 at time t3 .

The period from time point t3 to time point t4 is the resonant cycle (positive current). In this period, in the state of zero voltage switching, the first transistor 30 is turned off and the second transistor 40 is turned on. At this time, the output voltage VO is equal to the resonance capacitance The transvoltage Vcr of 20 is divided by the turns ratio n, the current starts to flow through the secondary side synchronous rectifier 70, and the energy stored in the transformer 10 is converted to the output terminal to generate the output voltage VO. Since the leakage inductance Lr of the transformer 10 and the resonant capacitor 20 (Cr) form an LC tank, the secondary side current is in the form of a sine wave in a period determined by the resonant frequency Lr and Cr. The primary side current of the transformer 10 is the sum of the excitation current IM and the secondary side switching current IS. The current flowing through the resonant tank (Lr, Cr) is still a positive current, which is mainly driven by the magnetizing inductance of the transformer 10 and flows through the resonant capacitor 20 .

The time period from time point t4 to time point t5 is the resonant period (negative current). During this period, the first transistor 30 continues to be turned off and the second transistor 40 continues to be turned on. The energy is continuously converted to the secondary side, but the current in the resonant tank is absorbed by the resonant capacitor The voltage of 20 is reverse driven, and the energy of the resonant capacitor 20 is not only converted to the secondary side, but also used to pull the excitation current level of the transformer 10 when the second transistor 40 is continuously turned on (for example, from time point t4 to time point t5). to a negative value.

The period from time point t5 to time point t6 is the reverse excitation transformer cycle (negative current). In this period, from the end of the demagnetization period TDS of the transformer 10 to when the second transistor 40 is turned off, the resonant capacitor 20 reversely excites the transformer 10, and produce a negative current.

The time period from time point t6 to time point t7 is the second circulating current period. During this time period, both the first transistor 30 and the second transistor 40 are turned off, and the negative current of the transformer 10 is induced from time point t5 to time point t6 to force The switching node voltage VHB on the switching node LX in the half-bridge circuit increases until it turns on the body diode 35 of the first transistor 30 .

After the time point t7, another period similar to the period from the time point t1 to the time point t2 starts, the first transistor 30 is turned on under the zero voltage switching state and the second transistor 40 is turned off, if the circulating current in the transformer resonant tank is still negative current, the excess energy in the resonant tank will be sent back to the input (the node supplying the input voltage VIN).

In the light load state, when the output power decreases, the pulse width of the driving signal SH and the driving signal SL will decrease correspondingly, so the switching frequency of the driving signal SH and the driving signal SL increases under the light load state, due to the core loss ( core loss), switching loss (switching loss) and other power losses increase, resulting in poor power conversion efficiency of the power converter.

FIG. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL. One way to improve the power efficiency is to reduce the switching frequency by prolonging the time between turning off the driving signal SL (such as time point t3) and turning on the driving signal SH (such as time point t5). However, turning off the driving signal SL will Circulating current is generated, thereby causing a voltage surge VPK of the switching node voltage VHB and a voltage drop VDP of the auxiliary signal VAUX. The voltage surge VPK and the voltage drop VDP will cause power loss and noise.

It should be noted that the turning on or off of the driving signal SH and the driving signal SL respectively correspond to the turning on or off of the first transistor 30 and the second transistor 40 .

FIG. 6 shows an operating waveform diagram of an embodiment of the resonant half-bridge flyback converter with omitted periods of the present invention.

Please refer to FIG. 6 , in one embodiment, the driving signal SH is turned on during the excitation cycle of the excitation transformer 10 (for example, from time point t1 to time point t2 ), so as to excite the transformer 10 . After the drive signal SH is turned off, the drive signal SL is turned on during the resonance period (for example, from time point t2 to time point t3), and has a resonance pulse (for example, from time point t2 to time point t3). One excitation cycle and one resonance cycle form a switching cycle ( For example, time point t1 to time point t3).

As shown in FIG. 6, in one embodiment, the omission period Tx starts at the non-conduction time point when the drive signal SH turns non-conduction (such as time point t4), and when the omission period Tx ends (such as time point t6), the drive signal SH SL turns on. In one embodiment, when the output power is reduced due to power saving, the skipping period Tx will correspondingly increase (ie, the switching frequency will decrease).

Please continue to refer to FIG. 6 , compared to the period without skipped periods, such as time point t1 to time point t3, the driving signal SL is not conducted during the skipped period (such as Tx) and there is no resonant pulse. For example, in the prior art, A pulse wave of the drive signal SL from time point t4 to time point t5, that is, a resonant pulse wave of the drive signal SL, has been omitted in this embodiment, as shown in FIG. At time t6), there is no negative circulation current. In the prior art, the voltage surge VPK generated by switching the node voltage VHB and the voltage drop VDP generated by the auxiliary signal VAUX are also avoided in this embodiment. In one embodiment, as shown in FIG. 6 , the driving signal SH is also in a non-conductive state during the omitted period (such as Tx).

In one embodiment, after the driving signal SH is turned off, during a part of the omitted period (for example, a part of the time between time point t4 and time point t5), a part of the demagnetization current of the transformer 10 flows through the second Body diode 45 of transistor 40 . In other words, in one embodiment, there is no double pulses in the driving signal SL. In one embodiment, there is no double pulse in the driving signal SH. From a point of view, after a single pulse of the driving signal SH, a single pulse of the driving signal SL is generated, and after a single pulse of the driving signal SL, a single pulse of the driving signal SH is generated, even if the resonant half-bridge The same goes for flyback converters operating with omitted periods. From another point of view, between two consecutive pulses of the driving signal SH, the driving signal SL includes at most one pulse, and between two consecutive pulses of the driving signal SL, the driving signal SH includes at most one pulse .

In one embodiment, when the output power is lower than a predetermined threshold, an omission period Tx is generated. In one embodiment, the omission period Tx increases correspondingly as the output power decreases. In one embodiment, even if the driving signal SL cannot achieve zero-voltage switching of the first transistor 30, the second driving signal does not include the second pulse between two consecutive pulses of the first driving signal , so the zero-voltage switching of the first transistor 30 is not achieved with the second pulse.

Please continue to refer to FIG. 6 , in one embodiment, the zero-voltage switching pulse (such as PZV) of the driving signal SL turns on the second transistor 40 after the omission period elapses, so as to achieve a zero-voltage switching period (such as time point t6 to time point t7 ).

As shown in FIG. 6 , in one embodiment, at least one switching cycle (for example, time point t7 to time point t9 ) is generated after the zero-voltage switching pulse PZV after the cycle is omitted.

Please continue to refer to FIG. 6 , in one embodiment, the resonant period may include a continuation of the zero-voltage switching period (for example, time point t3' to time point t3), and the continuation of the zero-voltage switching period is used to achieve zero-voltage switching of the first transistor 30. In other words, in this embodiment, the first part of the resonant pulse wave (such as time point t2 to time point t3') is used to achieve the resonance between the transformer 10 and the resonant capacitor 20, and the second part of the resonant pulse wave (such as time point t3' to time point t3 ) is used to generate circulating current to achieve zero-voltage switching of the first transistor 30 .

FIG. 7 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the primary controller 200 includes a timer 25 and a control element 240 . In one embodiment, the control element 240 is used to generate the driving signal SH and the driving signal SL according to the input voltage VIN (via the auxiliary signal VAUX) and the feedback signal VFB, and the timer 25 is used to generate the aforementioned skip period Tx.

As shown in Figure 7, in one embodiment, the timer 25 judges whether the output power is lower than the preset threshold according to the information related to the output power, and when the output power is judged to be lower than the preset threshold, the timer 25 starts Calculate the omission period Tx, and control the control element 240 to omit the pulses of the driving signal SH and the driving signal SL in the omission period Tx.

Please refer to Figure 4 again. When the resonant half-bridge flyback converter is in the middle-load or light-load state, the resonant period from time point t4 to time point t5 is short and cannot generate enough negative current (energy) to achieve zero-voltage switching , Therefore, the main part of the negative current is from the current generated from time point t5 to time point t6.

However, higher negative current will lead to higher power loss. In order to control the negative current to achieve zero voltage switching at an appropriate level, the control of the demagnetization period must be accurate, so it is necessary to generate the demagnetization signal Sdmg corresponding to the transformer 10 Demagnetization period TDS.

FIG. 8 shows a block diagram of an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the primary controller 208 includes a demagnetization simulator 250 and a control element 248 . In one embodiment, the control element 248 is used to generate the driving signal SH and the driving signal SL according to the input voltage VIN (via the auxiliary signal VAUX) and the feedback signal VFB, and the demagnetization simulator 250 is used to generate the demagnetization related signal. The demagnetization signal Sdmg is generated to simulate the demagnetization period TDS, wherein the demagnetization-related signals such as the reflected voltage of the transformer 10 (via the auxiliary signal VAUX).

Please refer to FIG. 9 at the same time. FIG. 9 shows the operation waveform diagram of the demagnetization signal generated by the demagnetization simulator of the present invention.

In the switching period, the resonant half-bridge flyback converter operates periodically in the discontinuous conduction mode (for example, from time point ta to time point tc'), and the driving signal SH first turns on the first transistor 30 to excite the transformer 10 to generate The primary side switch current IP (for example, from time point ta' to time point tb), after the first transistor 30 is turned off, the driving signal SL is used to conduct in the resonant period (from time point tb to time point tc) (for example, from time point tb to time point tc' ) the second transistor 40 for generating a circulating current (for example from time point tc to time point tc′) to achieve zero-voltage switching of the first transistor 30 . In the switching period of the non-discontinuous conduction mode, the conduction period TSL of the driving signal SL (such as time point tb to time point tc') is determined by the pulse width of the demagnetization signal Sdmg (such as TDSX'), wherein the demagnetization signal Sdmg is determined by the demagnetization signal Sdmg The magnetic simulator 250 is generated from corrections in the previously forced inserted discontinuous conduction mode. In one embodiment, the conduction period TDSX' of the demagnetization signal Sdmg is corrected during the previous actively forced discontinuous conduction mode, and is used to make the control element 248 control the minimum conduction time of the second transistor 40, thereby in the second transistor 40 During the discontinuous conduction mode after a transistor 30 is turned off, the transformer 10 is demagnetized. In one embodiment, as shown in FIG. 9 , the conduction period TSL of the driving signal SL (for example, from the time point tb to the time point tc') can be the conduction period TDSX' of the demagnetization signal Sdmg plus a delay time (for example, from the time point tc to the time point tc′) to establish a negative circulation current on the primary side switch current IP after the demagnetization period, so as to achieve zero-voltage switching of the first transistor 30 .

It should be noted that the non-discontinuous conduction mode refers to the operation mode that is not discontinuous conduction mode, such as: continuous conduction mode (continuous conduction mode, CCM), or quasi-resonant mode (quasi-resonant mode, QRM) operation, accurate The resonant mode is also called boundary conduction mode (boundary conduction mode, BCM).

In one embodiment, when the primary-side switch current IP has a preset number (such as a positive integer NC) of switching cycles (such as time point ta to time point t1) and operates in a non-discontinuous conduction mode (such as quasi-resonant mode) , at least one switching period is actively forced to operate in the discontinuous conduction mode (for example, time point t1 to time point t3). Therefore, the demagnetization simulator 250 is used to correct the conduction period TDSX of the demagnetization signal Sdmg according to the demagnetization period TDS of the transformer 10 in the forced insertion discontinuous conduction mode.

As shown in FIG. 9 , in the forced-inserted discontinuous conduction mode, the demagnetization period TDS of the transformer 10 starts from the rising edge of the auxiliary signal VAUX and ends between the auxiliary signal VAUX (such as time point t2 to time point t3 ). The falling edge (i.e. knee point kn) ends. Specifically, in this embodiment, the reflected voltage can be detected by sensing the auxiliary signal VAUX, which comes from the auxiliary winding NA of the transformer 10 during the off period of the first transistor 30 . The duration of the reflected voltage, that is, the pulse width of the auxiliary signal VAUX from the rising edge to the knee point kn, is related to the demagnetization period TDS of the transformer 10 .

In one embodiment, the primary-side controller 208 further includes a cycle counter 260. The cycle counter 260 is used to calculate the number of switching cycles operating in the discontinuous conduction mode according to the primary-side switch current IP, and when the primary-side switch current IP is When it is determined that there have been a predetermined number of switching cycles without operating in the discontinuous conduction mode, the cycle counter 260 is used to control the control element 248 to actively force the operation in the discontinuous conduction mode. In one embodiment, the cycle counter 260 can sense the primary side switch current IP through the current sensing signal VCS, so as to determine the operation in the non-discontinuous conduction mode.

In one embodiment, as shown in FIG. 9, during the forced discontinuous conduction mode switching period, the driving signal SL continuously controls the second transistor 40 to be non-conductive, so that the half-bridge circuit not only operates in the discontinuous conduction mode, but also operates In the asynchronous switching mode, during the forced discontinuous conduction mode switching period, a part of the demagnetization current (eg IP from time point t2 to time point t2 ′) of the transformer 10 flows through the body diode 45 of the second transistor 40 .

Please continue to refer to FIG. 9, after the discontinuous conduction mode DCM (such as time point t4 to time point t5), the first pulse wave of the driving signal SL conducts the second transistor 40 to excite the transformer 10 from the resonant capacitor 20 to the transformer 10, and then A negative circulating current (IP from time point t4 to time point t5 ) is generated to achieve zero-voltage switching of the first transistor 30 .

FIG. 10 shows a schematic diagram of a specific embodiment of a demagnetization simulator for generating a demagnetization signal Sdmg according to the present invention. In one embodiment, the demagnetization simulator 250 includes a timing generator 205 , a comparator 280 and a logic circuit 285 .

In one embodiment, the timing generator 205 includes an integrator. The integrator is composed of a switch 231 and a capacitor 230. The switch 231 is controlled by the sampling signal SMP. The sampling signal SMP is related to the driving signal SH to sample the current sensing signal VCS. The discharge current ID is related to n*VO, and is used to discharge the voltage VC across the capacitor 230 . The cross voltage VC is compared with the reference voltage Vref by the comparator 280 . The logic circuit 285 generates the demagnetization signal Sdmg according to the comparator output CPO and the sampling signal SMP corresponding to the driving signal SH. In one embodiment, the reference voltage Vref is 0 volts, and when the primary side switch current IP is 0, the current sensing voltage VCS is 0.

In one embodiment, the duration of the demagnetization signal Sdmg is related to the voltage level (Vinx) of the input voltage of the transformer 10, that is, as shown in FIG. 3, the coupling node NNP between the primary winding NP and the resonant capacitor 20 The voltage of the demagnetization signal Sdmg is also related to the voltage level of the output voltage of the transformer 10 (for example, n*VO) and the excitation period (TW) of the transformer 10 when the first transistor 30 is turned on. It should be noted that the voltage level Vinx of the input voltage of the transformer 10 is equal to the input voltage VIN minus the cross voltage Vcr of the resonant capacitor 20 .

According to the demagnetized magnetic flux of the transformer 10 is equal to the excited magnetic flux of the transformer 10, the following formula 1 can be listed:

Vinx*TW = n*VO*TDS (Formula 1)

Where TW is the appearance time of the voltage level Vinx of the input voltage of the transformer 10 during the excitation period of the transformer 10 ; n*VO is the voltage of the transformer 10 during the demagnetization period TDS of the transformer 10 . n is the turns ratio of the primary side winding NP and the secondary side winding NS, and VO is the voltage (ie output voltage) of the secondary side winding NS.

After the transformer 10 is energized, the level VCSp of the current sensing signal VCS is related to the peak value of the primary side switch current IP at the end of the energization process, and is generated on the resistor 60 shown in FIG. 3 , which can be represented by the following formula 2:

VCSp = (Vinx/L)*TW*Rs (Formula 2)

Where L is the inductance of the primary winding NP of the transformer 10, Rs is the resistance value of the resistor 60, and VCSp is the voltage level of the transformer 10 at the end of the excitation process.

Let ID=n*VO/Rt, where Rt is the resistance value of the resistor 55 .

The pulse width TDSX of the demagnetization signal Sdmg can be expressed as:

TDSX = (C*VCSp)/ID, where C is the capacitance of the capacitor 230 .

TDSX = (Rt*C*VCSp)/(n*VO)

TDSX = (Rt*C/(n*VO))*(Rs/L)*Vinx*TW

Let Rt = L/(Rs*C)

TDSX = (Vinx*TW)/(n*VO) (Formula 4)

When the condition of Equation 3 is satisfied, the conduction period TDSX of the demagnetization signal Sdmg shown in Equation 4 is equal to the demagnetization period TDS of the transformer 10 .

Please continue to refer to FIG. 10 , the switch 231 is turned on to sample the current sensing signal VCS to the capacitor 230, and when the switch 231 is turned off (that is, when the excitation ends), the level VCSp of the current sensing signal VCS is kept at the capacitor 230, The switch 231 is controlled by the sampling signal SMP. When the switch 231 is turned off, the demagnetization signal Sdmg is enabled (for example by the logic circuit 285 ), in other words, when the demagnetization signal Sdmg starts to be enabled, the voltage VC across the capacitor 230 is the peak value of the current sensing signal VCS. After the switch 231 is turned off, the discharge current ID starts to discharge the capacitor 230. When the capacitor 230 is fully discharged (VC=0V) through the discharge current ID (ID=n*VO/Rt), the demagnetization signal Sdmg is disabled. The resistor 55 shown in FIG. 10 and FIG. 3 is used to set the preset pulse width of the demagnetization signal Sdmg.

In one embodiment, in the forcedly inserted discontinuous conduction mode switching period, the pulse width TDSX of the demagnetization signal Sdmg can be compared with the demagnetization period TDS indicated by the pulse width of the auxiliary signal VAUX by the demagnetization simulator 250 Therefore, the pulse width TDSX of the demagnetization signal Sdmg can be corrected for the next DCM switching period. In one embodiment, the demagnetization simulator 250 is further used to adjust the resistance value of the resistor 255 according to the demagnetization period TDS detected in the discontinuous conduction mode, so as to correct the pulse period TDSX of the demagnetization signal Sdmg.

In other embodiments, in addition to adjusting the resistance value of the resistor 255, the demagnetization simulator 250 can also correct the pulse period TDSX of the demagnetization signal Sdmg in the following manner: adjust the voltage threshold Vth to determine the end of the demagnetization signal Sdmg , or adjust the capacitance of the capacitor 230, or adjust, for example, the ratio of the current mirror formed by the transistor 271 and the transistor 272 in FIG. 10 .

FIG. 11 shows a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-bridge flyback converter 900 is similar to the resonant half-bridge flyback converter 300 of FIG. 3 . In this embodiment, the resonant half-bridge flyback converter 900 includes a first transistor M1, a second transistor M2 and a third transistor M3, and the first transistor M1, the second transistor M2 and the third transistor M3 is used to form a half-bridge circuit. From a viewpoint, the first transistor M1 and the third transistor M3 are configured as the lower bridge transistors of the resonant half-bridge flyback converter 900, and the second transistor M2 is configured as the resonant half-bridge flyback converter 900 above the bridge transistor.

According to the feedback signal VFB and the input voltage VIN, the primary side controller 201 is used to generate the first driving signal S1, the second driving signal S2 and the third driving signal S3, the first driving signal S1, the second driving signal S2 and the third driving signal The driving signal S3 is coupled to switch the transformer 10 through the half-bridge circuit, thereby generating the output voltage VO on the secondary side of the transformer 10 . The second driving signal S2 drives the second transistor M2 to excite the transformer 10. The third driving signal S3 turns on the third transistor M3 during the demagnetization and resonance periods of the transformer 10. The third driving signal S3 is also used to turn on the third transistor M3. The transistor M3 is used to generate a circulating current flowing through the transformer 10 and achieve zero-voltage switching of the second transistor M2 in a heavy load state. In other words, the second transistor M2 is the primary-side upper bridge switch of the resonant half-bridge flyback converter 900 and may correspond to the first transistor 30 in FIG. 3 , and the third transistor M3 is the resonant half-bridge flyback converter. 900 is a primary side lower bridge switch and may correspond to the second transistor 40 in FIG. 3 . From a point of view, the first transistor M1 is connected in parallel with the third transistor M3 and serves as an auxiliary primary-side low-bridge switch, and has an independent control signal S1.

In one embodiment, the third transistor M3 is controlled during the demagnetization and resonance period of the transformer 10 after the transformer 10 is excited by turning on the second transistor M2 when operating in the discontinuous conduction mode under light load conditions. for conduction. After demagnetization, when the third transistor M3 is continuously turned off, the first driving signal S1 is used to turn on the first transistor M1 to generate a circulating current flowing through the transformer 10 to achieve zero-voltage switching of the second transistor M2 ,. Therefore, the third transistor M3 can avoid switching twice in one switching cycle of the discontinuous conduction mode.

Since the first transistor M1 is only used to generate circulating current to achieve zero-voltage switching, in one embodiment, the actual size (such as aspect ratio) of the first transistor M1 can be configured to be much smaller than the actual size of the third transistor M3 size. Therefore, the driving capability and parasitic capacitance (such as gate capacitance) of the first transistor M1 are lower than the parasitic capacitance of the third transistor M3, and the switching loss of the first transistor M1 is therefore lower than the switching loss of the third transistor M3. .

For example, the gate switching loss Pg of a transistor can be expressed as:

Pg = 0.5*Ciss*Vg*Vg*Freq

Among them, Ciss is the input capacitance of the transistor, Vg is the voltage level of the gate drive signal, and Freq is the switching frequency of the gate drive signal.

According to the above switching power loss equation, the first transistor M1 with a smaller actual size is dedicated to achieve zero-voltage switching of the second transistor M2 in the discontinuous conduction mode, so the gate switching loss of the first transistor M1 is lower than The third transistor M3 with larger actual size.

In addition, in one embodiment, the amplitude of the voltage level (Vg) of the first driving signal S1 is lower than the amplitude of the voltage level of the third driving signal S3, so that the switching loss of the first transistor M1 can be further reduced. And in one embodiment, the maximum rated value of the gate of the first transistor M1 (for example, the gate-source voltage) may also be lower than the maximum rated value of the gate of the third transistor M3.

The resistor 60 generates the current sensing signal VCS by detecting the primary-side switch current IP of the transformer 10, and the primary-side controller 201 is used to generate the first driving signal S1 according to the input voltage VIN, and output the first drive signal according to the input voltage VIN and/or The voltage VO is used to generate the third driving signal S3. The primary side controller 201 is further used to generate the second driving signal S2 according to the feedback signal VFB.

FIG. 12 shows an operation waveform diagram of a preferred embodiment of the primary-side controller 201 operating in the discontinuous conduction mode of the present invention. In the operation of the discontinuous conduction mode, the primary side controller 201 operates in the first switching period Tcyc1 and controls the first driving signal S1 to conduct the first transistor M1 in the first period TA, thereby generating a circulating current to achieve the second Zero-voltage switching when transistor M2 is on. After the first period TA, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1, the second The second transistor M2 and the third transistor M3. In one embodiment, the first non-conduction period Td1 is related to the quasi-resonant period for achieving zero-voltage switching of the second transistor M2. After the first non-conduction period Td1 , the second driving signal S2 turns on the second transistor M2 in the second period TB, and the conduction of the second transistor M2 is used to excite the transformer 10 . After the second period TB, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1, the second transistor M2 and the Three-transistor M3. In one embodiment, the second non-conduction period Td2 is related to another quasi-resonant period for achieving zero-voltage switching of the third transistor M3. After the second non-conduction period Td2, the third driving signal S3 turns on the third transistor M3 in the third period TC, and the third transistor M3 turns on in the demagnetization period of the transformer 10 . After the third period TC, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1, the second transistor M2 and the third transistor M2 in the third non-conduction period TZ. The tri-transistor M3, wherein the excitation current IM is maintained at zero in the third non-conduction period TZ (ie, discontinuous conduction mode). After the third non-conduction period TZ, another switching period Tcyc2 starts.

FIG. 13 shows a block diagram of a preferred embodiment of the primary side controller of the present invention. In one embodiment, the primary side controller 213 includes a timer 22 and a control element 243 . The control element 243 is used for generating the first driving signal S1 , the second driving signal S2 and the third driving signal S3 according to the input voltage VIN (via VAUX ) and the feedback signal VFB.

The timer 22 is used for timing to generate the third non-conduction period TZ, and the third non-conduction period TZ starts when the pulse of the third driving signal S3 ends (for example, a falling edge). In one embodiment, when the output power of the resonant half-bridge flyback converter decreases, the third non-conduction period TZ increases correspondingly. Therefore, the switching frequency of the resonant half-bridge flyback converter can also be reduced due to the resonant half-bridge flyback The output power of the Chi-mode converter is reduced correspondingly, thereby improving performance in light load operating conditions.

The present invention has been described above with reference to preferred embodiments, but the above description is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, and can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the term "processing or computing according to a certain signal or generating a certain output result" in the present invention is not limited to According to the signal itself, it also includes performing voltage-current conversion, current-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or computing the converted signal to generate a certain output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which will not be listed here. Accordingly, the scope of the invention should encompass the above and all other equivalent variations.

10:Transformer 100:Secondary side controller 20: Resonant capacitor 200: primary side controller 201: primary side controller 205: Clock generator 208: primary side controller 22: Timer 230: capacitance 231: switch 240: control element 243: Control elements 248: Control elements 25: Timer 250: Demagnetization Simulator 255: resistance 260: Cycle counter 271, 272: Transistor 280: Comparator 285: Logic Circuit 30: The first transistor 300: Resonant Half Bridge Flyback Converter 35:Body diode 40: second transistor 45:Body diode 51, 52, 55, 60: Resistors 70: Secondary side synchronous rectifier 75:Body diode 90: Optocoupler 900: Resonant half-bridge flyback converter C: capacitance value CPO: Comparator output DCM: discontinuous conduction mode ID: discharge current IM: excitation current IP: primary side switch current IS: Secondary side switching current kn: knee point Lr: leakage inductance LX: switch node M1: the first transistor M2: second transistor M3: The third transistor n, m: turns ratio NA: auxiliary winding NC: positive integer NNP: Coupling Node NP: primary side winding NS: Secondary side winding PW: pulse width PZV: zero voltage switching pulse Rs: resistance value Rt: resistance value S1: The first driving signal S2: The second driving signal S3: The third driving signal Sdmg: demagnetization signal SG: drive signal SH: drive signal SL: drive signal SMP: Sampling signal t1-t9: time point t3': time point ta-te: time point TA: the first period ta', tc': time point TB:Second period TC: the third period Tcyc1: switching cycle Tcyc2: switching cycle Td1: the first non-conduction period Td2: the second non-conduction period TDS: Demagnetization period TDSX: conduction period TDSX': conduction period TRH: time period TRL: time period TSL: conduction period TW: excitation period Tx: omit cycle TZ: the third non-conduction period VAUX: auxiliary signal VC: cross voltage Vcr: cross voltage VCS: current sense signal VCSp: voltage level VDP: voltage drop VFB: feedback signal Vg: voltage level VHB: switching node voltage VIN: input voltage Vinx: voltage level VNA: auxiliary winding signal VO: output voltage VPK: voltage surge Vref: reference voltage Vth: voltage threshold VX: reflected voltage

Figure 1 shows a prior art flyback converter with asymmetric duty cycle.

FIG. 2 shows a waveform diagram of a prior art half-bridge flyback converter operating in discontinuous conduction mode in a light load state.

FIG. 3 shows a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention.

FIG. 4 shows an operation waveform corresponding to the embodiment of FIG. 3 .

FIG. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL.

FIG. 6 shows an operating waveform diagram of an embodiment of the resonant half-bridge flyback converter with omitted periods of the present invention.

FIG. 7 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention.

FIG. 8 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention.

Fig. 9 shows the operation waveform diagram of the demagnetization simulator generating the demagnetization signal of the present invention.

FIG. 10 shows a schematic diagram of a specific embodiment of the demagnetization simulator generating the demagnetization signal Sdmg of the present invention.

FIG. 11 shows a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention.

FIG. 12 shows an operation waveform diagram of a preferred embodiment of the primary-side controller 201 operating in the discontinuous conduction mode of the present invention.

FIG. 13 shows a block diagram of a preferred embodiment of the primary side controller of the present invention.

none

10:Transformer

100:Secondary side controller

20: Resonant capacitor

201: primary side controller

51,52,60: resistance

70: Secondary side synchronous rectifier

75:Body diode

900: Resonant half-bridge flyback converter

IP: primary side switch current

IS: Secondary side switching current

M1: the first transistor

M2: second transistor

M3: The third transistor

NA: auxiliary winding

NP: primary side winding

NS: Secondary side winding

S1: The first driving signal

S2: The second driving signal

S3: The third driving signal

SG: drive signal

VAUX: auxiliary signal

VCS: current sense signal

VFB: feedback signal

VHB: switching node voltage

VIN: input voltage

VO: output voltage

Claims (16)

A half-bridge flyback converter comprising: a first transistor controlled by a first signal; a second transistor controlled by a second signal; a third transistor controlled by a third signal, wherein the first transistor, the second transistor and the third transistor are used to form a half-bridge circuit; and a switching control circuit for generating the first signal according to an input voltage of the half-bridge flyback converter, and generating the third signal according to an output voltage of the half-bridge flyback converter, and according to generating the second signal by a feedback signal, wherein the feedback signal is related to the output voltage of the half-bridge flyback converter; Wherein in a discontinuous conduction mode (discontinuous conduction mode, DCM) operation, the switching control circuit operates in a first switching period to control the first signal to conduct the first transistor in a first period, wherein After the first period, the switching control circuit controls the first signal, the second signal and the third signal to turn off the first transistor, the second transistor and the third signal in a first non-conduction period. The third transistor, wherein after the first non-conduction period, the switching control circuit controls the second signal to conduct the second transistor in a second period, wherein after the second period, the switching control circuit controlling the first signal, the second signal and the third signal to turn off the first transistor, the second transistor and the third transistor in a second non-conduction period, wherein after the second non-conduction After the conduction period, the switching control circuit controls the third signal to turn on the third transistor in a third period, wherein after the third period, the switching control circuit controls the first signal, the second signal and The third signal turns off the first transistor, the second transistor and the third transistor during a third non-conduction period. The half-bridge flyback converter as claimed in item 1, wherein the first transistor is turned on to generate a circulating current, wherein the circulating current is used to achieve the second transistor in the operation of the discontinuous conduction mode Zero Voltage Switching (Zero Voltage Switching, ZVS). The half-bridge flyback converter as claimed in claim 1, wherein the second transistor is turned on to excite a transformer of the half-bridge flyback converter. The half-bridge flyback converter as claimed in claim 3, wherein the third transistor is turned on during a demagnetization period of the transformer. The half-bridge flyback converter according to claim 1, wherein the first transistor and the third transistor are configured as lower bridge transistors of the half-bridge flyback converter, and the second transistor is configured is the upper bridge transistor of the half-bridge flyback converter. The half-bridge flyback converter as described in claim 1, further comprising a timer, wherein the timer is used for timing the third non-conduction period; wherein when the output power of the half-bridge flyback converter decreases , the third non-conduction period counted by the timer increases correspondingly. The half-bridge flyback converter as claimed in claim 1, wherein the actual size of the first transistor is smaller than the actual size of the third transistor. The half-bridge flyback converter as described in Claim 1, wherein: the amplitude of the first signal is lower than the amplitude of the third signal; and/or A maximum rating associated with the gate of the first transistor is lower than a maximum rating associated with the gate of the third transistor. A control method for controlling a half-bridge flyback converter, wherein the half-bridge flyback converter includes a first transistor, a second transistor and a third transistor, the control method comprising: generating a first signal to drive the first transistor according to an input voltage of the half-bridge flyback converter; generating a second signal for driving the second transistor according to a feedback signal, wherein the feedback signal is related to an output voltage of the half-bridge flyback converter; and generating a third signal to drive the third transistor according to the output voltage; Wherein the step of driving the first transistor, the second transistor and the third transistor comprises: In a discontinuous conduction mode of operation, controlling the first transistor to conduct in a first period; After the first period, controlling the first transistor, the second transistor and the third transistor to be turned off in a first non-conduction period; After the first non-conduction period, controlling the second transistor to conduct in a second period; After the second period, controlling the first transistor, the second transistor and the third transistor to be turned off in a second non-conduction period; After the second non-conduction period, controlling the third transistor to conduct in a third period; and After the third period, the first transistor, the second transistor and the third transistor are controlled to be turned off in a third non-conducting period. The control method as described in Claim 9, further comprising: generating a circulating current by turning on the first transistor to achieve zero voltage switching (Zero Voltage) of the second transistor in the operation of the discontinuous conduction mode Switching, ZVS). The control method as claimed in claim 9, wherein a transformer of the half-bridge flyback converter is excited by turning on the second transistor. The control method as claimed in claim 11, wherein the third transistor is turned on during a demagnetization period of the transformer. The control method according to claim 9, wherein the first transistor and the third transistor are the lower bridge transistors of the half-bridge flyback converter, and the second transistor is the half-bridge flyback converter Bridge transistors above the converter. The control method as described in Claim 9 further includes: When the output power of the half-bridge flyback converter decreases, the third non-conduction period increases correspondingly. The control method as claimed in claim 9, wherein the actual size of the first transistor is smaller than the actual size of the third transistor. The control method according to claim 9, wherein the amplitude of the first signal is lower than the amplitude of the third signal.

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