CN115776236A

CN115776236A - Half-bridge flyback converter and control method thereof

Info

Publication number: CN115776236A
Application number: CN202210688395.3A
Authority: CN
Inventors: 杨大勇; 苏英杰; 陈裕昌
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2021-09-06
Filing date: 2022-06-17
Publication date: 2023-03-10
Also published as: TWI822091B; TW202312644A

Abstract

A half-bridge flyback converter and a control method thereof. The half-bridge flyback converter comprises: the circuit comprises a first transistor, a second transistor and a third transistor, wherein the first transistor, the second transistor and the third transistor are used for forming a half-bridge circuit. The first transistor is turned on to generate a negative circulating current to achieve zero voltage switching of the second transistor. The second transistor is turned on to excite the transformer. The third transistor is turned on during a demagnetization period of the transformer to generate an output voltage. The actual size of the first transistor is smaller than the actual size of the third transistor.

Description

Half-bridge flyback converter and control method thereof

Technical Field

The invention relates to a half-bridge flyback converter, in particular to an asymmetric half-bridge flyback converter. The invention also relates to a control method for controlling an asymmetric half-bridge flyback converter.

Background

Referring to fig. 1, fig. 1 shows an asymmetric Duty Cycle Flyback Converter (asymmetric Duty Cycle Flyback Converter) of U.S. Pat. No. 5,959,850, which discloses a half-bridge Flyback Converter with Zero Voltage Switching (ZVS), thereby achieving higher power efficiency. Zero voltage switching may be defined as switching a transistor on when the voltage across the transistor (e.g., the drain-source voltage) is at or near zero. However, the prior art has a disadvantage that the power conversion efficiency of the power converter is low in the light load state.

Another disadvantage of the above prior art is that the output voltage of the power converter is not variable, and specifically, to change to a zero-voltage switching flyback converter with a variable output voltage, the switching of the transformer must be controlled by detecting the demagnetization time period of the transformer.

Another prior art, US 7,151,681, is a Multiple-sampling circuit (Multiple-sampling circuit) for measuring a reflected voltage and a discharge time of a transformer, which discloses a method for detecting an output voltage and a demagnetization time of a transformer, however, the prior art cannot realize zero voltage switching of a power converter, which is used for a Discontinuous Conduction Mode (DCM) operation.

Fig. 2 shows waveforms of a half-bridge flyback converter of the prior art operating in discontinuous conduction mode under light load condition. The driving signal SH is used to drive the upper bridge switch of the half-bridge flyback converter to excite the transformer, the driving signal SL is used to drive the lower bridge switch of the half-bridge flyback converter, and the signal waveform of the exciting current IM indicates that the transformer is operated in the discontinuous conduction mode. When the output power of the half-bridge flyback converter decreases, the pulse width PW of the drive signal SH decreases due to the feedback control of the half-bridge flyback converter, and the pulse width of the drive signal SL also decreases accordingly. When the driving signal SH goes low (off), the first pulse of the driving signal SL is enabled during the demagnetization period of the transformer. The second pulse of the drive signal SL is enabled to generate a circulating current, thereby achieving zero-voltage switching of the upper bridge switch.

The above-mentioned prior art has the disadvantage that when operating in the discontinuous conduction mode, the driving signal SL needs to be switched on/off twice in one switching period, thereby greatly increasing the average switching frequency of the driving signal SL, causing a large amount of switching loss and causing energy loss of the lower bridge switch.

Compared to the prior art U.S. Pat. No. 7,151,681, the present invention provides a resonant half-bridge flyback converter with a period omitted to improve power efficiency in the medium-load, light-load operating state.

Compared to the prior art, U.S. Pat. No. 5,959,850, the present invention provides a method for generating a demagnetization signal, wherein the duration of the demagnetization signal is equal to the demagnetization time interval of the transformer, and the switching control circuit thereof can be used in a zero-voltage switching flyback converter with programmable output voltage, such as: USB PD power converter.

Compared with the prior art shown in fig. 2, the present invention provides a control circuit of an asymmetric half-bridge (AHB) flyback converter, which uses three transistors to improve the power conversion efficiency in the medium-load and light-load operation states.

Disclosure of Invention

In one aspect, the present invention provides a half-bridge flyback converter, comprising: a first transistor controlled by a first signal; a second transistor controlled by a second signal; a third transistor controlled by a third signal, wherein the first transistor, the second transistor and the third transistor are used for forming a half-bridge circuit; and a switching control circuit for generating the first signal according to an input voltage of the half-bridge flyback converter, generating the third signal according to an output voltage of the half-bridge flyback converter, and generating the second signal according to a feedback signal related to the output voltage of the half-bridge flyback converter; in a Discontinuous Conduction Mode (DCM), the switching control circuit operates in a first switching cycle to control the first signal to turn on the first transistor in a first time period, wherein after the first time period, the switching control circuit controls the first signal, the second signal and the third signal in a first non-conducting time period to turn off the first transistor, the second transistor and the third transistor, wherein after the first non-conducting time period, the switching control circuit controls the second signal in a second time period to turn on the second transistor, wherein after the second time period, the switching control circuit controls the first signal, the second signal and the third signal in a second non-conducting time period to turn off the first transistor, the second transistor and the third transistor, wherein after the second non-conducting time period, the switching control circuit controls the third signal in a third time period, wherein after the third non-conducting time period, the third transistor and the third transistor are turned off, wherein after the third transistor and the third transistor are turned on, the switching control signal controls the third transistor in the third time period, the third transistor and the third transistor are turned off.

In a preferred embodiment, the first transistor is turned on to generate a circulating current, wherein the circulating current is used to realize Zero Voltage Switching (ZVS) of the second transistor in the discontinuous conduction mode of operation.

In a preferred embodiment, the second transistor is turned on to excite a transformer of the half-bridge flyback converter.

In a preferred embodiment, the third transistor is turned on during a demagnetization period of the transformer.

In a preferred embodiment, the first transistor and the third transistor are configured as lower bridge transistors of the half-bridge flyback converter, and the second transistor is configured as an upper bridge transistor of the half-bridge flyback converter.

In a preferred embodiment, the half-bridge flyback converter further comprises a timer, wherein the timer is used for timing the third non-conducting period; wherein when the output power of the half-bridge flyback converter decreases, the third off-period timed by the timer correspondingly increases.

In a preferred embodiment, the physical size of the first transistor is smaller than the physical size of the third transistor.

In a preferred embodiment, wherein: the amplitude of the first signal is lower than the amplitude of the third signal; and/or a maximum rating (maximum rating) associated with the gate of the first transistor is lower than a maximum rating associated with the gate of the third transistor.

From another perspective, the present invention also provides a control method for controlling a half-bridge flyback converter, wherein the half-bridge flyback converter includes a first transistor, a second transistor and a third transistor, the control method comprising: generating a first signal to drive the first transistor according to an input voltage of the half-bridge flyback converter; generating a second signal to drive the second transistor according to a feedback signal, wherein the feedback signal is related to an output voltage of the half-bridge flyback converter; and generating a third signal to drive the third transistor according to the output voltage; wherein the step of driving the first transistor, the second transistor, and the third transistor comprises: in a discontinuous conduction mode of operation, controlling the first transistor to be conducted in a first period of time; after the first time interval, controlling the first transistor, the second transistor and the third transistor to be turned off in a first non-conducting time interval; after the first non-conduction period, controlling the second transistor to be conducted in a second period; after the second time interval, controlling the first transistor, the second transistor and the third transistor to be turned off in a second non-conducting time interval; after the second non-conduction time interval, controlling the third transistor to be conducted in a third time interval; and after the third time interval, controlling the first transistor, the second transistor and the third transistor to be turned off in a third non-conducting time interval.

In a preferred embodiment, the control method further comprises: a circulating current is generated by turning on the first transistor to realize Zero Voltage Switching (ZVS) of the second transistor in the discontinuous conduction mode of operation.

In a preferred embodiment, a transformer of the half-bridge flyback converter is excited by turning on the second transistor.

In a preferred embodiment, the first transistor and the third transistor are lower bridge transistors of the half-bridge flyback converter, and the second transistor is an upper bridge transistor of the half-bridge flyback converter.

In a preferred embodiment, the control method further comprises: when the output power of the half-bridge flyback converter decreases, the third non-conducting period is correspondingly increased.

In a preferred embodiment, the amplitude of the first signal is lower than the amplitude of the third signal.

The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of specific embodiments.

Drawings

Fig. 1 shows a prior art asymmetric duty cycle flyback converter.

Fig. 2 shows waveforms of a half-bridge flyback converter operating in discontinuous conduction mode under light load condition according to the prior art.

Fig. 3 is a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention.

Fig. 4 shows waveforms of operation of the embodiment corresponding to fig. 3.

Fig. 5 shows the operation waveforms for reducing the switching frequency of the driving signal SH and the driving signal SL.

Fig. 6 is a waveform diagram illustrating the operation of an embodiment of the resonant half-bridge flyback converter with omitted cycles according to the present invention.

Fig. 7 is a block diagram of an embodiment of a primary controller in a resonant half-bridge flyback converter according to the present invention.

Fig. 8 is a block diagram of a primary controller of the resonant half-bridge flyback converter according to an embodiment of the present invention.

FIG. 9 is a waveform diagram illustrating the operation of the demagnetization simulator of the invention to generate a demagnetization signal.

FIG. 10 is a diagram of a demagnetizing simulator generating a demagnetizing signal Sdmg according to an embodiment of the present invention.

Fig. 11 is a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention.

Fig. 12 is a waveform diagram illustrating the operation of the primary controller 201 in the discontinuous conduction mode according to a preferred embodiment of the present invention.

FIG. 13 is a block diagram of a primary controller according to a preferred embodiment of the present invention.

Description of the symbols in the figures

10: transformer

100: secondary side controller

20: resonance capacitor

200: primary side controller

201: primary side controller

205: clock generator

208: primary side controller

22: time-meter

230: capacitor with a capacitor element

231: switch with a switch body

240: control element

243: control element

248: control element

25: time-meter

250: demagnetizing simulator

255: resistance (RC)

260: cycle counter

271, 272: transistor with a metal gate electrode

280: comparator with a comparator circuit

285: logic circuit

30: a first transistor

300: resonant half-bridge flyback converter

35: body diode

40: second transistor

45: body diode

51, 52, 55, 60: electric resistance

70: secondary side synchronous rectifier

75: body diode

90: optical coupler

900: resonant half-bridge flyback converter

C: capacitance value

CPO (carbon monoxide gas phase oxidation) of: comparator output

DCM: discontinuous conduction mode

ID: discharge current

IM: excitation current

IP: primary side switching current

IS: secondary side switch current

kn: knee point

Lr: leakage inductance

LX: switching node

M1: a first transistor

And M2: second transistor

And M3: a third transistor

n, m: turns ratio

NA: auxiliary winding

NC: positive integer

NNP: coupling node

NP: primary side winding

And NS: secondary side winding

PW: pulse width

PZV: zero voltage switching pulse

Rs: resistance value

Rt: resistance value

S1: a first drive signal

S2: the second drive signal

S3: third drive signal

Sdmg: demagnetizing signal

SG: drive signal

SH: drive signal

SL: drive signal

SMP: sampling signal

t1-t9: time point

t3': time point

ta-te: time point

TA: a first period of time

ta ', tc': time point

TB: for a second period of time

TC: for a third period of time

Tcyc1: switching period

Tcyc2: switching period

Td1: first non-conduction period

Td2: second non-conducting period

TDS: period of demagnetization

TDSX: during the conduction period

TDSX': during the conduction period

TRH: time period

TRL: time period

TSL: during the conduction period

TW: period of excitation

Tx: omit cycle

TZ: a third non-conduction period

VAUX: auxiliary signal

VC: over pressure

Vcr: over pressure

And (4) VCS: current sensing signal

VCSp: voltage level

VDP: voltage drop

VFB: feedback signal

Vg: voltage level of

VHB: switching node voltage

VIN: input voltage

Vinx: voltage level of

VNA: auxiliary winding signal

VO: output voltage

VPK: voltage surge

Vref: reference voltage

Vth: voltage threshold value

VX: reflected voltage

Detailed Description

The drawings in the present disclosure are schematic and are intended to show the coupling relationship between circuits and the relationship between signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

Fig. 3 is a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-bridge flyback converter 300 includes: the first transistor 30 and the second transistor 40 are used to form a half-bridge circuit. The transformer 10 and the resonant capacitor 20 are connected in series and coupled to a switching node LX of the half-bridge circuit, and the transformer 10 includes a primary winding NP, a secondary winding NS, and an auxiliary winding NA, where the primary winding NP and the secondary winding NS have a turn ratio n, and the secondary winding NS and the auxiliary winding NA have a turn ratio m. The primary controller 200 generates a driving signal SH and a driving signal SL, which switch the transformer 10 through the half-bridge circuit to generate an output voltage VO on the secondary side of the transformer 10. The driving signal SH drives the first transistor 30 to excite the transformer 10. The driving signal SL turns on the second transistor 40 during the demagnetization and resonance period of the transformer 10, and the driving signal SL is also used for turning on the second transistor 40 to generate a circulating current flowing through the transformer 10, so as to realize zero-voltage switching of the first transistor 30. The resistor 60 generates a current sensing signal VCS by detecting the primary-side switching current IP of the transformer 10.

The driving signal SH and the driving signal SL are generated according to a feedback signal VFB, wherein the feedback signal VFB is generated according to the output power of the resonant half-bridge flyback converter 300. The secondary side controller 100 is coupled to the output voltage VO to generate a feedback signal VFB, which is coupled to the primary side controller 200 via the optocoupler 90. The secondary controller 100 is also configured to generate a driving signal SG for driving the secondary synchronous rectifier 70 during the demagnetization time period TDS of the transformer 10. The auxiliary winding NA generates an auxiliary winding signal VNA when the transformer 10 is switched, and the

resistors

51 and 52 attenuate the auxiliary winding signal VNA to generate an auxiliary signal VAUX, which is coupled to the primary controller 200. In one embodiment, the resistor 55 is coupled to the primary controller 200, and the demagnetization signal Sdmg is generated by setting parameters through the resistor 55.

Fig. 4 shows waveforms of operation of the embodiment corresponding to fig. 3. When the driving signal SH is on, the transformer 10 is excited and generates an excitation current IM, and when the driving signal SH is off, the transformer 10 is demagnetized. In the demagnetization time interval TDS, the transformer 10 generates the secondary side switching current IS, and the driving signal SL IS related to the demagnetization time interval TDS of the transformer 10. In one embodiment, the on period TSL (i.e., the pulse width) of the driving signal SL is equal to or longer than the demagnetization period TDS of the transformer 10, thereby preventing the transformer 10 from operating in a Continuous Conduction Mode (CCM). In the demagnetizing period TDS of the transformer 10, a reflected voltage VX is generated on the resonant capacitor 20, wherein the relationship between the reflected voltage VX and the output voltage VO is: VX = n × VO.

The driving signal SL may be turned on when the driving signal SH is not turned on, and the driving signal SH may be turned on when the driving signal SL is not turned on. A dead time (e.g., the period TRH, the period TRL) may be included between the driving signal SH and the driving signal SL (i.e., when neither the driving signal SH nor the driving signal SL is conductive).

Details of the operation in the different periods of fig. 4 are described below.

The period from time t1 to time t2 is the transformer excitation period, in which the first transistor 30 is turned on and the second transistor 40 is turned off, the primary-side switching current IP flowing through the transformer 10 increases and the voltage of the resonant capacitor 20 also increases, at this time, the transformer 10 is excited and the resonant capacitor 20 is charged, the secondary-side synchronous rectifier 70 is turned off and the body diode 75 has a reverse bias, so that no energy is converted to the secondary side at this time.

The period from time t2 to time t3 is a first cycle current period, in which the first transistor 30 and the second transistor 40 are both turned off, and the cycle current of the transformer 10 forces the switching node voltage VHB of the half-bridge circuit to decrease until the body diode 45 of the second transistor 40 is turned on. The time period from the time point t2 to the time point t3 is related to a quasi-resonant period (quasi-resonant period) to realize zero voltage switching of the second transistor 40, where the primary side voltage of the transformer 10 is the same as the voltage of the resonant capacitor 20 at the time point t 3.

In the period from time t3 to time t4, which is a resonant cycle (positive current), in the zero-voltage switching state, the first transistor 30 is turned off and the second transistor 40 is turned on, at this time, the output voltage VO is equal to the voltage across Vcr of the resonant capacitor 20 divided by the turn ratio n, the current starts to flow through the secondary-side synchronous rectifier 70, and the energy stored in the transformer 10 is converted to the output terminal to generate the output voltage VO. Since the leakage inductance Lr of the transformer 10 and the resonant capacitor 20 (Cr) form an inductance-capacitance tank (LC tank), the secondary-side current is in the form of a sine wave in a period determined by the resonant frequencies Lr and Cr. The primary side current of the transformer 10 IS the sum of the excitation current IM and the secondary side switching current IS. The current flowing through the resonant tank (Lr, cr) is still a positive current, which is mainly driven by the exciting inductance of the transformer 10, and flows through the resonant capacitor 20.

The period from time t4 to time t5 is a resonant period (negative current), in which the first transistor 30 is continuously turned off and the second transistor 40 is continuously turned on, energy is continuously transferred to the secondary side, but the resonant tank current is reversely driven by the voltage of the resonant capacitor 20, and the energy of the resonant capacitor 20 is not only transferred to the secondary side, but also used for pulling the level of the exciting current of the transformer 10 to a negative value when the second transistor 40 is continuously turned on (e.g., from time t4 to time t 5).

The period from time t5 to time t6 is the reverse excitation transformer cycle (negative current), and in this period, from the end of the demagnetization period TDS of the transformer 10 to the time when the second transistor 40 is turned off, the resonant capacitor 20 reversely excites the transformer 10 and generates a negative current.

The period from time t6 to time t7 is the second cycle current period, in which the first transistor 30 and the second transistor 40 are both turned off, and the negative current of the transformer 10 is induced from time t5 to time t6 to force the switching node voltage VHB at the switching node LX in the half-bridge circuit to increase until it turns on the body diode 35 of the first transistor 30.

After time t7, another period similar to the period from time t1 to time t2 is started, the first transistor 30 is turned on in the zero-voltage switching state and the second transistor 40 is turned off, and if the circulating current in the resonant tank of the transformer is still negative, the excess energy in the resonant tank will be sent back to the input terminal (the node supplying the input voltage VIN).

In a light load state, when the output power is reduced, the pulse widths of the driving signal SH and the driving signal SL are reduced correspondingly, so that the switching frequency of the driving signal SH and the driving signal SL is increased in the light load state, and the power loss such as core loss (core loss) and switching loss (switching loss) is increased, thereby deteriorating the power conversion efficiency of the power converter.

Fig. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL. One way to improve the power efficiency is to reduce the switching frequency by prolonging the time between the turning-off of the driving signal SL (e.g., at time t 3) and the turning-on of the driving signal SH (e.g., at time t 5), however, the turning-off of the driving signal SL will generate a circulating current, which in turn will cause the voltage surge VPK of the switching node voltage VHB and the voltage drop VDP of the auxiliary signal VAUX, which will cause power loss and noise.

It should be noted that the turning on or off of the driving signal SH and the driving signal SL respectively correspond to the turning on or off of the first transistor 30 and the second transistor 40.

Fig. 6 is a waveform diagram illustrating the operation of an embodiment of the resonant half-bridge flyback converter with omitted cycle according to the present invention.

Referring to fig. 6, in an embodiment, the driving signal SH is turned on during an excitation period (e.g., time t1 to time t 2) of the excitation transformer 10 to excite the excitation transformer 10. After the driving signal SH is turned off, the driving signal SL is turned on in a resonant period (e.g., from time t2 to time t 3) and has resonant pulses (e.g., from time t2 to time t 3), and one excitation period and one resonant period form a switching period (e.g., from time t1 to time t 3).

As shown in fig. 6, in one embodiment, the omission period Tx starts at a non-conducting time (e.g., time t 4) when the driving signal SH is turned off, and the driving signal SL is turned on when the omission period Tx ends (e.g., time t 6). In one embodiment, when the output power is reduced due to power saving, the omission period Tx is correspondingly increased (i.e. the switching frequency is decreased).

Referring to fig. 6, compared to the period without the omission period, such as time t1 to time t3, the driving signal SL is not turned on and has no resonant pulse in the omission period (such as Tx), for example, in the prior art, one pulse of the driving signal SL existing in time t4 to time t5, i.e. the resonant pulse of the driving signal SL, is omitted in the present embodiment as shown in fig. 6, and therefore, no negative circulation current is generated in the omission period (time t4 to time t 6). In the prior art, the voltage surge VPK generated by the switching node voltage VHB and the voltage drop VDP generated by the auxiliary signal VAUX are also avoided in the present embodiment. In one embodiment, as shown in fig. 6, the driving signal SH is also in the non-conducting state during the omission period (e.g., tx).

In one embodiment, after the driving signal SH is turned off, a part of the demagnetization current of the transformer 10 flows through the body diode 45 of the second transistor 40 during a part of the omitted period (e.g., a part of the time between the time t4 and the time t 5). In other words, in one embodiment, there are no double pulses (double pulses) in the driving signal SL. In one embodiment, there are no double pulses in the driving signal SH. In one aspect, the single pulse of the driving signal SL is generated after the single pulse of the driving signal SH, and the single pulse of the driving signal SL is generated after the single pulse of the driving signal SL, even though the resonant half-bridge flyback converter is operated in a state with the omitted period. In another aspect, the driving signal SL comprises at most one pulse between two consecutive pulses of the driving signal SH, and the driving signal SH comprises at most one pulse between two consecutive pulses of the driving signal SL.

In one embodiment, the skip period Tx is generated when the output power is lower than a predetermined threshold. In one embodiment, the omission period Tx is correspondingly increased as the output power is decreased. In one embodiment, even in the case where the driving signal SL cannot achieve the zero-voltage switching of the first transistor 30, the second driving signal does not include the second pulse between two consecutive pulses of the first driving signal, and thus the zero-voltage switching of the first transistor 30 is not achieved with the second pulse.

Referring to fig. 6, in an embodiment, the zero-voltage switching pulse (e.g., PZV) of the driving signal SL turns on the second transistor 40 after the omission period elapses, so as to realize the zero-voltage switching period (e.g., from time t6 to time t 7).

As shown in fig. 6, in one embodiment, at least one switching period (e.g., time t7 to time t 9) is generated after the zero-voltage switching pulse PZV after the omission period.

With continued reference to fig. 6, in an embodiment, the resonant period may include a continuous zero-voltage switching period (e.g., from time t3' to time t 3) for implementing the zero-voltage switching of the first transistor 30. In other words, in the present embodiment, a first portion (e.g., time t2 to time t 3') of the resonant pulse is used to realize the resonance between the transformer 10 and the resonant capacitor 20, and a second portion (e.g., time t3 to time t 3) of the resonant pulse is used to generate a circulating current to realize the zero-voltage switching of the first transistor 30.

Fig. 7 is a block diagram of a primary controller of the resonant half-bridge flyback converter according to an embodiment of the present invention. In one embodiment, the primary side controller 200 includes a timer 25 and a control element 240. In one embodiment, the control element 240 is configured to generate the driving signal SH and the driving signal SL according to the input voltage VIN (via the auxiliary signal VAUX) and the feedback signal VFB, and the timer 25 is configured to generate the skip period Tx.

As shown in fig. 7, in an embodiment, the timer 25 determines whether the output power is lower than the predetermined threshold according to the information related to the output power, when the output power is determined to be lower than the predetermined threshold, the timer 25 starts to calculate the skipping period Tx, and controls the control element 240 to skip the pulses of the driving signal SH and the driving signal SL in the skipping period Tx.

Referring to fig. 4 again, when the resonant half-bridge flyback converter is in the medium-load and light-load states, the resonant period from t4 to t5 is short, and a sufficient negative current (energy) cannot be generated to achieve zero-voltage switching, so that a main portion of the negative current comes from the current generated from t5 to t 6.

However, a higher negative current will result in a higher power loss, and in order to control the negative current for zero-voltage switching to a proper level, the demagnetization time interval must be accurately controlled, so that the demagnetization signal Sdmg needs to be generated to correspond to the demagnetization time interval TDS of the transformer 10.

Fig. 8 is a block diagram of a primary controller in a resonant half-bridge flyback converter according to an embodiment of the present invention. In one embodiment, the primary side controller 208 includes a demagnetization simulator 250 and a control element 248. In one embodiment, the control element 248 is configured to generate the driving signal SH and the driving signal SL according to the input voltage VIN (via the auxiliary signal VAUX) and the feedback signal VFB, and the demagnetization simulator 250 is configured to generate the demagnetization signal Sdmg according to a demagnetization-related signal, such as a reflection voltage of the transformer 10 (via the auxiliary signal VAUX), so as to simulate the demagnetization time period TDS.

Referring to fig. 9, fig. 9 is a waveform diagram illustrating an operation of the demagnetization simulator of the present invention to generate a demagnetization signal.

In the switching period, the resonant half-bridge flyback converter is periodically operated in a non-discontinuous conduction mode (e.g., time ta to time tc '), the driving signal SH first turns on the first transistor 30 to excite the transformer 10 and thereby generate the primary-side switching current IP (e.g., time ta' to time tb), and after the first transistor 30 is turned off, the driving signal SL is used to turn on the second transistor 40 (e.g., time tb to time tc ') in the resonant period (e.g., time tb to time tc) and generate a circulating current (e.g., time tc to time tc') to achieve zero-voltage switching of the first transistor 30. In the switching period of the discontinuous conduction mode, the on period TSL (e.g., from the time point tb to the time point tc ') of the driving signal SL is determined by the pulse width (e.g., TDSX') of the demagnetization signal Sdmg, wherein the demagnetization signal Sdmg is generated by the demagnetization simulator 250 according to the calibration in the discontinuous conduction mode that is forced to be inserted previously. In one embodiment, the on period TDSX' of the degaussing signal Sdmg is corrected during the previous active forced discontinuous conduction mode, and is used to enable the control element 248 to control the minimum on time of the second transistor 40, thereby degaussing the transformer 10 during the non-discontinuous conduction mode after the first transistor 30 is turned off. In an embodiment, as shown in fig. 9, the on period TSL of the driving signal SL (e.g., from the time tb to the time tc ') is the on period TDSX ' of the demagnetization signal Sdmg plus a delay time (e.g., from the time tc to the time tc ') to establish a negative circulation current on the primary-side switching current IP after the demagnetization time, so as to achieve zero-voltage switching of the first transistor 30.

It should be noted that the non-discontinuous conduction mode refers to an operation mode that is not a discontinuous conduction mode, for example: continuous Conduction Mode (CCM), or quasi-resonant mode (QRM), also known as Boundary Conduction Mode (BCM).

In one embodiment, when the primary-side switch current IP has a predetermined number (e.g., a positive integer NC) of switching cycles (e.g., from time ta to time t 1) operating in the non-discontinuous conduction mode (e.g., the quasi-resonant mode), at least one switching cycle is actively forced to operate in the discontinuous conduction mode (e.g., from time t1 to time t 3). Therefore, the demagnetization simulator 250 is used to correct the turn-on period TDSX of the demagnetization signal Sdmg according to the demagnetization period TDS of the transformer 10 in the forcible insertion discontinuous conduction mode.

As shown in fig. 9, in the forced discontinuous conduction mode, the demagnetization period TDS of the transformer 10 starts from a rising edge (rising edge) of the auxiliary signal VAUX and ends at a falling edge (knee point kn) of the auxiliary signal VAUX (e.g., from time t2 to time t 3). Specifically, in the present embodiment, the reflected voltage can be detected by sensing the auxiliary signal VAUX from the auxiliary winding NA of the transformer 10 during the off period of the first transistor 30. The length of time during which the reflected voltage occurs, i.e., the pulse width of the auxiliary signal VAUX from the rising edge to the knee point kn, is related to the demagnetization time period TDS of the transformer 10.

In one embodiment, the primary controller 208 further includes a period counter 260, the period counter 260 is configured to count the number of the switching periods operating in the non-discontinuous conduction mode according to the primary switching current IP, and when the primary switching current IP is determined that a predetermined number of the switching periods are not operating in the discontinuous conduction mode, the period counter 260 is configured to control the control element 248 to actively force the non-discontinuous conduction mode to operate. In one embodiment, the period counter 260 may sense the primary-side switch current IP via the current sensing signal VCS, thereby determining to operate in the non-discontinuous conduction mode.

In one embodiment, as shown in fig. 9, the driving signal SL continuously controls the second transistor 40 to be non-conductive during the forced discontinuous conduction mode switching period, so that the half-bridge circuit not only operates in the discontinuous conduction mode, but also operates in the asynchronous switching mode, wherein a part of the demagnetization current of the transformer 10 (for example, IP from time t2 to time t 2') flows through the body diode 45 of the second transistor 40 during the forced discontinuous conduction mode switching period.

Referring to fig. 9, after the discontinuous conduction mode DCM (e.g. from time t4 to time t 5), the first pulse of the driving signal SL turns on the second transistor 40 to excite the transformer 10 from the resonant capacitor 20 to the transformer 10, so as to generate a negative circulating current (IP from time t4 to time t 5) to realize the zero-voltage switching of the first transistor 30.

FIG. 10 is a schematic diagram of an embodiment of the demagnetizing simulator generating a demagnetizing signal Sdmg according to the present invention. In one embodiment, the degaussing simulator 250 includes a timing generator 205, a comparator 280, and a logic circuit 285.

In one embodiment, the timing generator 205 comprises an integrator, the integrator is composed of a switch 231 and a capacitor 230, the switch 231 is controlled by a sampling signal SMP, and the sampling signal SMP is related to the driving signal SH to sample the current sensing signal VCS. The discharge current ID is related to n × VO for discharging the voltage VC across the capacitor 230. The cross voltage VC is compared with the reference voltage Vref by the comparator 280. The logic circuit 285 generates the demagnetization signal Sdmg according to the comparator output CPO and the sampling signal SMP related to the driving signal SH. In one embodiment, the reference voltage Vref is 0 volt, and the current sense voltage VCS is 0 when the primary-side switch current IP is 0.

In one embodiment, the duration of the demagnetization signal Sdmg is related to the voltage level (Vinx) of the input voltage of the transformer 10, i.e., the voltage at the coupling node NNP of the primary winding NP and the resonant capacitor 20 as shown in fig. 3, and also related to the voltage level (e.g., n × VO) of the output voltage of the transformer 10 and the excitation period (TW) of the transformer 10 when the first transistor 30 is turned on. It should be noted that the voltage level Vinx of the input voltage of the transformer 10 is equal to the input voltage VIN minus the voltage Vcr across the resonant capacitor 20.

From the fact that the demagnetized magnetic flux of the transformer 10 is equal to the excited magnetic flux of the transformer 10, the following equation 1 can be listed:

vinx TW = n VO TDS (formula 1)

Where TW is an occurrence time of a voltage level Vinx of the input voltage of the transformer 10 in an excitation period of the transformer 10; n VO is the voltage of the transformer 10 during the demagnetization time period TDS of the transformer 10. n is the turn ratio of the primary winding NP and the secondary winding NS, and VO is the voltage (i.e., output voltage) of the secondary winding NS.

After the transformer 10 is excited, the level VCSp of the current sensing signal VCS is related to the peak value of the primary-side switching current IP at the end of the excitation process and is generated on the resistor 60 shown in fig. 3, which can be represented by the following formula 2:

VCSp = (Vinx/L) × TW Rs (formula 2)

Where L is the inductance of the primary winding NP of the transformer 10, rs is the resistance of the resistor 60, and VCSp is the voltage level at which the excitation process of the transformer 10 is completed.

Let ID = n VO/Rt, where Rt is the resistance of the resistor 55.

The pulse width TDSX of the demagnetization signal Sdmg may be expressed as:

TDSX = (C × VCSp)/ID, where C is the capacitance value of the capacitor 230.

TDSX＝(Rt*C*VCSp)/(n*VO)

TDSX＝(Rt*C/(n*VO))*(Rs/L)*Vinx*TW

Let Rt = L/(Rs C) (formula 3)

TDSX = (Vinx TW)/(n VO) (formula 4)

When the condition of equation 3 is satisfied, the turn-on period TDSX of the demagnetization signal Sdmg shown in equation 4 is equal to the demagnetization period TDS of the transformer 10.

Referring to fig. 10, the switch 231 is turned on to sample the current sensing signal VCS to the capacitor 230, and when the switch 231 is turned off (i.e., the excitation is ended), the level VCSp of the current sensing signal VCS is maintained at the capacitor 230, and the switch 231 is controlled by the sampling signal SMP. When the switch 231 is turned off, the demagnetization signal Sdmg is enabled (e.g., by the logic circuit 285), in other words, when the demagnetization signal Sdmg starts to be enabled, the voltage VC across the capacitor 230 is the peak value of the current sensing signal VCs. After switch 231 is turned off, discharge current ID starts to discharge capacitor 230, and demagnetization signal Sdmg is disabled when capacitor 230 is completely discharged via discharge current ID (ID = n × VO/Rt) (VC = 0V). The resistor 55 shown in fig. 10 and 3 is used to set the predetermined pulse width of the demagnetization signal Sdmg.

In one embodiment, in the forced discontinuous conduction mode switching period, the pulse width TDSX of the degaussing signal Sdmg can be compared with the degaussing period TDS indicated by the pulse width of the auxiliary signal VAUX by the degaussing simulator 250, so that the pulse width TDSX of the degaussing signal Sdmg can be corrected for the next discontinuous conduction mode switching period. In one embodiment, the demagnetization simulator 250 is further configured to adjust the resistance of the resistor 255 according to the demagnetization time interval TDS detected in the discontinuous conduction mode, so as to correct the pulse time interval TDSX of the demagnetization signal Sdmg.

In other embodiments, in addition to adjusting the resistance value of the resistor 255, the demagnetization simulator 250 can also correct the pulse period TDSX of the demagnetization signal Sdmg by: the voltage threshold Vth is adjusted to determine the end of the demagnetization signal Sdmg, or the capacitance of the capacitor 230 is adjusted, or the ratio of the current mirror formed by the

transistors

271 and 272 in fig. 10 is adjusted.

Fig. 11 is a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention. Resonant half-bridge flyback converter 900 is similar to resonant half-bridge flyback converter 300 of fig. 3. In the present embodiment, the resonant half-bridge flyback converter 900 includes a first transistor M1, a second transistor M2, and a third transistor M3, and the first transistor M1, the second transistor M2, and the third transistor M3 are used to form a half-bridge circuit. In one aspect, the first transistor M1 and the third transistor M3 are configured as lower bridge transistors of the resonant half-bridge flyback converter 900, and the second transistor M2 is configured as upper bridge transistors of the resonant half-bridge flyback converter 900.

According to the feedback signal VFB and the input voltage VIN, the primary controller 201 is configured to generate a first driving signal S1, a second driving signal S2 and a third driving signal S3, wherein the first driving signal S1, the second driving signal S2 and the third driving signal S3 are coupled to switch the transformer 10 through a half-bridge circuit, so as to generate an output voltage VO on the secondary side of the transformer 10. The second driving signal S2 drives the second transistor M2 to excite the transformer 10, the third driving signal S3 turns on the third transistor M3 during the demagnetization and resonance period of the transformer 10, and the third driving signal S3 is also used to turn on the third transistor M3 to generate a circulating current flowing through the transformer 10, and to implement zero-voltage switching of the second transistor M2 in the heavy load state. In other words, the second transistor M2 is a primary-side on-bridge switch of the resonant half-bridge flyback converter 900 and may correspond to the first transistor 30 of fig. 3, and the third transistor M3 is a primary-side off-bridge switch of the resonant half-bridge flyback converter 900 and may correspond to the second transistor 40 of fig. 3. In one aspect, the first transistor M1 is configured to be connected in parallel to the third transistor M3 and serves as an auxiliary primary-side down-bridge switch, having an independent control signal S1.

In one embodiment, the third transistor M3 is controlled to be turned on during the demagnetization and resonant periods of the transformer 10 after the transformer 10 is excited by turning on the second transistor M2 under the light load condition and operating in the discontinuous conduction mode. After demagnetization, when the third transistor M3 is turned off continuously, the first driving signal S1 is used to turn on the first transistor M1 to generate a circulating current flowing through the transformer 10 to realize zero voltage switching of the second transistor M2. Therefore, the third transistor M3 can avoid switching twice in one switching period of the discontinuous conduction mode.

Since the first transistor M1 is only used to generate the circulating current to realize zero-voltage switching, in an embodiment, the actual size (e.g., length-to-width ratio) of the first transistor M1 may be configured to be much smaller than the actual size of the third transistor M3. Therefore, the driving capability and parasitic capacitance (e.g., gate capacitance) of the first transistor M1 are lower than those of the third transistor M3, and the switching loss of the first transistor M1 is therefore lower than that of the third transistor M3.

For example, the gate switching loss Pg of a transistor can be expressed as:

Pg＝0.5*Ciss*Vg*Vg*Freq

where Ciss is the input capacitance of the transistor, vg is the voltage level of the gate driving signal, and Freq is the switching frequency of the gate driving signal.

As shown in the above switching power loss equation, the first transistor M1 with a smaller physical size is dedicated to zero-voltage switching of the second transistor M2 in the discontinuous conduction mode, and therefore the gate switching loss of the first transistor M1 is lower than that of the third transistor M3 with a larger physical size.

In addition, in an embodiment, the amplitude of the voltage level (i.e., vg) of the first driving signal S1 is lower than the amplitude of the voltage level of the third driving signal S3, so that the switching loss of the first transistor M1 can be reduced, and in an embodiment, the maximum gate rating (e.g., the gate-source voltage) of the first transistor M1 can also be lower than the maximum gate rating of the third transistor M3.

The resistor 60 generates a current sensing signal VCS by detecting a primary-side switching current IP of the transformer 10, and the primary-side controller 201 is configured to generate a first driving signal S1 according to the input voltage VIN and/or generate a third driving signal S3 according to the input voltage VIN and/or the output voltage VO. The primary controller 201 is further configured to generate a second driving signal S2 according to the feedback signal VFB.

Fig. 12 is a waveform diagram illustrating the operation of the primary controller 201 in the discontinuous conduction mode according to a preferred embodiment of the present invention. In the discontinuous conduction mode, the primary controller 201 operates in the first switching period Tcyc1 and controls the first driving signal S1 to turn on the first transistor M1 in the first time period TA, thereby generating a circulating current to realize zero-voltage switching when the second transistor M2 is turned on. After the first time period TA, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used for turning off the first transistor M1, the second transistor M2 and the third transistor M3 in the first non-conducting time period Td1 (i.e. the dead time period). In one embodiment, the first non-conducting period Td1 is related to a quasi-resonant period for achieving zero-voltage switching of the second transistor M2. After the first non-conducting period Td1, the second driving signal S2 turns on the second transistor M2 in the second period TB, and the second transistor M2 is turned on to excite the transformer 10. After the second time period TB, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1, the second transistor M2 and the third transistor M3 (i.e. during the idle time period). In an embodiment, the second non-conducting period Td2 is related to another quasi-resonant period for achieving zero voltage switching of the third transistor M3. After the second non-conducting period Td2, the third driving signal S3 turns on the third transistor M3 in the third period TC, and the third transistor M3 turns on in the demagnetizing period of the transformer 10. After the third time period TC, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1, the second transistor M2 and the third transistor M3 in the third non-conducting time period TZ, wherein the exciting current IM is maintained at zero in the third non-conducting time period TZ (i.e. discontinuous conducting mode). After the third non-conduction period TZ another switching cycle Tcyc2 is started.

FIG. 13 is a block diagram of a primary controller according to a preferred embodiment of the present invention. In one embodiment, the primary controller 213 includes a timer 22 and a control element 243. The control element 243 is configured to generate a first driving signal S1, a second driving signal S2 and a third driving signal S3 according to the input voltage VIN (via VAUX) and the feedback signal VFB.

The timer 22 is used for timing to generate a third non-conducting period TZ, which starts when the pulse of the third driving signal S3 ends (e.g., falls). In one embodiment, when the output power of the resonant half-bridge flyback converter decreases, the third off-period TZ is correspondingly increased, so that the switching frequency of the resonant half-bridge flyback converter can also be correspondingly decreased due to the decrease of the output power of the resonant half-bridge flyback converter, thereby improving the performance in the light-load operating state.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. The various embodiments described are not limited to individual applications, but may also be used in combination, for example, two or more embodiments may be combined, and some components in one embodiment may be substituted for corresponding components in another embodiment. Further, equivalent variations and combinations are contemplated by those skilled in the art within the spirit of the present invention, and the term "processing or computing or generating an output result based on a signal" is not limited to the signal itself, and includes, if necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling on the signal, and then processing or computing the converted signal to generate an output result. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.

Claims

1. A half-bridge flyback converter, comprising:

a first transistor controlled by a first signal;

a second transistor controlled by a second signal;

a third transistor controlled by a third signal, wherein the first transistor, the second transistor and the third transistor are used for forming a half-bridge circuit; and

a switching control circuit for generating the first signal according to an input voltage of the half-bridge flyback converter, generating the third signal according to an output voltage of the half-bridge flyback converter, and generating the second signal according to a feedback signal, wherein the feedback signal is related to the output voltage of the half-bridge flyback converter;

in a discontinuous conduction mode, the switching control circuit operates in a first switching cycle to control the first signal to turn on the first transistor in a first time period, wherein after the first time period, the switching control circuit controls the first signal, the second signal and the third signal to turn off the first transistor, the second transistor and the third transistor in a first non-conduction time period, wherein after the first non-conduction time period, the switching control circuit controls the second signal to turn on the second transistor in a second time period, wherein after the second time period, the switching control circuit controls the first signal, the second signal and the third signal to turn on the third transistor in a second non-conduction time period, and wherein after the second non-conduction time period, the switching control circuit controls the third signal to turn on the third transistor in a third time period, wherein after the third non-conduction time period, the switching control circuit controls the third signal to turn on the third transistor and the third transistor in the third time period, and the third transistor is turned off.

2. The half-bridge flyback converter of claim 1, wherein the first transistor is turned on to generate a circulating current, wherein the circulating current is used to achieve zero-voltage switching of the second transistor in the discontinuous conduction mode of operation.

3. The half-bridge flyback converter of claim 1, wherein the second transistor is turned on to excite a transformer of the half-bridge flyback converter.

4. The half-bridge flyback converter of claim 3, wherein the third transistor is turned on during a demagnetization period of the transformer.

5. The half-bridge flyback converter of claim 1, wherein the first and third transistors are configured as lower bridge transistors of the half-bridge flyback converter, and the second transistor is configured as an upper bridge transistor of the half-bridge flyback converter.

6. The half-bridge flyback converter of claim 1, further comprising a timer, wherein the timer is configured to time the third off-period; wherein when the output power of the half-bridge flyback converter decreases, the third off-time period timed by the timer correspondingly increases.

7. The half-bridge flyback converter of claim 1, wherein a physical size of the first transistor is smaller than a physical size of the third transistor.

8. The half-bridge flyback converter of claim 1, wherein:

the amplitude of the first signal is lower than the amplitude of the third signal; and/or

A maximum rating associated with the gate of the first transistor is lower than a maximum rating associated with the gate of the third transistor.

9. A control method for controlling a half-bridge flyback converter, wherein the half-bridge flyback converter includes a first transistor, a second transistor and a third transistor, the control method comprising:

generating a first signal to drive the first transistor according to an input voltage of the half-bridge flyback converter;

generating a second signal to drive the second transistor according to a feedback signal, wherein the feedback signal is related to an output voltage of the half-bridge flyback converter; and

generating a third signal to drive the third transistor according to the output voltage;

wherein the step of driving the first transistor, the second transistor, and the third transistor comprises:

in a discontinuous conduction mode of operation, controlling the first transistor to be conducted in a first period of time;

after the first time interval, controlling the first transistor, the second transistor and the third transistor to be turned off in a first non-conducting time interval;

after the first non-conduction period, controlling the second transistor to be conducted in a second period;

after the second time interval, controlling the first transistor, the second transistor and the third transistor to be turned off in a second non-conducting time interval;

after the second non-conduction time interval, controlling the third transistor to be conducted in a third time interval; and

after the third time interval, the first transistor, the second transistor and the third transistor are controlled to be turned off in a third non-conducting time interval.

10. The control method according to claim 9, further comprising: the first transistor is turned on to generate a circulating current, so that zero-voltage switching of the second transistor is realized in the discontinuous conduction mode operation.

11. The control method of claim 9, wherein a transformer of the half-bridge flyback converter is excited by turning on the second transistor.

12. The method of claim 11, wherein the third transistor is turned on during a demagnetization period of the transformer.

13. The control method of claim 9, wherein the first transistor and the third transistor are lower bridge transistors of the half-bridge flyback converter, and the second transistor is an upper bridge transistor of the half-bridge flyback converter.

14. The control method according to claim 9, further comprising:

when the output power of the half-bridge flyback converter decreases, the third non-conducting period is correspondingly increased.

15. The control method of claim 9, wherein a physical size of the first transistor is smaller than a physical size of the third transistor.

16. The control method of claim 9, wherein the amplitude of the first signal is lower than the amplitude of the third signal.