TW202312446A - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method of forming the same are provided. The method of forming the semiconductor structure includes forming a floating gate layer on a substrate. A trench is formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

Description

Semiconductor structures and methods of forming them

The present disclosure relates to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures with air gaps and methods of forming the same.

Non-volatile memories generally include floating gates and control gates. The floating gate is used to capture and store electrons, while the control gate is used to control the potential and is connected to the word line. With the improvement of usage requirements, the semiconductor structure is expected to have a smaller size to increase the bulk density. However, shrinking the size of the semiconductor structure may cause coupling interference between adjacent floating gates, that is, interference between active regions. Alternatively, leakage current problems may also occur, resulting in reduced reliability and yield of the semiconductor structure.

Therefore, existing semiconductor structures and methods of forming them have not fully met the requirements in all aspects. Therefore, there are still some problems to be overcome regarding the semiconductor structure and its formation method that can be used as a non-volatile memory after further processing.

In view of the foregoing problems, the present disclosure is capable of disposing the first dielectric layer, the second dielectric layer, the third dielectric layer, and the dielectric stack in the trench in sequence, so that the third dielectric layer and the dielectric stack can An air gap is formed between them, so as to avoid the problems of coupling interference and leakage current through the air gap. In particular, since the present disclosure uses a multi-layer dielectric layer with a dielectric stack structure, the reliability of the semiconductor structure can be maintained when wet etching is used to form the air gap, thereby improving the reliability of the subsequently formed memory device and performance.

The present disclosure provides a method for forming a semiconductor structure including: forming a floating gate layer on a substrate. Trenches are formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

The present disclosure provides a semiconductor structure including: a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer and a dielectric stack. The substrate has trenches between the active areas. The first dielectric layer is disposed in the trench. The second dielectric layer is disposed on the first dielectric layer. The third dielectric layer is disposed on the second dielectric layer. A dielectric stack is disposed on the third dielectric layer. There is an air gap between the third dielectric layer and the dielectric stack.

The semiconductor structure of the present disclosure can be applied to various types of memory devices. In order to make the components and advantages of the present disclosure more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

FIG. 1 to FIG. 11 and FIG. 13 are schematic cross-sectional views illustrating various stages of forming the semiconductor structure 1 according to some embodiments of the present disclosure. Fig. 12 is a schematic perspective view of Fig. 11, and Fig. 14 is a schematic perspective view of Fig. 13. Furthermore, FIG. 15 is a schematic top view, and FIG. 1 to FIG. 11 and FIG. 13 are schematic cross-sectional views taken along line XX' in FIG. 15 .

Referring to FIG. 1, in some embodiments, a substrate 100 is provided, and a tunneling dielectric layer 110, a floating gate layer 200, a first hard mask 210, and a second hard mask 220 are sequentially formed on the substrate. 100 on. That is, the tunnel dielectric layer 110 is formed on the substrate 100; the floating gate layer 200 is formed on the tunnel dielectric layer 110; the first hard mask 210 is formed on the floating gate layer 200; and the second Two hard masks 220 are formed on the first hard mask 210 .

The substrate 100 can be, for example, a silicon wafer; it can be a bulk semiconductor, or a semiconductor-on-insulation (SOI) substrate. In general, a semiconductor-on-insulation substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer or similar material, which provides an insulating layer on a silicon or glass substrate. Other types of substrate 100 include, for example, multi-layer or gradient substrates. In some embodiments, the substrate 100 can be an elemental semiconductor, the aforementioned elemental semiconductor includes silicon, germanium (germanium); the substrate 100 can also be a compound semiconductor, and the aforementioned compound semiconductor includes: for example, silicon carbide (silicon carbide), arsenide Gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide, but not limited thereto; the substrate 100 can also be Alloy semiconductor, the aforementioned alloy semiconductor includes: for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate.

The tunneling dielectric layer 110 can be or include oxide, nitride, oxynitride, combinations thereof, or any other suitable dielectric material, but the disclosure is not limited thereto. The tunneling dielectric layer 110 is, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, any other suitable dielectric material, or a combination thereof. High-k dielectric materials can be metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconium silicate salt, zircoaluminate.

The tunnel dielectric layer 110 can be formed by a deposition process or a thermal oxidation process. The aforementioned deposition process may include or may be a chemical vapor deposition (chemical vapor deposition, CVD) process, and the aforementioned CVD process may be a low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD), low temperature chemical vapor deposition ( low temperature chemical vapor deposition, LTCVD), rapid thermal chemical vapor deposition (rapid thermal chemical vapor deposition, RTCVD), PECVD, atomic layer chemical vapor deposition (atomic layer deposition, ALD), normal pressure Chemical vapor deposition (atmospheric pressure chemical vapor deposition, APCVD) or other suitable process.

The floating gate layer 200 may include polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, combinations thereof, or other suitable materials, but the disclosure is not limited thereto. In some embodiments, the floating gate layer 200 can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation or any other suitable deposition process.

In some embodiments, a first hard mask 210 and a second hard mask 220 are formed on the floating gate layer 200 . The first hard mask 210 and/or the second hard mask 220 may include oxides, nitrides, oxynitrides, carbides, or combinations thereof. It can be understood that the first hard mask 210 and the second hard mask 220 can be formed by selecting appropriate materials according to the subsequent etching process conditions, and therefore the embodiments of the present disclosure are not limited thereto. The first hard mask 210 may include oxide, and the second hard mask 220 may include nitride. The first hard mask 210 and/or the second hard mask 220 can be obtained by CVD deposition or other suitable processes. In some embodiments, the second hard mask 220 may be omitted or other hard masks may be further used.

After the first hard mask 210 and the second hard mask 220 are formed, the first hard mask 210 and the second hard mask 220 can be patterned according to the desired shape of the trench 300 . The trench 300 can be formed by using the first hard mask 210 and the second hard mask 220 as etching masks to remove the floating gate layer 200 , the tunneling dielectric layer 110 and a part of the substrate 100 through an etching process. In the floating gate layer 200 , the tunneling dielectric layer 110 and the substrate 100 . The foregoing etching process may include dry etching, wet etching, or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. In addition, the etching process can also be pure chemical etching, pure physical etching, or any combination thereof.

The trench 300 is used to define an active area such as that shown in FIG. 15 that follows. In other words, a plurality of active regions can be separated from each other by the trench 300 . The floating gate layer 200 and the subsequently formed control gate layer may be disposed in the active region. The trench 300 may be a shallow trench isolation structure. The trench 300 may penetrate through the second hard mask 220 , the first hard mask 210 , the floating gate layer 200 and the tunnel dielectric layer 110 , but not through the substrate 100 .

As shown in FIG. 1 , after the trench 300 is formed, a liner 310 and a first dielectric layer 320 are formed. The liner 310 may be conformally disposed in the trench 300 , and the first dielectric layer 320 may be conformally disposed on the liner 310 . The material and forming process of the liner layer 310 and/or the first dielectric layer 320 may be the same as or different from the material and forming process of the tunneling dielectric layer 110 . The liner 310 may include oxide, such as high temperature oxide (HTO) or silicon oxide. The first dielectric layer 310 may include nitride, such as silicon nitride. In some embodiments, the liner layer 310 and/or the first dielectric layer 320 may be formed by a deposition process.

Referring to FIG. 2 , a second dielectric layer 330 is formed on the first dielectric layer 320 . A second dielectric layer 330 is blanket formed on the first dielectric layer 320 . The material and forming process of the second dielectric layer 330 may be the same as or different from the material and forming process of the tunneling dielectric layer 110 . The second dielectric layer 330 may be formed by high density plasma chemical vapor deposition (HDP-CVD). After forming the second dielectric layer 330 , a planarization process may be further performed so that the top surface of the second dielectric layer 330 is substantially flush with the top surface of the first dielectric layer 320 . The aforementioned planarization process may be a chemical mechanical planarization (CMP) process.

The second dielectric layer 330 may include oxide, for example, oxide or silicon oxide formed from tetraethoxysilane (TEOS) as a precursor. In some embodiments, the second dielectric layer 330 may be porous oxide.

Referring to FIG. 3, a portion of the second dielectric layer 330 is removed by dry etching to expose the first dielectric layer 320 in the trench 300, and the second dielectric layer 330A remains on the first dielectric layer 320. superior. In some embodiments, the upper portion of the second dielectric layer 330 is removed by dry etching. The aforementioned dry etching process may be a reactive ion etching process. Therefore, the size and shape of the subsequently formed air gap can be controlled by precisely controlling the size and shape of the second dielectric layer 330A remaining on the first dielectric layer 320 by using a dry etching process.

After performing the dry etching process, the second dielectric layer 330A is exposed to the first dielectric layer 320 near the upper portion of the trench 300 . The second dielectric layer 330A covers the first dielectric layer 320 near the lower portion of the trench 300 . The top surface of the second dielectric layer 330A may be lower than, flush with, or higher than the tunneling dielectric layer 110 . According to application requirements, the height of the top surface of the second dielectric layer 330A can affect the size and shape of the subsequently formed air gap.

The second dielectric layer 330A may include an extension portion, and the aforementioned extension portion extends upward. The extension of the second dielectric layer 330A is located at the upper portion of the trench 300 . The extension of the second dielectric layer 330A extends toward a subsequently formed dielectric stack. The width of the extension portion of the second dielectric layer 330A gradually becomes smaller upward.

After performing the dry etching process, the second dielectric layer 330A has a concave top surface, such as a U-shaped top surface, a V-shaped top surface, a concave-shaped top surface, or other similar top surfaces. The second dielectric layer 330A has a convex bottom surface, such as a convex bottom surface. In some embodiments, the second dielectric layer 330A has a tip portion, and the tip portion is interposed between the first dielectric layer 320 and the subsequently formed third dielectric layer 430 . In some embodiments, the upper portion of the second dielectric layer 330A is smaller than the lower portion of the second dielectric layer 330A.

The etch rate of the second dielectric layer 330 can be greater than that of the liner layer 310 , so the second dielectric layer 330 can be etched more easily by an etching process to control the size of the second dielectric layer 330A. The etch rate of the second dielectric layer 330 may be greater than the etch rate of the first dielectric layer 320, so when a part of the second dielectric layer 330 is removed by dry etching, the first layer located in the trench 300 may not be damaged. Dielectric layer 320 . In other words, the first dielectric layer 320 can serve as an etch stop layer when etching the second dielectric layer 330 . In some embodiments, the liner 310 and the first dielectric layer 320 on the top surface of the second hard mask 220 may be further removed to expose the second hard mask 220, the liner 310 and the first dielectric. The top surface of layer 320.

Referring to FIG. 4 , a third dielectric layer 340 is formed on the second dielectric layer 330 . In some embodiments, third dielectric layer 340 is conformally formed on second hard mask 220 , liner layer 310 , first dielectric layer 320 and second dielectric layer 330A. In some embodiments, the first dielectric layer 320 , the second dielectric layer 330 and the third dielectric layer 340 are in contact with each other. In some embodiments, the first dielectric layer 320 and the third dielectric layer 340 surround the second dielectric layer 330A. In some embodiments, the first dielectric layer 320 directly covers the bottom surface of the second dielectric layer 330A, and the third dielectric layer 340 directly covers the top surface of the second dielectric layer 330A. Since the third dielectric layer 340 is conformally formed on the second dielectric layer 330A, the third dielectric layer 340 may have a shape corresponding to the second dielectric layer 330A.

The material and forming process of the third dielectric layer 340 may be the same as or different from the material and forming process of the tunneling dielectric layer 110 . The third dielectric layer 340 may include nitride, such as silicon nitride. In some embodiments, since both the first dielectric layer 320 and the third dielectric layer 340 are silicon nitride, the first dielectric layer 320 and the third dielectric layer 340 may substantially have no interface. In some embodiments, the third dielectric layer 340 may be formed by atomic layer deposition.

In some embodiments, the liner layer 310 and the second dielectric layer 330 may include oxide, and the first dielectric layer 320 and the third dielectric layer 340 may include nitride. Therefore, in the trench 300 shown in FIG. 1 , layers with different etch rates can be alternately arranged in the trench 300 . Wherein, the etch rate of each layer in the trench 300 can be alternately high and low. In some embodiments, the etch rate of the liner layer 310 is greater than the etch rate of the first dielectric layer 320, the etch rate of the first dielectric layer 320 is less than the etch rate of the second dielectric layer 330, and the second dielectric layer 330 The etch rate of is greater than the etch rate of the third dielectric layer 340 . Therefore, the present disclosure can control the shape of the subsequently formed air gap by using a layer with a high etch rate, and can use a layer with a low etch rate as an etch stop layer to provide support in the subsequently formed semiconductor structure.

Referring to FIG. 5 , a first sacrificial layer 400 is formed on the third dielectric layer 340 . In some embodiments, the first sacrificial layer 400 is blanket formed on the third dielectric layer 340 . The material and forming process of the first sacrificial layer 400 may be the same as or different from the material and forming process of the second dielectric layer 330 . After forming the first sacrificial layer 400 , a planarization process may be further performed so that the top surface of the first sacrificial layer 400 is substantially flush with the top surface of the third dielectric layer 340 . The first sacrificial layer 400 may be an oxide formed from tetraethoxysilane as a precursor, or may be a spin-on glass (SOG) oxide. In some embodiments, the first sacrificial layer 400 may be a porous oxide formed from tetraethoxysilane as a precursor.

Referring to FIG. 6 , a portion of the first sacrificial layer 400 is removed by dry etching to expose the third dielectric layer 340 in the trench 300 and the first sacrificial layer 400A remains on the third dielectric layer 340 . The aforementioned dry etching process may be a dry etching process performed by SiCoNi etching technology. Among them, the SiCoNi etching technology is a remote plasma-assisted dry etching process. Therefore, the size and shape of the first sacrificial layer 400A remaining on the third dielectric layer 340 can be precisely controlled by using a dry etching process. In some embodiments, the shape of the first sacrificial layer 400A corresponds to the shape of the second dielectric layer 330A. In some embodiments, the first sacrificial layer 400A has a concave top surface. In some embodiments, the top surface of the first sacrificial layer 400A is lower than the floating gate layer 200 .

Referring to FIG. 7, by using the first sacrificial layer 400A as an etching mask, a part of the third dielectric layer 340 and the first dielectric layer 320 is removed, so that the first dielectric layer 320A and the third dielectric layer 340A to expose the upper portion of the liner 310 in the trench 300 . In some embodiments, the first dielectric layer 320A, the third dielectric layer 340A, and the first sacrificial layer 400A are substantially coplanar. In some embodiments, the top surfaces of the first dielectric layer 320A, the third dielectric layer 340A and the first sacrificial layer 400A are lower than the liner layer 310 . In some embodiments, the third dielectric layer 340 and the second hard mask 220 on the top surface of the floating gate layer 200 may be further removed.

Referring to FIG. 8, a second sacrificial layer 500 is formed on the first sacrificial layer 400A. In some embodiments, the second sacrificial layer 500 is blanket formed on the first dielectric layer 320A, the third dielectric layer 340A and the first sacrificial layer 400A. The material and forming process of the second sacrificial layer 500 may be the same as or different from the material and forming process of the first sacrificial layer 400 . After forming the second sacrificial layer 500 , a planarization process may be further performed so that the top surface of the second sacrificial layer 500 is substantially flush with the top surfaces of the liner layer 310 and the first hard mask 210 . The second sacrificial layer 500 may be a porous oxide formed from tetraethoxysilane as a precursor. In some embodiments, the second sacrificial layer 500 may be spin-on glass (SOG) oxide. In some embodiments, since both the first sacrificial layer 400A and the second sacrificial layer 500 are porous oxides, the first sacrificial layer 400A and the second sacrificial layer 500 may substantially have no interface. In this embodiment, the second dielectric layer 330A can also be a porous oxide.

Referring to FIG. 9 , the second sacrificial layer 500 and the first hard mask 210 on the floating gate layer 200 are removed to expose the floating gate layer 200 . In some embodiments, the upper portion of liner 310 is removed, and liner 310A remains. The second sacrificial layer 500 and the first hard mask 210 can be removed by RF plasma etching and SICONI techniques. In some embodiments, the second sacrificial layer 500 may be completely removed, leaving the first sacrificial layer 400A. In other embodiments, a portion of the second sacrificial layer 500 may be removed, and another portion of the second sacrificial layer 500 may remain on the first sacrificial layer 400A. Understandably, the extent of removing the first sacrificial layer 400A can be adjusted according to subsequent electrical requirements.

As shown in FIG. 9 , in some embodiments, a portion of the floating gate layer 200 may be further removed to form an opening 510 in the floating gate layer 200 . In some embodiments, the opening 510 may be formed by dry etching. In some embodiments, the width of the opening 510 is greater than the width of the trench 300 shown in FIG. 1 . In some embodiments, opening 510 may be used to define the dimensions of a subsequently formed control gate.

Referring to FIG. 10, a dielectric stack 600 is formed on the first sacrificial layer 400A. In some embodiments, the dielectric stack 600 is conformally formed over the opening 510 . The dielectric stack 600 is conformally formed on the floating gate layer 200 , the liner layer 310A, the first dielectric layer 320A, the third dielectric layer 340A and the first sacrificial layer 400A. The dielectric stack 600 on the floating gate layer 200 is further away from the substrate 100 than the dielectric stack 600 on the first sacrificial layer 400A. The dielectric stack 600 may serve as a control dielectric layer in a subsequently formed memory device.

The dielectric stack 600 may include a first sublayer, a second sublayer, and a third sublayer. The first sub-layer is disposed on the first sacrificial layer 400A. The second sublayer is disposed on the first sublayer. The third sublayer is disposed on the second sublayer. Wherein, the first sublayer and the third sublayer may include oxide, and the second sublayer may include nitride. Therefore, the dielectric stack 600 may be an oxide-nitride-oxide (ONO) structure.

In another embodiment, the dielectric stack 600 may further include a bottom layer and a top layer. The bottom layer may be disposed between the first sacrificial layer 400A and the first sublayer. The top layer may be disposed between the third sub-layer and the subsequently formed control gate layer. Wherein, the bottom layer and the top layer of the dielectric stack 600 may include nitride. Therefore, the dielectric stack 600 may be a nitride-oxide-nitride-oxide-nitride (NONON) structure. In yet another embodiment, the dielectric layer stack 600 may only include silicon nitride or silicon oxide.

Referring to FIG. 11 , a control gate layer 700 is formed on the dielectric stack 600 . In some embodiments, the control gate layer 700 is blanket formed on the dielectric stack 600 . The material and forming process of the control gate layer 700 may be the same as or different from the material and forming process of the floating gate layer 200 . The control gate layer 700 may include polysilicon.

As shown in FIG. 12 , a double patterning process can be further performed on the control gate layer 700 . In some embodiments, a patterned hard mask may be formed on the control gate layer 700 to pattern the control gate layer 700 to form word lines WL as shown in FIG. 15 . According to requirements, the word line WL may further include other layers or components. The patterned control gate layers 700 extend along the first direction D1 and are arranged at intervals in the second direction D2. In some embodiments, spacers may be further formed on the sidewalls of the control gate layer 700 to reduce leakage current generation.

Referring to FIG. 13, after forming the control gate layer 700 on the dielectric stack 600, the first sacrificial layer between the third dielectric layer 340A and the dielectric stack 600 is removed by a wet etching process. layer 400A to obtain a semiconductor structure 1 with an air gap 800 . In some embodiments, a wet etching process is used to substantially completely remove the first sacrificial layer 400A, and the third dielectric layer 340A and the dielectric stack 600 are used as an etch stop layer corresponding to the first sacrificial layer 400A. The air gap 800 is formed at the position to obtain the semiconductor structure 1 .

In some embodiments, the air gap 800 has the same shape as the first sacrificial layer 400A. In some embodiments, the air gap 800 has a concave top surface and a convex bottom surface. In some embodiments, air gap 800 has a pointed portion. In some embodiments, the pointed portion of the air gap 800 is gentler than the pointed portion of the second dielectric layer 330A. In some embodiments, the air gap 800 has an extending portion extending upward, and the width of the extending portion of the air gap 800 gradually becomes smaller upward.

Air gaps 800 are formed on the third dielectric layer 340A, and are formed on the third dielectric layer 340A and between the dielectric stacks 600 . In some embodiments, the air gap 800 is in direct contact with the third dielectric layer 340A and the dielectric stack 600 . In some embodiments, the air gap 800 is surrounded by the third dielectric layer 340A and the dielectric stack 600 . In other words, the air gap 800 is formed in the space formed by the third dielectric layer 340A and the dielectric stack 600 . In some embodiments, air gap 800 may be filled with air, vacuum, or other suitable gas.

The air gap 800 is supported by the second dielectric layer 330A below the air gap 800 , so the depth of the air gap 800 disposed in the trench 300 as shown in FIG. 1 can be adjusted. When the thickness of the second dielectric layer 330A is thinner, the depth of the air gap 800 in the trench 300 as shown in FIG. 1 is deeper.

In some embodiments, the etch rate of the first sacrificial layer 400A is greater than that of the third dielectric layer 340A and the dielectric stack 600, so that the third dielectric layer 340A and the dielectric stack can be maintained while the first sacrificial layer 400A is removed. Reliability of the stack 600. That is, the etch rate of the first sacrificial layer 400A is greater than the etch rate of the third dielectric layer 340A, and the etch rate of the first sacrificial layer 400A is greater than that of the layers in the dielectric stack 600 that are in direct contact with the first sacrificial layer 400A. etch rate.

In case the dielectric stack 600 is an ONO structure, the first sublayer of the dielectric stack 600 is in direct contact with the first sacrificial layer 400A. Therefore, the etch rate of the first sacrificial layer 400A is greater than the etch rate of the first sublayer of the dielectric stack 600 and greater than the etch rate of the third dielectric layer 340A, so as to ensure that the dielectric stack 600 and the third dielectric layer 340A reliability.

In case the dielectric stack 600 is a NONON structure, the bottom layer of the dielectric stack 600 is in direct contact with the first sacrificial layer 400A. Therefore, the etch rate of the first sacrificial layer 400A is greater than the etch rate of the bottom layer of the dielectric stack 600 and greater than the etch rate of the third dielectric layer 340A, so as to ensure the reliability of the dielectric stack 600 and the third dielectric layer 340A. sex.

It should be noted that, as shown in FIG. 13, the first dielectric layer 320A and the third dielectric layer 340A are disposed adjacent to the air gap 800, so even if the first sacrificial layer 400A under the dielectric stack 600 has been removed While the air gap 800 is formed, the first dielectric layer 320A and the third dielectric layer 340A can still provide effective supporting force for the dielectric stack 600 .

It should be noted that the shape and size of the air gap 800 are based on the shape and size of the first sacrificial layer 400A, and the shape and size of the first sacrificial layer 400A are based on the shape and size of the second dielectric layer 330A. . Therefore, in the case that the second dielectric layer 330A is formed by a precise dry etching process, the present disclosure can accurately form the first sacrificial layer 400A, that is, accurately form the air gap 800 . Furthermore, since the present disclosure can form the air gap 800 through the dry etching process, the air gap 800 can be adjusted simply by adjusting the parameters of the dry etching process, so the present disclosure can provide various air gaps 800 The shape and size of the air gap 800 can be improved to improve the adjustability of the process for forming the air gap 800 .

Further processing may be performed on the semiconductor structure 1 as shown in FIG. 13 to form a memory device. As shown in FIG. 14, in some embodiments, the region between the trenches 300 as shown in FIG. The first sacrificial layer 400A is removed in the direction of the extending direction of AA to form the air gap 800 . In some embodiments, the air gap 800 is disposed between adjacent active areas AA and is not disposed in the active area AA. In some embodiments, the air gaps 800 extend along the second direction D2 and are spaced apart from each other along the first direction D1. In some embodiments, the air gap 800 can be directly disposed under the dielectric stack 600 to avoid coupling interference between the active areas AA and avoid leakage current generation.

Referring to FIG. 15, in some embodiments, the air gap 800 shown in FIG. 14 may be disposed in the region R1 shown in FIG. 15, and the extending direction of the air gap 800 is perpendicular to the extending direction of the word line WL. direction. In some embodiments, the extending direction of the air gap 800 is parallel to the extending direction of the active area AA.

In some embodiments, a capping layer may be further formed on the word line WL. The capping layer may include oxide. And the covering layer can be formed by chemical vapor deposition. The cover layer may comprise a material with a high step coverage to completely cover the region R1 as shown in FIG. 15 . The cover layer can prevent components disposed under the cover layer from being exposed, and can provide support for the semiconductor structure.

To sum up, since the semiconductor structure of the present disclosure includes an air gap, it can effectively reduce the coupling interference between the active regions and avoid the generation of leakage current. Meanwhile, the present disclosure sequentially arranges the first dielectric layer, the second dielectric layer, the third dielectric layer, the air gap and the dielectric stack to form a semiconductor structure with multiple dielectric layers and the dielectric stack.

Since the air gap is directly between the third dielectric layer and the dielectric stack, and the etch rate of the first sacrificial layer is greater than that of the third dielectric layer and the dielectric stack, when performing wet etching to form the air gap , the integrity and reliability of the third dielectric layer and the dielectric stack can be maintained. In addition, since the first sacrificial layer is completely surrounded by the third dielectric layer and the dielectric stack, the etching time can be shortened without being restricted by the third dielectric layer and the dielectric stack during the wet etching process. Or reduce the concentration of etchant. Therefore, the process margin for executing the wet etching process can be improved.

In addition, the forming method of the present disclosure can avoid the problem of easily destroying the integrity of the air gap and the control gate layer when forming the air gap first and then forming the control gate layer on the air gap. For example, since the present disclosure first arranges components such as the first sacrificial layer at the predetermined position of the air gap, it can help to form a high-quality control gate layer on the first sacrificial layer, thereby ensuring that the control gate layer reliability.

Furthermore, since the shape and size of the air gap in the present disclosure correspond to the shape and size of the second dielectric layer, and the second dielectric layer is precisely formed by a dry etching process, the present disclosure can be easily borrowed. The shape and size of the air gap are controlled by controlling the parameters of the dry etching process. In addition, since the present disclosure has the liner, the first dielectric layer, and the third dielectric layer adjacent to the air gap at the upper portion of the trench, the supporting force of the dielectric stack can be improved while maintaining the reliability of the semiconductor structure. sex.

For example, where an air gap exists below the dielectric stack, support for the dielectric stack can be provided by the liner, first dielectric layer, and third dielectric layer adjacent to the air gap , thereby avoiding the breakdown of the dielectric stack. At the same time, the forming method provided by the present disclosure can be applied to existing semiconductor manufacturing equipment, so the manufacturing process cost can be reduced. In summary, the present disclosure can provide a semiconductor structure with high reliability and excellent performance and a method for forming the same.

Those with ordinary knowledge in the technical field should understand that they can design or modify other processes and structures based on the disclosed embodiments to achieve the same purpose and/or advantages as the embodiments introduced here, and they can Various changes, substitutions and substitutions may be made without departing from the spirit and scope of this disclosure.

1: Semiconductor structure 100: Substrate 110: tunnel dielectric layer 200: floating gate layer 210: First hard mask 220: second hard mask 300: Groove 310, 310A: lining 320, 320A: first dielectric layer 330, 330A: second dielectric layer 340, 340A: third dielectric layer 400, 400A: the first sacrificial layer 500: second sacrificial layer 510: opening 600: Dielectric Stacks 700: Control gate layer 800: air gap AA: active area D1: the first direction D2: Second direction R1: Region WL: character line

FIG. 1 to FIG. 11 are schematic cross-sectional views illustrating the formation of semiconductor structures in various stages according to some embodiments of the present disclosure. FIG. 12 is a perspective view illustrating a semiconductor structure according to some embodiments of the present disclosure. FIG. 13 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure. FIG. 14 is a perspective view illustrating a semiconductor structure according to some embodiments of the present disclosure. FIG. 15 is a schematic top view illustrating a semiconductor structure according to some embodiments of the present disclosure.

1: Semiconductor structure

100: Substrate

110: tunnel dielectric layer

200: floating gate layer

310A: lining

320A: first dielectric layer

330A: second dielectric layer

340A: third dielectric layer

600: Dielectric Stacks

700: Control gate layer

800: air gap

Claims (10)

A method of forming a semiconductor structure, comprising: forming a floating gate layer on a substrate; forming a trench in the floating gate layer and the substrate; forming a first dielectric layer in the trench; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; forming a first sacrificial layer on the third dielectric layer; forming a dielectric stack on the first sacrificial layer; forming a control gate layer on the dielectric stack; and The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack. The forming method according to claim 1, wherein forming the second dielectric layer on the first dielectric layer further comprises: blanket forming the second dielectric layer on the first dielectric layer; and A portion of the second dielectric layer is removed to expose the first dielectric layer in the trench. The forming method as claimed in claim 2, wherein the third dielectric layer is conformally formed on the floating gate layer, the first dielectric layer and the second dielectric layer. The forming method as claimed in claim 1, wherein a lining layer is formed in the groove, and the lining layer is interposed between the substrate and the first dielectric layer, and the first sacrificial layer is formed on the third The dielectric layer further includes: blanket forming the first sacrificial layer on the third dielectric layer; removing a portion of the first sacrificial layer to expose the third dielectric layer in the trench; and The third dielectric layer, the first dielectric layer and the liner layer are removed to expose the floating gate layer. The forming method as claimed in claim 4, wherein removing the third dielectric layer, the first dielectric layer and the liner layer further comprises: using the remaining portion of the first sacrificial layer as a mask, removing the third dielectric layer and the first dielectric layer to expose the liner; forming a second sacrificial layer on the remainder of the first sacrificial layer; The second sacrificial layer and the liner layer are removed to expose the floating gate layer. The forming method of claim 1, wherein after forming the dielectric stack on the first sacrificial layer, the first sacrificial layer is removed by wet etching. A semiconductor structure comprising: a substrate with a trench between a plurality of active regions; a first dielectric layer disposed in the trench; a second dielectric layer disposed on the first dielectric layer; a third dielectric layer disposed on the second dielectric layer; and A dielectric stack is disposed on the third dielectric layer with an air gap between the third dielectric layer and the dielectric stack. The semiconductor structure of claim 7, wherein the air gap is in direct contact with the third dielectric layer and the dielectric stack. The semiconductor structure of claim 7, wherein the air gap is surrounded by the third dielectric layer and the dielectric stack. The semiconductor structure of claim 7, wherein the second dielectric layer comprises oxide, and the first dielectric layer and the third dielectric layer comprise nitride.

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