TW202303767A - 半導體結構的製造方法 - Google Patents
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Abstract
半導體結構的製造方法包含在製造過程期間選擇性使用包覆層,以提供臨界尺寸均勻度。包覆層可在主動通道結構中形成凹口之前形成,或是可在以介電材料填充主動通道結構中的凹口之後形成。這些技術可用於半導體結構中,例如積體電路中實現的全繞式閘極電晶體結構。
Description
本發明實施例係有關於半導體技術,且特別是有關於半導體結構的製造方法。
本發明實施例一般有關於半導體裝置及半導體裝置的製造方法,且特別有關於透過半導體製造過程提供臨界尺寸均勻度(critical dimension uniformity)。隨著半導體裝置持續縮小尺寸,在製造過程的一致性方面可能會出現挑戰。半導體裝置用於各種電子產品中,並且通常期望在半導體裝置的生產和效能方面作出改進。
在一些實施例中,提供半導體結構的製造方法,此方法包含移除主動通道結構的一部分,以形成凹口;以介電材料填充凹口;形成包覆層相鄰於主動通道結構,但是不相鄰於介電材料;以及形成圍繞主動通道結構的閘極結構。
在一些實施例中,提供半導體結構的製造方法,此方法包含形成包覆層相鄰於主動通道結構的第一側、第二側、第三側和第四側;透過移除包覆層的一部分和主動通道結構的一部分來形成凹口,使得在形成凹口之後,包覆層相鄰於主動通道結構的第一側、第二側和第三側,但是不相鄰於主動通道結構的第四側;以介電材料填充凹口;以及形成圍繞主動通道結構的閘極結構。
在另外一些實施例中,提供半導體結構的製造方法,此方法包含形成圍繞主動通道結構的包覆層;在形成圍繞主動通道結構的包覆層之後,移除包覆層的一部分和主動通道結構的一部分;以及形成圍繞主動通道結構的閘極結構。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例,以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例,以求簡化揭露內容的說明。當然,這些僅為範例並非用以限定本發明。例如,元件之尺寸不限於本揭示之一實施方式之範圍或數值,但可取決於元件之處理條件及/或要求性質。此外,在隨後描述中在第二部件上方或在第二部件上形成第一部件之包括第一及第二部件形成為直接接觸之實施例,以及亦可包括額外部件可形成在第一及第二部件之間,使得第一及第二部件可不直接接觸之實施例。此外,揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者,為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係,可使用空間相關用語,例如“在...之下”、“下方”、“下部”、“在...之上”、“上部”及類似的用語。除了圖式所繪示的方位之外,空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如,旋轉90度或者位於其他方位),並對應地解讀所使用的空間相關用語的描述。
本發明實施例提供用於提供半導體結構(例如透過選擇性使用包覆層的全繞式場效電晶體(gate-all-around field-effect transistor,GAAFET)結構)的臨界尺寸均勻性的技術。包覆層可在主動通道結構中形成凹口之前形成,或是可在以介電材料填充主動通道結構中的凹口之後形成。可選擇性使用包覆層,以為在積體電路中形成閘極結構提供一致且更大的製程裕度。
請參照第1A圖,第1A圖為依據一些實施例之例示性半導體結構100的透視圖。半導體結構100一般包含複數個全繞式閘極電晶體結構。這些結構有時也被稱為環繞式閘極電晶體(surrounding-gate transistor,SGT)結構。相較於一些其他結構(例如鰭式場效電晶體(fin field-effect transistor,FinFET)結構),全繞式閘極電晶體結構一般可允許形成更小的電晶體結構,進而形成更小且更緊密的積體電路。應當理解的是,本文描述的方法可應用至除了全繞式閘極電晶體結構之外的其他類型的半導體結構。請參照第1B圖,第1B圖為依據一些實施例,從第1A圖顯示的剖面170截取的半導體結構100的剖面示意圖。
顯示的半導體結構100包含閘極結構112和閘極結構114。閘極結構112和閘極結構114可用作金屬閘極結構,例如高介電常數金屬閘極(high-k metal gate,HKMG)結構。在這些實施例中,形成包含導電金屬材料及具有高介電常數(high-k)的介電材料的堆疊物。堆疊物也可包含功函數層、蓋層及/或其他層,以形成用於預期應用的合適高介電常數金屬閘極結構。高介電常數金屬閘極結構可透過使用各種合適製程形成,這些製程包含閘極先製及閘極後製的實施例。閘極結構112和閘極結構114一般以平行關係設置,且可為包含未顯示於第1B圖中的額外、相似的閘極結構的平行閘極堆疊物的一部分。在一些應用中,相較於使用多晶矽閘極,使用高介電常數金屬閘極結構可提供減少的電荷洩漏,進而改善效能。然而,應當理解的是,本文描述的技術也可應用至具有多晶矽閘極結構以及其他類型的閘極結構的半導體裝置。
顯示的半導體結構100也包含磊晶區122和磊晶區124。磊晶區122和磊晶區124一般作為各自全繞式閘極電晶體結構的源極端子和汲極端子。磊晶區122和磊晶區124一般為晶體結構,且可透過使用磊晶成長製程形成,例如氣相磊晶(vapor-phase epitaxy,VPE)、分子束磊晶(molecular beam epitaxy,MBE)製程、液相磊晶(liquid-phase epitaxy,LPE)及其他合適的製程或前述之組合。磊晶區122和磊晶區124可使用合適的摻雜物來摻雜,包含n型和p型摻雜物,例如胂、磷化氫、乙硼烷、其他合適的摻雜物或前述之組合。
顯示的半導體結構100也包含絕緣層132、絕緣層134和絕緣層136。絕緣層132、絕緣層134和絕緣層136的每一者可例如用作層間介電(inter-layer dielectric,ILD)結構。絕緣層132、絕緣層134和絕緣層136也可用作接觸蝕刻停止層(contact etch stop layer,CESL)。絕緣層132、絕緣層134和絕緣層136可透過使用材料例如二氧化矽(SiO
2)、 氮氧化矽(SiON)、 氮化矽(Si
3N
4)、氮碳化矽(SiCN)、氮碳氧化矽(SiOCN)、氧化鉿(HfO
2)、氮化鉭(TaN)或其他合適的材料或前述之組合形成。
顯示的半導體結構100也包含複數個主動通道結構140。在一些實施例中,主動通道結構140用作被閘極結構112、閘極結構114、磊晶區122、磊晶區124圍繞的奈米片。然而,主動通道結構140也可透過使用其他方式使用,包含用作圓形奈米線。主動通道結構140一般透過使用矽形成,然而,主動通道結構140也可透過使用其他合適的材料或前述之組合來使用。
顯示的半導體結構100也包含介電區150。介電區150形成相鄰於閘極結構112和閘極結構114,且介電區150可與以下描述的包覆層一同在製造過程期間使用,以在半導體結構100中提供臨界尺寸均勻性。介電區可透過使用二氧化矽、氮氧化矽、 氮化矽、氮碳化矽、氮碳氧化矽、氧化鉿、氮化鉭或其他合適的材料或前述之組合形成。
顯示的半導體結構100也包含基底160。基底160可為n型基底或p型基底。舉例來說,基底160可由摻雜n型摻雜物(例如砷、磷或其他相似摻雜物)的矽材料(例如結晶矽)形成。基底160也可摻雜p型摻雜物(例如硼或其他相似摻雜物)。基底160可透過使用絕緣層上覆矽結構、藍寶石上覆矽結構、各種其他合適的材料或前述之組合來實現。
顯示的半導體結構100也包含隔離結構152。隔離結構152一般可防止半導體結構100的組件之間的漏電流。舉例來說,隔離結構152可實現用作淺溝槽隔離(shallow trench isolation,STI)結構。隔離結構152可透過在基底160中形成溝槽,以絕緣材料填充溝槽,並使用例如化學機械研磨(chemical-mechanical polishing,CMP)的製程移除多餘的絕緣材料來形成。隔離結構152一般提供用於其上形成半導體結構100的其他組件的基底。
在第1B圖中,寬度W
G1標註閘極結構112的寬度,寬度W
G2標註閘極結構114的寬度,寬度W
I標註絕緣層134的寬度。透過在製造過程(例如參考以下製程200和製程300描述)期間選擇性使用包覆層,可將寬度W
G1製作等於寬度W
G2。在一些實施例中,寬度W
G1和W
G2可大致相等,例如在彼此的5%中或彼此的10%中。臨界尺寸均勻度可在半導體裝置產率及半導體裝置效能上提供優點,特別是在較小節點尺寸的應用上。再者,可將寬度W
G1和W
G2製造小於寬度W
I。
應當理解的是,半導體結構100可包含未在本文明確描述的各種額外層及材料。舉例來說,間隙壁結構(例如具有高介電常數(high-k)的間隙壁結構)可形成圍繞閘極結構112和閘極結構114,以提供閘極結構112和閘極結構114的電性隔離。再者,額外介電層可形成於半導體結構100中的各個其他位置中。
請參照第1C和1D圖,第1C和1D圖顯示依據一些實施例,半導體結構100在製造過程期間的兩個透視俯視圖。在第1C圖中,包覆層220形成相鄰於主動通道結構140的第一側、主動通道結構140的第二側及主動通道結構140的第三側,但是不形成於主動通道結構140的第四側周圍。包覆層220可一般由矽鍺(SiGe)或其他合適的材料形成,如以下進一步討論細節。在第1D圖中,包覆層320相似地形成相鄰於主動通道結構140的第一側、主動通道結構140的第二側及主動通道結構140的第三側,但是不形成於主動通道結構140的第四側周圍。在第1D圖中,介電區150也形成於主動通道結構140中。包覆層320也可由矽鍺或其他合適的材料形成,如以下進一步討論細節。第1C和1D圖提供的俯視圖分別顯示選擇性使用包覆層220和320,包覆層220和320可提供臨界尺寸均勻度。
請參照第2A圖,第2A圖顯示依據一些實施例,製造半導體結構100的例示性製程200的流程圖。第2B-2M圖顯示半導體結構100在製程200的各步驟中的剖面示意圖。第2B、2D、2F、2H、2J和2L圖顯示在水平方向(例如從第1A圖顯示的剖面170截取的x方向)截取的半導體結構100的剖面示意圖,而第2C、2E、2G、2I、2K和2M圖顯示在垂直方向(例如y方向)截取的半導體結構100的剖面示意圖。製程200一般包含在製造過程期間,在切割主動通道結構140以形成凹口之前,形成包覆層220圍繞主動通道結構140。
在步驟201,形成主動通道結構(第2B和2C圖)。如第2B和2C圖顯示,主動通道結構140形成於基底160之上,且在複數個犧牲層210之間。如上所述,可實現主動通道結構140作為奈米結構(例如奈米片或奈米線),用以形成全繞式閘極場效電晶體。在形成閘極結構112和閘極結構114圍繞主動通道結構140之前,在製造過程期間使用犧牲層210來隔開主動通道結構140。犧牲層210可透過使用矽鍺、其他合適的材料或前述之組合形成。如以下討論,最終移除犧牲層210。
在步驟202,形成圍繞主動通道結構的包覆層(第2D和2E圖)。如第2D和2E圖顯示,包覆層220形成圍繞主動通道結構140。包覆層220可透過使用磊晶成長製程形成,例如氣相磊晶、分子束磊晶、液相磊晶、其他合適的製程或前述之組合。包覆層220可由矽鍺、其他合適的材料或前述之組合形成。在包覆層220和犧牲層210皆由矽鍺形成的實施例中,包覆層220一般可透過使用較高濃度的鍺來形成。應注意的是,步驟202中包覆層220的形成在切割主動通道結構140之前發生。在步驟202中,形成圍繞主動通道結構140的包覆層220,使得包覆層220形成相鄰於主動通道結構140的第一側、主動通道結構140的第二側、主動通道結構140的第三側以及主動通道結構140的第四側。
在步驟203,移除主動通道結構的一部分及包覆層的一部分,以形成凹口(第2F和2G圖)。如第2F和2G圖顯示,移除主動通道結構140、犧牲層210和包覆層220的一部分,以形成凹口230。步驟203的移除製程可使用一個或多個蝕刻製程進行,蝕刻製程包含乾蝕刻製程和濕蝕刻製程,以及反應性離子蝕刻製程及其他合適類型的蝕刻製程。再者,步驟203可使用各種不同的蝕刻化學物,以移除主動通道結構140、犧牲層210和包覆層220的一部分,以形成凹口230。應注意的是,由於在步驟203的移除製程之前形成包覆層220,因此包覆層220將僅相鄰於主動通道結構140的第一側、主動通道結構140的第二側及主動通道結構140的第三側,但是不在主動通道結構140的第四側,如以上第1C圖顯示。
在步驟204,以介電材料填充凹口,並形成虛設閘極結構(第2H和2I圖)。如第2H和2I圖顯示,以介電材料填充凹口230,並形成介電區150。介電區150可透過使用沉積製程(例如化學氣相沉積、其他合適的製程或前述之組合)形成於凹口230中。接著,虛設閘極結構242和虛設閘極結構244形成於介電區150和包覆層220之上。虛設閘極結構242和虛設閘極結構244可透過使用多晶矽、其他合適的材料或前述之組合形成。虛設閘極結構242和虛設閘極結構244可透過使用例如化學氣相沉積、其他合適的製程或前述之組合的製程形成。虛設閘極結構242和虛設閘極結構244一般在製造過程期間作為佔位物,且在形成閘極結構112和閘極結構114之前移除虛設閘極結構242和虛設閘極結構244。應理解的是,可在虛設閘極結構242、虛設閘極結構244及相鄰結構之間形成各種材料,例如絕緣層或其他類型層。
在步驟205,形成圍繞主動通道結構的磊晶區(第2J和2K圖)。如第2J圖所示,形成圍繞主動通道結構140的磊晶區122和磊晶區124。如上所述,磊晶區122和磊晶區124一般可作為電晶體的源極和汲極端子。因此,磊晶區122和磊晶區124可使用合適的摻雜物(包含n型摻雜物和p型摻雜物)摻雜。磊晶區122和磊晶區124可透過使用磊晶成長製程形成,例如氣相磊晶、分子束磊晶、液相磊晶、其他合適的製程或前述之組合。在一些實施例中,在形成磊晶層122和磊晶區124之前,使用合適的蝕刻製程移除犧牲層210及/或包覆層220的一部分。
在步驟206,移除虛設閘極結構,並形成圍繞主動通道結構的主動閘極結構(第2L和2M圖)。如第2L和2M圖所示,沿犧牲層210移除虛設閘極結構242和虛設閘極結構244。這些結構可使用各種合適的蝕刻製程來移除,蝕刻製包含乾蝕刻製程和濕蝕刻製程,以及反應性離子蝕刻製程及其他合適類型的蝕刻製程。接著,閘極結構112和閘極結構114形成圍繞主動通道結構140,以形成電晶體的主動閘極結構。由於在製程200選擇性使用包覆層220,因此在步驟206中形成閘極結構112和閘極結構114的製程裕度更加一致,進而形成閘極結構112的寬度等於閘極結構114的寬度。這些更加一致的製程裕度可幫助防止不期望的效果,例如相對於介電區150和其他結構的重疊偏移(overlap shift)。額外地,在步驟206中,絕緣層132、絕緣層134和絕緣層136可形成相鄰於閘極結構112和閘極結構114。透過在製程200中選擇性使用包覆層220而獲得改善的製程裕度還可以允許絕緣層134的寬度分別大於閘極結構112的寬度和閘極結構114的寬度。
請參照第3A圖,第3A圖顯示依據一些實施例,製造半導體結構100的例示性製程300的流程圖。第3B-3M圖顯示半導體結構100在製程300的各步驟中的剖面示意圖。第3B、3D、3F、3H、3J和3L圖顯示在水平方向(例如從第1A圖顯示的剖面170截取的x方向)截取的半導體結構100的剖面示意圖,而第3C、3E、3G、3I、3K和3M圖顯示在垂直方向(例如y方向)截取的半導體結構100的剖面示意圖。製程300一般包含在形成包覆層330圍繞主動通道結構140之前,切割主動通道結構140,以形成凹口,並以介電材料填充凹口。
在步驟301,形成主動通道結構(第3B和3C圖)。如第3B和3C圖顯示,主動通道結構140形成於基底160之上,且在複數個犧牲層310之間。如上所述,可實現主動通道結構140作為奈米結構,用以形成全繞式閘極場效電晶體。犧牲層310相似於犧牲層210,其中在形成閘極結構112和閘極結構114圍繞主動通道結構140之前,在製造過程期間使用犧牲層310來隔開主動通道結構140。犧牲層310可透過使用矽鍺、其他合適的材料或前述之組合形成。相似於犧牲層210,最終移除犧牲層310。
在步驟302,移除主動通道結構的一部分,以形成凹口(第3D和3E圖)。如第3D和3E圖所示,移除主動通道結構140和犧牲層310的一部分,以形成凹口330。步驟302的移除製程可使用一個或多個蝕刻製程進行,蝕刻製程包含乾蝕刻製程和濕蝕刻製程,以及反應性離子蝕刻製程及其他合適類型的蝕刻製程。再者,步驟302可使用各種不同的蝕刻化學物,以移除主動通道結構140、犧牲層310的一部分,以形成凹口330。應注意的是,不同於製程200,製程300的步驟302中進行的移除製程在形成包覆層320之前發生。
在步驟303,在凹口中形成介電材料,並形成圍繞主動通道結構的包覆層(第3F和3G圖)。如第3F和3G圖所示,在凹口330中形成介電區150。介電區150可透過使用沉積製程(例如化學氣相沉積、其他合適的製程或前述之組合)形成於凹口330中。接著,包覆層320形成圍繞主動通道結構140和介電區150。包覆層320可透過使用磊晶成長製程形成,例如氣相磊晶、分子束磊晶、液相磊晶、其他合適的製程或前述之組合。包覆層320可由矽鍺、其他合適的材料或前述之組合形成。在包覆層320和犧牲層310皆由矽鍺形成的實施例中,包覆層320一般可透過使用較高濃度的鍺來形成。應注意的是,由於包覆層320透過使用磊晶成長製程形成,因此包覆層320不會成長於介電區150上,但是將成長於主動通道結構140上。因此,在步驟303中,形成圍繞主動通道結構140的包覆層320,由於存在介電區150的緣故,使得包覆層320形成相鄰於主動通道結構140的第一側、主動通道結構140的第二側、主動通道結構140的第三側,但是不形成於主動通道結構140的第四側,如以上第1D圖所示。
在步驟304,形成虛設閘極結構(第3H和3I圖)。如第3H和3I圖所示,虛設閘極結構342和虛設閘極結構344形成於介電區150和包覆層320之上。虛設閘極結構342和虛設閘極結構344可透過使用多晶矽、其他合適的材料或前述之組合形成。虛設閘極結構342和虛設閘極結構344可透過使用例如化學氣相沉積、其他合適的製程或前述之組合的製程形成。虛設閘極結構342和虛設閘極結構344一般在製造過程期間作為佔位物,且在形成閘極結構112和閘極結構114之前移除虛設閘極結構342和虛設閘極結構344。應理解的是,可在虛設閘極結構342、虛設閘極結構344及相鄰結構之間形成各種材料,例如絕緣層或其他類型層。
在步驟305,形成圍繞主動通道結構的磊晶區(第3J和3K圖)。如第3J圖所示,形成圍繞主動通道結構140的磊晶區122和磊晶區124。如上所述,磊晶區122和磊晶區124一般可作為電晶體的源極和汲極端子。因此,磊晶區122和磊晶區124可使用合適的摻雜物(包含n型摻雜物和p型摻雜物)摻雜。磊晶區122和磊晶區124可透過使用磊晶成長製程形成,例如氣相磊晶、分子束磊晶、液相磊晶、其他合適的製程或前述之組合。在一些實施例中,在形成磊晶層122和磊晶區124之前,使用合適的蝕刻製程移除犧牲層310及/或包覆層320的一部分。
在步驟306,移除虛設閘極結構,並形成圍繞主動通道結構的主動閘極結構(第3L和3M圖)。如第3L和3M圖所示,沿犧牲層310移除虛設閘極結構342和虛設閘極結構344。這些結構可使用各種合適的蝕刻製程來移除,蝕刻製包含乾蝕刻製程和濕蝕刻製程,以及反應性離子蝕刻製程及其他合適類型的蝕刻製程。接著,閘極結構112和閘極結構114形成圍繞主動通道結構140,以形成電晶體的主動閘極結構。由於在製程300選擇性使用包覆層320,因此在步驟306中形成閘極結構112和閘極結構114的製程裕度更加一致,進而形成閘極結構112的寬度等於閘極結構114的寬度。這些更加一致的製程裕度可幫助防止不期望的效果,例如相對於介電區150和其他結構的重疊偏移(overlap shift)。額外地,在步驟306中,絕緣層132、絕緣層134和絕緣層136可形成相鄰於閘極結構112和閘極結構114。透過在製程300中選擇性使用包覆層320而獲得改善的製程裕度還可以允許絕緣層134的寬度分別大於閘極結構112的寬度和閘極結構114的寬度。
應當理解的是,以上描述的製程200和製程300僅供範例,而製程200和製程300的各種變化也在本發明實施例考慮的範圍中。
如上所述,本發明實施例提出透過選擇性使用包覆層,在半導體結構(例如全繞式閘極場效電晶體(GAAFET))中提供臨界尺寸均勻度的技術。包覆層可在主動通道結構中形成凹口之前形成,或是可在以介電材料填充主動通道結構中的凹口之後形成。可選擇性使用包覆層,以為在積體電路中形成閘極結構提供一致且更大的製程裕度。
本發明一實施例為半導體結構的製造方法,此方法包含移除主動通道結構的一部分,以形成凹口;以介電材料填充凹口;形成包覆層相鄰於主動通道結構,但是不相鄰於介電材料;以及形成圍繞主動通道結構的閘極結構。
在一些其他實施例中,其中形成包覆層的步驟包含形成矽鍺層相鄰於主動通道結構,但是不相鄰於介電材料。
在一些其他實施例中,其中形成包覆層的步驟包含使用磊晶成長製程形成包覆層。
在一些其他實施例中,其中閘極結構包含主動閘極結構,上述方法更包含:形成圍繞主動通道結構的虛設閘極結構;以及在形成主動閘極結構之前,移除虛設閘極結構。
在一些其他實施例中,其中閘極結構包含第一閘極結構,上述方法更包含形成圍繞主動閘極結構的第二閘極結構,使得第一閘極結構的寬度等於第二閘極結構的寬度。
在一些其他實施例中,上述方法更包含形成圍繞主動通道結構的磊晶區。
在一些其他實施例中,上述方法更包含在形成包覆層相鄰於主動通道結構之前,移除相鄰於主動通道結構的隔離結構的一部分。
在一些其他實施例中,其中形成包覆層的步驟包含形成矽鍺層相鄰於主動通道結構的第一側、第二側、第三側和第四側。
在一些其他實施例中,上述方法更包含形成圍繞主動通道結構的磊晶區。
本發明另一實施例為半導體結構的另一製造方法,此方法包含形成包覆層相鄰於主動通道結構的第一側、第二側、第三側和第四側;透過移除包覆層的一部分和主動通道結構的一部分來形成凹口,使得在形成凹口之後,包覆層相鄰於主動通道結構的第一側、第二側和第三側,但是不相鄰於主動通道結構的第四側;以介電材料填充凹口;以及形成圍繞主動通道結構的閘極結構。
在一些其他實施例中,其中閘極結構包含主動閘極結構,上述方法更包含:形成圍繞主動通道結構的虛設閘極結構;以及在形成主動閘極結構之前,移除虛設閘極結構。
在一些其他實施例中,其中閘極結構包含第一閘極結構,上述方法更包含形成圍繞主動通道結構的第二閘極結構,使得第一閘極結構的寬度等於第二閘極結構的寬度。
在一些其他實施例中,其中以介電材料填充凹口的步驟包含以介電材料填充凹口,使得介電材料的寬度大於第一閘極結構的寬度和第二閘極結構的寬度。
在一些其他實施例中,其中形成包覆層的步驟包含使用磊晶成長製程形成包覆層。
本發明另一實施例為半導體結構的另一製造方法,此方法包含形成圍繞主動通道結構的包覆層;在形成圍繞主動通道結構的包覆層之後,移除包覆層的一部分和主動通道結構的一部分;以及形成圍繞主動通道結構的閘極結構。
在一些其他實施例中,其中形成包覆層的步驟包含使用磊晶成長製程成長圍繞主動通道結構的包覆層。
在一些其他實施例中,其中移除包覆層的一部分和主動通道結構的一部分的步驟包含移除包覆層的一部分和主動通道結構的一部分,以形成凹口,上述方法更包含在凹口中形成介電材料。
在一些其他實施例中,其中閘極結構包含主動閘極結構,上述方法更包含:形成圍繞主動通道結構的虛設閘極結構;以及在形成主動閘極結構之前,移除虛設閘極結構。
在一些其他實施例中,上述方法更包含形成圍繞主動通道結構的磊晶區。
在一些其他實施例中,其中閘極結構包含第一閘極結構,上述方法更包含形成圍繞主動通道結構的第二閘極結構,使得第一閘極結構的寬度等於第二閘極結構的寬度。
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解,且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構,並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下,可對本發明實施例進行各種改變、置換或修改。
100:半導體結構
112,114:閘極結構
122,124:磊晶區
132,134,136:絕緣層
140:主動通道結構
150:介電區
152:隔離結構
160:基底
170:剖面
200,300:方法
201,202,203,204,205,206,301,302,303,304,305,306:步驟
210,310:犧牲層
220,320:包覆層
230,330:凹口
242,244,342,344:虛設閘極結構
W
G1,W
G2,W
I:寬度
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是,根據本產業的標準慣例,圖示中的各種部件(feature)並未必按照比例繪製。事實上,可能任意的放大或縮小各種部件的尺寸,以做清楚的說明。
第1A圖為依據一些實施例之例示性半導體結構的透視圖。
第1B圖為依據一些實施例,第1A圖的例示性半導體結構的剖面示意圖。
第1C和1D圖為依據一些實施例,第1A圖的半導體結構在製造過程期間的透視俯視圖。
第2A圖顯示依據一些實施例,製造第1A圖的半導體結構的例示性製程的流程圖。
第2B-2M圖顯示第1A圖的半導體結構在第2A圖的製程的各步驟中的剖面示意圖。
第3A圖顯示依據一些實施例,製造第1A圖的半導體結構的另一例示性製程的流程圖。
第3B-3M圖顯示第1A圖的半導體結構在第3A圖的製程的各步驟中的剖面示意圖。
200:方法
201,202,203,204,205,206:步驟
Claims (1)
- 一種半導體結構的製造方法,包括: 移除一主動通道結構的一部分,以形成一凹口; 以一介電材料填充該凹口; 形成一包覆層相鄰於該主動通道結構,但是不相鄰於該介電材料;以及 形成圍繞該主動通道結構的一閘極結構。
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