CN115332319A - 半导体结构的制造方法 - Google Patents

半导体结构的制造方法 Download PDF

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Publication number
CN115332319A
CN115332319A CN202210670355.6A CN202210670355A CN115332319A CN 115332319 A CN115332319 A CN 115332319A CN 202210670355 A CN202210670355 A CN 202210670355A CN 115332319 A CN115332319 A CN 115332319A
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active channel
channel structure
cladding layer
gate
forming
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高魁佑
林士尧
陈振平
林志翰
张铭庆
陈昭成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体结构的制造方法包含在制造过程期间选择性使用包覆层，以提供临界尺寸均匀度。包覆层可在主动通道结构中形成凹口之前形成，或是可在以介电材料填充主动通道结构中的凹口之后形成。这些技术可用于半导体结构中，例如集成电路中实现的全绕式栅极晶体管结构。

Description

半导体结构的制造方法
技术领域
本发明实施例涉及半导体技术，且特别涉及半导体结构的制造方法。
背景技术
本发明实施例一般有关于半导体装置及半导体装置的制造方法，且特别有关于通过半导体制造过程提供临界尺寸均匀度(critical dimension uniformity)。随着半导体装置持续缩小尺寸，在制造过程的一致性方面可能会出现挑战。半导体装置用于各种电子产品中，并且通常期望在半导体装置的生产和效能方面作出改进。
发明内容
在一些实施例中，提供半导体结构的制造方法，此方法包含移除主动通道结构的一部分，以形成凹口；以介电材料填充凹口；形成包覆层相邻于主动通道结构，但是不相邻于介电材料；以及形成围绕主动通道结构的栅极结构。
在一些实施例中，提供半导体结构的制造方法，此方法包含形成包覆层相邻于主动通道结构的第一侧、第二侧、第三侧和第四侧；通过移除包覆层的一部分和主动通道结构的一部分来形成凹口，使得在形成凹口之后，包覆层相邻于主动通道结构的第一侧、第二侧和第三侧，但是不相邻于主动通道结构的第四侧；以介电材料填充凹口；以及形成围绕主动通道结构的栅极结构。
在另外一些实施例中，提供半导体结构的制造方法，此方法包含形成围绕主动通道结构的包覆层；在形成围绕主动通道结构的包覆层之后，移除包覆层的一部分和主动通道结构的一部分；以及形成围绕主动通道结构的栅极结构。
附图说明
根据以下的详细说明并配合说明书附图可以更加理解本发明实施例。应注意的是，根据本产业的标准惯例，图示中的各种部件(feature)并未必按照比例绘制。事实上，可能任意的放大或缩小各种部件的尺寸，以做清楚的说明。
图1A为依据一些实施例的例示性半导体结构的透视图。
图1B为依据一些实施例，图1A的例示性半导体结构的剖面示意图。
图1C和1D为依据一些实施例，图1A的半导体结构在制造过程期间的透视俯视图。
图2A显示依据一些实施例，制造图1A的半导体结构的例示性工艺的流程图。
图2B-2M显示图1A的半导体结构在图2A的工艺的各步骤中的剖面示意图。
图3A显示依据一些实施例，制造图1A的半导体结构的另一例示性工艺的流程图。
图3B-3M显示图1A的半导体结构在图3A的工艺的各步骤中的剖面示意图。
附图标记说明：
100：半导体结构
112,114：栅极结构
122,124：外延区
132,134,136：绝缘层
140：主动通道结构
150：介电区
152：隔离结构
160：基底
170：剖面
200,300：方法
201,202,203,204,205,206,301,302,303,304,305,306：步骤
210,310：牺牲层
220,320：包覆层
230,330：凹口
242,244,342,344：虚设栅极结构
WG1,WG2,WI：宽度
具体实施方式
要了解的是以下的公开内容提供许多不同的实施例或范例，以实施提供的主体的不同部件。以下叙述各个构件及其排列方式的特定范例，以求简化公开内容的说明。当然，这些仅为范例并非用以限定本发明。例如，元件的尺寸不限于本公开的一实施方式的范围或数值，但可取决于元件的处理条件及/或要求性质。此外，在随后描述中在第二部件上方或在第二部件上形成第一部件的包括第一及第二部件形成为直接接触的实施例，以及亦可包括额外部件可形成在第一及第二部件之间，使得第一及第二部件可不直接接触的实施例。此外，公开内容中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或部件与另一(多个)元件或(多个)部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“下部”、“在...之上”、“上部”及类似的用语。除了附图所示出的方位之外，空间相关用语也涵盖装置在使用或操作中的不同方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。
本发明实施例提供用于提供半导体结构(例如通过选择性使用包覆层的全绕式场效晶体管(gate-all-around field-effect transistor，GAAFET)结构)的临界尺寸均匀性的技术。包覆层可在主动通道结构中形成凹口之前形成，或是可在以介电材料填充主动通道结构中的凹口之后形成。可选择性使用包覆层，以为在集成电路中形成栅极结构提供一致且更大的工艺裕度。
请参照图1A，图1A为依据一些实施例的例示性半导体结构100的透视图。半导体结构100一般包含多个全绕式栅极晶体管结构。这些结构有时也被称为环绕式栅极晶体管(surrounding-gate transistor，SGT)结构。相较于一些其他结构(例如鳍式场效晶体管(fin field-effect transistor，FinFET)结构)，全绕式栅极晶体管结构一般可允许形成更小的晶体管结构，进而形成更小且更紧密的集成电路。应当理解的是，本文描述的方法可应用至除了全绕式栅极晶体管结构之外的其他类型的半导体结构。请参照图1B，图1B为依据一些实施例，从图1A显示的剖面170截取的半导体结构100的剖面示意图。
显示的半导体结构100包含栅极结构112和栅极结构114。栅极结构112和栅极结构114可用作金属栅极结构，例如高介电常数金属栅极(high-k metal gate，HKMG)结构。在这些实施例中，形成包含导电金属材料及具有高介电常数(high-k)的介电材料的堆叠物。堆叠物也可包含功函数层、盖层及/或其他层，以形成用于预期应用的合适高介电常数金属栅极结构。高介电常数金属栅极结构可通过使用各种合适工艺形成，这些工艺包含栅极先制及栅极后制的实施例。栅极结构112和栅极结构114一般以平行关系设置，且可为包含未显示于图1B中的额外、相似的栅极结构的平行栅极堆叠物的一部分。在一些应用中，相较于使用多晶硅栅极，使用高介电常数金属栅极结构可提供减少的电荷泄漏，进而改善效能。然而，应当理解的是，本文描述的技术也可应用至具有多晶硅栅极结构以及其他类型的栅极结构的半导体装置。
显示的半导体结构100也包含外延区122和外延区124。外延区122和外延区124一般作为各自全绕式栅极晶体管结构的源极端子和漏极端子。外延区122和外延区124一般为晶体结构，且可通过使用外延成长工艺形成，例如气相外延(vapor-phase epitaxy，VPE)、分子束外延(molecular beam epitaxy，MBE)工艺、液相外延(liquid-phase epitaxy，LPE)及其他合适的工艺或前述的组合。外延区122和外延区124可使用合适的掺杂物来掺杂，包含n型和p型掺杂物，例如胂、磷化氢、乙硼烷、其他合适的掺杂物或前述的组合。
显示的半导体结构100也包含绝缘层132、绝缘层134和绝缘层136。绝缘层132、绝缘层134和绝缘层136的每一者可例如用作层间介电(inter-layer dielectric，ILD)结构。绝缘层132、绝缘层134和绝缘层136也可用作接触蚀刻停止层(contact etch stop layer，CESL)。绝缘层132、绝缘层134和绝缘层136可通过使用材料例如二氧化硅(SiO2)、氮氧化硅(SiON)、氮化硅(Si3N4)、氮碳化硅(SiCN)、氮碳氧化硅(SiOCN)、氧化铪(HfO2)、氮化钽(TaN)或其他合适的材料或前述的组合形成。
显示的半导体结构100也包含多个主动通道结构140。在一些实施例中，主动通道结构140用作被栅极结构112、栅极结构114、外延区122、外延区124围绕的纳米片。然而，主动通道结构140也可通过使用其他方式使用，包含用作圆形纳米线。主动通道结构140一般通过使用硅形成，然而，主动通道结构140也可通过使用其他合适的材料或前述的组合来使用。
显示的半导体结构100也包含介电区150。介电区150形成相邻于栅极结构112和栅极结构114，且介电区150可与以下描述的包覆层一同在制造过程期间使用，以在半导体结构100中提供临界尺寸均匀性。介电区可通过使用二氧化硅、氮氧化硅、氮化硅、氮碳化硅、氮碳氧化硅、氧化铪、氮化钽或其他合适的材料或前述的组合形成。
显示的半导体结构100也包含基底160。基底160可为n型基底或p型基底。举例来说，基底160可由掺杂n型掺杂物(例如砷、磷或其他相似掺杂物)的硅材料(例如结晶硅)形成。基底160也可掺杂p型掺杂物(例如硼或其他相似掺杂物)。基底160可通过使用绝缘层上覆硅结构、蓝宝石上覆硅结构、各种其他合适的材料或前述的组合来实现。
显示的半导体结构100也包含隔离结构152。隔离结构152一般可防止半导体结构100的组件之间的漏电流。举例来说，隔离结构152可实现用作浅沟槽隔离(shallow trenchisolation，STI)结构。隔离结构152可通过在基底160中形成沟槽，以绝缘材料填充沟槽，并使用例如化学机械研磨(chemical-mechanical polishing，CMP)的工艺移除多余的绝缘材料来形成。隔离结构152一般提供用于其上形成半导体结构100的其他组件的基底。
在图1B中，宽度WG1标注栅极结构112的宽度，宽度WG2标注栅极结构114的宽度，宽度WI标注绝缘层134的宽度。通过在制造过程(例如参考以下工艺200和工艺300描述)期间选择性使用包覆层，可将宽度WG1制作等于宽度WG2。在一些实施例中，宽度WG1和WG2可大致相等，例如在彼此的5％中或彼此的10％中。临界尺寸均匀度可在半导体装置产率及半导体装置效能上提供优点，特别是在较小节点尺寸的应用上。再者，可将宽度WG1和WG2制造小于宽度WI。
应当理解的是，半导体结构100可包含未在本文明确描述的各种额外层及材料。举例来说，间隙壁结构(例如具有高介电常数(high-k)的间隙壁结构)可形成围绕栅极结构112和栅极结构114，以提供栅极结构112和栅极结构114的电性隔离。再者，额外介电层可形成于半导体结构100中的各个其他位置中。
请参照图1C和1D，图1C和1D显示依据一些实施例，半导体结构100在制造过程期间的两个透视俯视图。在图1C中，包覆层220形成相邻于主动通道结构140的第一侧、主动通道结构140的第二侧及主动通道结构140的第三侧，但是不形成于主动通道结构140的第四侧周围。包覆层220可一般由硅锗(SiGe)或其他合适的材料形成，如以下进一步讨论细节。在图1D中，包覆层320相似地形成相邻于主动通道结构140的第一侧、主动通道结构140的第二侧及主动通道结构140的第三侧，但是不形成于主动通道结构140的第四侧周围。在图1D中，介电区150也形成于主动通道结构140中。包覆层320也可由硅锗或其他合适的材料形成，如以下进一步讨论细节。图1C和1D提供的俯视图分别显示选择性使用包覆层220和320，包覆层220和320可提供临界尺寸均匀度。
请参照图2A，图2A显示依据一些实施例，制造半导体结构100的例示性工艺200的流程图。图2B-2M显示半导体结构100在工艺200的各步骤中的剖面示意图。图2B、2D、2F、2H、2J和2L显示在水平方向(例如从图1A显示的剖面170截取的x方向)截取的半导体结构100的剖面示意图，而图2C、2E、2G、2I、2K和2M显示在垂直方向(例如y方向)截取的半导体结构100的剖面示意图。工艺200一般包含在制造过程期间，在切割主动通道结构140以形成凹口之前，形成包覆层220围绕主动通道结构140。
在步骤201，形成主动通道结构(图2B和2C)。如图2B和2C显示，主动通道结构140形成于基底160之上，且在多个牺牲层210之间。如上所述，可实现主动通道结构140作为纳米结构(例如纳米片或纳米线)，用以形成全绕式栅极场效晶体管。在形成栅极结构112和栅极结构114围绕主动通道结构140之前，在制造过程期间使用牺牲层210来隔开主动通道结构140。牺牲层210可通过使用硅锗、其他合适的材料或前述的组合形成。如以下讨论，最终移除牺牲层210。
在步骤202，形成围绕主动通道结构的包覆层(图2D和2E)。如图2D和2E显示，包覆层220形成围绕主动通道结构140。包覆层220可通过使用外延成长工艺形成，例如气相外延、分子束外延、液相外延、其他合适的工艺或前述的组合。包覆层220可由硅锗、其他合适的材料或前述的组合形成。在包覆层220和牺牲层210皆由硅锗形成的实施例中，包覆层220一般可通过使用较高浓度的锗来形成。应注意的是，步骤202中包覆层220的形成在切割主动通道结构140之前发生。在步骤202中，形成围绕主动通道结构140的包覆层220，使得包覆层220形成相邻于主动通道结构140的第一侧、主动通道结构140的第二侧、主动通道结构140的第三侧以及主动通道结构140的第四侧。
在步骤203，移除主动通道结构的一部分及包覆层的一部分，以形成凹口(图2F和2G)。如图2F和2G显示，移除主动通道结构140、牺牲层210和包覆层220的一部分，以形成凹口230。步骤203的移除工艺可使用一个或多个蚀刻工艺进行，蚀刻工艺包含干蚀刻工艺和湿蚀刻工艺，以及反应性离子蚀刻工艺及其他合适类型的蚀刻工艺。再者，步骤203可使用各种不同的蚀刻化学物，以移除主动通道结构140、牺牲层210和包覆层220的一部分，以形成凹口230。应注意的是，由于在步骤203的移除工艺之前形成包覆层220，因此包覆层220将仅相邻于主动通道结构140的第一侧、主动通道结构140的第二侧及主动通道结构140的第三侧，但是不在主动通道结构140的第四侧，如以上图1C显示。
在步骤204，以介电材料填充凹口，并形成虚设栅极结构(图2H和2I)。如图2H和2I显示，以介电材料填充凹口230，并形成介电区150。介电区150可通过使用沉积工艺(例如化学气相沉积、其他合适的工艺或前述的组合)形成于凹口230中。接着，虚设栅极结构242和虚设栅极结构244形成于介电区150和包覆层220之上。虚设栅极结构242和虚设栅极结构244可通过使用多晶硅、其他合适的材料或前述的组合形成。虚设栅极结构242和虚设栅极结构244可通过使用例如化学气相沉积、其他合适的工艺或前述的组合的工艺形成。虚设栅极结构242和虚设栅极结构244一般在制造过程期间作为占位物，且在形成栅极结构112和栅极结构114之前移除虚设栅极结构242和虚设栅极结构244。应理解的是，可在虚设栅极结构242、虚设栅极结构244及相邻结构之间形成各种材料，例如绝缘层或其他类型层。
在步骤205，形成围绕主动通道结构的外延区(图2J和2K)。如图2J所示，形成围绕主动通道结构140的外延区122和外延区124。如上所述，外延区122和外延区124一般可作为晶体管的源极和漏极端子。因此，外延区122和外延区124可使用合适的掺杂物(包含n型掺杂物和p型掺杂物)掺杂。外延区122和外延区124可通过使用外延成长工艺形成，例如气相外延、分子束外延、液相外延、其他合适的工艺或前述的组合。在一些实施例中，在形成外延层122和外延区124之前，使用合适的蚀刻工艺移除牺牲层210及/或包覆层220的一部分。
在步骤206，移除虚设栅极结构，并形成围绕主动通道结构的主动栅极结构(图2L和2M)。如图2L和2M所示，沿牺牲层210移除虚设栅极结构242和虚设栅极结构244。这些结构可使用各种合适的蚀刻工艺来移除，蚀刻制包含干蚀刻工艺和湿蚀刻工艺，以及反应性离子蚀刻工艺及其他合适类型的蚀刻工艺。接着，栅极结构112和栅极结构114形成围绕主动通道结构140，以形成晶体管的主动栅极结构。由于在工艺200选择性使用包覆层220，因此在步骤206中形成栅极结构112和栅极结构114的工艺裕度更加一致，进而形成栅极结构112的宽度等于栅极结构114的宽度。这些更加一致的工艺裕度可帮助防止不期望的效果，例如相对于介电区150和其他结构的重叠偏移(overlap shift)。额外地，在步骤206中，绝缘层132、绝缘层134和绝缘层136可形成相邻于栅极结构112和栅极结构114。通过在工艺200中选择性使用包覆层220而获得改善的工艺裕度还可以允许绝缘层134的宽度分别大于栅极结构112的宽度和栅极结构114的宽度。
请参照图3A，图3A显示依据一些实施例，制造半导体结构100的例示性工艺300的流程图。图3B-3M显示半导体结构100在工艺300的各步骤中的剖面示意图。图3B、3D、3F、3H、3J和3L显示在水平方向(例如从图1A显示的剖面170截取的x方向)截取的半导体结构100的剖面示意图，而图3C、3E、3G、3I、3K和3M显示在垂直方向(例如y方向)截取的半导体结构100的剖面示意图。工艺300一般包含在形成包覆层330围绕主动通道结构140之前，切割主动通道结构140，以形成凹口，并以介电材料填充凹口。
在步骤301，形成主动通道结构(图3B和3C)。如图3B和3C显示，主动通道结构140形成于基底160之上，且在多个牺牲层310之间。如上所述，可实现主动通道结构140作为纳米结构，用以形成全绕式栅极场效晶体管。牺牲层310相似于牺牲层210，其中在形成栅极结构112和栅极结构114围绕主动通道结构140之前，在制造过程期间使用牺牲层310来隔开主动通道结构140。牺牲层310可通过使用硅锗、其他合适的材料或前述的组合形成。相似于牺牲层210，最终移除牺牲层310。
在步骤302，移除主动通道结构的一部分，以形成凹口(图3D和3E)。如图3D和3E所示，移除主动通道结构140和牺牲层310的一部分，以形成凹口330。步骤302的移除工艺可使用一个或多个蚀刻工艺进行，蚀刻工艺包含干蚀刻工艺和湿蚀刻工艺，以及反应性离子蚀刻工艺及其他合适类型的蚀刻工艺。再者，步骤302可使用各种不同的蚀刻化学物，以移除主动通道结构140、牺牲层310的一部分，以形成凹口330。应注意的是，不同于工艺200，工艺300的步骤302中进行的移除工艺在形成包覆层320之前发生。
在步骤303，在凹口中形成介电材料，并形成围绕主动通道结构的包覆层(图3F和3G)。如图3F和3G所示，在凹口330中形成介电区150。介电区150可通过使用沉积工艺(例如化学气相沉积、其他合适的工艺或前述的组合)形成于凹口330中。接着，包覆层320形成围绕主动通道结构140和介电区150。包覆层320可通过使用外延成长工艺形成，例如气相外延、分子束外延、液相外延、其他合适的工艺或前述的组合。包覆层320可由硅锗、其他合适的材料或前述的组合形成。在包覆层320和牺牲层310皆由硅锗形成的实施例中，包覆层320一般可通过使用较高浓度的锗来形成。应注意的是，由于包覆层320通过使用外延成长工艺形成，因此包覆层320不会成长于介电区150上，但是将成长于主动通道结构140上。因此，在步骤303中，形成围绕主动通道结构140的包覆层320，由于存在介电区150的缘故，使得包覆层320形成相邻于主动通道结构140的第一侧、主动通道结构140的第二侧、主动通道结构140的第三侧，但是不形成于主动通道结构140的第四侧，如以上图1D所示。
在步骤304，形成虚设栅极结构(图3H和3I)。如图3H和3I所示，虚设栅极结构342和虚设栅极结构344形成于介电区150和包覆层320之上。虚设栅极结构342和虚设栅极结构344可通过使用多晶硅、其他合适的材料或前述的组合形成。虚设栅极结构342和虚设栅极结构344可通过使用例如化学气相沉积、其他合适的工艺或前述的组合的工艺形成。虚设栅极结构342和虚设栅极结构344一般在制造过程期间作为占位物，且在形成栅极结构112和栅极结构114之前移除虚设栅极结构342和虚设栅极结构344。应理解的是，可在虚设栅极结构342、虚设栅极结构344及相邻结构之间形成各种材料，例如绝缘层或其他类型层。
在步骤305，形成围绕主动通道结构的外延区(图3J和3K)。如图3J所示，形成围绕主动通道结构140的外延区122和外延区124。如上所述，外延区122和外延区124一般可作为晶体管的源极和漏极端子。因此，外延区122和外延区124可使用合适的掺杂物(包含n型掺杂物和p型掺杂物)掺杂。外延区122和外延区124可通过使用外延成长工艺形成，例如气相外延、分子束外延、液相外延、其他合适的工艺或前述的组合。在一些实施例中，在形成外延层122和外延区124之前，使用合适的蚀刻工艺移除牺牲层310及/或包覆层320的一部分。
在步骤306，移除虚设栅极结构，并形成围绕主动通道结构的主动栅极结构(图3L和3M)。如图3L和3M所示，沿牺牲层310移除虚设栅极结构342和虚设栅极结构344。这些结构可使用各种合适的蚀刻工艺来移除，蚀刻制包含干蚀刻工艺和湿蚀刻工艺，以及反应性离子蚀刻工艺及其他合适类型的蚀刻工艺。接着，栅极结构112和栅极结构114形成围绕主动通道结构140，以形成晶体管的主动栅极结构。由于在工艺300选择性使用包覆层320，因此在步骤306中形成栅极结构112和栅极结构114的工艺裕度更加一致，进而形成栅极结构112的宽度等于栅极结构114的宽度。这些更加一致的工艺裕度可帮助防止不期望的效果，例如相对于介电区150和其他结构的重叠偏移(overlap shift)。额外地，在步骤306中，绝缘层132、绝缘层134和绝缘层136可形成相邻于栅极结构112和栅极结构114。通过在工艺300中选择性使用包覆层320而获得改善的工艺裕度还可以允许绝缘层134的宽度分别大于栅极结构112的宽度和栅极结构114的宽度。
应当理解的是，以上描述的工艺200和工艺300仅供范例，而工艺200和工艺300的各种变化也在本发明实施例考虑的范围中。
如上所述，本发明实施例提出通过选择性使用包覆层，在半导体结构(例如全绕式栅极场效晶体管(GAAFET))中提供临界尺寸均匀度的技术。包覆层可在主动通道结构中形成凹口之前形成，或是可在以介电材料填充主动通道结构中的凹口之后形成。可选择性使用包覆层，以为在集成电路中形成栅极结构提供一致且更大的工艺裕度。
本发明一实施例为半导体结构的制造方法，此方法包含移除主动通道结构的一部分，以形成凹口；以介电材料填充凹口；形成包覆层相邻于主动通道结构，但是不相邻于介电材料；以及形成围绕主动通道结构的栅极结构。
在一些其他实施例中，其中形成包覆层的步骤包含形成硅锗层相邻于主动通道结构，但是不相邻于介电材料。
在一些其他实施例中，其中形成包覆层的步骤包含使用外延成长工艺形成包覆层。
在一些其他实施例中，其中栅极结构包含主动栅极结构，上述方法还包含：形成围绕主动通道结构的虚设栅极结构；以及在形成主动栅极结构之前，移除虚设栅极结构。
在一些其他实施例中，其中栅极结构包含第一栅极结构，上述方法还包含形成围绕主动栅极结构的第二栅极结构，使得第一栅极结构的宽度等于第二栅极结构的宽度。
在一些其他实施例中，上述方法还包含形成围绕主动通道结构的外延区。
在一些其他实施例中，上述方法还包含在形成包覆层相邻于主动通道结构之前，移除相邻于主动通道结构的隔离结构的一部分。
在一些其他实施例中，其中形成包覆层的步骤包含形成硅锗层相邻于主动通道结构的第一侧、第二侧、第三侧和第四侧。
在一些其他实施例中，上述方法还包含形成围绕主动通道结构的外延区。
本发明另一实施例为半导体结构的另一制造方法，此方法包含形成包覆层相邻于主动通道结构的第一侧、第二侧、第三侧和第四侧；通过移除包覆层的一部分和主动通道结构的一部分来形成凹口，使得在形成凹口之后，包覆层相邻于主动通道结构的第一侧、第二侧和第三侧，但是不相邻于主动通道结构的第四侧；以介电材料填充凹口；以及形成围绕主动通道结构的栅极结构。
在一些其他实施例中，其中栅极结构包含主动栅极结构，上述方法还包含：形成围绕主动通道结构的虚设栅极结构；以及在形成主动栅极结构之前，移除虚设栅极结构。
在一些其他实施例中，其中栅极结构包含第一栅极结构，上述方法还包含形成围绕主动通道结构的第二栅极结构，使得第一栅极结构的宽度等于第二栅极结构的宽度。
在一些其他实施例中，其中以介电材料填充凹口的步骤包含以介电材料填充凹口，使得介电材料的宽度大于第一栅极结构的宽度和第二栅极结构的宽度。
在一些其他实施例中，其中形成包覆层的步骤包含使用外延成长工艺形成包覆层。
本发明另一实施例为半导体结构的另一制造方法，此方法包含形成围绕主动通道结构的包覆层；在形成围绕主动通道结构的包覆层之后，移除包覆层的一部分和主动通道结构的一部分；以及形成围绕主动通道结构的栅极结构。
在一些其他实施例中，其中形成包覆层的步骤包含使用外延成长工艺成长围绕主动通道结构的包覆层。
在一些其他实施例中，其中移除包覆层的一部分和主动通道结构的一部分的步骤包含移除包覆层的一部分和主动通道结构的一部分，以形成凹口，上述方法还包含在凹口中形成介电材料。
在一些其他实施例中，其中栅极结构包含主动栅极结构，上述方法还包含：形成围绕主动通道结构的虚设栅极结构；以及在形成主动栅极结构之前，移除虚设栅极结构。
在一些其他实施例中，上述方法还包含形成围绕主动通道结构的外延区。
在一些其他实施例中，其中栅极结构包含第一栅极结构，上述方法还包含形成围绕主动通道结构的第二栅极结构，使得第一栅极结构的宽度等于第二栅极结构的宽度。
前述内文概述了许多实施例的特征，使本技术领域中技术人员可以从各个方面更加了解本发明实施例。本技术领域中技术人员应可理解，且可轻易地以本发明实施例为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本发明的发明构思与范围。在不背离本发明的发明构思与范围的前提下，可对本发明实施例进行各种改变、置换或修改。

Claims (1)

1.一种半导体结构的制造方法，包括：
移除一主动通道结构的一部分，以形成一凹口；
以一介电材料填充该凹口；
形成一包覆层相邻于该主动通道结构，但是不相邻于该介电材料；以及
形成围绕该主动通道结构的一栅极结构。
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