TW202303106A - Piezoelectric element, and sensor and actuator employing same - Google Patents
Piezoelectric element, and sensor and actuator employing same Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/16—Measuring force or stress, in general using properties of piezoelectric devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/30—Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/85—Piezoelectric or electrostrictive active materials
- H10N30/853—Ceramic compositions
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- Chemical & Material Sciences (AREA)
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Abstract
Description
本發明係關於一種、壓電元件、及使用其之感測器及致動器。The present invention relates to a piezoelectric element, a sensor and an actuator using the same.
歷來,利用物質的壓電效應之壓電元件為眾所用。壓電效應指物質受壓力施加時發生與壓力成比例分極之現象。利用壓電效應,現已創出應力感測器、加速度感測器、用於檢測彈性波之AE(Acoustic Emission,聲射)感測器等各種各樣的感測器。Historically, piezoelectric elements utilizing the piezoelectric effect of matter have been widely used. Piezoelectric effect refers to the phenomenon that when a substance is subjected to pressure, it splits in proportion to the pressure. Utilizing the piezoelectric effect, various sensors such as stress sensors, acceleration sensors, and AE (Acoustic Emission) sensors for detecting elastic waves have been created.
近年,壓電元件被應用於智慧手機等電子設備的觸控屏、作為高頻帶通濾波器的體聲波(Bulk Acoustic Wave: BAW)濾波器。應用於觸控屏等壓力感測器時,為了能夠高感度地檢測出手指操作,要求具備較高的壓力應答性。應用於BAW濾波器時,為了能夠以壓電薄膜厚度方向之振動作為動作原理,要求在厚度方向具有良好的壓電特性。無論任何應用,均要求元件的小型化及低耗電。In recent years, piezoelectric elements have been used in touch screens of electronic devices such as smartphones, and bulk acoustic wave (Bulk Acoustic Wave: BAW) filters as high-frequency bandpass filters. When applied to pressure sensors such as touch panels, high pressure responsiveness is required in order to detect finger manipulation with high sensitivity. When applied to a BAW filter, good piezoelectric characteristics in the thickness direction are required in order to operate based on vibration in the thickness direction of the piezoelectric film. Regardless of any application, miniaturization and low power consumption of components are required.
已有提案在採用鈣鈦礦型結晶的壓電薄膜元件之上部電極與下部電極之間,藉由插入電流阻擋層,以將電極間電阻值保持於規定值以上的結構(例如,參照專利文獻1)。 <先前技術文件> <專利文獻> It has been proposed to insert a current blocking layer between the upper electrode and the lower electrode of the piezoelectric thin film element using a perovskite crystal to maintain the inter-electrode resistance value above a specified value (for example, refer to the patent document 1). <Prior technical documents> <Patent Document>
專利文獻1:日本特開2009-130182號公報Patent Document 1: Japanese Patent Laid-Open No. 2009-130182
<發明所欲解決之問題><The problem that the invention intends to solve>
作為在利用壓電效應的感測器及致動器等中使用的壓電材料,使用於c軸方向具有結晶取向性之纖鋅礦型結晶。纖鋅礦型結晶具有六方晶系的結晶結構,使用ZnO、AlN、GaN等。其中,II-VI族化合物之ZnO易成為n型半導體,易產生微小漏電流。III-V族化合物之GaN或AlN也示出半導體性傾向,因此存有產生微小漏電流的擔憂。微小漏電流可導致壓電特性降低。Wurtzite crystals having crystal orientation in the c-axis direction are used as piezoelectric materials used in sensors and actuators utilizing the piezoelectric effect. The wurtzite type crystal has a hexagonal crystal structure, and ZnO, AlN, GaN, etc. are used. Among them, ZnO, which is a group II-VI compound, tends to become an n-type semiconductor and easily generates a small leakage current. GaN and AlN, which are group III-V compounds, also show a tendency to be semiconducting, so there is a concern that a small leakage current may be generated. Small leakage currents can cause piezoelectric characteristics to degrade.
本發明一方面之目的在於提供一種可抑制漏電流、提高壓電特性之壓電元件。 <用於解決問題之手段> An object of the present invention is to provide a piezoelectric element capable of suppressing leakage current and improving piezoelectric characteristics. <Means used to solve problems>
根據本發明之一形態,於壓電元件之基板上依序疊層有壓電體層及第1電極,於該第1電極與該壓電體層之間,或該基板與該壓電體層之間的至少一方配置有漏電流抑制層。According to an aspect of the present invention, a piezoelectric layer and a first electrode are sequentially stacked on the substrate of the piezoelectric element, between the first electrode and the piezoelectric layer, or between the substrate and the piezoelectric layer. At least one of them is provided with a leakage current suppression layer.
該漏電流抑制層每單位面積的靜電容量相對於該壓電體層每單位面積的靜電容量之比為1.20以上且小於60.00。 <發明之功效> A ratio of the capacitance per unit area of the leakage current suppression layer to the capacitance per unit area of the piezoelectric layer is 1.20 or more and less than 60.00. <Efficacy of Invention>
實現可抑制漏電流、提高壓電特性之壓電元件。Realize piezoelectric elements that can suppress leakage current and improve piezoelectric characteristics.
實施方式中,於基板上設置的壓電體層與第1電極之間,或基板與壓電體層之間的至少一方設置可滿足規定的靜電容量關係的漏電流抑制層,以抑制漏電流,提高壓電特性。本說明書中提及壓電特性時,其意思包括每單位印加應力所生成的電壓量(正壓電效應),及每單位印加電場的機械性變位比率(逆壓電效應)之兩者。 <元件結構> In the embodiment, at least one of the piezoelectric layer and the first electrode provided on the substrate, or between the substrate and the piezoelectric layer, is provided with a leakage current suppression layer that satisfies a predetermined capacitance relationship to suppress leakage current and improve Piezoelectric properties. When referring to piezoelectric characteristics in this specification, it means to include both the amount of voltage generated per unit applied stress (direct piezoelectric effect) and the rate of mechanical displacement per unit applied electric field (converse piezoelectric effect). <Component structure>
圖1A係作為實施方式之第1結構例的壓電元件10A之模式圖。壓電元件10A於其基板11上依序疊層有電極12、壓電體層13及電極16,並於壓電體層13與電極16之間設有漏電流抑制層15。簡單起見,可將電極16稱為“第1電極”或上部電極,可將電極12稱為“第2電極”或下部電極。如後文所述,根據基板11之電氣特性,亦可省略電極12。FIG. 1A is a schematic diagram of a
基板11能夠穩定支撐電極12、壓電體層13、漏電流抑制層15及電極16之疊層體即可,對其種類不限。作為基板11可以使用塑膠基板、玻璃基板、陶瓷基板等。作為一結構例,基板11可採用可賦予壓電元件10A彎折性的可撓性基材。基板11之厚度為1μm以上150μm以下,優選為10以上100μm以下,更優選為20以上80μm以下。若小於1μm,難以穩定支撐包含持電極12、壓電體層13、漏電流抑制層15及電極16的疊層體。此外,基板11變得易翹曲,而基板11翹曲則會影響壓電特性。基板11之厚度超過150μm時,難以使壓電元件10A整體具有理想的彎折性。The
作為可撓性基材,例如可以使用聚對苯二甲酸二乙酯(PET)、聚萘二甲酸乙二酯(PEN)、聚碳酸酯(PC)、丙烯酸系樹脂、環烯烴系聚合物、聚亞醯胺(PI)、薄膜玻璃等。這些材料中,聚對苯二甲酸二乙酯(PET)、聚萘二甲酸乙二酯(PEN)、聚碳酸酯(PC)、丙烯酸系樹脂、環烯烴系聚合物、薄膜玻璃係無色透明材料,尤其適合將壓電元件10A用於觸控屏等透射性部件之情形。而對於壓電元件10A無透光性要求之情形下,例如,用於脈搏計、心率計等保健用品或車載壓力檢測片等情形下,則可以使用半透明或非透明的塑膠材料。As the flexible base material, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), acrylic resin, cycloolefin polymer, Polyimide (PI), film glass, etc. Among these materials, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), acrylic resins, cycloolefin-based polymers, and film glass-based colorless and transparent materials , especially when the
電極12與電極16中的一者或兩者可以是由對於可見光透明的導電材料形成的透明電極。根據壓電元件10A的應用領域,電極12與電極16之透明性並非必不可缺,而壓電元件10A被應用於觸控屏等顯示器之情形下,則要求對可見光具有透光性。作為對可見光透明的導電材料,能夠使用ITO(Indium Tin Oxide)、IZO(Indium Zinc Oxide)、IZTO(Indium Zinc Tin Oxide)、IGZO(Indium Gallium Zinc Oxide)等。One or both of the
不要求透光性之情形下,可形成金屬電極。形成金屬電極時,可以使用具有與纖鋅礦相同的晶格結構的六方晶系金屬材料。作為六方晶系的金屬,可以使用鈦(Ti)、鋯(Zr)、鉿(Hf)、釕(Ru)、鋅(Zn)、釔(Y)、鈧(Sc)及這些的組合等。In the case where light transmission is not required, metal electrodes can be formed. When forming the metal electrode, a hexagonal metal material having the same lattice structure as wurtzite can be used. As the hexagonal metal, titanium (Ti), zirconium (Zr), hafnium (Hf), ruthenium (Ru), zinc (Zn), yttrium (Y), scandium (Sc), combinations thereof, and the like can be used.
作為壓電體層13,可以使用纖鋅礦型結晶、鈣鈦礦型結晶等。實施方式中,作為壓電體層13之主成分,使用結晶結構比鈣鈦礦型結晶更單純的纖鋅礦型結晶。壓電體層13中還可以作為副成分添加規定量的不純物元素。As the
作為纖鋅礦型壓電材料,優選透過200℃以下之低溫製程進行結晶化的材料。作為一例,可以使用氧化鋅(ZnO)、硫化鋅(ZnS)、硒化鋅(ZnSe)、碲化鋅(ZnTe)、氮化鋁(AlN)、氮化鎵(GaN)、硒化鎘(CdSe)、碲化鎘(CdTe)、碳化矽(SiC)。亦可組合使用上述材料中的2種以上。組合2種以上的材料時,可使各化合物疊層,亦可使用複數個靶形成一個層。As the wurtzite-type piezoelectric material, it is preferable to crystallize it through a low-temperature process below 200°C. As an example, zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), aluminum nitride (AlN), gallium nitride (GaN), cadmium selenide (CdSe ), cadmium telluride (CdTe), silicon carbide (SiC). Two or more of the above materials may be used in combination. When combining two or more materials, each compound may be laminated, or a single layer may be formed using a plurality of targets.
向壓電材料添加副成分時,優選使用添加至主成分後不會顯現導電性,且不會妨礙壓電特性的元素。作為一例,可以使用鎂(Mg)、矽(Si)、鈣(Ca)、釩(V)、鈦(Ti)、鋯(Zr)、鍶(Sr)、鋰(Li),或這些的混合物。When adding subcomponents to the piezoelectric material, it is preferable to use elements that do not exhibit electrical conductivity and do not inhibit piezoelectric characteristics when added to the main component. As an example, magnesium (Mg), silicon (Si), calcium (Ca), vanadium (V), titanium (Ti), zirconium (Zr), strontium (Sr), lithium (Li), or a mixture thereof can be used.
壓電體層13之厚度為50nm以上5000nm(5μm)以下,優選為50nm以上3000nm(3μm)以下,更優選為50nm以上2000nm(2μm)以下,更優選為100nm以上1000nm(1μm)以下,更優選為150nm以上500nm以下。壓電體層14之厚度超過5000nm時,易產生龜裂。龜裂為因可造成電極間的漏洩路徑。壓電體層14之厚度小於50nm時,則難以在膜厚方向發揮充分的壓電特性。The thickness of the
纖鋅礦型結晶的壓電體層13於c軸方向上具有良好的結晶取向性,即意味著厚度方向的壓電特性良好。可根據對規定的結晶晶格面進行X線繞射的搖擺曲線測定所獲得的峰值之半峰全幅值(Full Width at Half Maximum:FWHM),評價c軸方向之結晶取向性。壓電體層14的FMHM優選為5°以下,應用於感測器及致動器時,優選為4°以下。The wurtzite-type
漏電流抑制層15為無機絕緣層,優選為非結晶無機絕緣層。作為無機絕緣層,可以使用Al
2O
3、SiO
2、Si
3N
4、ZrO
2、TiO
2、AlN、Ta
2O
5,或組合上述中的2種以上的材料。可透過濺射、化學氣相沉積(Chemical Vapor Deposition: CVD)法等乾式法,或溶膠凝膠法等濕式法,形成上述膜。
The leakage
漏電流抑制層15為非結晶無機絕緣層,但並非是指無機絕緣層整體為完全非結晶。漏電流抑制層15中非結晶(非晶質)成分所佔比率優選為90%以上,更優選為95%以上。The leakage current suppressing
漏電流抑制層15之材料及/或膜厚,選擇可使漏電流抑制層15每單位面積的靜電容量C
LS相對於壓電體層13每單位面積的靜電容量C
PIEZ之比(C
LS/C
PIEZ)成為1.20以上且小於60.00的值。如後文所述,滿足1.20≦C
LS/C
PIEZ<60.00之條件時,可提高壓電元件10A的壓電特性。
The material and/or film thickness of the leakage
漏電流抑制層15之靜電容量C
LS可表示為如下。
C
LS=(εr
LS×ε
0×S)/d
LS(1) 在此,ε
0為真空介電係數,係不依賴於材料之常數。S為漏電流抑制層15之面積,d
LS為漏電流抑制層15之膜厚。
The capacitance C LS of the leakage
壓電體層13之靜電容量C
PIEZ可表示如下。
C
PIEZ=(εr
PIEZ×ε
0×S)/d
PIEZ(2) 在此,S為壓電體層13之面積,根據壓電元件10A之結構,與漏電流抑制層15面積S相同。d
PIEZ為壓電體層13之膜厚。
The capacitance C PIEZ of the
根據式(1)與式(2),漏電流抑制層15每單位面積的靜電容量C
LS相對於壓電體層13每單位面積的靜電容量C
PIEZ之比C
LS/C
PIEZ可表示如下。
C
LS/C
PIEZ=(εr
LS×d
PIEZ)/(εr
PIEZ×d
LS) (3) 根據式(3),將壓電體層13之材料與厚度以及漏電流抑制層15之材料與厚度設計成可滿足1.20≦C
LS/C
PIEZ<60.00之條件。從而,能夠抑制微小漏電流,改善壓電特性。
According to the formulas (1) and (2), the ratio C LS /C PIEZ of the capacitance C LS per unit area of the leakage current suppressing
圖1B係實施方式之第2結構例之壓電元件10B的模式圖。壓電元件10B中,於基板11上依序疊層有電極12、壓電體層13及電極16,於基板11與壓電體層13之間,更具體而言在電極12與壓電體層13之間,設有漏電流抑制層15。FIG. 1B is a schematic diagram of a
壓電元件10B中,沿著疊層方向位於壓電體層13之下層的漏電流抑制層15為非結晶絕緣層之情形下,漏電流抑制層15可作為壓電體層13之基底取向膜發揮功能。藉由在電極12與壓電體層13之間配置非結晶絕緣層,幾乎不受電極12結晶狀態之影響,可使壓電體層13以良好的取向性成長。In the
圖1B之配置結構中,漏電流抑制層15與壓電體層13之靜電容量關係被設計成,可使漏電流抑制層15每單位面積的靜電容量C
LS相對於壓電體層13每單位面積的靜電容量C
PIEZ之比C
LS/C
PIEZ成為1.20以上且小於60.00之值。由此,可在壓電元件10B抑制微小漏電流,提高壓電特性。
In the arrangement structure of FIG. 1B , the relationship between the capacitance of the leakage
圖1C係示出作為實施方式之第3結構例的壓電元件10C之模式圖。壓電元件10C中,於基板11上依序疊層有電極12、壓電體層13及電極16,於電極12與壓電體層13之間設有漏電流抑制層15-1,於電極16與壓電體層13之間設有漏電流抑制層15-2。FIG. 1C is a schematic diagram showing a
圖1C的配置結構中,漏電流抑制層15-1及15-2與壓電體層13之靜電容量關係也被設計為滿足1.20≦C
LS/C
PIEZ<60.00。設置漏電流抑制層15-1與15-2之情形下,2層漏電流抑制層的每單位面積的靜電容量C
LS可表示如下。
C
LS=C
LS1×C
LS2/(C
LS1+C
LS2)
In the arrangement structure of FIG. 1C , the capacitance relationship between the leakage current suppression layers 15 - 1 and 15 - 2 and the
在此,C LS1為一方漏電流抑制層15-1每單位面積的靜電容量,C LS2則為另一方漏電流抑制層15-2每單位面積的靜電容量。 Here, C LS1 is the capacitance per unit area of one leakage current suppression layer 15 - 1 , and C LS2 is the capacitance per unit area of the other leakage current suppression layer 15 - 2 .
漏電流抑制層15-1被形成為非結晶絕緣層之情形下,還可作為壓電體層13之基底取向膜發揮功能。漏電流抑制層15-2被形成為非結晶絕緣層之情形下,還可作為電極16之基底取向膜發揮功能。藉由在電極12與壓電體層13之間設置漏電流抑制層15-1,在電極16與壓電體層13之間設置漏電流抑制層15-2,能夠在疊層方向上的壓電體層13下層的電極12側及上層的電極16側之兩方,抑制漏洩路徑的形成。又可提高壓電體層13與電極16的結晶性,進一步提高壓電特性。When the leakage current suppressing layer 15 - 1 is formed as an amorphous insulating layer, it can also function as a base alignment film of the
圖1D係作為實施方式之第4結構例的壓電元件10D之模式圖。壓電元件10D中採用導電性基板21。基板21上依序疊層有壓電體層13與電極16,並於電極16與壓電體層13之間設有漏電流抑制層15。該結構中,基板21可作為下部電極發揮功能。基板21可為金屬基板,亦可為ITO、IZO、IZTO、IGZO等導電性透明基板。採用金屬基板21之情形下,可採用Al箔、Cu箔、Al-Ti合金箔、Cu-Ti合金箔、不鏽鋼箔等金屬膜。金屬膜之厚度較薄的情形下,基板21成為可撓性基板。可在基板21與壓電體層13之間插入Ti、Ni等金屬密接膜。FIG. 1D is a schematic diagram of a
與圖1A同樣,藉由對壓電體層13之材料與厚度,及漏電流抑制層15之材料與厚度進行設計,以使漏電流抑制層15每單位面積的靜電容量C
LS之比C
LS/C
PIEZ成為1.20以上且小於60.00的值。由此,可抑制微小漏電流,提高壓電特性。
1A, by designing the material and thickness of the
圖1E係作為實施方式之第5結構例的壓電元件10E之模式圖。壓電元件10E中也採用導電性基板21。於基板21上依序疊層有壓電體層13與電極16。於基板21與壓電體層13之間設有漏電流抑制層15。FIG. 1E is a schematic diagram of a
與圖1D同樣,基板21可為金屬基板,亦可為ITO、IZO、IZTO、IGZO等的導電性透明基板。採用金屬基板21之情形下,可採用Al箔、Cu箔、Al-Ti合金箔、Cu-Ti合金箔、不鏽鋼箔等金屬膜。金屬膜之厚度較薄的情形下,基板21成為可撓性基板。在基板21與漏電流抑制層15之間可插入Ti、Ni等金屬密接膜。Similar to FIG. 1D , the
漏電流抑制層15被形成為非結晶絕緣層之情形下,漏電流抑制層5可作為壓電體層13之基底取向膜發揮功能。藉由在基板21與壓電體層13之間配置非結晶絕緣層,幾乎不受基板21的結晶狀態之影響,可使壓電體層13以良好的取向性成長。When the leakage
藉由對壓電體層13之材料與厚度,及漏電流抑制層15之材料與厚度進行設計,以使漏電流抑制層15每單位面積的靜電容量C
LS相對於壓電體層13每單位面積的靜電容量C
PIEZ之比C
LS/C
PIEZ成為1.20以上且小於60.00的值。由此,可抑制微小漏電流,提高壓電特性。
By designing the material and thickness of the
圖1E之結構中,可抑制基板21與電極16之間形成漏洩路徑,並抑制微小漏電流。又可提高壓電體層13之結晶性,進而提高壓電特性。In the structure of FIG. 1E , the formation of a leakage path between the
圖1F係作為實施方式之第6結構例的壓電元件10F之模式圖。壓電元件10F中也採用導電性基板21。於基板21上依序疊層有壓電體層13與電極16。於基板21與壓電體層13之間設有漏電流抑制層15-1,於壓電體層13與電極16之間設有漏電流抑制層15-2。FIG. 1F is a schematic diagram of a
與圖1D同樣,基板21可為金屬基板,亦可為ITO、IZO、IZTO、IGZO等導電性透明基板。採用金屬基板21之情形下,可以使用Al箔、Cu箔、Al-Ti合金箔、Cu-Ti合金箔、不鏽鋼箔等金屬膜。金屬膜之厚度較薄的情形下,基板21成為可撓性基板。基板21與漏電流抑制層15之間可插入Ti、Ni等金屬密接膜。Similar to FIG. 1D , the
漏電流抑制層15-1被形成為非結晶絕緣層之情形下,漏電流抑制層15-1可作為壓電體層13之基底取向膜發揮功能。藉由在基板21與壓電體層13之間配置非結晶絕緣層,幾乎不受基板21結晶狀態之影響,可使壓電體層13以良好的取向性成長。漏電流抑制層15-2被形成為非結晶絕緣層之情形下,可作為電極16之基底取向膜發揮功能。When the leakage current suppression layer 15 - 1 is formed as an amorphous insulating layer, the leakage current suppression layer 15 - 1 can function as a base alignment film of the
圖1F的結構中的漏電流抑制層15-1及5-12之2層的每單位面積的靜電容量C
LS,如上文中參照圖1C進行的說明,C
LS/C
PIEZ被設計成1.20以上且小於60.00。藉由在基板21與壓電體層13之間設置漏電流抑制層15-1,在壓電體層13と電極16之間設置漏電流抑制層15-2,可在壓電體層13之基板21側及電極16側之兩側均能抑制形成漏洩路徑。又可提高壓電體層13與電極16之結晶性,進而提高壓電特性。
<特性評價>
The capacitance C LS per unit area of the two leakage current suppression layers 15-1 and 5-12 in the structure of FIG. 1F, as described above with reference to FIG. 1C , C LS /C PIEZ is designed to be 1.20 or more and Less than 60.00. By providing the leakage current suppression layer 15-1 between the
如上所述,實施方式之壓電元件10被設計成其漏電流抑制層15與壓電體層13之靜電容量關係可滿足規定的關係。以下,基於對實際製作的複數個樣品進行測定‧評價之結果,就上述靜電容量簡易系統之依據進行說明。As described above, the
圖2示出實施例樣品及比較例樣品之元素。除了比較例1之外,所有的樣品中形成有漏電流抑制層。樣品結構採用圖1A之結構,除了比較例1之外,於電極16(第1電極)與壓電體層13之間設有漏電流抑制層15。如下文所述,以未設漏電流抑制層15的比較例1之壓電特性作為基準,對各樣品的特性進行評價。全樣品中共同的固定條件如下。Fig. 2 shows the elements of the sample of the example and the sample of the comparative example. Except for Comparative Example 1, leakage current suppressing layers were formed in all samples. The sample structure adopted the structure of FIG. 1A , except for Comparative Example 1, and a leakage
作為基板11,使用厚度50μm之PET薄膜。於PET薄膜上,作為第2電極12,使用批次焊濺(Batchspatter)裝置形成了厚度100nm之IZO膜。在成膜電力為DC400W、成膜壓力為0.4Pa、氬氣(Ar)與1%的氧(O
2)之混合氣體氛圍中成膜。
As the
於第2電極12之上,使用相同的成膜裝置形成MgZnO的壓電體層13。在成膜電力為RF500W、成膜壓力為0.2Pa、Ar氣體與13%的O
2之混合氣體氛圍中進行成膜。壓電體層13中Mg之組成佔12wt.%。該壓電體層13之相對電容率εr
PIEZ為9,藉由在MgZnO(002)面透過X線繞射搖擺曲線法所獲得的FWHM為4.6°。以上為全樣品之共同條件。
On the
其次,對漏電流抑制層15之有無、種類、膜厚及壓電體層13之厚度進行變更,製作了複數個樣品,並計算漏電流抑制層15每單位面積的靜電容量相對於壓電體層13每單位面積的靜電容量之比C
LS/C
PIEZ。另外,作為壓電特性,測定各樣品之壓電常數d33[pC/N]。d33係表示分極方向之伸縮模式的值,其表示沿著分極方向施加的每單位壓力之分極電荷量。實施方式之結構中,表示膜厚方向,即c軸方向之伸縮模式。
Next, a plurality of samples were produced by changing the presence, type, film thickness, and thickness of the leakage
按照以下程式評價壓電常數d33。以第2電極12位元於下側的方式,將樣品置於臺上,用壓頭對樣品之上面施加規定的壓力,測定c軸(膜厚)方向的分極所生成的電荷。用作為負荷差的1N除以施加負荷從5N變為6N時發生的電荷量除,以其值作為d33值。The piezoelectric constant d33 was evaluated according to the following formula. Place the sample on the stage with the 12th electrode on the lower side, apply a predetermined pressure to the upper surface of the sample with an indenter, and measure the charge generated by polarization in the c-axis (film thickness) direction. Divide 1N, which is the load difference, by the amount of charge generated when the applied load changes from 5N to 6N, and use its value as the d33 value.
實施例1~4、6、9、10中,作為漏電流抑制層15形成Al
2O
3。Al
2O
3膜係使用批次焊濺裝置,在電力RF300W、壓力0.3Pa之條件下,並在Ar氣體與11.5%的O
2之混合氣體氛圍中成膜。Al
2O
3之相對電容率為9。首先,關於作為漏電流抑制層15設有Al
2O
3膜的實施例1~4、6、9、10進行說明。
In Examples 1 to 4, 6, 9, and 10, Al 2 O 3 was formed as the leakage
實施例1的壓電體層13之厚度為200nm,漏電流抑制層15之膜厚為25nm。該樣品之壓電常數d33為19.8pC/N,靜電容量之比C
LS/C
PIEZ為8.000。
In Example 1, the
實施例2的壓電體層13之厚度為200nm,漏電流抑制層15之膜厚為50nm。該樣品之壓電常數d33為14.7pC/N,靜電容量之比C
LS/C
PIEZ為4.000。
In Example 2, the
實施例3的壓電體層13之厚度為200nm,漏電流抑制層15之膜厚為75nm。該樣品之壓電常數d33為13.4pC/N,靜電容量之比C
LS/C
PIEZ為2.667。
In Example 3, the
實施例4的壓電體層13之厚度為200nm,漏電流抑制層15之膜厚為125nm。該樣品之壓電常數d33為12.1pC/N,靜電容量之比C
LS/C
PIEZ為1.600。實施例1~4中,漏電流抑制層15之膜厚相對於壓電體層13之厚度的比率反映於靜電容量比C
LS/C
PIEZ,膜厚比較小的情形下,有靜電容量比與壓電常數d33增大之傾向。
In Example 4, the
實施例6的壓電體層13之厚度為500nm,漏電流抑制層15之膜厚為100nm。該樣品之壓電常數d33為15.1pC/N,靜電容量之比C
LS/C
PIEZ為5.000。
In Example 6, the
實施例9的壓電體層13之厚度為300nm,漏電流抑制層15之膜厚為10nm。該樣品之壓電常數d33為20.9pC/N,靜電容量之比C
LS/C
PIEZ為30.000。
In Example 9, the
實施例10的壓電體層13之厚度為500nm,漏電流抑制層15之膜厚為10nm。該樣品之壓電常數d33為25.0pC/N,靜電容量之比C
LS/C
PIEZ為50.000。
In Example 10, the
實施例9與10相較於實施例1~4,藉由增加了壓電體層13之厚度,壓電常數d33有提高。另一方面,實施例6中,壓電體層13之厚度與實施例10相同,而漏電流抑制層15之膜厚比實施例10厚10倍。因漏電流抑制層15相對於壓電體層13之膜厚比的不同,致使壓電特性有差異,但實施例6、9、10均示出良好的壓電常數d33值。Compared with Examples 1-4, Examples 9 and 10 increase the piezoelectric constant d33 by increasing the thickness of the
其次,關於作為漏電流抑制層15使用SiO
2膜時的特性進行說明。實施例5與實施例8中使用了SiO
2膜。實施例5中,形成厚度200nm之壓電體層13,作為漏電流抑制層15形成膜厚15nm之SiO
2。使用與Al
2O
3成膜時同樣的批次焊濺裝置,在電力RF300W、壓力0.3Pa之條件下,並於Ar氣體與5.4%的O
2之混合氣體氛圍中形成SiO
2膜。SiO
2之相對電容率為4。實施例5的樣品之壓電常數d33為15.3pC/N,靜電容量之比C
LS/C
PIEZ為5.926。
Next, the characteristics when a SiO 2 film is used as the leakage current suppressing
實施例8中,形成厚度500nm之壓電體層13,作為漏電流抑制層15,形成膜厚50nm之SiO
2。使用與Al
2O
3成膜時同樣的批次焊濺裝置,在電力RF300W、壓力0.3Pa之條件下,並在Ar氣體與5.4%的O
2之混合氣體氛圍中形成SiO
2膜。SiO
2之相對電容率為4。實施例8的樣品之壓電常數d33為14.8pC/N,靜電容量之比C
LS/C
PIEZ為4.444。實施例5與實施例8之測定結果僅有微小差距,其理由可推測為因壓電體層13與漏電流抑制層15之膜厚比有些許差異所致。然而,實施例5與8均具有良好的壓電常數d33的值,可知SiO
2膜作為漏電流抑制層發揮著有效功能。
In Example 8, the
其次,關於作為漏電流抑制層15使用Si
3N
4膜時的特性進行說明。實施例7中使用了Si
3N
4膜。實施例7中,形成厚度500nm之壓電體層13,作為漏電流抑制層15,形成膜厚50nm之Si
3N
4膜。Si
3N
4膜、使用與Al
2O
3成膜時同樣的批次焊濺裝置,在電力RF300W、壓力0.3Pa之條件下,並在Ar氣體與20%的N
2氣體之混合氣體氛圍中進行成膜。Si
3N
4之相對電容率為8。實施例7的樣品之壓電常數d33為18.5pC/N、靜電容量之比C
LS/C
PIEZ為8.889。實施方式7中也能獲得良好的壓電常數d33的值,可知Si
3N
4膜作為漏電流抑制層有效發揮著其功能。
Next, the characteristics when a Si 3 N 4 film is used as the leakage
以下,關於比較例進行說明。比較例1中,設有厚度200nm的壓電體層13,並未使用漏電流抑制層15。該樣品之壓電常數d33為10.2pC/N。以比較例1之壓電特性作為評價基準。Hereinafter, comparative examples will be described. In Comparative Example 1, the
比較例2中,設置厚度200nm的壓電體層13,作為漏電流抑制層15形成膜厚225nm的Al
2O
3膜。該樣品之壓電常數d33為8.3pC/N,靜電容量之比C
LS/C
PIEZ為0.889。相較於實施例1~4,漏電流抑制層15之厚度增大,相應地靜電容量比減小,壓電特性降低。
In Comparative Example 2, the
比較例3中,設置厚度200nm的壓電體層13,作為漏電流抑制層15,形成膜厚300nm的Al
2O
3膜。該樣品之壓電常數d33為7.5pC/N,靜電容量之比C
LS/C
PIEZ為0.667。相較於比較例2,漏電流抑制層15之厚度進一步增大,靜電容量比減少、壓電特性降低。
In Comparative Example 3, the
比較例4中,設置厚度200nm的壓電體層13,作為漏電流抑制層15,形成膜厚80nm的SiO
2膜。該樣品之壓電常數d33為9.0pC/N,靜電容量之比C
LS/C
PIEZ為1.111。作為漏電流抑制層15使用與實施例5相同的SiO
2膜,但漏電流抑制層15之厚度比起實施例5有所增大,相應地靜電容量比較小,壓電特性降低。
In Comparative Example 4, a
比較例5中,設置厚度300nm的壓電體層13,作為漏電流抑制層15,形成膜厚5nm之Al
2O
3膜。該樣品之壓電常數d33為9.5pC/N、靜電容量之比C
LS/C
PIEZ為60.000。作為漏電流抑制層15使用與實施例1~4、6、9、10相同的Al
2O
3膜,但漏電流抑制層15之厚度是較薄的5nm,靜電容量比有所増大,而壓電特性相較於作為基準的比較例1有所降低。可知漏電流抑制層15之厚度過薄時,無法獲得漏電流抑制效果。
In Comparative Example 5, a
圖3是基於圖2之評價結果繪製的漏電流抑制層15之膜厚與壓電常數d33之關係的圖。以未設置漏電流抑制層15的比較例1作為基準(初期特性),將壓電特性相較於初期有所提高的實施例1~10之樣品作為有效樣品。圖3中,縱軸上的白色△表示比較例1之壓電特性。與橫軸為水準的虛線為基準線。比較例2~5之壓電特性低於基準。其中,比較例2、3、4的漏電流抑制層15相對於壓電體層13之膜厚比過大,因此,靜電容量比降低而無法獲得充分的壓電特性。相對而言,比較例5中,漏電流抑制層15相對於壓電體層13之膜厚比過小,因此靜電容量比會增大,卻因漏電流抑制層15無法發揮出漏電流抑制效果,而導致壓電特性降低。FIG. 3 is a graph showing the relationship between the film thickness of the leakage
圖4A與圖4B係作為靜電容量之比C
LS/C
PIEZ的函數繪出的壓電常數d33的圖。圖5係圖4A與圖4B之閾值近旁的擴大圖。圖4A中示出靜電容量之比C
LS/C
PIEZ為0以上10以下範圍的壓電常數d33之分佈,圖4B中示出靜電容量之比C
LS/C
PIEZ為0以上70以下範圍的壓電常數d33之分佈。若僅看圖4A,可見透過加大靜電容量比可提高壓電特性。而參照圖4B,便可知靜電容量比過大,即,漏電流抑制層15過薄,亦無法獲得充分的壓電管制。根據圖4B,靜電容量比優選為小於60.00。
4A and 4B are graphs of the piezoelectric constant d33 plotted as a function of the capacitance ratio C LS /C PIEZ . Fig. 5 is an enlarged view near the threshold of Fig. 4A and Fig. 4B. Fig. 4A shows the distribution of the piezoelectric constant d33 when the capacitance ratio C LS /C PIEZ is in the range of 0 to 10, and Fig. 4B shows the capacitance ratio C LS /C PIEZ in the range of 0 to 70. Distribution of electrical constant d33. If we only look at Figure 4A, it can be seen that the piezoelectric characteristics can be improved by increasing the capacitance ratio. Referring to FIG. 4B , it can be seen that the capacitance ratio is too large, that is, the leakage
圖5中,為了求出靜電容量之比C LS/C PIEZ的下限閾值,利用與橫軸水準的基準線(虛線)近旁的資料點進行擬合(fitting)。基於基準線近旁的資料點所獲得的擬合曲線被表示為y=4.4272In(x)+9.0353。該擬合曲線之決定係數R 2為0.9479,認定具有極強的關連性。 In FIG. 5 , in order to obtain the lower threshold value of the capacitance ratio C LS /C PIEZ , fitting is performed using data points near the reference line (dotted line) on the horizontal axis. The fitted curve obtained based on the data points near the baseline is expressed as y=4.4272In(x)+9.0353. The coefficient of determination R 2 of the fitting curve is 0.9479, which is considered to have a strong correlation.
若以未設置漏電流抑制層15的比較例1之壓電特性作為基準,當靜電容量之比C
LS/C
PIEZ為1.20以上且小於6.00、優選為1.25以上且小於60.00、進而優選為1.29以上且小於60.00時,壓電特性會等同於初期特性或有提高。靜電容量之比C
LS/C
PIEZ為1.20時的d33值在初期特性的±3%之範圍內,靜電容量之比C
LS/C
PIEZ為1.25時的d33值在初期特性±2%之範圍內,可視之為落在誤差範圍範圍內。由此,作為壓電元件10的漏電流抑制層15與壓電體層13之靜電容量關係,可導出以下關係。
1.20≦C
LS/C
PIEZ<6.00
Based on the piezoelectric characteristics of Comparative Example 1 in which the leakage
圖6係採用實施方式之壓電元件10的感測器100之模式圖。感測器100具有壓電元件10、電荷放大器24及顯示裝置25。壓電元件10被施加機械性力量時,藉由壓電效應,會生成與施加之力成比例的量的電荷。由電荷放大器24對該生成的電荷進行放大,並輸出到顯示裝置25,可將其用為壓力感測器。FIG. 6 is a schematic diagram of a
除了對該生成的電荷量直接進行測定的結構,取而代之亦可對失真(distorted)所致的電阻變化進行測定。在此情形下,可將第1電極16與第2電極12之間(使用導電性基板21的情形下,則是第1電極16與基板21之間)連接於電橋電路,將電阻變化轉換為電壓變化,進行放大、模數轉換等之後輸出。In addition to the structure in which the amount of generated charge is directly measured, the resistance change due to distortion may be measured instead. In this case, a bridge circuit can be connected between the
利用壓電元件10的逆壓電效應之情形下,可以使用電場施加手段,控制施加於壓電元件10的電場,以用為致動器。因逆壓電效應,會產生與所施加的電場相應的失真。在壓電元件中,借助漏電流抑制層15,代表分極方向之伸縮模式的d33特性良好,由此可實現驅動效率良好的致動器。In the case of utilizing the inverse piezoelectric effect of the
無論利用壓電效應之情形,亦或利用逆壓電效應之情形,均可抑制壓電元件10中的壓電體層13發生微小漏電流,從而可在採用壓電元件10的裝置中體現出良好的壓電特性。Regardless of the use of the piezoelectric effect or the use of the inverse piezoelectric effect, the
以上,基於特定的實施例說明瞭本發明,而本發明並不限定於上述結構例。例如,可將壓電體層13形成為2層以上的壓電體膜的疊層。各壓電體膜之主成分可為相同材料,亦可為不同材料。從晶格常數的整合性之觀點而言,主成分可以使用相同材料。可以在至少一部分壓電體膜添加副成份。添加於各層的副成分可相同,亦可不同。無論何種情形,壓電體層成模的整體厚度為5μm以下,優選為3μm以下,更優選為2μm以下,更優選為1μm以下,進而優選為500nm以下。漏電流抑制層之材料與厚度,依據壓電體層整體的相對電容率與膜厚之關係,被定為滿足1.20≦C
LS/C
PIEZ<60.00。在可滿足該靜電容量比條件的範圍內,漏電流抑制層除了使用Al
2O
3、SiO
2、Si
3N
4之外,亦可以使用ZrO
2、TiO
2、AlN、Ta
2O
5,或其中2種以上的組合材料。漏電流抑制層之介電係數過高時,高頻信號難以通過,有時信號波形會發生圓形失真(waveformrounding)。壓電元件應用於高頻裝置之情形下,上述材料中的Al
2O
3、SiO
2、Si
3N
4尤其適於漏電流抑制層。
As mentioned above, although this invention was demonstrated based on the specific Example, this invention is not limited to the said structural example. For example, the
本申請基於2021年2月1日提出的日本國專利申請第2021-014369號,及2022年1月24日提出的日本國專利申請第2022-008468號請求優先權,並引用上述日本國專利申請之全部內容。This application is based on the Japanese patent application No. 2021-014369 filed on February 1, 2021, and the Japanese patent application No. 2022-008468 filed on January 24, 2022 to claim priority, and cites the above Japanese patent application the entire content.
10A~10F:壓電元件 11,21:基板 12:電極(第2電極) 13:壓電體層 15,15-1,15-2:漏電流抑制層 16:電極(第1電極) 100:感測器10A~10F:
圖1A係實施方式之壓電元件之第1結構例。 圖1B係實施方式之壓電元件之第2結構例。 圖1C係實施方式之壓電元件之第3結構例。 圖1D係實施方式之壓電元件之第4結構例。 圖1E係實施方式之壓電元件之第5結構例。 圖1F係實施方式之壓電元件之第6結構例。 圖2係示出實施例與比較例之測定結果的圖。 圖3係示出漏電流抑制層之膜厚與壓電常數d33之關係的圖。 圖4A係靜電容量比與壓電常數d33之關係的圖。 圖4B係示出擴大靜電容量比範圍後其與壓電常數d33之關係的圖。 圖5係示出圖4A及圖4B之閾值近旁的擴大圖。 圖6係示出採用實施方式之壓電元件的感測器之一例的模式圖。Fig. 1A is a first structural example of the piezoelectric element of the embodiment. Fig. 1B is a second structural example of the piezoelectric element of the embodiment. Fig. 1C is a third structural example of the piezoelectric element of the embodiment. Fig. 1D is a fourth structural example of the piezoelectric element of the embodiment. Fig. 1E is a fifth structural example of the piezoelectric element of the embodiment. Fig. 1F is a sixth structural example of the piezoelectric element of the embodiment. Figure 2 is a graph showing the measurement results of Examples and Comparative Examples. Fig. 3 is a graph showing the relationship between the film thickness of the leakage current suppression layer and the piezoelectric constant d33. Figure 4A is a graph showing the relationship between the capacitance ratio and the piezoelectric constant d33. Fig. 4B is a graph showing the relationship between the capacitance ratio and the piezoelectric constant d33 after expanding the capacitance ratio range. Figure 5 is an enlarged view showing the vicinity of the threshold in Figures 4A and 4B. FIG. 6 is a schematic diagram showing an example of a sensor using the piezoelectric element of the embodiment.
Claims (11)
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