TW202300729A - Semiconductor substrate and fabrication method of semiconductor device - Google Patents

Semiconductor substrate and fabrication method of semiconductor device Download PDF

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TW202300729A
TW202300729A TW110122585A TW110122585A TW202300729A TW 202300729 A TW202300729 A TW 202300729A TW 110122585 A TW110122585 A TW 110122585A TW 110122585 A TW110122585 A TW 110122585A TW 202300729 A TW202300729 A TW 202300729A
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silicon carbide
carbide wafer
distance
semiconductor substrate
wafer
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TW110122585A
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TWI807347B (en
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林欽山
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環球晶圓股份有限公司
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Priority to CN202210379910.XA priority patent/CN115579377A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Abstract

A semiconductor substrate includes a silicon carbide wafer having a first surface, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface. There is a first inclined surface and/or a first curved surface between the first surface and the side surface. There is a second inclined surface and/or a second curved surface between the second surface and the side surface. In the first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface.

Description

半導體基底以及半導體裝置的製造方法Semiconductor substrate and method for manufacturing semiconductor device

本發明是有關於一種半導體基底，且特別是有關於一種包括碳化矽晶圓的半導體基底以及半導體裝置的製造方法。The present invention relates to a semiconductor substrate, and in particular to a semiconductor substrate including a silicon carbide wafer and a method for manufacturing a semiconductor device.

在半導體產業中，製造晶圓的方法包括先形成晶碇(Ingot)，接著將晶碇切片以獲得晶圓。晶碇例如是在高溫的環境中製造。在一些晶碇的製造過程中，晶種被置放於高溫爐中，晶種接觸氣態或液態的原料，並形成半導體材料於晶種的表面，直到獲得具有預期尺寸的晶碇為止。晶碇可以視製造方式與製造原料而有不同的結晶構造。In the semiconductor industry, a wafer manufacturing method includes forming an ingot first, and then slicing the ingot to obtain wafers. Crystal anchors are manufactured, for example, in a high-temperature environment. In some anchor manufacturing processes, the seed crystal is placed in a high-temperature furnace, the seed crystal contacts gaseous or liquid raw materials, and semiconductor materials are formed on the surface of the seed crystal until an anchor with a desired size is obtained. Crystal anchors can have different crystalline structures depending on the manufacturing method and raw materials.

在晶碇生長完成後，以爐冷或其他方式使晶碇降溫至室溫。在晶碇降溫之後，利用切割機把晶碇形狀較差的頭尾兩端移除，接著用磨輪將晶碇研磨到想要的尺寸(例如3英吋至12英吋)。在一些晶碇的製造過程中，於晶碇的邊緣研磨出一道平邊或V型槽。此平邊或V型槽適用於作為晶碇的結晶方向的記號。接著將晶碇切片，以獲得多個晶圓(Wafer)。在一些情況中，晶圓的邊角容易因為碰撞而破裂。After the growth of the anchor is completed, the anchor is cooled down to room temperature by furnace cooling or other means. After the crystal anchor cools down, use a cutting machine to remove the poorly shaped head and tail ends of the anchor, and then use a grinding wheel to grind the anchor to a desired size (for example, 3 inches to 12 inches). In the manufacturing process of some anchors, a flat edge or V-shaped groove is ground on the edge of the anchor. This flat edge or V-groove is suitable as a marker of the crystallographic orientation of the anchor. Then the wafer is sliced to obtain multiple wafers (Wafers). In some cases, the corners of the wafers are prone to cracking due to collisions.

本發明提供一種半導體基底，能改善碳化矽晶圓在研磨過後出現邊角破裂的問題。The invention provides a semiconductor substrate, which can solve the problem of corner cracking of silicon carbide wafers after grinding.

本發明提供一種半導體裝置的製造方法，能改善碳化矽晶圓在研磨過後出現邊角破裂的問題。The invention provides a method for manufacturing a semiconductor device, which can solve the problem of corner cracking of a silicon carbide wafer after grinding.

本發明的至少一實施例提供一種半導體基底。半導體基底包括碳化矽晶圓，具有第一面、平行於第一面的第二面以及垂直於第一面與第二面的側面。第一面與側面之間包括第一斜面及/或第一弧面。第二面與側面之間包括第二斜面及/或第二弧面。在平行第一面的第一方向上，第一面與側面的距離A1大於第二面與側面的距離A2。At least one embodiment of the present invention provides a semiconductor substrate. The semiconductor base includes a silicon carbide wafer, which has a first surface, a second surface parallel to the first surface, and side surfaces perpendicular to the first surface and the second surface. A first inclined surface and/or a first arc surface are included between the first surface and the side surface. A second inclined surface and/or a second arc surface are included between the second surface and the side surface. In the first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface.

本發明的至少一實施例提供一種半導體裝置的製造方法，包括：提供碳化矽晶圓；以及加工碳化矽晶圓的邊緣。碳化矽晶圓在加工後包括第一面、平行於第一面的第二面以及垂直於第一面與第二面的側面。第一面與側面之間包括第一斜面及/或第一弧面。第二面與側面之間包括第二斜面及/或第二弧面。在平行第一面的第一方向上，第一面與側面的距離A1大於第二面與側面的距離A2。At least one embodiment of the present invention provides a method of manufacturing a semiconductor device, including: providing a silicon carbide wafer; and processing an edge of the silicon carbide wafer. After processing, the silicon carbide wafer includes a first surface, a second surface parallel to the first surface, and side surfaces perpendicular to the first surface and the second surface. A first inclined surface and/or a first arc surface are included between the first surface and the side surface. A second inclined surface and/or a second arc surface are included between the second surface and the side surface. In the first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface.

圖1A至圖1H是依照本發明的一實施例的一種半導體裝置的製造方法的製造方法的示意圖。1A to 1H are schematic diagrams of a manufacturing method of a semiconductor device according to an embodiment of the present invention.

請參考圖1A，圖1A是晶碇100的切割製程的斜視圖。以切割工具200切割晶碇100。切割工具200包括固定裝置210、滾輪220以及切割線230。固定裝置210用於固定晶碇100。切割線230包括鋼線以及鋼線上的磨粒(例如鑽石顆粒)。利用切割線230纏繞於滾輪220上，並定義出多個切削段，以切割線230反覆切割晶碇100，以將晶碇100切割成數十至數百片的晶圓。在本實施中，以鑽石線切割晶碇100，但本發明不以此為限。在其他實施例中，以刀具、雷射、水刀或其他方式切割晶碇100。Please refer to FIG. 1A , which is a perspective view of the cutting process of the crystal anchor 100 . The anchor 100 is cut with a cutting tool 200 . The cutting tool 200 includes a fixing device 210 , a roller 220 and a cutting wire 230 . The fixing device 210 is used for fixing the crystal anchor 100 . The cutting wire 230 includes a steel wire and abrasive grains (such as diamond grains) on the steel wire. The dicing wire 230 is wound on the roller 220 to define a plurality of cutting segments, and the dicing wire 230 is used to cut the peg 100 repeatedly, so as to cut the peg 100 into tens to hundreds of wafers. In this embodiment, the anchor 100 is cut with a diamond wire, but the invention is not limited thereto. In other embodiments, the anchor 100 is cut by a knife, laser, water jet or other methods.

在本實施例中，晶碇100的材料包括碳化矽。晶碇100在切割後形成多個碳化矽晶圓。In this embodiment, the material of the anchor 100 includes silicon carbide. After dicing, the anchor 100 forms a plurality of silicon carbide wafers.

圖1B至圖1H是依照本發明的一實施例的一種半導體裝置的製造方法的剖面示意圖。1B to 1H are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

請參考圖1B，提供碳化矽晶圓110。在本實施例中，碳化矽晶圓110在加工前包括第一面112、平行於第一面112的第二面114以及垂直於第一面112與第二面114的側面116。在一些實施例中，在加工碳化矽晶圓110前，第一面112與側面116相連，且第一面112與側面116之間的夾角約為直角，第二面114與側面116相連，且第二面114與側面116之間的夾角約為直角。Referring to FIG. 1B , a silicon carbide wafer 110 is provided. In this embodiment, the silicon carbide wafer 110 includes a first surface 112 , a second surface 114 parallel to the first surface 112 , and a side surface 116 perpendicular to the first surface 112 and the second surface 114 before processing. In some embodiments, before processing the silicon carbide wafer 110, the first surface 112 is connected to the side surface 116, and the angle between the first surface 112 and the side surface 116 is about a right angle, the second surface 114 is connected to the side surface 116, and The angle between the second surface 114 and the side surface 116 is approximately a right angle.

加工碳化矽晶圓110的邊緣116。舉例來說，以磨頭300研磨碳化矽晶圓110的邊緣。磨頭300包括第一凸出部310以及第二凸出部320。第一凸出部310用於加工碳化矽晶圓110的上側的邊緣，即側面116靠近第二面114的部分。第二凸出部320用於加工碳化矽晶圓110的下側的邊緣，即側面116靠近第一面112的部分。第一凸出部310的形狀不同於第二凸出部320的形狀。在本實施例中，在朝向碳化矽晶圓110的方向上，第一凸出部310相較於第二凸出部320更凸出，因此，在旋轉碳化矽晶圓110以研磨碳化矽晶圓110的邊緣時，第二凸出部320較第一凸出部310移除更多的碳化矽晶圓110。Edge 116 of silicon carbide wafer 110 is machined. For example, the edge of the silicon carbide wafer 110 is ground by the grinding head 300 . The grinding head 300 includes a first protruding portion 310 and a second protruding portion 320 . The first protruding portion 310 is used for processing the edge of the upper side of the silicon carbide wafer 110 , that is, the portion of the side surface 116 close to the second surface 114 . The second protruding portion 320 is used for processing the edge of the lower side of the silicon carbide wafer 110 , that is, the portion of the side surface 116 close to the first surface 112 . The shape of the first protrusion 310 is different from the shape of the second protrusion 320 . In this embodiment, in the direction toward the SiC wafer 110, the first protruding portion 310 is more protruding than the second protruding portion 320, therefore, when the SiC wafer 110 is rotated to grind the SiC crystal When the edge of the circle 110 is reached, the second protrusion 320 removes more SiC wafer 110 than the first protrusion 310 .

請參考圖1C，碳化矽晶圓110在加工後包括第一面112a、平行於第一面112a的第二面114a以及垂直於第一面112a與第二面114a的側面116a。第一面112a與側面116a之間包括第一斜面及/或第一弧面。在本實施例中，第一面112a與側面116a之間包括第一弧面113。第二面114a與側面116a之間包括第二斜面及/或第二弧面。在本實施例中，第二面114a與側面116a之間包括第二弧面115。Referring to FIG. 1C , the silicon carbide wafer 110 includes a first surface 112 a , a second surface 114 a parallel to the first surface 112 a and a side surface 116 a perpendicular to the first surface 112 a and the second surface 114 a after processing. A first inclined surface and/or a first arc surface are included between the first surface 112a and the side surface 116a. In this embodiment, a first arc surface 113 is included between the first surface 112a and the side surface 116a. A second inclined surface and/or a second arc surface are included between the second surface 114a and the side surface 116a. In this embodiment, a second arc surface 115 is included between the second surface 114a and the side surface 116a.

在平行第一面112a的第一方向D1上，第一面112a與側面116a的距離A1大於第二面114a與側面116a的距離A2。在平行側面116a的第二方向D2上，第一面112a與側面116a的距離B1大於第二面114a與側面116a的距離B2。第一方向D1垂直於第二方向D2。在一些實施例中，A1:B1為150:80至250:160，A2:B2為60:40至80:60。在本實施例中，距離A1大於距離A2，且第二面114a的面積大於第一面112a的面積。在一些實施例中，距離A1為150微米至250微米，距離B1為80微米至160微米，距離A2為60微米至80微米，距離B2為40微米至60微米。In the first direction D1 parallel to the first surface 112a, the distance A1 between the first surface 112a and the side surface 116a is greater than the distance A2 between the second surface 114a and the side surface 116a. In the second direction D2 parallel to the side surface 116a, the distance B1 between the first surface 112a and the side surface 116a is greater than the distance B2 between the second surface 114a and the side surface 116a. The first direction D1 is perpendicular to the second direction D2. In some embodiments, A1:B1 is 150:80 to 250:160, and A2:B2 is 60:40 to 80:60. In this embodiment, the distance A1 is greater than the distance A2, and the area of the second surface 114a is greater than the area of the first surface 112a. In some embodiments, the distance A1 is 150 microns to 250 microns, the distance B1 is 80 microns to 160 microns, the distance A2 is 60 microns to 80 microns, and the distance B2 is 40 microns to 60 microns.

在一些實施例中，在加工碳化矽晶圓110的邊緣116之前或之後，對碳化矽晶圓110進行物理研磨製程及/或化學機械研磨製程(Chemical-Mechanical Polishing)。化學機械研磨製程是以具有腐蝕性的研磨液以及磨料配合拋光墊，對碳化矽晶圓110的表面(例如第一面及/或第二面)進行研磨。化學機械研磨製程中的具有腐蝕性的研磨液可以與晶圓表面發生化學反應，使晶圓表面凹凸不平的部分轉變成硬度較小的材料，藉此使磨料能更容易的移除晶圓表面凹凸不平的部分。在一些實例中，在化學機械研磨製程之後，對碳化矽晶圓110進行退火(anneal)，以使碳化矽晶圓110內部的原子能夠排列的較整齊，藉此減少晶圓內部的晶體缺陷(defect)。In some embodiments, before or after processing the edge 116 of the silicon carbide wafer 110 , a physical polishing process and/or a chemical-mechanical polishing process (Chemical-Mechanical Polishing) is performed on the silicon carbide wafer 110 . In the chemical mechanical polishing process, the surface (eg, the first surface and/or the second surface) of the silicon carbide wafer 110 is polished with a corrosive polishing liquid and abrasive materials together with a polishing pad. The corrosive polishing liquid in the chemical mechanical polishing process can chemically react with the wafer surface, turning the uneven part of the wafer surface into a material with less hardness, so that the abrasive can be removed from the wafer surface more easily Bumpy parts. In some examples, after the chemical mechanical polishing process, the silicon carbide wafer 110 is annealed, so that the atoms inside the silicon carbide wafer 110 can be arranged more orderly, thereby reducing crystal defects inside the wafer ( defect).

請參考圖1D，形成磊晶層120於第二面114a上。在一些實施例中，第一面112a為碳面，第二面114a為矽面，因此，形成磊晶層120於第二面114a上能獲得較好的磊晶品質。在本實施例中，磊晶層120形成於第二弧面115上，並從第二弧面115延伸至第二面114a中央。藉由第二弧面115的設置，磊晶層120不會形成於具有直角或銳角的邊緣，藉此減少磊晶層120因為邊緣的直角或銳角出現局部應力集中而導致裂痕產生。Referring to FIG. 1D , an epitaxial layer 120 is formed on the second surface 114 a. In some embodiments, the first surface 112a is a carbon surface, and the second surface 114a is a silicon surface. Therefore, forming the epitaxial layer 120 on the second surface 114a can obtain better epitaxial quality. In this embodiment, the epitaxial layer 120 is formed on the second arc surface 115 and extends from the second arc surface 115 to the center of the second surface 114a. With the arrangement of the second curved surface 115 , the epitaxial layer 120 will not be formed on the edge with a right angle or an acute angle, thereby reducing the generation of cracks in the epitaxial layer 120 due to local stress concentration at the edge at a right angle or an acute angle.

請參考圖1E，形成多個半導體元件130於磊晶層120上或磊晶層120中。在圖1E中，半導體元件130位於磊晶層120的上表面上方，但本發明不以此為限。在其他實施例中，半導體元件130鑲入磊晶層120中。形成半導體元件130的方法例如包括離子佈植、微影蝕刻、化學氣相沉積、物裡氣相沉積、原子層沉積或其他製程。Referring to FIG. 1E , a plurality of semiconductor elements 130 are formed on or in the epitaxial layer 120 . In FIG. 1E , the semiconductor device 130 is located above the upper surface of the epitaxial layer 120 , but the invention is not limited thereto. In other embodiments, the semiconductor device 130 is embedded in the epitaxial layer 120 . The method of forming the semiconductor device 130 includes, for example, ion implantation, lithography etching, chemical vapor deposition, material vapor deposition, atomic layer deposition or other processes.

請參考圖1E與圖1F，對第一面112a執行研磨製程以減少碳化矽晶圓110的厚度。研磨第一面112a以獲得第三面118，第三面118與碳化矽晶圓110a的邊緣之間的夾角α為直角或鈍角。舉例來說，研磨第一面112a直到第一弧面113完全被移除，則所獲得之第三面118與側面116a之間的夾角為直角。若未研磨至第一弧面113被完全移除，則所獲得之第三面118與殘留之第一弧面113之間的夾角為鈍角。Referring to FIG. 1E and FIG. 1F , a grinding process is performed on the first surface 112 a to reduce the thickness of the silicon carbide wafer 110 . The first surface 112 a is ground to obtain the third surface 118 , and the angle α between the third surface 118 and the edge of the SiC wafer 110 a is a right angle or an obtuse angle. For example, if the first surface 112a is ground until the first arc surface 113 is completely removed, then the angle between the third surface 118 and the side surface 116a is a right angle. If the grinding is not performed until the first arc surface 113 is completely removed, the angle between the obtained third surface 118 and the remaining first arc surface 113 is an obtuse angle.

若增加距離A2使距離A2等於或大於距離A1，則側面116a容易在研磨後被完全移除，使研磨後所獲得之第三面118與第一弧面115相連，並產生銳角，會導致碳化矽晶圓110的邊緣容易破裂，如圖2所示。因此，距離A1大於距離A2能使碳化矽晶圓110在執行第一面112a的研磨製程之後不易破裂，藉此提高製程良率。此外，距離A1越大能使第一面112a的面積越小，而第一面112a的面積越小能使第一面112a的研磨製程越容易進行。If the distance A2 is increased so that the distance A2 is equal to or greater than the distance A1, the side surface 116a is easily removed completely after grinding, so that the third surface 118 obtained after grinding is connected to the first arc surface 115, and an acute angle is formed, which will cause carbonization The edge of the silicon wafer 110 is easily broken, as shown in FIG. 2 . Therefore, the distance A1 being greater than the distance A2 can make the SiC wafer 110 less likely to break after performing the grinding process on the first surface 112a, thereby improving the process yield. In addition, the larger the distance A1, the smaller the area of the first surface 112a, and the smaller the area of the first surface 112a, the easier the grinding process of the first surface 112a is.

在一些實施例中，研磨製程前碳化矽晶圓110的厚度T約為250微米至500微米，且在研磨製程後碳化矽晶圓110的厚度T’約為50微米至150微米，但本發明不以此為限。碳化矽晶圓110的厚度可以依照實際需求而進行調整。In some embodiments, the thickness T of the silicon carbide wafer 110 before the grinding process is about 250 microns to 500 microns, and the thickness T' of the silicon carbide wafer 110 after the grinding process is about 50 microns to 150 microns, but the present invention This is not the limit. The thickness of the silicon carbide wafer 110 can be adjusted according to actual needs.

請參考圖1G，形成多層導電層144、148與多層絕緣層142、146於半導體元件120上。導電層144、148與絕緣層142、146構成重新分佈層(Redistribution Layer)140，並與半導體元件120電性連接。Referring to FIG. 1G , multiple conductive layers 144 , 148 and multiple insulating layers 142 , 146 are formed on the semiconductor device 120 . The conductive layers 144 , 148 and the insulating layers 142 , 146 constitute a redistribution layer (Redistribution Layer) 140 , and are electrically connected to the semiconductor device 120 .

在一些實施例中，形成封裝材料(未繪出)於重新分佈層140，以保護重新分佈層140以及半導體元件120，但本發明不以此為限。In some embodiments, an encapsulation material (not shown) is formed on the redistribution layer 140 to protect the redistribution layer 140 and the semiconductor device 120 , but the invention is not limited thereto.

請參考圖1H，切割碳化矽晶圓110以及重新分佈層140，以獲得多個晶片10。晶片10包括碳化矽基底110a、磊晶層120a、半導體元件130以及重新分佈層140a。在一些實施例中，晶片10還包括封裝材料。Referring to FIG. 1H , the silicon carbide wafer 110 and the redistribution layer 140 are cut to obtain a plurality of wafers 10 . The wafer 10 includes a silicon carbide substrate 110a, an epitaxial layer 120a, a semiconductor device 130 and a redistribution layer 140a. In some embodiments, wafer 10 also includes encapsulation material.

基於上述，在研磨第一面112a之前，距離A1大於距離A2能使碳化矽晶圓110在對第一面112a執行研磨製程之後不易破裂，藉此提升製程良率。Based on the above, before grinding the first surface 112a, the distance A1 is greater than the distance A2, so that the silicon carbide wafer 110 is not easily broken after performing the grinding process on the first surface 112a, thereby improving the process yield.

圖3是依照本發明的一實施例的一種晶圓的剖面示意圖。在此必須說明的是，圖3的實施例沿用圖1A至圖1H的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 3 is a schematic cross-sectional view of a wafer according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 3 follows the component numbers and part of the content of the embodiment in FIG. 1A to FIG. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖3的碳化矽晶圓110a與圖1C的碳化矽晶圓110的差異在於：碳化矽晶圓110a的第一面112a與側面116a之間包括第一斜面113A，且第二面114a與側面116a之間包括第二斜面115A。The difference between the silicon carbide wafer 110a of FIG. 3 and the silicon carbide wafer 110 of FIG. 1C is that: the first slope 113A is included between the first surface 112a and the side surface 116a of the silicon carbide wafer 110a, and the second surface 114a and the side surface 116a A second slope 115A is included therebetween.

請參考圖3，第一斜面113A連接第一面112a與側面116a，且第一斜面113A與第一面112a之間的導圓角的角度為β1。第二斜面115A連接第二面114a與側面116a，且第二斜面115A與第二面116a之間的導圓角的角度為β2，β1大於β2。在一些實施例中，β1為130r(µm)至200r(µm)，β2為100r(µm)至140r(µm)。第一斜面113A與側面116a之間的導圓角的角度為γ1，第二斜面115A與側面116a之間的導圓角的角度為γ2，γ2大於γ1。在一些實施例中，γ1為110°至130°，γ2為105°至125°。Referring to FIG. 3 , the first inclined surface 113A connects the first surface 112 a and the side surface 116 a, and the fillet angle between the first inclined surface 113A and the first surface 112 a is β1. The second inclined surface 115A connects the second surface 114a and the side surface 116a, and the fillet angle between the second inclined surface 115A and the second surface 116a is β2, and β1 is greater than β2. In some embodiments, β1 is 130r (µm) to 200r (µm), and β2 is 100r (µm) to 140r (µm). The rounding angle between the first slope 113A and the side surface 116a is γ1, the rounding angle between the second slope 115A and the side surface 116a is γ2, and γ2 is larger than γ1. In some embodiments, γ1 is 110° to 130° and γ2 is 105° to 125°.

基於上述，在研磨第一面112a之前，距離A1大於距離A2能使碳化矽晶圓110在對第一面112a執行研磨製程之後不易破裂，藉此提升製程良率。Based on the above, before grinding the first surface 112a, the distance A1 is greater than the distance A2, so that the silicon carbide wafer 110 is not easily broken after performing the grinding process on the first surface 112a, thereby improving the process yield.

圖4是依照本發明的一實施例的一種晶圓的剖面示意圖。在此必須說明的是，圖4的實施例沿用圖3的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 4 is a schematic cross-sectional view of a wafer according to an embodiment of the invention. It must be noted here that the embodiment in FIG. 4 follows the component numbers and partial content of the embodiment in FIG. 3 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖4的碳化矽晶圓110b與圖3的碳化矽晶圓110a的差異在於：碳化矽晶圓110b的第一面112a與側面116a之間包括第一斜面113A以及第三斜面113B。The difference between the silicon carbide wafer 110b in FIG. 4 and the silicon carbide wafer 110a in FIG. 3 is that the silicon carbide wafer 110b includes a first slope 113A and a third slope 113B between the first surface 112a and the side surface 116a.

在本實施例中，第一斜面113A與第三斜面113B之間的導圓角的角度為δ1。由於第一面112a與側面116a之間包括第一斜面113A與第三斜面113B，第三斜面113B與側面116a之間的導圓角的角度γ1以及第一面112a與側面116a之間的導圓角的角度β1可以增加，藉此進一步降低研磨第一面112a時出現碳化矽晶圓110b破裂的問題。In this embodiment, the angle of the fillet between the first slope 113A and the third slope 113B is δ1. Since the first surface 112a and the side surface 116a include the first inclined surface 113A and the third inclined surface 113B, the angle γ1 of the rounding angle between the third inclined surface 113B and the side surface 116a and the rounding angle between the first surface 112a and the side surface 116a The angle β1 of the corner can be increased, thereby further reducing the cracking problem of the SiC wafer 110b when grinding the first surface 112a.

10:晶片 100:晶碇 110、110a、110b:碳化矽晶圓 112、112a:第一面 113:第一弧面 113A:第一斜面 113B:第三斜面 114、114a:第二面 115:第二弧面 115A:第二斜面 116、116a:側面 118:第三面 120:磊晶層 130:半導體元件 140:重新分佈層 142、146:絕緣層 144、148:導電層 200:切割工具 210:固定裝置 220:滾輪 230:切割線 300:磨頭 310:第一凸出部 320:第二凸出部 A1、A2、B1、B2:距離 D1:第一方向 D2:第二方向 厚度:T、T’ α:夾角 β1、β2、γ1、γ2、δ1:角度 10: Wafer 100: crystal anchor 110, 110a, 110b: silicon carbide wafer 112, 112a: the first side 113: The first arc surface 113A: first bevel 113B: the third slope 114, 114a: the second side 115: Second arc surface 115A: Second slope 116, 116a: side 118: The third side 120: epitaxial layer 130: Semiconductor components 140:Redistribution layer 142, 146: insulating layer 144, 148: conductive layer 200: cutting tools 210: Fixtures 220: roller 230: cutting line 300: grinding head 310: first protrusion 320: second protrusion A1, A2, B1, B2: Distance D1: the first direction D2: Second direction Thickness: T, T' α: included angle β1, β2, γ1, γ2, δ1: angle

圖1A至圖1H是依照本發明的一實施例的一種半導體裝置的製造方法的製造方法的示意圖。 圖2是依照本發明的一實施例的一種晶圓的剖面示意圖。 圖3是依照本發明的一實施例的一種晶圓的剖面示意圖。 圖4是依照本發明的一實施例的一種晶圓的剖面示意圖。 1A to 1H are schematic diagrams of a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a wafer according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a wafer according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a wafer according to an embodiment of the invention.

110:碳化矽晶圓 110:Silicon carbide wafer

112a:第一面 112a: first side

113:第一弧面 113: The first arc surface

114a:第二面 114a: second side

115:第二弧面 115: Second arc surface

116a:側面 116a: side

A1、A2、B1、B2:距離 A1, A2, B1, B2: Distance

D1:第一方向 D1: the first direction

D2:第二方向 D2: Second direction

Claims (14)

一種半導體基底，包括： 一碳化矽晶圓，具有一第一面、平行於該第一面的一第二面以及垂直於該第一面與該第二面的一側面，其中該第一面與該側面之間包括一第一斜面及/或一第一弧面，且該第二面與該側面之間包括一第二斜面及/或一第二弧面，其中在平行該第一面的一第一方向上，該第一面與該側面的距離A1大於該第二面與該側面的距離A2。 A semiconductor substrate comprising: A silicon carbide wafer has a first surface, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface, wherein the first surface and the side surface include A first inclined surface and/or a first arc surface, and a second inclined surface and/or a second arc surface are included between the second surface and the side surface, wherein in a first direction parallel to the first surface , the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface. 如請求項1所述的半導體基底，其中在平行該側面的一第二方向上，該第一面與該側面的距離B1大於該第二面與該側面的距離B2。The semiconductor substrate as claimed in claim 1, wherein in a second direction parallel to the side surface, a distance B1 between the first surface and the side surface is greater than a distance B2 between the second surface and the side surface. 如請求項2所述的半導體基底，其中A1:B1為150:80至250:160。The semiconductor substrate as claimed in claim 2, wherein A1:B1 is 150:80 to 250:160. 如請求項2所述的半導體基底，其中A2:B2為60:40至80:60。The semiconductor substrate according to claim 2, wherein A2:B2 is 60:40 to 80:60. 如請求項1所述的半導體基底，其中該第一斜面連接該第一面與該側面，且該第一斜面與該第一面之間的導圓角的角度為β1，其中該第二斜面連接該第二面與該側面，且該第二斜面與該第二面之間的導圓角的角度為β2，β1大於β2。The semiconductor substrate as claimed in claim 1, wherein the first slope connects the first surface and the side surface, and the fillet angle between the first slope and the first surface is β1, wherein the second slope The second surface and the side surface are connected, and the angle of the fillet between the second inclined surface and the second surface is β2, and β1 is greater than β2. 如請求項5所述的半導體基底，其中β1為130r(µm)至200r(µm)，β2為100r(µm)至140r(µm)。The semiconductor substrate as claimed in item 5, wherein β1 is 130r (µm) to 200r (µm), and β2 is 100r (µm) to 140r (µm). 如請求項1所述的半導體基底，其中該第一面為碳面，該第二面為矽面。The semiconductor substrate as claimed in claim 1, wherein the first surface is a carbon surface, and the second surface is a silicon surface. 如請求項1所述的半導體基底，更包括： 一磊晶層，形成於該第二面上。 The semiconductor substrate as described in Claim 1, further comprising: An epitaxial layer is formed on the second surface. 如請求項1所述的半導體基底，其中該第二面的面積大於該第一面的面積。The semiconductor substrate as claimed in claim 1, wherein the area of the second surface is larger than the area of the first surface. 一種半導體裝置的製造方法，包括： 提供一碳化矽晶圓；以及 加工該碳化矽晶圓的邊緣，其中該碳化矽晶圓在加工後包括一第一面、平行於該第一面的一第二面以及垂直於該第一面與該第二面的一側面，其中該第一面與該側面之間包括一第一斜面及/或一第一弧面，且該第二面與該側面之間包括一第二斜面及/或一第二弧面，其中在平行該第一面的一第一方向上，該第一面與該側面的距離A1大於該第二面與該側面的距離A2。 A method of manufacturing a semiconductor device, comprising: providing a silicon carbide wafer; and Processing the edge of the silicon carbide wafer, wherein the silicon carbide wafer includes a first surface after processing, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface , wherein a first inclined surface and/or a first arc surface are included between the first surface and the side surface, and a second inclined surface and/or a second arc surface are included between the second surface and the side surface, wherein In a first direction parallel to the first surface, a distance A1 between the first surface and the side surface is greater than a distance A2 between the second surface and the side surface. 如請求項10所述的半導體裝置的製造方法，更包括： 形成一磊晶層於該第二面上； 形成多個半導體元件於該磊晶層上或該磊晶層中； 對該第一面執行一研磨製程以減少該碳化矽晶圓的厚度； 形成多層導電層與多層絕緣層於該些半導體元件上；以及 切割該碳化矽晶圓。 The method for manufacturing a semiconductor device as described in Claim 10, further comprising: forming an epitaxial layer on the second surface; forming a plurality of semiconductor elements on or in the epitaxial layer; performing a grinding process on the first side to reduce the thickness of the silicon carbide wafer; forming multiple conductive layers and multiple insulating layers on the semiconductor elements; and The silicon carbide wafer is diced. 如請求項10所述的半導體裝置的製造方法，其中研磨該第一面以獲得一第三面，且該第三面與該碳化矽晶圓的邊緣之間的夾角為直角或鈍角。The method for manufacturing a semiconductor device according to claim 10, wherein the first surface is ground to obtain a third surface, and the angle between the third surface and the edge of the silicon carbide wafer is a right angle or an obtuse angle. 如請求項10所述的半導體裝置的製造方法，其中在該研磨製程前該碳化矽晶圓的厚度約為250微米至500微米，且在該研磨製程後該碳化矽晶圓的厚度約為50微米至150微米。The method for manufacturing a semiconductor device according to claim 10, wherein the thickness of the silicon carbide wafer is about 250 microns to 500 microns before the grinding process, and the thickness of the silicon carbide wafer is about 50 microns after the grinding process microns to 150 microns. 如請求項10所述的半導體裝置的製造方法，其中加工該碳化矽晶圓的邊緣的方法包括： 以一磨頭研磨該碳化矽晶圓的邊緣，其中該磨頭包括一第一凸出部以及一第二凸出部，該第一凸出部用於加工該碳化矽晶圓的上側的邊緣，且該第二凸出部用於加工該碳化矽晶圓的下側的邊緣，該第一凸出部的形狀不同於該第二凸出部的形狀。 The method for manufacturing a semiconductor device as claimed in item 10, wherein the method for processing the edge of the silicon carbide wafer comprises: Grinding the edge of the silicon carbide wafer with a grinding head, wherein the grinding head includes a first protrusion and a second protrusion, the first protrusion is used to process the edge of the upper side of the silicon carbide wafer , and the second protruding portion is used for processing the edge of the lower side of the silicon carbide wafer, and the shape of the first protruding portion is different from that of the second protruding portion.
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