TW202249247A - Dynamic random access memory and method for manufacturing the same - Google Patents

Abstract

A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes bit line contact structures, bit line structures, first insulating structures, a capacitor contact structure, a first connecting pad, a second insulating structure, and a capacitor structure. The bit line structure extends along a first direction. The first insulating structure extends along a second direction that intersects the first direction. The capacitor contact structure is located between two of the bit lines and two of the first insulating structures. The first connecting pad is formed on the capacitor contact structure. The second insulating structure surrounds the first connecting pad, in which the top width of the second insulating structure is greater than the bottom width thereof.

Description

Dynamic random access memory and manufacturing method thereof

The present invention relates to a memory device, and in particular to a dynamic random access memory and a manufacturing method thereof.

With the trend of miniaturization of electronic products, there is also a demand for miniaturization of memory devices. However, with the miniaturization of memory devices, it becomes more difficult to improve the performance and yield of memory devices.

For example, in dynamic random access memory (DRAM), the bit line structure has sidewall spacers formed of nitride/oxide/nitride. In wet etching, since the oxide is less resistant to wet etching than nitride, the top of the oxide in the sidewall spacer is often damaged, resulting in thinning or even complete removal of the top of the sidewall spacer ( That is, the top surface of the sidewall spacer is lower than the top surface of the cap layer above the conductive structure). If the top of the sidewall spacer of the bitline structure is completely removed, the top of the cap layer in the bitline structure will be exposed, causing the cap layer to also possibly be deformed (e.g., making the cap layer have a rounded top surface), causing the tops of the connection pads on either side of the bitline structure to become wider than expected. In other words, the distance between the tops of adjacent connection pads becomes closer. In this way, the risk of short circuit of the memory device will be increased, thereby reducing the performance and yield of the product. With the miniaturization of memory devices, the distance between adjacent connection pads will shrink, so the above-mentioned short circuit problem will become more serious.

Embodiments of the present invention provide a DRAM and a manufacturing method thereof, which can reduce the risk of short circuit and are beneficial to miniaturization.

One embodiment of the present invention discloses a dynamic random access memory, comprising: a plurality of bit line contact structures formed on a substrate; a plurality of bit line contact structures formed on the bit line contact structures, and extending along a first direction; a plurality of first insulating structures formed on the substrate and extending along a second direction intersecting with the first direction; capacitive contact structures located between adjacent bit line structures and adjacent Between the first insulating structures; the first connection pad is formed on the capacitive contact structure; the second insulating structure surrounds the first connection pad, and the width of the top of the second insulating structure is greater than the width of the bottom; and the capacitive structure is formed on the first connection pad and electrically connected with the first connection pad.

One embodiment of the present invention discloses a manufacturing method of a dynamic random access memory, comprising: forming a plurality of bit line contact structures on a substrate; forming a plurality of bit line structures on the bit line contact structures, wherein each element line structure extends along a first direction; forms a plurality of first insulating structures on the substrate, wherein each first insulating structure extends along a second direction intersecting with the first direction; forms a capacitive contact structure located adjacent to Between the bit line structures and the adjacent first insulating structures; forming a first connection pad on the capacitive contact structure; forming a second insulating structure surrounding the first connecting pad, wherein the top width of the second insulating structure greater than the width of the bottom; and forming a capacitive structure on the first connection pad and electrically connecting with the first connection pad.

In the DRAM and its manufacturing method provided by the embodiments of the present invention, the risk of short circuit can be reduced by forming the second insulating structure surrounding the first connection pad. Furthermore, since the width of the top of the second insulating structure is greater than that of the bottom, proper contact resistance can be provided between the first connection pad and the capacitor structure, and the parasitic capacitance between the bit line structure and the first connection pad can be reduced. In this way, performance and yield can be improved.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings. Furthermore, repeated reference signs and/or words may be used in different examples of the invention. These repeated symbols or words are used for the purpose of simplification and clarity, and are not used to limit the relationship between various embodiments and/or the appearance structures. Here, the terms "about" and "approximately" usually mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The quantities given here are approximate quantities, which means that the meanings of "about" and "approximately" can still be implied without specific instructions.

The present invention provides a dynamic random access memory (DRAM) and a manufacturing method thereof. In order to simplify the drawings, FIG. 1 only shows a bit line contact structure 104, an insulating pattern 106, an insulating cover layer 110, an insulating spacer 112, The first connection pad 122 , the first insulating structure 132 and the second insulating structure 140 . Referring to FIG. 1 and FIG. 2A at the same time, insulating patterns 106 and bit line contact structures 104 are alternately formed on the substrate 102 . The bitline contact structure 104 is configured to electrically connect the substrate 102 to a subsequently formed bitline structure.

The material of the substrate 102 may include silicon, silicon-containing semiconductors, silicon on insulator (SOI), other suitable materials, or a combination of the above materials. In this embodiment, the substrate 102 is a silicon substrate. In some embodiments, shallow trench isolation structures and buried word lines may be formed in the substrate 102 . In some embodiments, other structures may also be formed in the substrate 102 . For example, a p-type well region, an n-type well region or a conductive region may be formed in the substrate 102 by an implantation process. In order to simplify the description, the above-mentioned shallow trench isolation structure, buried word line and other structures are not shown in the drawing, and the structure and formation method of the substrate 102 will not be described in detail here.

The material of the insulating pattern 106 may include oxide, nitride, oxynitride, carbide, other suitable insulating materials or combinations thereof. In this embodiment, the insulating pattern 106 is silicon nitride. In other embodiments, the insulating pattern 106 is a double-layer structure formed of silicon oxide and silicon nitride formed on the silicon oxide. The material of the bit line contact structure 104 may include doped polysilicon, other suitable conductive materials, or a combination thereof. In order to adjust the work function and the resistance value in a proper range, the material of the bit line contact structure 104 may be different from the material of the conductive structure 108 of the subsequently formed bit line structure. For example, the material of the bit line contact structure 104 can be doped polysilicon.

Next, a conductive structure 108 is formed on the insulating pattern 106 and the bit line contact structure 104 , and an insulating capping layer 110 is formed on the conductive structure 108 . Wherein, a plurality of insulating capping layers 110 are formed on the substrate 102 parallel to each other, and each insulating capping layer 110 extends along the first direction D1.

In some embodiments, the conductive structure 108 may be formed of a single material. In such an embodiment, the material of the conductive structure 108 may include tungsten, aluminum, copper, gold, silver, alloys thereof, or other suitable metal materials. In other embodiments, the conductive structure 108 includes a first conductive layer and a second conductive layer formed on the first conductive layer. In such an embodiment, the material of the first conductive layer may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or combinations thereof. The material of the second conductive layer may include tungsten, aluminum, copper, gold, silver, alloys of the above, other suitable metal materials, or combinations thereof. In this embodiment, the conductive structure 108 is formed of tungsten. The material of the insulating capping layer 110 may include oxide, nitride, oxynitride, other suitable insulating materials, or combinations thereof. In this embodiment, the insulating capping layer 110 is silicon nitride. The conductive structure 108 and the insulating capping layer 110 can be independently formed by chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, other suitable deposition processes, or a combination thereof.

Next, insulating spacers 112 are conformally formed on respective sidewalls of the bit line contact structure 104 , the insulating pattern 106 , the conductive structure 108 and the insulating capping layer 110 . In this specification, the conductive structure 108 , the insulating cap layer 110 and the insulating spacer 112 are collectively referred to as a bit line structure. In some embodiments, the first spacer layer 112 a , the second spacer layer 112 b and the third spacer layer 112 c may be sequentially formed to form the insulating spacer 112 . The first spacer layer 112a, the second spacer layer 112b, and the third spacer layer 112c can be independently formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a combination thereof, After the deposition process, any known etching process is used to form the insulating spacer 112 to expose the respective top surfaces of the substrate 102 and the insulating cap layer 110 . The first spacer layer 112a, the second spacer layer 112b, and the third spacer layer 112c may each independently include oxide, nitride, oxynitride, carbide, other suitable insulating materials, or combinations thereof.

In this embodiment, the first spacer layer 112a and the third spacer layer 112c are nitrides, and the second spacer layer 112b is oxide. In the manufacturing process of the insulating spacer 112 of this embodiment, because the removal rate of the second spacer layer 112b is relatively high, and the thickness of the third spacer layer 112c is relatively thin, therefore, the second spacer layer 112b and the second spacer layer 112b The top surface of the third spacer layer 112c is lower than the top surface of the first spacer layer 112a. In other embodiments, the top surface of the insulating spacer 112 is lower than the top surface of the insulating capping layer 110, that is, the insulating spacer 112 exposes the sidewall of the top of the insulating capping layer 110, and the insulating capping layer 110 has a rounded top surface. .

Please refer to FIG. 1 , FIG. 2A and FIG. 3 at the same time. After the insulating spacers 112 are formed, a plurality of first insulating structures 132 are formed on the substrate 102 . The first insulating structures 132 are formed parallel to each other on the substrate 102 , and each first insulating structure 132 extends along a second direction D2 crossing the first direction D1 . Thereby, a contact region 105 is defined between two adjacent insulating cap layers 110 and two adjacent first insulating structures 132 . In detail, a contact region 105 is defined between two insulating spacers 112 disposed on different insulating capping layers 110 and two adjacent first insulating structures 132 . Moreover, compared with the insulating cap layer 110 and the first insulating structure 132 , the contact region 105 at this time is a recessed region.

Next, a capacitive contact structure 119 electrically connected to the substrate 102 is formed in the contact region 105 , and the top surface of the capacitive contact structure 119 is lower than the top surface of the insulating cap layer 110 . In this embodiment, the capacitive contact structure 119 includes a first contact part 114 , a buffer layer 116 and a second contact part 118 sequentially formed on the substrate 102 . The step of forming the first contact part 114 includes, for example, forming a conductive material on the substrate 102 and etching back a portion of the conductive material to form the first contact part 114 in the contact region 105 . The material of the first contact member 114 may be the same or similar to that of the bit line contact structure 104 . In this embodiment, in order to adjust the work function and the resistance value within a proper range, the material of the first contact member 114 is doped polysilicon.

The top surface of the second contact part 118 is lower than the top surface of the insulating capping layer 110 . In this embodiment, the second contact part 118 includes a conductive lining layer 118a and a conductive layer 118b. The step of forming the second contact member 118 may include conformally forming a conductive liner material covering the buffer layer 116 in the contact region 105 . Next, a conductive material is formed on the conductive liner material. Afterwards, the conductive liner material and the conductive layer material are partially removed by an etch-back process. The material of the buffer layer 116 is, for example, metal silicide. The conductive liner material may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride or combinations thereof. The conductive layer material may include tungsten, aluminum, copper, gold, silver, alloys of the above, other suitable metal materials, or combinations thereof. Through the capacitive contact structure 119, the substrate 102 can be electrically connected to the subsequently formed capacitive structure 130 (shown in FIG. 2G).

Referring to FIG. 2B , a first material layer 120 with a non-uniform thickness is formed on the insulating cover layer 110 , the insulating spacer 112 and the capacitive contact structure 119 . The overhang portion 120 a of the first material layer 120 is formed on top of the insulating capping layer 110 . The tapered portion 120b of the first material layer 120 is formed on the sidewall of the insulating spacer 112 . A horizontal portion 120c of the first material layer 120 is formed on the top surface of the capacitive contact structure 119 . The maximum value of the thickness of the overhang portion 120a is greater than the maximum value of the thickness of the tapered portion 120b. In this embodiment, the first material layer 120 having the overhang portion 120 a can help to improve the yield, and this part will be discussed in detail below.

In one embodiment, in order to efficiently form the first material layer 120 with the overhang portion 120a, the first material layer 120 may be formed by a method with poor step coverage, for example, plasma-enhanced chemical vapor deposition. . In one embodiment, the first material layer 120 will not be completely removed in subsequent processes, and the remaining first material layer 120 becomes a part of the second insulating structure formed subsequently. The first material layer 120 may include a first insulating material, such as oxide, nitride, oxynitride, other suitable insulating materials, or a combination thereof. In this embodiment, the first material layer 120 includes oxide.

Referring to FIG. 2C , a first etching process is performed to partially remove the first material layer 120 and expose the top surface of the capacitive contact structure 119 . In more detail, after the first etching process, the horizontal portion 120c of the first material layer 120 is completely removed, and the top surface of the second contact part 118 is exposed. The first etching process may be an isotropic etching process, such as a wet etching process.

Referring to FIG. 2D , the first connection pad 122 is formed on the capacitive contact structure 119 , and the top surface of the first connection pad 122 is coplanar with the top surface of the insulating cover layer 110 . The step of forming the first connection pad 122 may include depositing a conductive material on the first material layer 120 and the capacitive contact structure 119 to fill up the contact region 105 . Afterwards, a planarization process is performed to make the top surfaces of the first material layer 120 , the top surface of the insulating capping layer 110 and the top surfaces of the first connection pads 122 coplanar. The conductive material may include tungsten, aluminum, copper, gold, silver, alloys of the above, other suitable metal materials, or combinations thereof. In this embodiment, the conductive material is tungsten.

Referring to FIG. 2E , a second etching process is performed to remove the first material layer 120 and form a recess 115 exposing the insulating spacer 112 . In this embodiment, the second etching process is to remove the overhang portion 120 a of the first material layer 120 , and the notch 115 further exposes the tapered portion 120 b of the first material layer 120 .

Referring to FIG. 2F , the recess 115 is filled with the second insulating material 124 , and the top surface of the second insulating material 124 , the top surface of the insulating cap layer 110 and the top surface of the first connection pad 122 are coplanar. In order to protect the first material layer 120 from being affected by the subsequent etching process, the second insulating material 124 may be different from the material of the first material layer 120 . The second insulating material 124 may include oxide, nitride or oxynitride. In this embodiment, the second insulating material 124 is nitride. The second insulating material 124 can be formed by a suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and combinations thereof.

Please refer to FIG. 1 and FIG. 2F at the same time. In this embodiment, the tapered portion 120 b of the first material layer 120 and the second insulating material 124 form a second insulating structure 140 surrounding the first connection pad 122 . The second insulating structure 140 is formed between the first connection pad 122 and the insulating capping layer 110 . The top width of the second insulating structure is larger than the bottom width. The second insulating structure 140 of this embodiment can help to improve the yield, which will be discussed in detail below.

Referring to FIG. 2G , after the second insulating structure 140 is formed, an interlayer dielectric layer 128 is formed on the substrate 102 . Next, a third etching process is performed on the interlayer dielectric layer 128 to form a plurality of openings exposing the first connection pads 122 . Capacitive structures 130 are then formed in these openings of the interlayer dielectric layer 128 . The capacitor structure 130 can be electrically connected to the capacitor contact structure 119 through the first connection pad 122 .

In this embodiment, the material of the interlayer dielectric layer 128 is different from that of the second insulating material 124, so that when the third etching process is performed, the removal rate of the interlayer dielectric layer 128 is much greater than that of the second insulating material 124. removal rate. In this way, the conductive material in the capacitor structure 130 can be prevented from being formed at the position originally intended to be filled in the second insulating structure 140 , thereby avoiding a short circuit. Furthermore, during the third etching process, the second insulating material 124 can prevent the etching solution from entering the substrate 102 through the tapered portion 120b and the second spacer layer 112b. In this way, the yield rate of the DRAM 100 can be further improved. In some embodiments, in the third etching process, the ratio R1/R2 of the removal rate R1 of the interlayer dielectric layer 128 to the removal rate R2 of the second insulating material 124 is 1.5-20. The material of the interlayer dielectric layer 128 may include oxide, nitride, oxynitride or a combination thereof. In this embodiment, the interlayer dielectric layer 128 is oxide.

The configuration range of the capacitor structure 130 may not completely overlap with the configuration range of the first connection pad 122 . In this embodiment, a capacitor structure 130 is disposed on the first connection pad 122 , the second insulating structure 140 and the insulating capping layer 110 . The capacitor structure 130 can be formed by known methods, which will not be described in detail here. After the capacitor structure 130 is formed, other conventional processes may be performed subsequently to complete the DRAM 100 . In order to simplify the description, other known manufacturing processes are not described in detail here.

Please refer to FIG. 1, FIG. 2G and FIG. 3 at the same time. The DRAM 100 of some embodiments of the present invention includes a substrate 102, a bit line contact structure 104, a bit line structure, a first insulating structure 132, a capacitor contact structure 119, The first connection pad 122 , the second insulating structure 140 and the capacitor structure 130 . The bit line structure includes a conductive structure 108 , an insulating cap layer 110 and an insulating spacer 112 .

The bit line contact structure 104 , the conductive structure 108 and the insulating capping layer 110 are sequentially formed on the substrate 102 . The bit line structure extends along the first direction D1. The first insulating structure 132 extends along a second direction D2 intersecting the first direction D1. The capacitive contact structure 119 , the first connection pad 122 and the second insulating structure 140 are located between two adjacent bit line structures and two adjacent first insulating structures 132 . Insulating spacers 112 are formed on respective sidewalls of the bit line contact structure 104 , the conductive structure 108 and the insulating capping layer 110 . The first connection pad 122 is formed on the capacitive contact structure 119 . Each second insulating structure 140 surrounds a first connection pad 122 . The top surface of the second insulating structure 140 is flush with the top surface of the first connection pad 122 , and the second insulating structure 140 has a width gradually narrowed downward. The capacitor structure 130 is formed on the first connection pad 122 and electrically connected to the first connection pad 122 . For other details about the DRAM 100 , reference can be made to the aforementioned description of the manufacturing method, and thus will not be repeated here.

In the DRAM 100 provided in this embodiment, by making the top of the first connection pad 122 narrower and disposing the second insulating structure 140 around the first connection pad 122, the risk of short circuit can be reduced, and the conductive structure 108 can also be reduced. and the parasitic capacitance between the first connection pad 122 . Therefore, the writing speed can be increased and the performance and yield can be improved.

In some embodiments, the second insulating structure 140 includes a first portion and a second portion. The first portion extends upward from the top surface of the capacitive contact structure 119 with a gradually wider width. The second portion extends downward from the top surface of the first connection pad 122 and has a narrower width. In the embodiment shown in FIG. 2F , the first portion of the second insulating structure 140 includes the first material layer 120 , and the second portion of the second insulating structure 140 includes the second insulating material 124 .

As shown in FIG. 2F, the top surface of the second insulating structure 140 has a first width W1. There is a maximum distance W2 between the surface of the first portion of the second insulating structure 140 and the surface of the third spacer layer 112c. The top surface of the insulating capping layer 110 has a sixth width W6. In this embodiment, the distance between the top portions of two adjacent first connection pads 122 is the sixth width W6 plus twice the first width W1 plus twice the thickness W7 of the first spacer layer 112a ( That is, W6+2*W1+2*W7). In some embodiments, the ratio W1/W2 of the first width W1 to the maximum distance W2 is 1.5-10.0. Thereby, an appropriate distance can be provided between the tops of two adjacent first connection pads 122, a suitable contact impedance can be provided between the first connection pads 122 and the capacitive structure 130, and the contact resistance between the conductive structure 108 and the second connection pad can be reduced. A parasitic capacitance between the connection pads 122 can improve yield and performance.

Furthermore, in some other embodiments, before forming the capacitor structure 130 , a second connection pad (not shown) electrically connected to the first connection pad 122 may be formed on the first connection pad 122 . In such an embodiment, the second connection pads and the first connection pads 122 may be dislocated. By forming the second portion of the second insulating structure 140 described in this embodiment, it is possible to effectively prevent one second connection pad from being electrically connected to two adjacent first connection pads 122 at the same time, thereby reducing the risk of short circuit. , thereby improving performance and yield.

In this embodiment, the first connection pad 122 includes an upper portion 122a and a lower portion 122b. Since the first connection pad 122 is in contact with the second insulating structure 140 and surrounded by the second insulating structure 140, the upper portion 122a of the first connection pad 122 has a width gradually narrowed upward, and the lower portion 122b of the first connection pad 122 It also has a width that tapers upwards. Furthermore, the width of the bottom surface of the first connection pad 122 may be smaller than or equal to the width of the top surface of the capacitive contact structure 119 . The width W5 of the bottom surface of the first connection pad 122 may be greater than the width W4 of the top surface of the first connection pad 122 . With the first connection pads 122 of this embodiment, the contact resistance between the first connection pads 122 and the capacitive contact structure 119 can be avoided from being too large, and the risk of a short circuit between two adjacent first connection pads 122 can be reduced. . In this way, the performance and yield of the DRAM 100 can be further improved.

As shown in FIG. 2F, the first connection pad 122 has a third width W3 at the junction of the upper portion 122a and the lower portion 122b. The top surface of the first connection pad 122 has a width W4. In some embodiments, the ratio W3/W4 of the third width W3 to the width W4 is 1.1-2.5. In this way, the first connection pads 122 can have an appropriate resistance value, so that there is an appropriate distance between the tops of two adjacent first connection pads 122, and the formation of gaps in the first connection pads 122 can be avoided. Effectively improve yield and performance.

Please refer to FIG. 2A and FIG. 2B. In this embodiment, the conductive lining layer 118a can improve the adhesion between the conductive layer 118b and the third spacer layer 112c. Moreover, by forming the second insulating structure 140 On the second contact part 118, peeling or delamination of the conductive layer 118b can also be avoided.

In addition, in this embodiment, the adhesive force between the first connection pad 122 and the second contact member 118 is greater than the adhesion force between the first connection pad 122 and the second insulating structure 140 , and the bottom of the first connection pad 122 The width of the surface is less than or equal to the width of the top surface of the second contact member 118 . Thereby, peeling or delamination of the first connection pads 122 can be effectively avoided, and the yield of the DRAM 100 can be further improved.

As shown in FIG. 2F, the second insulating structure 140 has a first height H1. The total height of the first connection pad 122 and the second contact member 118 is a third height H3. In order to facilitate the formation of the overhang portion 120a of the first material layer 120 and avoid peeling or delamination of the conductive layer 118b, in some embodiments, after the etch-back process, the top surface of the second contact member 118 may be flush with or lower than the top surface of the second spacer layer 112b or the third spacer layer 112c. In addition, in some embodiments, the ratio H3/H1 of the third height H3 relative to the first height H1 is 1.5-5, thereby improving the yield.

In this embodiment, the first portion of the second insulating structure 140 (ie, the tapered portion 120 b of the first material layer 120 ) includes oxide, so as to reduce the parasitic capacitance between the conductive structure 108 and the first connection pad 122 . Moreover, the width of the first portion of the second insulating structure 140 may be smaller than the width of the second portion, so as to reduce the resistance value of the first connection pad 122 . In this way, performance can be further improved.

As shown in FIG. 2F, the second portion of the second insulating structure 140 has a minimum thickness H2. In order to effectively prevent the etchant of the third etching process from destroying the elements under the second part of the second insulating structure 140 (such as the second spacer layer 112b and the substrate 102 ), reduce the parasitic between the conductive structure 108 and the first connection pad 122 To facilitate miniaturization, in some embodiments, the ratio H1/H2 of the first height H1 to the minimum thickness H2 is 1.5-10.0.

The DRAM 200 shown in FIG. 4 is similar to the DRAM 100 shown in FIG. 2F , so the same reference numerals are used to denote the same components. The difference is that the first part of the second insulating structure 240 in FIG. 4 is formed by the air gap 126 . To simplify the description, the same components as those shown in FIG. 2F and their manufacturing steps are not described in detail here.

The second insulating structure 240 can be formed through the following process steps. In the second etching process, the first material layer 120 is completely removed, and an opening exposing the sidewall of the first connection pad 122 is formed, wherein the upper part of the opening is a recess 115 exposing the top of the insulating spacer 112 , the lower part is used to form the air gap 126 . After that, a second insulating material 124 is formed in the notch 115 . In this embodiment, the first material layer 120 is completely removed as a sacrificial layer.

In this embodiment, a method with poor step coverage (such as plasma enhanced chemical vapor deposition) can be selected to deposit the second insulating material 124, so that the second insulating material 124 is formed in the recess 115, and the air gap 126 is formed in the recess 115. under the second insulating material 124 .

In this embodiment, the first portion of the second insulating structure 240 includes the air gap 126 , and the second portion of the second insulating structure 240 includes the second insulating material 124 . Using the air gap 126 as the first portion further reduces the parasitic capacitance between the conductive structure 108 and the first connection pad 122 compared to the case where the first portion of the insulating structure is formed of oxide. In this way, performance can be further improved.

As shown in FIG. 4, the second insulating structure 240 has a first height H1. The second contact member 118 has a fourth height H4. In some embodiments, the ratio H1/H4 of the first height H1 to the fourth height H4 is 0.5-10.0, so as to avoid peeling or delamination of the second contact member 118 and facilitate the formation of the overhang of the first material layer 120. protruding portion 120a, thereby improving yield.

In this embodiment, the first material layer 120 may include oxides, nitrides, oxynitrides, carbon-based materials (eg, graphite or other carbides), polysilicon, or combinations thereof. Therefore, the process flexibility is high. In addition, in this embodiment, a material that is easier to form the overhang portion 120a can be selected, or a material that has a higher removal rate during the second etching process can be selected to make the first material layer 120, thus helping to shorten the length of the first material layer 120. manufacturing time and improved yield.

The DRAM 300 shown in FIG. 5 is similar to the DRAM 100 shown in FIG. 2F , so the same reference numerals are used to denote the same components. The difference is that the second insulating structure 340 in FIG. 5 is only formed by the first material layer 120 . To simplify the description, the same components as those shown in FIG. 2F and their manufacturing steps are not described in detail here.

In this embodiment, the second insulating structure 340 is formed through the steps shown in FIG. 2D. Therefore, after forming the structure shown in FIG. 2D, the steps described in FIG. 2E and FIG. 2F can be omitted, and the steps described in FIG. 2G can be directly performed, thereby simplifying the manufacturing process and reducing production time and cost. In this embodiment, the first material layer 120 is nitride. The material of the first material layer 120 is different from that of the interlayer dielectric layer, so that when the third etching process is performed, the removal rate of the interlayer dielectric layer is much greater than the removal rate of the second insulating structure 340 . In this way, the conductive material in the capacitor structure can be prevented from being formed at the position originally intended to be filled in the second insulating structure 340 , thereby avoiding a short circuit. Furthermore, during the third etching process, the second insulating structure 340 can prevent the etching solution from penetrating into the substrate 102 .

The DRAM 400 shown in FIG. 6 is similar to the DRAM 100 shown in FIG. 2F , so the same reference numerals are used to represent the same components. The difference is that the second insulating structure 440 shown in FIG. 6 includes a first part, a second part and the third part. The first portion extends upward from the top surface of the capacitive contact structure 119 . The second portion extends downward from the top surface of the first connection pad 122 . The third section is located between the first section and the second section. To simplify the description, the same components as those shown in FIG. 2F and their manufacturing steps are not described in detail here.

The second insulating structure 440 can be formed through the following process steps. After the structure shown in FIG. 2D is formed, a second etching process may be performed to partially remove the first material layer 120 and form the recess 115 exposing a part of the sidewall of the first connection pad 122 . After that, the second insulating material 124 is deposited in the notch 115 , and the second insulating material 124 does not fill the notch 115 . If a method with poor step coverage (for example, plasma enhanced chemical vapor deposition) is selected to deposit the second insulating material 124, the second insulating material 124 can be formed on the upper part of the recess 115, and an air gap 126 can be formed in the recess. Lower part of port 115. Thereby, an air gap 126 can be formed between the remaining first material layer 120b' and the second insulating material 124.

In this embodiment, the first portion of the second insulating structure 440 includes the remaining first material layer 120b'. The second portion of the second insulating structure 440 includes the second insulating material 124 . The third portion of the second insulating structure 440 includes the air gap 126 . The second insulating material 124 is different from the first material layer 120 . The first material layer 120 may include oxide, nitride, oxynitride, other suitable insulating materials or combinations thereof. The second insulating material 124 may include oxide, nitride, oxynitride, carbide or other suitable insulating materials. In this embodiment, the first material layer 120 is oxide, and the second insulating material 124 is nitride. In this embodiment, the first portion of the second insulating structure 440 is an oxide, and the third portion is an air gap. Therefore, the parasitic capacitance between the conductive structure 108 and the first connection pad 122 can be reduced, thereby improving the performance of the memory device.

To sum up, in the manufacturing method of the DRAM provided by the embodiment of the present invention, the first material layer with the overhang portion is formed to cover and cover the top portion of the insulating cap layer, so as to reduce the risk of short circuit of the memory device, and improve yield. Moreover, the second insulating structure surrounding the first connection pad includes low dielectric constant material to reduce the parasitic capacitance between the bit line and the first connection pad, and improve the performance of the memory device.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention, and anyone with ordinary knowledge in the technical field may make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100:DRAM 102: Substrate 104: Bit line contact structure 105: Contact area 106: Insulation pattern 108: Conductive structure 110: insulation cover 112: spacer layer 112a: first spacer layer 112b: second spacer layer 112c: the third spacer layer 114: first contact part 115: notch 116: buffer layer 118: the second contact part 118a: Conductive lining 118b: conductive layer 119: Capacitive contact structure 120: the first material layer 120a: overhanging part 120b: tapering part 120b': remaining first layer of material 120c: horizontal part 122: First connection pad 122a: upper part 122b: Lower part 124: second insulating material 126: air gap 128: interlayer dielectric layer 130:Capacitance structure 132: The first insulation structure 140: Second insulation structure 200:DRAM 240: second insulation structure 300:DRAM 340: second insulation structure 400:DRAM 440: second insulation structure H1: first height H2: minimum thickness H3: third height H4: fourth height W1: first width W2: maximum distance W3: third width W4: width W5: width W6: sixth width W7: Thickness

FIG. 1 is a schematic top view of a DRAM according to some embodiments of the present invention. FIG. 2A to FIG. 2G are cross-sectional schematic diagrams drawn along the section line AA' as shown in FIG. 1 at various stages of the manufacturing process of the DRAM according to an embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of a DRAM according to some embodiments of the present invention drawn along the section line BB' as shown in Fig. 1 . FIG. 4 is a schematic cross-sectional view of a DRAM according to another embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a DRAM according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a DRAM according to another embodiment of the present invention.

100: Dynamic Random Access Memory

102: Substrate

104: Bit line contact structure

106: Insulation pattern

108: Conductive structure

110: insulation cover

112: spacer layer

112a: first spacer layer

112b: second spacer layer

112c: the third spacer layer

114: first contact part

116: buffer layer

118: the second contact part

118a: Conductive lining

118b: conductive layer

119: Capacitive contact structure

120b: tapering part

122: First connection pad

122a: upper part

122b: Lower part

124: second insulating material

128: interlayer dielectric layer

130:Capacitance structure

140: Second insulation structure

Claims (16)

A dynamic random access memory comprising: A plurality of bit line contact structures formed on a substrate; a plurality of bit line structures formed on the bit line contact structures and extending along a first direction; a plurality of first insulating structures formed on the substrate and extending along a second direction intersecting with the first direction; a capacitive contact structure formed on the substrate and located between the adjacent bit line structures and the adjacent first insulating structures; a first connection pad formed on the capacitive contact structure; a second insulating structure surrounding the first connection pad, and the width of the top of the second insulating structure is greater than the width of the bottom; and A capacitor structure is formed on the first connection pad and electrically connected to the first connection pad. The DRAM according to claim 1, wherein a top surface of the second insulating structure is flush with a top surface of the first connection pad, and the second insulating structure comprises: a first portion extending upward from a top surface of the capacitive contact structure, wherein the first portion has a width gradually narrowing downward; and a second portion extending downward from the top surface of the first connection pad, wherein the second portion has a width gradually narrowing downward, wherein the top surface of the second insulating structure has a first width W1, Wherein there is a maximum distance W2 between the surface of the first portion of the second insulating structure and the sidewall surfaces of the bit line structures, and wherein the ratio (W1/W2) of the first width W1 to the maximum distance W2 is 1.5 -10.0. The DRAM according to claim 2, wherein the first portion includes a first insulating material, the second portion includes a second insulating material, and the second insulating material is different from the first insulating material. The dynamic random access memory of claim 2, wherein the first portion includes an air gap, and the second portion includes an insulating material. The DRAM according to claim 2, wherein the first part and the second part comprise the same insulating material. The dynamic random access memory of claim 2, wherein the second insulating structure has a first height H1, the second portion has a minimum thickness H2, and wherein the ratio of the first height H1 to the minimum thickness H2 (H1/H2) is 1.5-10.0. The DRAM according to claim 2, wherein the second insulating structure further includes a third portion between the first portion and the second portion, the first portion includes a first insulating material, and the second portion A second insulating material is included, the third portion includes an air gap, and the second insulating material is different from the first insulating material. Such as the dynamic random access memory of claim 1, wherein the bit line structures include: a conductive structure formed on the bit line contact structure; an insulating capping layer formed on the conductive structure; An insulating spacer is located between the conductive structure and the capacitive contact structure, and includes: a first spacer layer formed on a sidewall of the insulating capping layer and a sidewall of the conductive structure; a second spacer layer formed on the first spacer layer, wherein a top surface of the second spacer layer is lower than a top surface of the first spacer layer; and A third spacer layer is formed on the second spacer layer, wherein a top surface of the third spacer layer is lower than the top surface of the first spacer layer. The dynamic random access memory of claim 1, wherein a width of a bottom surface of the first connection pad is greater than a width of a top surface of the first connection pad, and a lower portion of the first connection pad is connected to an upper portion The ratio of the width of the junction to the width of the top surface of the first connection pad is 1.1-2.5. A method of manufacturing a dynamic random access memory, comprising: forming a plurality of bit line contact structures on a substrate; forming a plurality of bit line structures on the bit line contact structures, wherein each of the bit line structures extends along a first direction; forming a plurality of first insulating structures on the substrate, wherein each of the first insulating structures extends along a second direction intersecting with the first direction; forming a capacitive contact structure on the substrate, wherein the capacitive contact structure is located between the adjacent bit line structures and the adjacent first insulating structures; forming a first connection pad on the capacitive contact structure; forming a second insulating structure surrounding the first connection pad, wherein the width of the top of the second insulating structure is greater than the width of the bottom; and A capacitor structure is formed on the first connection pad and electrically connected to the first connection pad. The method for manufacturing a dynamic random access memory according to claim 10, wherein forming the second insulating structure and forming the first connection pad include: forming a first material layer with non-uniform thickness on the bit line structures and the capacitive contact structure, wherein the first material layer includes a first insulating material; performing a first etching process to partially remove the first material layer and expose a top surface of the capacitive contact structure; depositing a conductive material on the first material layer and the capacitive contact structure; performing a planarization process so that a top surface of the first material layer is coplanar with a top surface of the conductive material, wherein after the planarization process, the conductive material forms the first connection pad; performing a second etching process to remove a portion of the first material layer and form a recess adjacent to the first connection pad; and forming a second insulating material in the recess, wherein the second insulating material is different from the first insulating material, Wherein a top surface of the second insulating structure is flush with a top surface of the first connection pad. The method for manufacturing a dynamic random access memory according to claim 11, wherein a protrusion portion of the first material layer is removed by the first etching process to form the notch. The method for manufacturing a dynamic random access memory according to claim 11, wherein the second insulating material fills the notch, and the remaining first material layer and the second insulating material form the second insulating structure. The manufacturing method of dynamic random access memory according to claim 11, wherein the second insulating material does not completely fill the notch, and an air gap is formed in the notch and is located between the first material layer and the second insulating material Between, and wherein the remaining first material layer, the second insulating material and the air gap form the second insulating structure. The method for manufacturing a dynamic random access memory according to claim 10, wherein forming the second insulating structure and forming the first connection pad include: forming a first material layer with non-uniform thickness on the bit line structures and the capacitive contact structure; performing a first etching process to partially remove the first material layer and expose a top surface of the capacitive contact structure; depositing a conductive material on the first material layer and the capacitive contact structure; performing a planarization process so that a top surface of the first material layer is coplanar with a top surface of the conductive material; After the planarization process, the conductive material forms the first connection pad, and the first connection pad is in direct contact with the capacitive contact structure; performing a second etching process to completely remove the first material layer and form an opening exposing the sidewall of the first connection pad; and The second insulating structure is formed in the opening, wherein the material of the second insulating structure is different from that of the first material layer. The manufacturing method of DRAM according to claim 15, wherein forming the second insulating structure in the opening includes forming an insulating material, and the insulating material does not completely fill the opening, and forms an air gap in the opening The opening is located under the insulating material, and wherein the insulating material and the air gap form the second insulating structure.

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