CN111785718B - Dynamic random access memory and manufacturing method thereof - Google Patents

Abstract

The invention provides a dynamic random access memory and a manufacturing method thereof. The dynamic random access memory comprises an embedded bit line, a plurality of embedded word lines, a bit line contact structure and a conductive plug. The embedded bit line is formed in the substrate. The bottom surface of the buried word line is higher than the top surface of the buried bit line. The bit line contact structure is formed on the embedded bit line and has a through hole. The bit line contact structure is not in direct contact with the embedded bit line. The material of the bit line contact structure is different from that of the embedded bit line. The conductive plug is formed between the bit line contact structure and the embedded bit line and fills the through hole. The buried bit line is electrically connected to the bit line contact structure through the conductive plug. The invention can obviously improve the efficiency and the yield of the memory device.

Description

Dynamic random access memory and manufacturing method thereof

Technical Field

The present invention relates to a memory device, and more particularly, to a dynamic random access memory having a buried bit line and a method for fabricating the same.

Background

As Dynamic Random Access Memories (DRAMs) are increasingly miniaturized, the distance between a bit line and an adjacent capacitor contact structure is reduced, which makes short circuits between the bit line and the adjacent capacitor contact structure easy to occur. Furthermore, if the parasitic capacitance between the bit line and the adjacent capacitive contact structure is too large, the value of the corresponding stored data will be difficult to distinguish. Thus, the efficiency and yield of the product are reduced.

To reduce parasitic capacitance, one known DRAM proposes to reduce the height (or thickness) of the bitlines, and another known DRAM proposes to reduce the length of the bitlines. However, the former causes the resistance of the bit line to increase, which is detrimental to the operation of the memory device and reduces performance. In addition, the latter reduces the number of bits corresponding to each bit line, which results in an increase in chip area, and is not favorable for miniaturization of the memory device.

Therefore, there is still a need in the art for a miniaturized DRAM with high performance and high yield and a method for forming the same.

Disclosure of Invention

Embodiments of the present invention provide a DRAM and a method for manufacturing the same, which can reduce parasitic capacitance between a bit line and an adjacent capacitor contact structure, and facilitate reduction of a resistance value of the bit line and miniaturization of the DRAM.

An embodiment of the present invention discloses a DRAM, comprising: a buried bit line formed in the substrate, wherein the buried bit line extends along a first direction; a plurality of embedded word lines formed in the substrate, wherein the embedded word lines are parallel to each other and extend along a second direction crossing the first direction, and bottom surfaces of the embedded word lines are higher than top surfaces of the embedded bit lines; a bit line contact structure formed in the substrate, wherein the bit line contact structure is located on the embedded bit line and has a through hole, the bit line contact structure is not in direct contact with the embedded bit line, and a material of the bit line contact structure is different from a material of the embedded bit line; a conductive plug formed between the bit line contact structure and the embedded bit line and filling the through hole, wherein the embedded bit line is electrically connected to the bit line contact structure through the conductive plug; and a capacitor structure formed on the substrate and located between two adjacent embedded word lines.

An embodiment of the present invention discloses a method for manufacturing a DRAM, comprising: forming a buried bit line in a substrate, wherein the buried bit line extends along a first direction; forming a plurality of embedded word lines in the substrate, wherein the embedded word lines are parallel to each other and extend along a second direction crossing the first direction, and a bottom surface of the embedded word lines is higher than a top surface of the embedded bit lines; forming a bit line contact structure on the embedded bit line and having a through hole, wherein the bit line contact structure is not in direct contact with the embedded bit line, and the material of the bit line contact structure is different from that of the embedded bit line; forming a conductive plug between the bit line contact structure and the embedded bit line, wherein the conductive plug fills the through hole, and the embedded bit line is electrically connected to the bit line contact structure through the conductive plug; and forming a capacitor structure on the substrate, wherein the capacitor structure is located between two adjacent embedded word lines.

In the DRAM provided by the embodiments of the present invention, the bit lines are buried in the substrate, so that the distance between the bit lines and the adjacent capacitor contact structures can be increased. Therefore, the parasitic capacitance can be reduced. Furthermore, since the bit line is buried in the substrate, the resistance value of the bit line can be reduced by increasing the thickness (or depth) of the bit line. According to the DRAM provided by the embodiment of the invention, even if the thickness of the bit line is increased, the parasitic capacitance is not increased. Therefore, the efficiency and yield of the memory device can be obviously improved.

Drawings

FIGS. 1A to 1G are schematic cross-sectional views illustrating steps of manufacturing a DRAM according to some embodiments of the present invention.

FIG. 2 is a top view of a DRAM according to some embodiments of the present invention.

Fig. 3A to 3C are schematic cross-sectional views of different conductive plugs according to other embodiments of the invention.

Fig. 4A to 4C are schematic cross-sectional views illustrating steps of manufacturing a conductive plug according to other embodiments of the present invention.

Fig. 5A to 5C are schematic cross-sectional views illustrating steps of manufacturing a conductive plug according to other embodiments of the present invention.

Reference numerals

100 DRAM 106 insulating layer

102 to substrate 112 to first insulating liner layer

104 isolation structure 114 buried bit line

114a, first liner 154, and conductive plug

114b to first conductive layer 154a to second liner layer

115 buried bit line trench 154b second conductive layer

118 to first insulating layer 154x to first portion

122-second insulating liner 154 y-second portion

124 buried word lines 154z third portions

124a to second liner 155 to perforation

124 b-second conductive layer 156-conductive liner layer

125 buried word line trench 158 insulating layer

128-second insulation layer 160-capacitor contact structure

130 mask layer 170 capacitor structure

132-bit line contact structure 132D-distance

132' to conductive material layer T to thickness

134 to insulating spacer Wa to second pitch

135 to the first opening Wc to the first distance

142-drain doped regions W1, W3, W5, W7-first width

144-source doped regions W2, W4, W6, W8-second width

145 to second opening

Detailed Description

In order to make the objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Fig. 1A to fig. 1G are schematic cross-sectional views corresponding to steps of a method for manufacturing a DRAM100 according to some embodiments of the invention. Referring to fig. 1A, a plurality of isolation structures 104 are formed in a substrate 102, and an insulating layer 106 is formed to cover the substrate 102 and the isolation structures 104. The material of the substrate 102 may include silicon, a silicon-containing semiconductor, a silicon-on-insulator (SOI), or a combination thereof. In the present embodiment, the substrate 102 is a silicon substrate. In some embodiments, other structures may be formed in the substrate 102, such as p/n type wells or conductive regions (not shown) formed in the substrate 102 by an implantation process. In the present embodiment, the Isolation structure 104 is a Shallow Trench Isolation (Shallow Trench Isolation).

Next, the buried bit lines 114 are formed in the substrate 102. In detail, a mask layer (not shown) may be formed to cover the substrate 102 and the insulating layer 106, and the mask layer, the substrate 102 and the insulating layer 106 are patterned to form the buried bit line trench 115 in the substrate 102. Then, a first insulating liner 112 and a first liner material are sequentially and conformally formed in the buried bit line trench 115. Next, the first conductive material is filled in the buried bit line trench 115. Then, a portion of the first liner layer material and the first conductive material are removed by an etch-back process to form a first liner layer 114a and a first conductive layer 114b. In this specification, the first liner layer 114a and the first conductive layer 114b are collectively referred to as a "buried bit line 114". Next, an insulating material is filled in the buried bit line trench 115 to form a first insulating layer 118.

Next, the buried word line 124 is formed in the substrate 102. In detail, a mask layer (not shown) may be formed to cover the substrate 102 and the insulating layer 106, and the mask layer, the substrate 102 and the insulating layer 106 are patterned to form the buried word line trench 125 in the substrate 102. Then, a second insulating liner 122 and a second liner material are sequentially and conformally formed in the buried word line trench 125. Next, the second conductive material is filled in the buried word line trench 125. Then, a portion of the second liner material and the second conductive material are removed by an etch-back process to form a second liner layer 124a and a second conductive layer 124b. In this specification, the second liner layer 124a and the second conductive layer 124b are collectively referred to as "embedded word lines 124". Next, an insulating material is filled in the buried word line trench 125 to form a second insulating layer 128.

The materials of the first insulating liner 112, the first insulating layer 118, the second insulating liner 122, and the second insulating layer 128 may be selected from oxides, nitrides, oxynitrides, carbides, other suitable insulating materials, or combinations thereof. The material of the first insulating layer 118 is different from the material of the insulating layer 106 and the first insulating liner layer 112. The material of the second insulating liner 122 is different from the material of the second insulating layer 128. The first and second liner materials may be selected from titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or combinations thereof. The first conductive material and the second conductive material may be selected from tungsten, aluminum, copper, gold, silver, alloys thereof, other suitable metal materials, or combinations thereof. In the present embodiment, the material of the first insulating layer 118 and the second insulating liner layer 122 is silicon oxide; the insulating layer 106, the first insulating liner 112 and the second insulating layer 128 are made of silicon nitride; the first lining layer material and the second lining layer material are titanium nitride; the first conductive material and the second conductive material are tungsten.

Referring to fig. 1B, a mask layer 130 is formed to cover the substrate 102, the insulating layer 106, the first insulating layer 118 and the second insulating layer 128. The opening of the mask layer 130 exposes the first insulating layer 118 and the insulating layer 106 around the first insulating layer, that is, the opening of the mask layer 130 is larger than the opening of the buried bit line trench 115. Next, the first insulating layer 118 is partially removed by an anisotropic etching process to form a first opening 135 over the first insulating layer 118. In this anisotropic etching process, the etching rate of the first insulating layer 118 is much greater than that of the insulating layer 106. As such, the first opening 135 may be formed in the blb trench 115 in a self-aligned manner.

In addition, since the first insulating liner 112 is conformally formed in the buried bit line trench 115, it is easily removed in the anisotropic etching process. In some embodiments, an additional etch may be performed as needed to ensure removal of the first insulating liner 112. Wherein the thickness of the first insulating liner layer 112 is smaller than that of the insulating layer 106. For example, the thickness of the insulating layer 106 is at least three times the thickness of the first insulating liner layer 112.

Referring to fig. 1C, the first opening 135 is filled with a conductive material layer 132', and the conductive material layer 132' is etched back to make the top surface of the conductive material layer 132' lower than the top surface of the insulating layer 106. The material of the conductive material layer 132' may be different from that of the buried bit line 114. The material of the conductive material layer 132' may comprise doped polysilicon. In the present embodiment, the material of the conductive material layer 132' is polysilicon doped with arsenic. In the present embodiment, the dopant in the conductive material layer 132' may be diffused into the substrate 102 by the high temperature of the process to form the doped drain region 142. In other embodiments, the drain doping region 142 may be formed by an implantation process.

Next, an insulating spacer 134 is formed on the sidewall of the first opening 135, and the insulating spacer 134 defines a second opening 145. The top width of the second opening 145 is greater than the bottom width of the second opening 145. The material of the insulating spacers 134 may include an oxide, nitride, oxynitride, carbide, or a combination thereof. In the present embodiment, the insulating spacer 134 is silicon nitride formed by chemical vapor deposition.

Referring to fig. 1D, a first etching process is performed to form a through hole 155 extending through the conductive material layer 132' and into the first insulating layer 118. In this embodiment, the first etching process is an anisotropic dry etching process. Furthermore, in the first etching process, the etching rate of the first insulating layer 118 or the etching rate of the conductive material layer 132' is much greater than that of the insulating spacers 134. Accordingly, the insulating spacers 134 may serve as an etch mask to protect the underlying conductive material layer 132' from being removed. In other words, the through holes 155 may be formed in a self-aligned manner at positions corresponding to the second openings 145. Therefore, the process can be greatly simplified, and the time and cost required by production can be reduced. In a subsequent step, the buried bit line 114 may be electrically connected to the drain doping region 142 through the conductive material layer 132'. Therefore, in this specification, the conductive material layer 132' having the through holes 155 is also referred to as a "bit line contact structure 132".

Referring to fig. 1E, after the first etching process, a second etching process is performed to completely remove the first insulating layer 118 and expose the buried bit lines 114. The second etching process may include an isotropic etching process, an anisotropic etching process, or a combination thereof. In this embodiment, the second etching process is an isotropic wet etching process. Furthermore, in the second etching process, the etching rate of the first insulating layer 118 is much greater than that of the insulating spacers 134 or that of the conductive material layer 132'. Accordingly, the portion of the via 155 under the bit line contact structure 132 is widened.

Referring to fig. 1F, the second opening 145 and the through hole 155 are filled with a conductive material. Then, a portion of the conductive material is etched back to form conductive plug 154. The top surface of the conductive plug 154 is lower than the top surface of the insulating layer 106. The conductive plug 154 directly contacts the buried bit line 114. Accordingly, the buried bit line 114 may be electrically connected to the bit line contact structure 132 through the conductive plug 154. The conductive material with better hole-filling capability can be selected as the material of the conductive plug 154 to reduce or eliminate the void in the conductive plug 154, thereby reducing the resistance of the conductive plug 154 or avoiding open circuit, and further improving the performance of the DRAM 100. The material of the conductive plug 154 may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or combinations thereof. In the present embodiment, the material of the conductive plug 154 is titanium nitride. In addition, the top surface of the conductive plug 154 is higher than the top surface of the bit line contact structure 132 to ensure that the bit line contact structure 132 is not damaged when the conductive material is etched back. Thus, the bit line contact structure 132 is prevented from being broken, and the yield of the DRAM100 is improved.

Referring to fig. 1G, the insulating layer 106 between the embedded word line 124 and the isolation structure 104 is removed, and a conductive material is deposited to form a capacitor contact structure 160 on the substrate 102. Next, an insulating layer 158 is formed to cover the substrate 102. The insulating layer 158 is patterned to form a plurality of capacitor structures 170 in the insulating layer 158. The material of the insulating layer 158 may include an oxide, a nitride, an oxynitride, or a combination thereof. The material of the capacitive contact structure 160 may include doped crystalline silicon, doped polysilicon, doped amorphous silicon, or a combination thereof. In the present embodiment, the material of the insulating layer 158 is silicon oxide, and the material of the capacitor contact structure 160 is polysilicon doped with arsenic. In the present embodiment, the dopant in the capacitor contact structure 160 may be diffused into the substrate 102 by the high temperature of the process to form the source doping region 144. In other embodiments, the source doping region 144 may be formed by an implantation process. Thereafter, other known processes may be performed to complete the DRAM100, which will not be described in detail herein.

In the method for manufacturing the DRAM of the present embodiment, the buried bit lines 114 are formed first, and then the buried word lines 124 are formed. Therefore, the thickness of the embedded bit line 114 can be adjusted as needed without affecting the embedded word line 124. The resistance of the buried bit line 114 is lower as the thickness is larger, thereby improving the performance of the DRAM 100. In addition, since the buried bit line 114 and the capacitor contact structure 160 are respectively located above and below the substrate 102, even if the thickness of the buried bit line 114 is increased, the parasitic capacitance between the buried bit line 114 and the capacitor contact structure 160 is not increased, and the performance and the yield of the DRAM100 can be significantly improved.

FIG. 2 is a top view of a DRAM100 according to some embodiments of the present invention. FIG. 1G is a schematic cross-sectional view taken along section line AA in FIG. 2. Referring to fig. 1G and fig. 2, the dram100 includes a plurality of buried word lines 124 and buried bit lines 114 formed in a substrate 102, and a bottom surface of the buried word lines 124 is higher than a top surface of the buried bit lines 114. The buried bit lines 114 extend along a first direction. The buried word lines 124 are parallel to each other and extend along a second direction crossing the first direction. In the present embodiment, the first direction is substantially perpendicular to the second direction. DRAM100 includes bitline contact structure 132 formed in a substrate and having a via 155. The bit line contact structure 132 is located on the buried bit line 114 and does not directly contact the buried bit line 114. The bit line contact structure 132 is made of a material different from that of the buried bit line 114. In some embodiments, the buried bit line 114 includes a first liner layer 114a and a first conductive layer 114b, and the material of the bit line contact structure 132 is different from the material of the first liner layer 114a and also different from the material of the first conductive layer 114b. The DRAM100 includes a conductive plug 154 formed between the bit line contact structure 132 and the buried bit line 114 and filling the via 115. In some embodiments, the material of the conductive plug 154 is different from that of the bit line contact structure 132, and the material of the conductive plug 154 is also different from that of the first conductive layer 114b of the buried bit line 114. The buried bit line 114 is electrically connected to the bit line contact structure 132 through a conductive plug 154. The DRAM100 includes a capacitor structure 170 formed on the substrate 102 and between two adjacent buried word lines 124.

In some embodiments, the bit line contact structure 132 is spaced apart from the buried bit line 114 by a distance D, and the distance D is smaller than the thickness T of the buried bit line 114. Thereby, the resistance of the buried bit line 114 can be reduced. Furthermore, the buried bit line 114 is located at a depth D below the bit line contact structure 132, and the buried word line 124 is located between the buried bit line 114 and the bit line contact structure 132, so that a distance is maintained between the buried bit line 114 and the capacitor contact structure 160. Therefore, even if the thickness T of the buried bit line 114 is increased, the parasitic capacitance between the buried bit line 114 and the capacitor contact structure 160 is small.

In the present embodiment, the conductive plug 154 includes a first portion, a second portion, and a third portion. A first portion of the conductive plug 154 extends upward from the top surface of the buried bit line 114 and has a first width W1. A second portion of conductive plug 154 extends downward from the top surface of bit line contact structure 132 and abuts the first portion. The second portion of the conductive plug 154 has a second width W2, and the second width W2 is smaller than the first width W1. A third portion of the conductive plug 154 extends upward from the top surface of the bit line contact structure 132, and has a width gradually narrowing downward. In this embodiment, by arranging the first portion to be wider, the resistance value of the conductive plug 154 can be reduced. Furthermore, as described above, by disposing the third portion of the conductive plug 154, it can be ensured that the bit line contact structure 132 is not damaged when the conductive material is etched back. In other embodiments, the conductive plug 154 includes only a first portion and a second portion. In other words, the top surface of the conductive plug 154 is coplanar with the top surface of the bit line contact structure 132.

Referring to fig. 1C, in the present embodiment, the DRAM100 includes an isolation structure 104, a buried bit line trench 115, and a buried word line trench 125 (shown in fig. 1A) formed in a substrate 102. A portion of the buried word line trench 125 (e.g., the second buried word line trench 125 on the left in fig. 1C) is located between the isolation structure 104 and the buried bit line trench 115. The buried bit line 114 is formed in the buried bit line trench 115, and the buried word line 124 is formed in the buried word line trench 125. The isolation structure 104 is spaced apart from the adjacent buried word line trench 125 by a first distance Wc, and the buried bit line trench 115 is spaced apart from the buried word line trench 125 by a second distance Wa. The first pitch Wc is greater than the second pitch Wa. Referring to fig. 1G, the dopants in the doped drain region 142 and the doped source region 144 are from the bit line contact structure 132 and the capacitor contact structure 160, respectively. Because the bit line contact structure 132 has a smaller volume, the dopant content in the bit line contact structure 132 is less. Therefore, if the second distance Wa is smaller than the first distance Wc, the resistance of the doped drain region 142 can be made to be similar to the resistance of the doped source region 144, which is advantageous for the operation of the DRAM.

Fig. 3A to 3C are schematic cross-sectional views of different conductive plugs 154 according to other embodiments of the present invention. For simplicity, fig. 3A to 3C only show the elements located in the buried bit line trench 115, and other elements of the DRAM100 may be the same as those in fig. 1G and are omitted. In fig. 3A to 3C, the same elements as those shown in fig. 1G are denoted by the same reference numerals. For simplicity, the same elements and steps as those shown in fig. 1G and their formation process steps will not be described in detail.

The conductive plug 154 shown in fig. 3A is similar to the conductive plug 154 shown in fig. 1G, except that the conductive plug 154 of fig. 3A includes a second liner 154a and a second conductive layer 154b. The second liner 154a is in direct contact with the buried bit line 114, and the second liner 154a is formed on the surface of the through hole 155 of the bit line contact structure 132. After the structure shown in fig. 1E is formed, a second liner 154a may be conformally formed on the surfaces of the through holes 155 and the second openings 145. Then, the through hole 155 and the second opening 145 are filled with the second conductive layer 154b. Portions of the second liner layer 154a and the second conductive layer 154b are etched back to form the conductive plug 154 shown in FIG. 3A.

In the embodiment shown in fig. 3A, the second liner layer 154a has better filling capability, and the second liner layer 154a has better adhesion with the bit line contact structure 132. Therefore, the second liner 154a can be conformally formed on the surface of the through hole 155, and the adhesion between the second conductive layer 154b and the bit line contact structure 132 can be improved. Further, the second conductive layer 154b is preferably conductive. Therefore, the resistance of the conductive plug 154 can be reduced, thereby improving the performance of the DRAM 100. The material of the second liner 154a may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, or a combination thereof. The material of the second conductive layer 154b may include tungsten, aluminum, copper, gold, silver, alloys thereof, or combinations thereof. In the present embodiment, the material of the second liner layer 154a is titanium nitride, and the material of the second conductive layer 154b is tungsten.

The difference between the conductive plugs 154 shown in fig. 3B and fig. 1G is that in fig. 3B, a first insulating layer 118 surrounding the conductive plugs 154 is included between the bit line contact structures 132 and the buried bit lines 114. After the structure shown in fig. 1D is formed, the first etching process may be continued until the top surface of the first conductive layer 114b is exposed. Then, the through hole 155 and the second opening 145 are filled with a conductive material having a better hole-filling capability without performing the second etching process. Then, an etch back process is performed to form the conductive plug 154 as shown in fig. 3B.

In the present embodiment, the conductive plug 154 includes a first portion 154x, a second portion 154y, and a third portion 154z. The first portion 154x extends upward from the top surface of the buried bit line 114 and has a first width W3. The second portion 154y extends downward from the top surface of the bit line contact structure 132 and abuts the first portion. The second portion of the conductive plug 154 has a second width W4, and the second width W4 is substantially equal to the first width W3. The third portion 154z extends upward from the top surface of the bit line contact structure 132 and has a width that gradually narrows downward.

In the present embodiment, the lower portion of the through hole 155 is not widened, so that the void generated in the conductive plug 154 can be reduced or eliminated, thereby improving the yield of the DRAM 100. Furthermore, in the present embodiment, the second etching process is not required, so that the process can be simplified. Furthermore, the etching solution of the second etching process can be prevented from remaining in the DRAM100, and the risk of damaging other devices can be reduced. In other embodiments, the second width W4 is less than the first width W3.

The conductive plug 154 shown in fig. 3C is similar to the conductive plug 154 shown in fig. 3B, except that the conductive plug 154 shown in fig. 3C includes a second liner 154a and a second conductive layer 154B. In the present embodiment, the second conductive layer 154b has better conductivity than the second liner layer 154 a. Therefore, the resistance of the conductive plug 154 can be reduced, thereby improving the performance of the DRAM 100.

Fig. 4A to 4C are schematic cross-sectional views illustrating steps of manufacturing a conductive plug according to other embodiments of the present invention. To simplify the drawings, fig. 4A to 4C only show the elements located in the buried bit line trench, and other elements of the DRAM100 may be the same as those in fig. 1G and omitted. In fig. 4A to 4C, the same elements as those shown in fig. 1G are denoted by the same reference numerals. For simplicity, the same elements and steps as those shown in fig. 1G and their formation process steps will not be described in detail.

Referring to fig. 4A, after the structure shown in fig. 1D is formed, a conductive liner 156 is conformally formed on the surfaces of the through hole 155 and the second opening 145. Referring to fig. 4B, a second etching process is performed to remove the conductive liner 156 at the bottom of the via 155 and a portion of the first insulating layer 118, and expose the buried bit line 114. Then, the through hole 155 and the second opening 145 are filled with a conductive material having a better hole filling capability. A portion of the conductive liner 156 and the conductive material are then etched back to form the conductive plug 154 as shown in fig. 4C.

The material of the conductive liner 156 and the conductive plug 154 may be selected from titanium, titanium nitride, tungsten nitride, tantalum nitride, or a combination thereof. In the present embodiment, the conductive liner 156 and the conductive plug 154 are made of titanium nitride, so the process is simplified. In the present embodiment, since the materials of the conductive liner 156 and the conductive plug 154 are the same, the conductive liner 156 is considered as a part of the conductive plug 154. In other embodiments, the conductive plug 154 includes a second liner layer 154a and a second conductive layer 154b. The second etching process may include an isotropic etching process, an anisotropic etching process, or a combination thereof. In this embodiment, the second etching process is an anisotropic dry etching process.

Referring to fig. 4C, in the present embodiment, the conductive plug 154 includes a first portion 154x, a second portion 154y and a third portion 154z. The first portion 154x extends upward from the top surface of the buried bit line 114 and has a first width W5. The second portion 154y extends downward from the top surface of the bit line contact structure 132 and abuts the first portion. The second portion of the conductive plug 154 has a second width W6 (i.e., the combined width of the conductive liner 156 and the conductive plug 154), and the second width W6 is greater than the first width W5. The third portion 154z extends upward from the top surface of the bit line contact structure 132 and has a width that gradually narrows downward.

In the present embodiment, when the second etching process is performed, the conductive liner 156 covers the sidewalls of the bit line contact structure 132, thereby ensuring that the bit line contact structure 132 is not damaged by the second etching process (e.g., lateral etching). Furthermore, in the present embodiment, the second etching process is a dry etching process, so that the etching solution can be prevented from remaining in the DRAM 100. In addition, in the present embodiment, the lower portion of the through hole 155 is not widened, and thus, voids generated in the conductive plug 154 may be reduced or eliminated. By the above improvement, the yield of the DRAM100 can be further improved.

Fig. 5A to 5C are schematic cross-sectional views illustrating steps of manufacturing a conductive plug according to other embodiments of the present invention. To simplify the drawings, fig. 5A to 5C only show the elements located in the buried bit line trench, and other elements of the DRAM100 may be the same as those in fig. 1G and omitted. In fig. 5A to 5C, the same elements as those shown in fig. 1G are denoted by the same reference numerals. For simplicity, the elements and their formation steps that are the same as those shown in fig. 1G will not be described in detail.

Referring to fig. 5A, after the structure shown in fig. 1D is formed, a conductive liner 156 is conformally formed on the surfaces of the through hole 155 and the second opening 145. Referring to fig. 5B, a second etching process is performed to remove the conductive liner 156 at the bottom of the via 155 and a portion of the first insulating layer 118, and expose the buried bit line 114. Then, the through hole 155 and the second opening 145 are filled with a conductive material having a better hole filling capability. A portion of the conductive liner 156 and the conductive material are then etched back to form the conductive plug 154 as shown in fig. 5C.

In the present embodiment, the conductive liner layer 156 and the conductive plug 154 are made of titanium nitride, and therefore, the conductive liner layer 156 is regarded as a portion of the conductive plug 154. In other embodiments, the conductive plug 154 includes a second liner 154a and a second conductive layer 154b. The second etching process may include an isotropic etching process, an anisotropic etching process, or a combination thereof. In this embodiment, the second etching process is an isotropic wet etching process.

Referring to fig. 5C, the first insulating layer 118 is not completely removed, and the first insulating layer 118 located between the bit line contact structure 132 and the buried bit line 114 surrounds the conductive plug 154. In the present embodiment, the conductive plug 154 includes a first portion 154x, a second portion 154y, and a third portion 154z. The first portion 154x extends upward from the top surface of the buried bit line 114, and a sidewall of the first portion 154x protrudes toward the first insulating layer 118. The maximum width of the first portion 154x is defined as a first width W7. The second portion 154y extends downward from the top surface of the bit line contact structure 132 and is adjacent to the first portion. The second portion of the conductive plug 154 has a second width W8 (i.e., the combined width of the conductive liner 156 and the conductive plug 154), and the second width W8 is less than the first width W7. The third portion 154z extends upward from the top surface of the bit line contact structure 132, and has a width that gradually narrows downward. In the present embodiment, the lower portion of the through hole 155 is widened, so that the resistance of the conductive plug 154 can be reduced, thereby improving the performance of the DRAM 100.

In summary, in the method for manufacturing a DRAM according to the embodiments of the present invention, the thickness of the embedded bit line can be increased as required to reduce the resistance thereof. Therefore, the performance of the DRAM can be improved. Moreover, because the embedded bit line and the capacitor contact structure are respectively positioned above and below the substrate, the parasitic capacitance between the embedded bit line and the capacitor contact structure can be reduced. Therefore, the performance and yield of the DRAM can be greatly improved. In addition, the through holes can be formed on the bit line contact structure in a self-aligned manner, so that the process can be greatly simplified, and the time and the cost required by production can be reduced.

Although the present invention has been described with reference to a few preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (18)

1. A dynamic random access memory, comprising:

a buried bit line formed in a substrate, wherein the buried bit line extends along a first direction;

a plurality of embedded word lines formed in the substrate, wherein the plurality of embedded word lines are parallel to each other and extend along a second direction crossing the first direction, and bottom surfaces of the plurality of embedded word lines are higher than a top surface of the embedded bit line;

a bit line contact structure formed in the substrate, wherein the bit line contact structure is located on the embedded bit line and has a through hole, the bit line contact structure is not in direct contact with the embedded bit line, and the material of the bit line contact structure is different from that of the embedded bit line;

a conductive plug formed between the bit line contact structure and the embedded bit line and filling the via hole, wherein the embedded bit line is electrically connected to the bit line contact structure through the conductive plug; and

and the capacitor structure is formed on the substrate and is positioned between the two adjacent embedded word lines.

2. The dram of claim 1, wherein the bit line contact structure is spaced apart from the buried bit line by a distance that is less than a thickness of the buried bit line.

3. The dram of claim 1 wherein the buried bit line comprises a first liner and a first conductive layer, wherein the first conductive layer comprises a first conductive material, and wherein the bit line contact structure comprises a second conductive material different from the first conductive material.

4. The dynamic random access memory of claim 3 wherein the conductive plug is formed of a third conductive material, and the third conductive material is different from the first conductive material and the second conductive material.

5. The dram of claim 1, further comprising an insulating layer formed between the bit line contact structure and the buried bit line and surrounding the conductive plug.

6. The dynamic random access memory of claim 5, wherein the conductive plug comprises:

a first portion extending upward from the top surface of the buried bit line, wherein the first portion has a first width; and

a second portion extending downward from a top surface of the bit line contact structure and adjacent to the first portion, wherein the second portion has a second width greater than the first width.

7. The dynamic random access memory of claim 1, wherein the conductive plug comprises:

a first portion extending upward from the top surface of the buried bit line, wherein the first portion has a first width; and

a second portion extending downward from a top surface of the bit line contact structure and adjacent to the first portion, wherein the second portion has a second width, and wherein the second width is equal to or less than the first width.

8. The dram of claim 7, further comprising an insulating layer formed between the bit line contact structure and the buried bit line and surrounding the conductive plug, wherein a sidewall of the first portion of the conductive plug protrudes toward the insulating layer.

9. The dynamic random access memory according to claim 3, wherein the conductive plug comprises a second liner layer and a second conductive layer, wherein the second liner layer is in direct contact with the embedded bit line, and the second liner layer is formed on the surface of the through hole of the bit line contact structure.

10. The dynamic random access memory of claim 1, wherein a top surface of the conductive plug is higher than a top surface of the bit line contact structure.

11. The dynamic random access memory of claim 1, further comprising:

an isolation structure formed in the substrate;

a plurality of buried word line trenches formed in the substrate, wherein the plurality of buried word lines are formed in the buried word line trenches;

a buried bit line trench formed in the substrate, wherein the buried bit line is formed in the buried bit line trench;

a portion of each embedded word line trench is located between the isolation structure and the embedded bit line trench, and the isolation structure is spaced apart from the portion of the embedded word line trench by a first distance.

12. A method of fabricating a dynamic random access memory, comprising:

forming an embedded bit line in a substrate, wherein the embedded bit line extends along a first direction;

forming a plurality of embedded word lines in the substrate, wherein the plurality of embedded word lines are parallel to each other and extend along a second direction crossing the first direction, and bottom surfaces of the plurality of embedded word lines are higher than a top surface of the embedded bit line;

forming a bit line contact structure on the embedded bit line and having a through hole, wherein the bit line contact structure is not in direct contact with the embedded bit line, and the material of the bit line contact structure is different from that of the embedded bit line;

forming a conductive plug between the bit line contact structure and the embedded bit line, wherein the conductive plug fills the through hole, and the embedded bit line is electrically connected to the bit line contact structure through the conductive plug; and

and forming a capacitor structure on the substrate, wherein the capacitor structure is located between two adjacent embedded word lines.

13. The method of claim 12, wherein forming the bit line contact structure comprises:

forming an insulating layer on the embedded bit line;

forming a conductive material layer on the insulating layer; and

a first etching process is performed to form the through hole in the conductive material layer, wherein the through hole penetrates through the conductive material layer and extends into the insulating layer.

14. The method of claim 13, further comprising:

after the first etching process, performing a second etching process to completely remove the insulating layer and expose the embedded bit line; and

filling a second conductive material into the through hole to form the conductive plug.

15. The method of claim 13, further comprising:

filling a second conductive material into the through hole to form the conductive plug,

wherein the via exposes a portion of the top surface of the buried bit line, and the insulating layer surrounds the conductive plug.

16. The method of claim 13, further comprising:

conformably forming a conductive liner in the via after the first etching process;

performing a second etching process to remove the conductive liner layer at the bottom of the via hole and a portion of the insulating layer and expose the top surface of the embedded bit line; and

filling a second conductive material into the through hole to form the conductive plug.

17. The method as claimed in claim 16, wherein the second etching process is an anisotropic etching process.

18. The method as claimed in claim 16, wherein the second etching process is an isotropic etching process.

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