TW202247730A - Multilayer circuit board and method for manufacturing the same - Google Patents
Multilayer circuit board and method for manufacturing the same Download PDFInfo
- Publication number
- TW202247730A TW202247730A TW110119744A TW110119744A TW202247730A TW 202247730 A TW202247730 A TW 202247730A TW 110119744 A TW110119744 A TW 110119744A TW 110119744 A TW110119744 A TW 110119744A TW 202247730 A TW202247730 A TW 202247730A
- Authority
- TW
- Taiwan
- Prior art keywords
- groove
- circuit board
- conductive
- blind hole
- insulating layer
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本發明涉及線路板製造技術領域,尤其涉及一種多層線路板及其製造方法。The invention relates to the technical field of circuit board manufacturing, in particular to a multilayer circuit board and a manufacturing method thereof.
多層線路板(一般指3層及3層以上)大多採用導電材料塞孔的方式實現任意層互連,可有效降低線路板的製作難度,縮短線路板的製作流程,而且更環保,因此該技術具有廣闊的發展前景。Multi-layer circuit boards (generally referring to 3 layers and above) mostly use conductive materials to plug holes to realize any layer interconnection, which can effectively reduce the difficulty of making circuit boards, shorten the production process of circuit boards, and is more environmentally friendly. Therefore, this technology Has broad development prospects.
目前,常用的導電材料為導電膏,導電膏是一種固化或乾燥後具有一定導電性能的膠黏劑,通常以基體樹脂和導電粒子為主要成分,藉由基體樹脂的黏接作用把導電粒子結合在一起,形成導電通路。但是在實際高溫層壓過程中導電膏容易溢出,造成層內孔間短路,嚴重影響線路板的品質。At present, the commonly used conductive material is conductive paste. Conductive paste is an adhesive with certain conductive properties after curing or drying. It usually uses matrix resin and conductive particles as the main components. The conductive particles are combined by the bonding effect of the matrix resin. Together, a conductive path is formed. However, in the actual high-temperature lamination process, the conductive paste is easy to overflow, causing a short circuit between holes in the layer, which seriously affects the quality of the circuit board.
有鑑於此,為克服上述缺陷的至少之一,有必要提供一種線路板的製造方法。In view of this, in order to overcome at least one of the above defects, it is necessary to provide a method for manufacturing a circuit board.
還有必要提供一種採用上述線路板的製造方法製造的線路板。It is also necessary to provide a circuit board manufactured by the above method for manufacturing a circuit board.
本發明提供了一種多層線路板的製造方法,該方法包括:The invention provides a method for manufacturing a multilayer circuit board, the method comprising:
提供至少一第一線路板,所述第一線路板包括疊設的第一絕緣層以及第一導電線路層,所述第一絕緣層中設有第一盲孔以及位於所述第一盲孔周圍的至少一第一凹槽,所述第一盲孔內設有與所述第一導電線路層電性連接的第一導電膏塊,所述第一導電膏塊凸伸出所述第一絕緣層。At least one first circuit board is provided, the first circuit board includes a stacked first insulating layer and a first conductive circuit layer, the first insulating layer is provided with a first blind hole and a At least one first groove around the first blind hole, a first conductive paste block electrically connected to the first conductive circuit layer is provided in the first blind hole, and the first conductive paste block protrudes out of the first Insulation.
提供至少一第二線路板,所述第二線路板包括疊設的第二絕緣層以及第二導電線路層,所述第二絕緣層中設有第二盲孔以及位於所述第二盲孔周圍的至少一第二凹槽,所述第二盲孔內設有與所述第二導電線路層電性連接的第二導電膏塊,所述第二導電膏塊凸伸出所述第二絕緣層。At least one second circuit board is provided, the second circuit board includes a stacked second insulating layer and a second conductive circuit layer, a second blind hole is provided in the second insulating layer and a second blind hole is located in the second blind hole At least one second groove around the second blind hole, a second conductive paste block electrically connected to the second conductive circuit layer is provided in the second blind hole, and the second conductive paste block protrudes out of the second Insulation.
層疊至少一所述第一線路板和至少一所述第二線路板,得到一中間體。Stacking at least one first circuit board and at least one second circuit board to obtain an intermediate body.
以及,壓合所述中間體,以使所述第一導電膏塊和所述第二導電膏塊分別填充於所述第一凹槽和所述第二凹槽中,其中,位於所述第一盲孔內的所述第一導電膏塊形成第一導電部,位於所述第一凹槽中的第一導電膏塊形成第一溢出部,位於所述第二盲孔內的所述第二導電膏塊形成第二導電部,位於所述第二凹槽中的第二導電膏塊形成第二溢出部,從而得到所述多層線路板。And, pressing the intermediate body so that the first conductive paste block and the second conductive paste block are respectively filled in the first groove and the second groove, wherein the The first conductive paste block in a blind hole forms a first conductive portion, the first conductive paste block in the first groove forms a first overflow portion, and the first conductive paste block in the second blind hole forms a first overflow portion. Two conductive paste blocks form the second conductive portion, and the second conductive paste block located in the second groove forms the second overflow portion, thereby obtaining the multilayer circuit board.
本申請實施方式中,所述第一線路板的製作包括:In the implementation manner of the present application, the making of the first circuit board includes:
提供一第一線路基板,所述第一線路基板包括疊設的所述第一絕緣層以及所述第一導電線路層。A first circuit substrate is provided, and the first circuit substrate includes the first insulating layer and the first conductive circuit layer stacked.
於所述第一絕緣層上形成第一剝離膜。A first release film is formed on the first insulating layer.
貫穿所述第一絕緣層開設至少一所述第一盲孔,所述第一盲孔還貫穿所述第一剝離膜,所述第一盲孔的直徑自所述第一剝離膜至所述第一絕緣層的方向逐漸減小。At least one first blind hole is opened through the first insulating layer, the first blind hole also passes through the first peeling film, and the diameter of the first blind hole is from the first peeling film to the The direction of the first insulating layer gradually decreases.
於每一所述第一盲孔中填充導電膏得到所述第一導電膏塊,其中,所述第一導電膏塊包括遠離所述第一導電線路層的第一端面。Filling conductive paste into each of the first blind holes to obtain the first conductive paste block, wherein the first conductive paste block includes a first end surface away from the first conductive circuit layer.
於所述第一端面周圍的所述第一絕緣層開設至少一第一凹槽,所述第一凹槽貫穿所述第一剝離膜。At least one first groove is defined in the first insulating layer around the first end surface, and the first groove penetrates through the first peeling film.
以及,去除所述第一剝離膜,使得所述第一端面凸伸出所述第一絕緣層,從而得到所述第一線路板。And, removing the first peeling film, so that the first end surface protrudes from the first insulating layer, so as to obtain the first circuit board.
本申請實施方式中,所述第二線路板的製作包括:In the implementation manner of the present application, the production of the second circuit board includes:
提供一第二線路基板,所述第二線路基板包括疊設的所述第二絕緣層以及所述第二導電線路層。A second circuit substrate is provided, and the second circuit substrate includes the second insulating layer and the second conductive circuit layer stacked.
於所述第二絕緣層上形成第二剝離膜。A second release film is formed on the second insulating layer.
貫穿所述第二絕緣層開設至少一所述第二盲孔,所述第二盲孔還貫穿所述第二剝離膜,所述第二盲孔的直徑自所述第二剝離膜至所述第二絕緣層的方向逐漸減小。At least one second blind hole is opened through the second insulating layer, the second blind hole also passes through the second peeling film, and the diameter of the second blind hole is from the second peeling film to the The direction of the second insulating layer gradually decreases.
於每一所述第二盲孔中填充導電膏得到所述第二導電膏塊,其中,所述第二導電膏塊包括遠離所述第二導電線路層的第二端面。Filling conductive paste into each of the second blind holes to obtain the second conductive paste block, wherein the second conductive paste block includes a second end surface away from the second conductive circuit layer.
於所述第二端面周圍的所述第二絕緣層開設至少一第二凹槽,所述第二凹槽貫穿所述第二剝離膜。At least one second groove is provided on the second insulating layer around the second end surface, and the second groove penetrates through the second peeling film.
以及,去除所述第二剝離膜,使得所述第二端面凸伸出所述第二絕緣層,從而得到所述第二線路板。And, removing the second peeling film, so that the second end surface protrudes from the second insulating layer, so as to obtain the second circuit board.
本申請實施方式中,所述第一凹槽為環形凹槽,所述第一凹槽環繞所述第一導電膏塊;和/或所述第二凹槽為環形凹槽,所述第二凹槽環繞所述第二導電膏塊。In the embodiment of the present application, the first groove is an annular groove, and the first groove surrounds the first conductive paste block; and/or the second groove is an annular groove, and the second The groove surrounds the second conductive paste block.
本申請實施方式中,所述第一凹槽的數量為多個,多個所述第一凹槽同心設置,多個所述第一凹槽的深度沿遠離所述第一盲孔的方向依次增大或依次減小;和/或,所述第二凹槽的數量為多個,多個所述第二凹槽同心設置,多個所述第二凹槽的深度沿遠離所述第二盲孔的方向依次增大或依次減小。In the embodiment of the present application, the number of the first grooves is multiple, the multiple first grooves are arranged concentrically, and the depths of the multiple first grooves are sequentially along the direction away from the first blind hole increase or decrease sequentially; and/or, the number of the second grooves is multiple, the multiple second grooves are arranged concentrically, and the depths of the multiple second grooves are along the distance away from the second grooves. The direction of blind holes increases or decreases sequentially.
本申請實施方式中,所述第一凹槽的數量為多個,每一個所述第一凹槽的橫截面為矩形、圓形以及梯形中的至少一種;和/或所述第二凹槽的數量為多個,每一個所述第二凹槽的橫截面為矩形、圓形以及梯形中的至少一種。In the embodiment of the present application, the number of the first grooves is multiple, and the cross section of each of the first grooves is at least one of rectangle, circle and trapezoid; and/or the second groove The number is multiple, and the cross section of each second groove is at least one of rectangle, circle and trapezoid.
本申請實施方式中,壓合步驟後,所述第一導電膏塊和所述第二導電膏塊均呈梯型。In the implementation manner of the present application, after the pressing step, both the first conductive paste block and the second conductive paste block are trapezoidal.
本發明還提供一種多層線路板,該多層線路板包括:至少一第一線路板和至少一第二線路板。所述第一線路板包括疊設的第一絕緣層以及第一導電線路層,所述第一絕緣層中設有第一盲孔以及位於所述第一盲孔周圍的至少一第一凹槽,所述第一盲孔內設有第一導電部,所述第一凹槽內設有第一溢出部,所述第一導電部與所述第一導電線路層電性連接。所述第二線路板包括疊設的第二絕緣層以及第二導電線路層,所述第二絕緣層中設有第二盲孔以及位於所述第二盲孔周圍的至少一第二凹槽,所述第二盲孔內設有第二導電部,所述第二凹槽內設有第二溢出部,所述第二導電部與所述第二導電線路層電性連接。The present invention also provides a multilayer circuit board, which includes: at least one first circuit board and at least one second circuit board. The first circuit board includes a stacked first insulating layer and a first conductive circuit layer, the first insulating layer is provided with a first blind hole and at least one first groove around the first blind hole , a first conductive portion is disposed in the first blind hole, a first overflow portion is disposed in the first groove, and the first conductive portion is electrically connected to the first conductive circuit layer. The second circuit board includes a stacked second insulating layer and a second conductive circuit layer, and the second insulating layer is provided with a second blind hole and at least one second groove around the second blind hole , the second blind hole is provided with a second conductive part, the second groove is provided with a second overflow part, and the second conductive part is electrically connected with the second conductive circuit layer.
本申請實施方式中,所述第一凹槽為環形凹槽,所述第一凹槽環繞所述第一導電膏塊;和/或所述第二凹槽為環形凹槽,所述第二凹槽環繞所述第二導電膏塊。In the embodiment of the present application, the first groove is an annular groove, and the first groove surrounds the first conductive paste block; and/or the second groove is an annular groove, and the second The groove surrounds the second conductive paste block.
本申請實施方式中,所述第一凹槽的數量為多個,多個所述第一凹槽同心設置,多個所述第一凹槽的深度沿遠離所述第一盲孔的方向依次增大或依次減小;和/或所述第二凹槽的數量為多個,多個所述第二凹槽同心設置,多個所述第二凹槽的深度沿遠離所述第二盲孔的方向依次增大或依次減小。In the embodiment of the present application, the number of the first grooves is multiple, the multiple first grooves are arranged concentrically, and the depths of the multiple first grooves are sequentially along the direction away from the first blind hole increase or decrease sequentially; and/or the number of the second grooves is multiple, the multiple second grooves are arranged concentrically, and the depth of the multiple second grooves is along the distance from the second blind The direction of the holes increases or decreases sequentially.
本申請實施方式中,所述第一凹槽的數量為多個,每一個所述第一凹槽的橫截面為矩形、圓形以及梯形中的至少一種;和/或所述第二凹槽的數量為多個,每一個所述第二凹槽的橫截面為矩形、圓形以及梯形中的至少一種。In the embodiment of the present application, the number of the first grooves is multiple, and the cross section of each of the first grooves is at least one of rectangle, circle and trapezoid; and/or the second groove The number is multiple, and the cross section of each second groove is at least one of rectangle, circle and trapezoid.
相較於習知技術,本發明提供的多層線路板的製備方法藉由在第一盲孔和第二盲孔的周圍分別設置第一凹槽和第二凹槽,當第一線路板和第二線路板在壓合過程中,使凸出第一絕緣層是第一導電膏塊和凸出第二絕緣層的第二導電膏塊分別溢流填充進第一凹槽和第二凹槽內,第一凹槽和第二凹槽能夠限制導電膏的流動,可以避免導電膏溢出面積過大與周邊線路連接導致短路的問題或溢出的銅膏與上下兩層銅層形成電容的現象。再者,能夠增加所述第一導電膏塊與所述第一絕緣層的接觸面積、以及所述第二導電膏塊與所述第二絕緣層的接觸面積,進而分別增加了所述第一導電膏塊與所述第一絕緣層的附著力、以及所述第二導電膏塊與所述第二絕緣層的附著力,降低了所述第一導電膏塊以及所述第二導電膏塊受冷熱處理的影響,從而提高了所述多層線路板的信賴性。Compared with the prior art, the preparation method of the multilayer circuit board provided by the present invention is by setting the first groove and the second groove around the first blind hole and the second blind hole respectively, when the first circuit board and the second blind hole During the pressing process of the two circuit boards, the first conductive paste block protruding from the first insulating layer and the second conductive paste block protruding from the second insulating layer are overflow-filled into the first groove and the second groove respectively , the first groove and the second groove can limit the flow of conductive paste, which can avoid the problem of short circuit caused by excessive overflow area of conductive paste and connection with peripheral lines, or the phenomenon that the overflowed copper paste forms capacitance with the upper and lower copper layers. Furthermore, the contact area between the first conductive paste block and the first insulating layer and the contact area between the second conductive paste block and the second insulating layer can be increased, thereby increasing the first The adhesion between the conductive paste block and the first insulating layer, and the adhesion between the second conductive paste block and the second insulating layer, reduce the thickness of the first conductive paste block and the second conductive paste block. Affected by cold and heat treatment, the reliability of the multilayer circuit board is improved.
下面將結合本發明實施例中的附圖,對本發明實施例中的技術方案進行清楚、完整地描述,顯然,所描述的實施例僅僅是本發明一部分實施例,而不是全部的實施例。基於本發明中的實施例,本領域普通技術人員在沒有作出創造性勞動前提下所獲得的所有其他實施例,都屬於本發明保護的範圍。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
除非另有定義,本文所使用的所有的技術和科學術語與屬於本發明的技術領域的技術人員通常理解的含義相同。本文中在本發明的說明書中所使用的術語只是為了描述具體的實施例的目的,不是旨在於限制本發明。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention.
為能進一步闡述本發明達成預定目的所採取的技術手段及功效,以下結合附圖及較佳實施方式,對本發明作出如下詳細說明。In order to further explain the technical means and effects adopted by the present invention to achieve the intended purpose, the present invention will be described in detail below in conjunction with the accompanying drawings and preferred embodiments.
本發明較佳實施例提供一種多層線路板的製造方法,包括如下步驟:A preferred embodiment of the present invention provides a method for manufacturing a multilayer circuit board, comprising the following steps:
步驟S1,請參閱圖1,提供至少一第一線路基板10以及至少一第二線路基板20。Step S1 , please refer to FIG. 1 , providing at least one
本實施方式中,所述第一線路基板10包括層疊設置的一第一絕緣層101以及一第一導電線路層102,所述第一導電線路層102形成於所述第一絕緣層101的表面。所述第二線路基板20包括層疊設置的一第二絕緣層201以及一第二導電線路層202,所述第二導電線路層202內埋於所述第二絕緣層201。其中,所述第二導電線路層202包括多個連接墊2021。在本實施方式中,提供兩個所述第一線路基板10以及兩個所述第二線路基板20。In this embodiment, the
所述第一絕緣層101以及所述第二絕緣層201的材質均可以選自環氧樹脂(epoxy resin)、半固化片(Prepreg,PP)、BT樹脂、聚苯醚(Polyphenylene Oxide,PPO)、聚醯亞胺(polyimide,PI)、聚對苯二甲酸乙二醇酯(Polyethylene Terephthalate,PET)以及聚萘二甲酸乙二醇酯(Polyethylene Naphthalate,PEN)等樹脂中的一種。在本實施方式中,所述第一絕緣層101以及所述第二絕緣層201的材質均為半固化片。The material of the first
本實施方式中,所述第一絕緣層101以及所述第二絕緣層201的厚度T均為5~150微米。In this embodiment, the thickness T of the first
步驟S2,分別在所述第一絕緣層101以及所述第二絕緣層201上形成一第一剝離膜30以及一第二剝離膜40。Step S2 , forming a
本實施方式中,所述第一剝離膜30和所述第二剝離膜40的厚度均為25微米左右。In this embodiment, the thicknesses of the
本實施方式中,所述第一剝離膜30和所述第二剝離膜40均為PET膜。In this embodiment, both the
步驟S3,請參閱圖2,在所述第一線路基板10中開設貫穿所述第一絕緣層101的第一盲孔50,所述第一盲孔50還貫穿所述第一剝離膜30,在所述第二線路基板20中開設貫穿所述第二絕緣層201的第二盲孔51,所述第二盲孔51還貫穿所述第二剝離膜40。Step S3, please refer to FIG. 2 , opening a first
其中,所述第一盲孔50的直徑的大小自所述第一剝離膜30至所述第一絕緣層101的方向逐漸減小,所述第二盲孔51的直徑的大小自所述第二剝離膜40至所述第二絕緣層201的方向逐漸減小。Wherein, the diameter of the first
所述第一盲孔50遠離所述第一導電線路層102一端的半徑(即所述第一盲孔50的最大半徑)與所述第二盲孔51遠離所述第二導電線路層202一端的半徑(即所述第二盲孔51的最大半徑)大致相同。如圖9所示,定義盲孔的所述半徑為R,所述半徑R均為50~150微米。The radius of the end of the first
本實施方式中,所述半徑R大致為100微米。In this embodiment, the radius R is approximately 100 microns.
本實施方式中,所述第一盲孔50以及所述第二盲孔51均藉由鐳射打孔的方式形成。In this embodiment, both the first
步驟S4,請參閱圖3,分別在每一所述第一盲孔50以及每一所述第二盲孔51中填充導電膏,經固化,得到分別與所述第一導電線路層102以及所述第二導電線路層202電性連接的第一導電膏塊60以及第二導電膏塊61。Step S4, please refer to FIG. 3 , fill conductive paste in each of the first
其中,所述第一導電膏塊60包括遠離所述第一導電線路層102的第一端面601,所述第二導電膏塊61包括遠離所述第二導電線路層202的第二端面611。Wherein, the first
本實施方式中,所述第一導電膏塊60和所述第二導電膏塊61均為梯形體。In this embodiment, both the first
本實施方式中,所述導電膏可為錫膏或銅膏等。具體地,所述導電膏為錫膏。In this embodiment, the conductive paste may be solder paste or copper paste. Specifically, the conductive paste is solder paste.
步驟S5,請參閱圖4,於所述第一端面601周圍的所述第一絕緣層101開設第一凹槽70,所述第一凹槽70貫穿所述第一剝離膜30;於所述第二端面611周圍的所述第二絕緣層201開設第二凹槽71,所述第二凹槽71貫穿所述第二剝離膜40。Step S5, please refer to FIG. 4 , a
所述第一端面601沿所述第一線路基板10的厚度方向在所述第一絕緣層101的投影區域周圍的所述第一絕緣層101形成第一溢出區域A,所述第一凹槽70位於所述第一溢出區域A;所述第二端面611沿所述第二線路基板20的厚度方向在所述第二絕緣層201的投影區域周圍的所述第二絕緣層201形成第二溢出區域B,所述第二凹槽71位於所述第二溢出區域B。本實施方式中,僅在所述第一溢出區域A和所述第二溢出區域B藉由鐳射打孔的方式分別去除部分第一絕緣層101和部分第二絕緣層201,從而形成第一凹槽70和第二凹槽71,鐳射打孔的第一絕緣層101材料單一,工藝簡單,時效性好,對位要求低,對鐳射打孔設備要求低。The
請參閱圖4至圖8,本發明中所述第一凹槽70和所述第二凹槽71的形狀、開口大小、深度、排列方式以及凹槽與凹槽之間的間距可以根據實際需要具體設計。Referring to Fig. 4 to Fig. 8, the shape, opening size, depth, arrangement and spacing between the
請參閱圖4與圖5,本實施方式中,所述第一凹槽70可以為環形凹槽,所述第一凹槽70環繞所述第一導電膏塊60。所述第二凹槽71可以為環形凹槽,所述第二凹槽71環繞所述第二導電膏塊61。Referring to FIG. 4 and FIG. 5 , in this embodiment, the
請再次參閱圖4與圖5,本實施方式中,所述第一凹槽70的數量為多個,多個所述第一凹槽70同心設置,多個所述第一凹槽70的深度沿遠離所述第一端面601的方向依次減小。所述第二凹槽71的數量可以為多個,多個所述第二凹槽71同心設置,多個所述第二凹槽71的深度沿遠離所述第二端面611的方向依次減小。Please refer to FIG. 4 and FIG. 5 again. In this embodiment, the number of the
請參閱圖6,另一實施方式中,所述第一凹槽70的數量為多個,多個所述第一凹槽70同心設置,多個所述第一凹槽70的深度沿遠離所述第一端面601的方向依次增大。所述第二凹槽71的數量可以為多個,多個所述第二凹槽71同心設置,多個所述第二凹槽71的深度沿遠離所述第二端面611的方向依次增大。可以理解的是,不同深度的第一凹槽70也可以無規律排布,不同深度的第二凹槽71也可以無規律排布,相鄰兩個所述第一凹槽70之間的間距以及所述第二凹槽71之間的間距可以根據實際需要設計。Please refer to FIG. 6 , in another embodiment, the number of the
請參閱圖7與圖8,又一實施方式中,所述第一凹槽72的數量為多個,每一個所述第一凹槽72的橫截面可以為矩形、圓形以及梯形中的至少一種,多個第一凹槽72可以散佈在所述第一溢出區域A內,多個第一凹槽72圍繞第一導電膏塊60設置。本實施方式中,所述第二凹槽73的數量也可以為多個,每一個所述第二凹槽73的橫截面可以為矩形、圓形以及梯形中的至少一種,多個第二凹槽73可以散佈在所述第二溢出區域B內,多個第二凹槽73圍繞第二導電膏塊61設置。本實施方式中,藉由將第一凹槽72和第二凹槽73設計成尺寸較小的槽,而且槽的尺寸和形狀沒有特殊的要求,精度要求低,成型方便。Please refer to FIG. 7 and FIG. 8 , in yet another embodiment, the number of the
步驟S6,請參閱圖9,分別去除所述第一剝離膜30和所述第二剝離膜40,使得所述第一端面601和所述第二端面611分別凸伸於所述第一絕緣層101和所述第二絕緣層201,得到第一線路板80以及第二線路板81。Step S6, please refer to FIG. 9 , remove the
步驟S7,層疊至少一所述第一線路板80和至少一所述第二線路板81,得到一中間體(圖未示)。Step S7, stacking at least one
本實施方式中,依次層疊一個所述第一線路板80、兩個所述第二線路板81以及一個所述第一線路板80。具體地,其中一個所述第一線路板80中的所述第一端面601與其中一個所述第二線路板81中的所述第二端面611一一對應,另一個所述第一線路板80中的所述第一端面601與另一個所述第二線路板81中的連接墊2021一一對應。In this embodiment, one
步驟S8,請參閱圖10,壓合所述中間體,以使所述第一導電膏塊60和所述第二導電膏塊61分別填充於所述第一凹槽70和所述第二凹槽71中,其中,位於所述第一盲孔內的所述第一導電膏塊60形成第一導電部90,位於所述第一凹槽70中的第一導電膏塊60形成第一溢出部91,位於所述第二盲孔內的所述第二導電膏塊61形成第二導電部92,位於所述第二凹槽71中的第二導電膏塊61形成第二溢出部93,從而得到所述多層線路板100。Step S8, please refer to FIG. 10 , pressing the intermediate body so that the first
本實施方式中,在壓合步驟後,凸伸出所述第一絕緣層101的部分所述第一導電膏塊60和凸伸出所述第二絕緣層201的部分所述第二導電膏塊61分別被擠壓填充於所述第一凹槽70和所述第二凹槽71中,其中,位於所述第一盲孔內的第一導電部90與位於所述第一凹槽70中的第一溢出部91連接,位於所述第二盲孔內的第二導電部92與位於所述第二凹槽71中的第二溢出部93連接。In this embodiment, after the pressing step, the part of the first
本實施方式中,其中一個所述第一線路板80中的第一導電部90與其中一個所述第二線路板81中的所述第二導電部92相互黏結以電性連接所述第一導電線路層102和所述第二導電線路層202,另一個所述第二線路板81中的所述第二導電部92與其中一個所述第二導電線路層202的所述連接墊2021相互黏結以電性連接兩個所述第二導電線路層202,另一個所述第一線路板80中的所述第一導電部90與另一個所述第二導電線路層202的所述連接墊2021相互黏結以電性連接所述第一導電線路層102和所述第二導電線路層202。In this embodiment, the first
請參閱圖10,結合參閱圖3,本實施方式中,所述第一端面601的半徑r大致與所述第一盲孔50的所述半徑相等,大致為100微米,第一導電膏塊60凸伸出第一絕緣層101的部分厚度H與PET的厚度相等,大致為25μm。第二盲孔51和第二導電膏塊61的結構尺寸與第一盲孔50和第一導電膏塊60大致相同。因此,所述第一導電膏塊60凸伸出所述第一絕緣層101部分的體積V和所述第二導電膏塊61凸伸出所述第二絕緣層201部分的體積V大致相等,V=PET的厚度*第一端面601或第二端面611的面積=25μm*3.14*100μm*100μm =785000 μm
3。當第一導電膏塊60和第二導電膏塊61對疊壓合時,凸出的銅膏總體積V總:2*V=2*785000=1570000μm
3,假設沒有第一凹槽70和第二凹槽71時,溢流出銅膏厚度在8~10μm,此時,銅膏溢出範圍為R溢,則V總=3.14*R溢
2,則可以推導出銅膏溢出範圍約為707μm,銅膏溢出邊緣距離盲孔邊緣之間的最大距離大約是607μm,在這個範圍內,溢出的銅膏很容易與周圍線路連接造成短路,或溢出的銅膏與上下兩層銅層形成電容的現象。
Please refer to FIG. 10 , and refer to FIG. 3 . In this embodiment, the radius r of the
本發明藉由在第一盲孔50和第二盲孔51的周圍分別製作出一第一凹槽70和第二凹槽71,當第一線路板80和第二線路板81在壓合過程中,使凸出第一絕緣層101是第一導電膏塊60和凸出第二絕緣層201的第二導電膏塊61分別溢流填充進第一凹槽70和第二凹槽71內,可以避免導電膏溢出面積過大與周邊線路連接導致短路的問題或溢出的銅膏與上下兩層銅層形成電容的現象。The present invention makes a
請參閱圖10,本發明一實施例還提供一種多層線路板100,所述多層線路板100包括至少一第一線路板80和至少一第二線路板81。所述第一線路板80包括疊設的第一絕緣層101以及第一導電線路層102,所述第一絕緣層101中設有第一盲孔50以及位於所述第一盲孔50周圍的至少一第一凹槽70,所述第一盲孔50內設有第一導電部90,所述第一凹槽70內設有第一溢出部91,所述第一導電部90與所述第一導電線路層102電性連接。所述第二線路板81包括疊設的第二絕緣層201以及第二導電線路層202,所述第二絕緣層201中設有第二盲孔51以及位於所述第二盲孔51周圍的至少一第二凹槽71,所述第二盲孔51內設有第二導電部92,所述第二凹槽71內設有第二溢出部93,所述第二導電部92與所述第二導電線路層202電性連接。Referring to FIG. 10 , an embodiment of the present invention also provides a
本實施方式中,所述第一絕緣層101的材質可以選自環氧樹脂(epoxy resin)、半固化片(Prepreg,PP)、BT樹脂、聚苯醚(Polyphenylene Oxide,PPO)、聚醯亞胺(polyimide,PI)、聚對苯二甲酸乙二醇酯(Polyethylene Terephthalate,PET)以及聚萘二甲酸乙二醇酯(Polyethylene Naphthalate,PEN)等樹脂中的一種。在本實施方式中,所述第一絕緣層101的材質為聚丙烯。In this embodiment, the material of the first insulating
本實施方式中,所述第二絕緣層201的材質可以選自環氧樹脂(epoxy resin)、半固化片(Prepreg,PP)、BT樹脂、聚苯醚(Polyphenylene Oxide,PPO)、聚醯亞胺(polyimide,PI)、聚對苯二甲酸乙二醇酯(Polyethylene Terephthalate,PET)以及聚萘二甲酸乙二醇酯(Polyethylene Naphthalate,PEN)等樹脂中的一種。在本實施方式中,所述第一絕緣層101的材質為聚丙烯。In this embodiment, the material of the second insulating
本實施方式中,所述第一絕緣層101和所述第二絕緣層201的厚度T均為5~150微米。In this implementation manner, the thickness T of the first insulating
本實施方式中,所述第一盲孔50的直徑自所述第一剝離膜30至所述第一絕緣層101的方向逐漸減小,所述第二盲孔51的直徑自所述第二剝離膜40至所述第二絕緣層201的方向逐漸減小。In this embodiment, the diameter of the first
請參閱圖4至圖8,本發明中所述第一凹槽70和所述第二凹槽71的形狀、開口大小、深度、排列方式以及凹槽與凹槽之間的間距可以根據實際需要具體設計。Referring to Fig. 4 to Fig. 8, the shape, opening size, depth, arrangement and spacing between the
請參閱圖4與圖5,本實施方式中,所述第一凹槽70可以為環形凹槽,所述第一凹槽70環繞所述第一盲孔50。所述第二凹槽71可以為環形凹槽,所述第二凹槽71環繞所述第二盲孔51。Referring to FIG. 4 and FIG. 5 , in this embodiment, the
請再次參閱圖4與圖5,本實施方式中,所述第一凹槽70的數量為多個,多個所述第一凹槽70同心設置,多個所述第一凹槽70的深度沿遠離所述第一盲孔50的方向依次減小。所述第二凹槽71的數量可以為多個,多個所述第二凹槽71同心設置,多個所述第二凹槽71的深度沿遠離所述第二盲孔51的方向依次減小。Please refer to FIG. 4 and FIG. 5 again. In this embodiment, the number of the
請參閱圖6,另一實施方式中,所述第一凹槽70的數量為多個,多個所述第一凹槽70同心設置,多個所述第一凹槽70的深度沿遠離所述第一盲孔50的方向依次增大。所述第二凹槽71的數量可以為多個,多個所述第二凹槽71同心設置,多個所述第二凹槽71的深度沿遠離所述第二盲孔51的方向依次增大。可以理解的是,不同深度的第一凹槽70也可以無規律排布,不同深度的第二凹槽71也可以無規律排布,相鄰兩個所述第一凹槽70之間的間距以及所述第二凹槽71之間的間距可以根據實際需要設計。Please refer to FIG. 6 , in another embodiment, the number of the
請參閱圖7與圖8,又一實施方式中,所述第一凹槽72的數量為多個,每一個所述第一凹槽72的橫截面可以為矩形、圓形以及梯形中的至少一種,多個第一凹槽72可以散佈在所述第一盲孔50周圍,多個第一凹槽72圍繞第一盲孔50設置。本實施方式中,所述第二凹槽73的數量也可以為多個,每一個所述第二凹槽73的橫截面可以為矩形、圓形以及梯形中的至少一種,多個第二凹槽73可以散佈在所述第二盲孔51內,多個第二凹槽73圍繞第二盲孔51設置。本實施方式中,藉由將第一凹槽72和第二凹槽73設計成尺寸較小的槽,而且槽的尺寸和形狀沒有特殊的要求,精度要求低,成型方便。Please refer to FIG. 7 and FIG. 8 , in yet another embodiment, the number of the
本實施方式中,所述第二導電線路層202包括多個連接墊2021。In this embodiment, the second
本實施方式中,所述第一線路板80為兩層,所述第二線路板81的數量為兩個,其中一個所述第一線路板80中的第一導電部90與其中一個所述第二線路板81中的所述第二導電部92相互黏結以電性連接所述第一導電線路層102和所述第二導電線路層202,另一個所述第二線路板81中的所述第二導電部92與其中一個所述第二導電線路層202的所述連接墊2021相互黏結以電性連接兩個所述第二導電線路層202,另一個所述第一線路板80中的所述第一導電部90與另一個所述第二導電線路層202的所述連接墊2021相互黏結以電性連接所述第一導電線路層102和所述第二導電線路層202。In this embodiment, the
請參閱圖11,本發明另一實施例還提供一種多層線路板200,該多層線路板200中的所述第一線路板80還包括第一連接部94,所述第一導電部90和第一溢出部91藉由所述第一連接部94連接。所述第二線路板81還包括第二連接部95,所述第二導電部92與所述第二溢出部93藉由第二連接部94連接。Please refer to FIG. 11 , another embodiment of the present invention also provides a
綜上所述,本發明提供的多層線路板的製備方法藉由在第一盲孔50和第二盲孔51的周圍分別設置第一凹槽70和第二凹槽71,當第一線路板80和第二線路板81在壓合過程中,使凸出第一絕緣層101是第一導電膏塊60和凸出第二絕緣層201的第二導電膏塊61分別溢流填充進第一凹槽70和第二凹槽71內,第一凹槽70和第二凹槽71能夠限制導電膏的流動,可以避免導電膏溢出面積過大與周邊線路連接導致短路的問題或溢出的銅膏與上下兩層銅層形成電容的現象。再者,能夠增加所述第一導電膏塊60與所述第一絕緣層101的接觸面積、以及所述第二導電膏塊61與所述第二絕緣層201的接觸面積,進而分別增加了所述第一導電膏塊60與所述第一絕緣層101的附著力、以及所述第二導電膏塊61與所述第二絕緣層201的附著力,降低了所述第一導電膏塊60以及所述第二導電膏塊61受冷熱處理的影響,從而提高了所述多層線路板100的信賴性。To sum up, the method for preparing a multilayer circuit board provided by the present invention is provided with a
100,200:多層線路板
10:第一線路基板
101:第一絕緣層
102:第一導電線路層
20:第二線路基板
201:第二絕緣層
202:第二導電線路層
2021:連接墊
30:第一剝離膜
40:第二剝離膜
50:第一盲孔
51:第二盲孔
60:第一導電膏塊
601:第一端面
61:第二導電膏塊
611:第二端面
70,72:第一凹槽
71,73:第二凹槽
80:第一線路板
81:第二線路板
90:第一導電部
91:第一溢出部
92:第二導電部
93:第二溢出部
94:第一連接部
95:第二連接部
A:第一溢出區域
B:第二溢出區域
100,200: multi-layer circuit board
10: The first circuit substrate
101: The first insulating layer
102: the first conductive line layer
20: Second circuit substrate
201: second insulating layer
202: the second conductive line layer
2021: Connection Pads
30: The first release film
40: Second release film
50: The first blind hole
51: Second blind hole
60: The first conductive paste block
601: the first end face
61: Second conductive paste block
611:
圖1為分別在本發明一實施例提供的第一線路基板和第二線路基板上形成第一剝離膜和第二剝離膜後的結構示意圖。FIG. 1 is a schematic structural view after forming a first peeling film and a second peeling film on a first circuit substrate and a second circuit substrate respectively according to an embodiment of the present invention.
圖2為在圖1所示的第一線路基板以及第二線路基板中分別開設第一盲孔以及第二盲孔後的結構示意圖。FIG. 2 is a schematic structural diagram of first blind holes and second blind holes respectively opened in the first circuit substrate and the second circuit substrate shown in FIG. 1 .
圖3為在圖2所示的第一盲孔以及第二盲孔中分別填充導電膏分別形成第一導電膏塊和第二導電膏塊後的結構示意圖。FIG. 3 is a schematic structural view of filling conductive paste in the first blind hole and the second blind hole shown in FIG. 2 to form a first conductive paste block and a second conductive paste block respectively.
圖4為在圖3所示的第一絕緣層和第二絕緣層上形成第一凹槽和第二凹槽後的結構示意圖。FIG. 4 is a schematic structural view after forming a first groove and a second groove on the first insulating layer and the second insulating layer shown in FIG. 3 .
圖5為本發明一實施例提供的第一盲孔和第一凹槽的結構示意圖。Fig. 5 is a schematic structural diagram of a first blind hole and a first groove provided by an embodiment of the present invention.
圖6為本發明另一實施方式提供的的第一凹槽和第二凹槽的結構示意圖。Fig. 6 is a schematic structural diagram of a first groove and a second groove provided by another embodiment of the present invention.
圖7與圖8為又一實施方式提供的的第一凹槽和第二凹槽的結構示意圖。7 and 8 are structural schematic diagrams of the first groove and the second groove provided in another embodiment.
圖9為將圖4所示的第一剝離膜以及第二剝離膜分別去除後的結構示意圖。FIG. 9 is a schematic structural diagram after the first peeling film and the second peeling film shown in FIG. 4 are respectively removed.
圖10為將圖9所示的第一線路板以及第二線路板層疊,並壓合後得到的多層線路板的結構示意圖。FIG. 10 is a schematic structural view of a multilayer circuit board obtained by laminating and pressing the first circuit board and the second circuit board shown in FIG. 9 .
圖11為本發明另一實施方式提供的多層線路板的結構示意圖。FIG. 11 is a schematic structural diagram of a multilayer circuit board provided by another embodiment of the present invention.
100:多層線路板 100: multilayer circuit board
101:第一絕緣層 101: The first insulating layer
102:第一導電線路層 102: the first conductive line layer
201:第二絕緣層 201: second insulating layer
202:第二導電線路層 202: the second conductive line layer
2021:連接墊 2021: Connection Pads
50:第一盲孔 50: The first blind hole
51:第二盲孔 51: Second blind hole
70:第一凹槽 70: first groove
71:第二凹槽 71: Second groove
80:第一線路板 80: The first circuit board
81:第二線路板 81: Second circuit board
90:第一導電部 90: The first conductive part
91:第一溢出部 91: The first overflow part
92:第二導電部 92: the second conductive part
93:第二溢出部 93: Second overflow part
Claims (11)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110553871.6 | 2021-05-20 | ||
CN202110553871.6A CN115379669A (en) | 2021-05-20 | 2021-05-20 | Multilayer wiring board and method for manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI778645B TWI778645B (en) | 2022-09-21 |
TW202247730A true TW202247730A (en) | 2022-12-01 |
Family
ID=84059893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110119744A TWI778645B (en) | 2021-05-20 | 2021-05-31 | Multilayer circuit board and method for manufacturing the same |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN115379669A (en) |
TW (1) | TWI778645B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN118055575A (en) * | 2022-11-17 | 2024-05-17 | 庆鼎精密电子(淮安)有限公司 | Manufacturing method of circuit board assembly and circuit board assembly |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103188882B (en) * | 2011-12-31 | 2015-12-16 | 深南电路有限公司 | A kind of circuit board and preparation method thereof |
CN105592639B (en) * | 2014-10-23 | 2019-01-25 | 碁鼎科技秦皇岛有限公司 | Circuit board and preparation method thereof |
TWI713419B (en) * | 2018-02-09 | 2020-12-11 | 大陸商深南電路股份有限公司 | Printed circuit board and method of manufacturing the same and electronic apparatus |
CN112752429B (en) * | 2019-10-31 | 2022-08-16 | 鹏鼎控股(深圳)股份有限公司 | Multilayer circuit board and manufacturing method thereof |
-
2021
- 2021-05-20 CN CN202110553871.6A patent/CN115379669A/en active Pending
- 2021-05-31 TW TW110119744A patent/TWI778645B/en active
Also Published As
Publication number | Publication date |
---|---|
TWI778645B (en) | 2022-09-21 |
CN115379669A (en) | 2022-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI645519B (en) | Component embedded package carrier and manufacturing method thereof | |
JP3961092B2 (en) | Composite wiring board, flexible substrate, semiconductor device, and method of manufacturing composite wiring board | |
JP5018826B2 (en) | Electronic device and manufacturing method thereof | |
JP3112059B2 (en) | Thin film multilayer wiring board and method of manufacturing the same | |
WO2022007274A1 (en) | Circuit board and manufacturing method therefor | |
US10098243B2 (en) | Printed wiring board and semiconductor package | |
TWI737033B (en) | Multiayer circuit board and manufacturing method thereof | |
TWI466610B (en) | Package structure and method for manufacturing same | |
US20140347834A1 (en) | Electronic component embedded printed circuit board and method for manufacturing the same | |
TW201410089A (en) | Package on package structure and method for manufacturing same | |
TWI778645B (en) | Multilayer circuit board and method for manufacturing the same | |
CN108235602A (en) | The processing method that second order buries copper billet circuit board | |
US11178777B2 (en) | Component embedded circuit board with antenna structure and method for manufacturing the same | |
TW201624631A (en) | Package structure and method of fabricating the same | |
TW202310693A (en) | Circuit board and method for manufacturing the circuit board | |
JP2002246745A (en) | Three-dimensional mounting package and its manufacturing method, and adhesive therefor | |
TWI846342B (en) | Electronic package, carrier substrate and fabricating method thereof | |
US9443830B1 (en) | Printed circuits with embedded semiconductor dies | |
US20230137841A1 (en) | Circuit carrier and manufacturing method thereof and package structure | |
JP2001223289A (en) | Lead frame, its manufacturing method, semiconductor integrated circuit device and its manufacturing method | |
TWI769010B (en) | Heterogeneous substrate structure and manufacturing method thereof | |
TW202435377A (en) | Fabricating method of package substrate | |
TW202435374A (en) | Electronic package, carrier substrate and fabricating method thereof | |
TW202222114A (en) | Method for preparing circuit board | |
WO2021081867A1 (en) | Thin circuit board and manufacturing method therefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent |