TW202247494A - 發光元件 - Google Patents

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Publication number
TW202247494A
TW202247494A TW110119457A TW110119457A TW202247494A TW 202247494 A TW202247494 A TW 202247494A TW 110119457 A TW110119457 A TW 110119457A TW 110119457 A TW110119457 A TW 110119457A TW 202247494 A TW202247494 A TW 202247494A
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Taiwan
Prior art keywords
layer
electrode
light
insulating layer
semiconductor
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TW110119457A
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English (en)
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TWI817129B (zh
Inventor
陳昭興
林羿宏
洪國慶
許啟祥
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晶元光電股份有限公司
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Priority to TW110119457A priority Critical patent/TWI817129B/zh
Priority to KR1020220063864A priority patent/KR20220161191A/ko
Priority to US17/827,622 priority patent/US20220384687A1/en
Priority to CN202210594547.3A priority patent/CN115411163A/zh
Publication of TW202247494A publication Critical patent/TW202247494A/zh
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Publication of TWI817129B publication Critical patent/TWI817129B/zh

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Abstract

一發光元件，包含一半導體疊層包含一第一半導體層及一第二半導體層，其中於一俯視圖下，半導體疊層包含一外周部及一內側區域，外周部露出第一半導體層，且第二半導體層係設置於外周部以外的內側區域；一絕緣層包含複數個第一絕緣層外側開口及一第二絕緣層開口；一第一電極覆蓋複數個第一絕緣層外側開口，且藉由複數個第一絕緣層外側開口接觸第一半導體層；一第二電極覆蓋第二絕緣層開口；以及一保護層覆蓋絕緣層，其中絕緣層及保護層於外周部相接觸之部分包含一總厚度自外周部向內側區域漸減。

Description

發光元件
本發明係關於一種發光元件，且特別係關於一種包含多個電極接觸區的覆晶式發光元件。
發光二極體(Light-Emitting Diode, LED)為固態半導體發光元件，其優點為功耗低，產生的熱能低，工作壽命長，防震，體積小，反應速度快和具有良好的光電特性，例如穩定的發光波長。因此發光二極體被廣泛應用於家用電器，設備指示燈，及光電產品等。
一發光元件，包含一半導體疊層包含一第一半導體層及一第二半導體層，其中於一俯視圖下，半導體疊層包含一外周部及一內側區域，外周部露出第一半導體層，且第二半導體層係設置於外周部以外的內側區域；一絕緣層包含複數個第一絕緣層外側開口及一第二絕緣層開口；一第一電極覆蓋複數個第一絕緣層外側開口，且藉由複數個第一絕緣層外側開口接觸第一半導體層；一第二電極覆蓋第二絕緣層開口；以及一保護層覆蓋絕緣層，其中絕緣層及保護層於外周部相接觸之部分包含一總厚度自外周部向內側區域漸減。
為了使本發明之敘述更加詳盡與完備，請參照下列實施例之描述並配合相關圖示。惟，以下所示之實施例係用於例示本發明之發光元件，並非將本發明限定於以下之實施例。又，本說明書記載於實施例中的構成零件之尺寸、材質、形狀、相對配置等在沒有限定之記載下，本發明之範圍並非限定於此，而僅是單純之說明而已。且各圖示所示構件之大小或位置關係等，會由於為了明確說明有加以誇大之情形。更且，於以下之描述中，為了適切省略詳細說明，對於同一或同性質之構件用同一名稱、符號顯示。
第1圖係本發明一實施例所揭示之一發光元件1的結構俯視圖。第2圖係沿著第1圖之切線X-X’的結構剖面圖。
如第1圖及第2圖所示，發光元件1，包含一基板10；以及一半導體疊層20位於基板10上，其包含一第一半導體層201，一第二半導體層202，及一活性層203位於第一半導體層201及第二半導體層202之間。於發光元件1之一俯視圖及一側視圖下，半導體疊層20包含一外周部2011及一內側區域2010。第一半導體層201於外周部2011係露出，第二半導體層202及活性層203則設置於為外周部2011所環繞的內側區域2010。一絕緣層50包含複數個第一絕緣層外側開口5011位於外周部2011，一第一絕緣層內側開口5012位於內側區域2010，及一第二絕緣層開口502位於內側區域2010。一第一電極61覆蓋複數個第一絕緣層外側開口5011，且藉由複數個第一絕緣層外側開口5011於外周部2011接觸第一半導體層201並形成複數個第一電極第一接觸區611。第一電極61覆蓋第一絕緣層內側開口5012，且藉由第一絕緣層內側開口5012於內側區域2010接觸第一半導體層201並形成第一電極第二接觸區612。一第二電極62覆蓋第二絕緣層開口502，且藉由第二絕緣層開口502電連接至第二半導體層202。一保護層70覆蓋絕緣層50，第一電極61，以及第二電極62，其中絕緣層50及保護層70於外周部2011相接觸之部分包含一總厚度自外周部2011向內側區域2010漸減。
基板10可以為一成長基板以磊晶成長半導體疊層20。基板10包括用以磊晶成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓，或用以成長氮化鎵(GaN)、氮化銦鎵(InGaN) 、或氮化鋁鎵(AlGaN)之藍寶石(Al 2O 3)晶圓、氮化鎵(GaN)晶圓、碳化矽(SiC)晶圓、或氮化鋁(AlN)晶圓。
第3A圖係依據本發明一實施例所揭示之發光元件1的局部剖面圖，並且是在第2圖用虛線表示的區域P的放大圖。基板10與半導體疊層20相接的一面可以為粗糙化的表面。粗糙化的表面可以為具有不規則形態的表面或具有規則形態的表面。例如，相對於基板10的上表面101，基板10包含一或複數個凸部100凸出於上表面101，或是包含一或複數個凹部(圖未示)凹陷於上表面101。於一剖面圖下，凸部100或凹部(圖未示)可以為半球形狀或者多邊錐形狀。
複數個凸部100包含一第一層1001及一第二層1002，第一層1001包含與基板10相同的材料，例如砷化鎵(GaAs)、藍寶石(Al 2O 3)、氮化鎵(GaN)、碳化矽(SiC)、或氮化鋁(AlN)。第二層1002包含與構成第一層1001、基板10不同的材料。第二層1002的材料包含絕緣材料，例如氧化矽、氮化矽、或氮氧化矽。自發光元件1的側面觀之，凸部100包含半球形狀、炮彈形狀或錐形狀。凸部100的最頂端可以是曲面或尖點。於本發明之一實施例中，凸部100僅包含第二層1002，缺少第一層1001，其中第二層1002之一底面與基板10的上表面101齊平。
於本發明之一實施例中，藉由金屬有機化學氣相沉積法(MOCVD)、分子束磊晶(MBE)、氫化物氣相沉積法(HVPE)、物理氣相沉積法(PVD) 、或離子電鍍方法以於基板10上形成具有光電特性之半導體疊層20，例如發光(light-emitting)疊層，其中物理氣象沉積法包含濺鍍 (Sputtering)或蒸鍍(Evaporation)法。
半導體疊層20包含第一半導體層201，第二半導體層202，以及形成在第一半導體層201和第二半導體層202之間的活性層203。藉由改變半導體疊層20中一層或多層的物理及化學組成以調整發光元件1發出光線的波長。半導體疊層20之材料包含Ⅲ-Ⅴ族半導體材料，例如Al xIn yGa (1-x-y)N或Al xIn yGa (1-x-y)P，其中0≦x，y≦1；(x+y)≦1。當半導體疊層20之材料為AlInGaP系列材料時，可發出波長介於610 nm及650 nm之間的紅光。當半導體疊層20之材料為InGaN系列材料時，可發出波長介於400 nm及490 nm之間的藍光，或波長介於530 nm及570 nm之間的綠光。當半導體疊層20之材料為AlGaN系列或AlInGaN系列材料時，可發出波長介於250 nm及400 nm之間的紫外光。
第一半導體層201和第二半導體層202可為包覆層(cladding layer)或侷限層(confinement layer)，兩者具有不同的導電型態、電性、極性，或依摻雜的元素以提供電子或電洞，例如第一半導體層201為n型電性的半導體，第二半導體層202為p型電性的半導體。活性層203形成在第一半導體層201和第二半導體層202之間，電子與電洞於一電流驅動下在活性層203複合，將電能轉換成光能，以發出一光線。活性層203可為單異質結構(single heterostructure, SH)，雙異質結構(double heterostructure, DH)，雙側雙異質結構(double-side double heterostructure, DDH)，或是多層量子井結構(multi-quantum well, MQW)。活性層203之材料可為中性、p型或n型電性的半導體。第一半導體層201、第二半導體層202、或活性層203可為一單層或包含複數子層的結構。
於本發明之一實施例中，半導體疊層20還可包含一緩衝層(圖未示)位於第一半導體層201和基板10之間，用以釋放基板10和半導體疊層20之間因材料晶格不匹配而產生的應力，以減少差排及晶格缺陷，進而提升磊晶品質。緩衝層可為一單層或包含複數子層的結構。於一實施例中，可選用PVD氮化鋁(AlN)做為緩衝層，形成於半導體疊層20及基板10之間，用以改善半導體疊層20的磊晶品質。在一實施例中，用以形成PVD氮化鋁(AlN)的靶材係由氮化鋁所組成。在另一實施例中，可使用由鋁組成的靶材，於氮源的環境下與鋁靶材反應性地形成氮化鋁。
於本發明之一實施例中，如第1圖及第2圖所示，發光元件1包含一第一電極墊81及一第二電極墊82形成於半導體疊層20之同一側，形成為倒裝晶片(flip chip)結構或是正裝的水平晶片(lateral chip)結構。
如第1圖所示，自發光元件1之俯視圖觀之，半導體疊層20在俯視時大致為矩形，包含四個角落及四個側壁。四個側壁包含直線，方波紋，波浪紋或前述任兩種之組合。半導體疊層20之四個側壁包含一第一側壁21，一與第一側壁21相對之第二側壁22，一第三側壁23，以及一與第三側壁23相對之第四側壁24。四個角落包含弧形或直線形。半導體疊層20之四個角落包含一第一角落C1，一第二角落C2，一第三角落C3，以及一第四角落C4。
於本實施例中，藉由蝕刻製程對半導體疊層20進行圖案化，移除部分的第二半導體層202及活性層203並露出第一半導體層201，形成外周部2011以及為外周部2011所包圍的內側區域2010。內側區域2010包含一或複數個半導體台面20m，及一或複數個孔穴2000。自發光元件1之俯視圖觀之，如第1圖所示，外周部2011包含複數個凹陷部2006，且兩相鄰的凹陷部2006為一凸出部2007所分隔。凹陷部2006未設有第二半導體層202及活性層203，凹陷部2006露出第一半導體層201。凸出部2007則具有第一半導體層201，第二半導體層202，及活性層203。相較於凹陷部2006，凸出部2007之一俯視圖形包含弧形或矩形。在本實施例中，在發光疊層20的各側壁21～24上形成有複數個具有半圓形的第一絕緣層外側開口5011，且大小相同。第一絕緣層外側開口5011的俯視形狀可以為半圓形，三角形，梯形或矩形。第一絕緣層外側開口5011的大小、形狀不限於此。另外，也可以包含大小或形狀不同的第一絕緣層外側開口5011。
鄰近第一側壁21的複數個第一絕緣層外側開口5011之間的第一間距與鄰近第二側壁22的複數個第一絕緣層外側開口5011之間的第二間距相同。但，鄰近第一側壁21的複數個第一絕緣層外側開口5011之間的第一間距與鄰近第三側壁23的複數個第一絕緣層外側開口5011之間的第三間距不同。
據此，第二半導體層202及活性層203各具有小於第一半導體層201的上表面積。半導體台面20m位於第一半導體層201上，並包含第二半導體層202及活性層203。凹陷部2006及孔穴2000露出第一半導體層201。複數個孔穴2000形成於內側區域2010，並以一固定的距離彼此間隔排列成一直線或一陣列。
於發光元件1之俯視圖或側視圖下，孔穴2000包含一寬度介於5 μm~20 μm之間，更佳介於8 μm~15 μm之間。孔穴2000的俯視圖形包含圓形、橢圓形、半圓形、矩形、或長條形。
複數個孔穴2000之一個與發光元件1之一第一邊11以一第一最短距離相間隔，複數個孔穴2000之一個與發光元件1之一第二邊12以一第二最短距離相間隔，第一邊與第二邊係為相對邊，且第一最短距離大於或等於第二最短距離。複數個孔穴2000之一個與發光元件1之一第三邊13以一第三最短距離相間隔，第三邊係正交於第一邊，且第一最短距離及/或第二最短距離大於第三最短距離。
複數個孔穴2000及外周部2011係藉由移除部分的第二半導體層202及活性層203以露出第一半導體層201而形成。被蝕刻而露出的第二半導體層202及活性層203的側邊20S相對於露出的第一半導體層201是傾斜面，其中傾斜面可以包含覆數個斜率的面。
第一電極61藉由位於內側區域2010的複數個孔穴2000及位於外周部2011的凹陷部2006以接觸第一半導體層201，並和第一半導體層201形成電連接。第二電極62形成於第二半導體層202上，藉由一接觸電極40和第二半導體層202形成電連接。
第3A圖係依據本發明一實施例所揭示之發光元件1的局部剖面圖，並且是在第2圖用虛線表示的區域P的放大圖。第3B圖係依據本發明另一實施例所揭示之發光元件1的局部剖面圖，並且是在第2圖用虛線表示的區域P的放大圖。
一鈍化層30覆蓋半導體台面20m，包含一或複數個第一鈍化層開口301以及一或複數個第二鈍化層開口302。自發光元件1之俯視圖觀之，第一鈍化層開口301設置於孔穴2000及凹陷部2006上並露出第一半導體層201。第二鈍化層開口302設置於半導體台面20m上並露出第二半導體層202。如第3A圖及第3B圖所示，鈍化層30包含一第一鈍化層部份31接觸第一半導體層201，以及一第二鈍化層部份32接觸第二半導體層202。第一鈍化層部份31包含一第一長度L1介於5 μm~10 μm之間。第二鈍化層部份32包含一第二長度L2介於13 μm~16 μm之間。
接觸電極40設置於第二鈍化層開口302中並接觸第二半導體層202。接觸電極40大致覆蓋半導體台面20m的上表面。例如，接觸電極40可以覆蓋半導體台面20m的80%以上，更佳的為覆蓋90%以上。於本發明之一實施例中，接觸電極40可以包含一透明導電層401，一反射層402，及一阻障層403中的任一層或是多層。
透明導電層401可以設置在反射層402及第二半導體層202之間。為了減少接觸電阻並提高電流擴散的效率，透明導電層401之材料包含對於活性層203所發出的光線為透明的材料，例如透明導電氧化物。透明導電氧化物包含氧化銦錫(ITO)或氧化銦鋅(IZO)。於本發明之一實施例，透明導電層401可為具有厚度小於500埃之金屬層。
反射層402的材料包含具有反射性的金屬，例如鋁(Al)、銀(Ag)、銠(Rh)、或鉑(Pt)等金屬或上述材料之合金。反射層402係用來反射活性層203所發出的光線，且使經反射的光線朝向基板10而向外射出。
如第3B圖所示，阻障層403可包覆反射層402之一側邊以避免反射層402氧化而劣化其反射率。阻障層403之材料包含金屬材料，例如鈦(Ti)、鎢(W)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉻(Cr)、鉑(Pt)等金屬或上述材料之合金。於一實施例中，如第3A圖所示，阻障層403不包覆反射層402，阻障層403之一側邊可與反射層402之一側邊齊平或露出反射層402之部分上表面。
接觸電極40能夠使經由第二電極62供給的電流向第二半導體層202擴散。另外，接觸電極40具有良好的光反射性，可以作為使發光元件1所發出的光向光輸出面(即，基板10之一側)反射的層來使用。
如第3A圖所示，接觸電極40未接觸鈍化層30，一間距S位於鈍化層30及接觸電極40之間。部分絕緣層50位於接觸電極40及鈍化層30之間的間距S內，使得絕緣層50包含一絕緣凹部50a對應於間距S。
如第3B圖所示，接觸電極40包含一第一接觸部分40a覆蓋鈍化層30及一第二接觸部分40b直接接觸第二半導體層202。接觸電極40之第一接觸部分40a包含一厚度小於第二接觸部分40b的厚度，並且第一接觸部分40a的厚度自半導體台面20m之內側往外側漸減。所述厚度係對應於在垂直於第二半導體層202的上表面的方向上測量的厚度。第一接觸部分40a的邊緣與半導體台面20m的側邊20S之間的第三長度L3可小於第一接觸部分40a覆蓋鈍化層30的第四長度L4以增加電極的附著力並增加反射面積。於考量製程變異的情況下，第一接觸部分40a的邊緣與半導體台面20m的側邊20S之間的第三長度L3可大於第一接觸部分40a覆蓋鈍化層30的第四長度L4。於本實施例中，第三長度L3可介於0μm~8μm之間，更佳介於0μm~3μm之間。第四長度L4可介於5μm~18μm之間，更佳介於10μm~13μm之間。
絕緣層50覆蓋半導體台面20m，包含一或覆數個第一絕緣層外側開口5011，第一絕緣層內側開口5012，以及一第二絕緣層開口502。自發光元件1之俯視圖觀之，第一絕緣層外側開口5011設置於凹陷部2006上，並露出第一半導體層201。第一絕緣層內側開口5012設置於孔穴2000上以對應孔穴2000之位置，並露出第一半導體層201。第二絕緣層開口502設置於接觸電極40上，並露出接觸電極40的透明導電層401、反射層402及/或阻障層403中的任一層或是多層。位於外周部2011的複數個第一絕緣層外側開口5011沿著發光元件1之四個邊的方向依序排列，發光元件1之絕緣層50覆蓋半導體疊層20的四個角落。
於發明之一實施例中，如第2圖所示，絕緣層50包含一絕緣層平台500位於第二電極62及第二電極墊82下方。於發光元件1之俯視圖中，如第1圖所示，絕緣層平台500為第二絕緣層開口502所環繞。絕緣層平台500可以形成於第二電極墊82之一投影面積以內或是以外。於發光元件1之側視圖中，絕緣層平台500為第二電極62所包覆。
第一電極61覆蓋絕緣層50之複數個第一絕緣層外側開口5011及第一絕緣層內側開口5012，並接觸第一半導體層201。第二電極62覆蓋絕緣層50之第二絕緣層開口502，並接觸第二半導體層202及/或接觸電極40。在發光元件1之俯視圖中，第二電極62與第二絕緣層開口502具有相同的形狀，於一實施例中，第二電極62與第二絕緣層開口502同樣地大致為矩形。於一實施例中，第二電極62可以形成得比第二絕緣層開口502大。第一電極61與第二電極62藉由絕緣層50而相間隔。第一電極61與第二電極62之間具有一間距G位於半導體台面20m上並露出絕緣層50，間距G係介於3μm~30μm之間，較佳介於5μm~25μm之間，更佳介於18μm~22μm之間。
如第1圖及第2圖所示，第一電極61覆蓋複數個第一絕緣層內側開口5012，且藉由複數個第一絕緣層內側開口5012接觸第一半導體層201以形成複數個第一電極第二接觸區612。第一電極61覆蓋複數個第一絕緣層外側開口5011，且藉由複數個第一絕緣層外側開口5011於外周部2011接觸第一半導體層201並形成複數個第一電極第一接觸區611。各複數個第一電極第一接觸區611包含一第一接觸面積小於各複數個第一電極第二接觸區612之一第二接觸面積。複數個第一電極第一接觸區611包含一第一接觸總面積大於複數個第一電極第二接觸區612之一第二接觸總面積。
本實施例藉由在外周部2011配置複數個第一電極第一接觸區611，減少內側區域2010的第一電極第二接觸區612的第二接觸總面積，既能夠抑制正向電壓V f的上升，又能夠確保較寬大的發光區域。
在發光元件1的俯視下，複數個第一電極第一接觸區611形成於四個角落以外的區域，並且複數個第一電極第一接觸區611等間隔或非等間隔地散佈形成在外周部2011之上以改善電流密度的分佈。
如第1圖所示，發光元件1包含一頂針區60位於半導體疊層20上的幾何中心處。頂針區60不與第一電極61及第二電極62相接觸，並與第一電極61及第二電極62電性隔緣。頂針區60係作為保護磊晶層之結構以避免磊晶層於後段製程，例如晶粒分離、翻轉、測試晶粒、封裝，為頂針所損害。
保護層70包含一第一保護層開口701位於內側區域2010及一第二保護層開口702位於內側區域2010，且第一保護層開口701包含一第一開口寬度W1大於第二保護層開口702的一第二開口寬度W2。
發光元件1包含一第一電極墊81及一第二電極墊82。如第1圖所示，第一電極墊81鄰近半導體疊層20之第一側壁21及第二電極墊82鄰近半導體疊層20之第二側壁22。第一電極墊81與第一側壁21之間的一第一距離小於第二電極墊82與第二側壁22之間的一第二距離。
如第2圖所示，第一電極墊81藉由第一保護層開口701接觸第一電極61，第二電極墊82藉由第二保護層開口702接觸第二電極62。
第一電極墊81及第二電極墊82具有不同的導電性，例如第一電極墊81可以是N型電極墊，第二電極墊82可以是P型電極墊。第一電極墊81及第二電極墊82位於半導體台面20m上，並分別位於第一保護層開口701及第二保護層開口702上以接觸第一電極61及第二電極62，並分別電連接至第一半導體層201及第二半導體層202。
頂針區60，第一電極61，第二電極62，第一電極墊81及第二電極墊82包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、銀(Ag)等金屬或上述材料之合金。頂針區60，第一電極61，第二電極62，第一電極墊81及第二電極墊82可由單個層或是多個層所組成。例如，頂針區60，第一電極61，第二電極62，第一電極墊81或第二電極墊82可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層、Cr/Al/Cr/Ni/Au層或Ag/NiTi/TiW/Pt層。第一電極墊81及第二電極墊82可做為外部電源供電至第一半導體層201及第二半導體層202之電流路徑。第一電極61，第二電極62，第一電極墊81及第二電極墊82各包含一厚度介於1μm~100μm之間，較佳為1.2μm~60μm之間，更佳為1.5μm~6μm之間。
鈍化層30、絕緣層50及/或保護層70設置在在半導體疊層20上，是作為發光元件1的保護膜及防靜電的層間絕緣膜。作為絕緣膜，鈍化層30、絕緣層50及/或保護層70可以為一單層結構，包含金屬氧化物或金屬氮化物，例如可優選使用選自由Si、Ti、Zr、Nb、Ta、Al構成的組中的至少一種氧化物或氮化物。鈍化層30、絕緣層50、及/或保護層70也可以包含不同折射率的兩種以上之材料交替堆疊以形成一分布式布拉格反射鏡(DBR)結構，選擇性地反射特定波長之光。例如，可通過層疊SiO 2/TiO 2或SiO 2/Nb 2O 5等層來形成高反射率的絕緣反射結構。當SiO 2/TiO 2或SiO 2/Nb 2O 5形成分布式布拉格反射鏡(DBR)結構時，分布式布拉格反射鏡(DBR)結構的每一個層被設計成活性層212發出的光的波長的四分之一的光學厚度的一或整數倍。分布式布拉格反射鏡(DBR)結構的每一個層的厚度在λ/4的一或整數倍的基礎上可具有±30%的偏差。由於分布式布拉格反射鏡(DBR)結構的的每一個層的厚度會影響到反射率，因此優選地利用電子束蒸鍍(E-beam evaporation)來形成介電層30，絕緣層50，及/或保護層70以穩定的控制分布式布拉格反射鏡(DBR)結構的每一個層的厚度。
發光元件1包含切割道10d位於基板10之側邊10S與第一半導體層201之一側邊21S之間，且切割道10d包含一寬度介於5μm~50μm之間，較佳小於30μm，更佳小於15μm。切割道10d露出基板10之上表面101，並位於發光元件1之周圍以環繞半導體疊層20。
第4圖係第1圖用虛線表示的區域Ⅰ的放大圖。第5圖係第4圖之切線Ⅰ-Ⅰ’的結構剖面圖。第6圖係第1圖用虛線表示的區域Ⅱ的放大圖。第7圖係第6圖之切線Ⅱ-Ⅱ’的結構剖面圖。如第4圖及第5圖所示，於平行於發光元件1之第一邊11或第二邊12的方向上，凸出部2007包含一最大寬度介於30μm~60μm之間。凹陷部2006包含一最大寬度介於30μm~60μm之間。
絕緣層50及保護層70於外周部2011相接觸之部分包含一第一厚度T1及一第二厚度T2，且第二厚度T2大於第一厚度T1。於發明之一實施例中，第一厚度T1係介於3 μm~30 μm之間，第二厚度T2係介於6μm~60μm之間。所述厚度係對應於在垂直於第二半導體層202的上表面的方向上測量的厚度。
鈍化層30及絕緣層50於半導體台面20m上相接觸之部分包含一第三厚度T3及一第四厚度T4，且第四厚度T4大於第三厚度T3。於發明之一實施例中，第三厚度T3係介於3 μm~30 μm之間，第四厚度T4係介於6 μm~60 μm之間。所述厚度係對應於在垂直於第二半導體層202的上表面的方向上測量的厚度。
如第5圖所示，鄰近發光元件1之第一邊11的切割道10d包含一第一寬度D1。如第7圖所示，鄰近發光元件1之第二邊12的切割道10d包含一第二寬度D2。第一寬度D1與第二寬度D2可相同或不相同。於本實施例中，第二寬度D2大於第一寬度D1，第二寬度D2與第一寬度D1之間具有一比值(D2/D1)大於2，但小於4。
第8圖係第1圖用虛線表示的區域Ⅲ的放大圖。第9圖係第8圖之切線Ⅲ-Ⅲ’的結構剖面圖。第10圖係第1圖用虛線表示的區域Ⅳ的放大圖。第11圖係第10圖之切線Ⅳ-Ⅳ’的結構剖面圖 。於平行於發光元件1之第三邊13或第四邊14的方向上，凸出部2007包含一最大寬度介於30μm~60μm之間。凹陷部2006包含一最大寬度介於30μm~60μm之間。
如第9圖所示，鄰近發光元件1之第三邊13或第四邊14(圖未示)的切割道10d之一部分包含一第三寬度D3。如第11圖所示，鄰近發光元件1之第三邊13或第四邊14(圖未示)的切割道10d之另一部分包含一第四寬度D4。第三寬度D3與第四寬度D4不相同。換言之，鄰近發光元件1之第三邊13或第四邊14的切割道10d包含兩種以上的寬度，第四寬度D4大於第三寬度D3，且第四寬度D4與第三寬度D3之間的比值(D4/D3)大於2，但小於4。於平行於發光元件1之第三邊13或第四邊14的一方向上，具有第三寬度D3的切割道10d之一部分的長度可大於、小於或等於具有第四寬度D4的切割道10d之另一部分的長度。為了保留較多的發光面積，優選的為具有第三寬度D3的切割道10d之一部分的長度大於具有第四寬度D4的切割道10d之另一部分的長度。
如第5圖及第7圖所示，第一電極61包含一第一電極第一側表面611S鄰近發光元件1之第一邊11及一第一電極第二側表面612S鄰近發光元件1之第二邊12。第一電極第一側表面611S與發光元件1之第一邊11之間的距離小於第一電極第二側表面612S與發光元件1之第二邊12之間的距離。
如第9圖及第11圖所示，第一電極61更包含一第一電極第三側表面613S鄰近發光元件1之第三邊13及發光元件1之第一邊11，及一第一電極第四側表面614S鄰近發光元件1之第三邊13及發光元件1之第二邊12。第一電極第三側表面613S與發光元件1之第三邊13之間的距離小於第一電極第四側表面614S與發光元件1之第三邊13之間的距離。
第13圖係為依本發明一實施例之發光裝置2之示意圖。將前述實施例中的發光元件1以倒裝晶片之形式安裝於封裝基板51之第一墊片511及第二墊片512上。第一墊片51511及第二墊片512之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片安裝係將與電極墊形成面相對之成長基板側向上設為主要的光取出面，例如發光元件1之基板10係為發光元件1之主要的光取出面。為了增加發光裝置2之光取出效率，可於發光元件1之周圍設置一反射結構54。
第14圖係為依本發明一實施例之發光裝置3之示意圖。發光裝置3為一球泡燈包括一燈罩602、一反射鏡604、一發光模組600、一燈座610、一散熱片614、一連接部616以及一電連接元件618。發光模組600包含一承載部606，以及複數個發光單元608位於承載部606上，其中複數個發光體608可為前述實施例中的發光元件1或發光裝置2。
本發明所列舉之各實施例僅用以說明本發明，並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。
1:發光元件
10:基板
10d:切割道
10S:側邊
100:凸部
1001:第一層
1002:第二層
101:上表面
11:第一邊
12:第二邊
13:第三邊
2:發光裝置
20:半導體疊層
20m:半導體台面
20S:側邊
201:第一半導體層
202:第二半導體層
203:活性層
2000:孔穴
2006:凹陷部
2007:凸出部
2010:內側區域
2011:外周部
21:側壁
21S:側邊
22:側壁
23:側壁
24:側壁
3:發光裝置
30:鈍化層
301:第一鈍化層開口
302:第二鈍化層開口
31:第一鈍化層部份
32:第二鈍化層部份
40:接觸電極
40a:第一接觸部分
40b:第二接觸部分
401:透明導電層
402:反射層
403:阻障層
50:絕緣層
50a:絕緣凹部
502:第二絕緣層開口
500:絕緣層平台
5011:第一絕緣層外側開口
5012:第一絕緣層內側開口
51:封裝基板
511:第一墊片
512:第二墊片
53:絕緣部
54:反射結構
60:頂針區
600:發光模組
602:燈罩
604:反射鏡
606:承載部
608:發光單元
61:第一電極
610:燈座
611:第一電極第一接觸區
611S:第一電極第一側表面
612:第一電極第二接觸區
612S:第一電極第二側表面
613S:第一電極第三側表面
614S:第一電極第四側表面
614:散熱片
616:連接部
618:電連接元件
62:第二電極
70:第二電極
701:第一保護層開口
702:第二保護層開口
81:第一電極墊
82:第二電極墊
C1:第一角落
C2:第二角落
C3:第三角落
C4:第四角落
D1:第一寬度
D2:第二寬度
D3:第三寬度
D4:第四寬度
G:間距
L1:第一長度
L2:第二長度
L3:第三長度
L4:第四長度
S:間距
T1:第一厚度
T2:第二厚度
T3:第三厚度
T4:第四厚度
W1:第一開口寬度
W2:第二開口寬度
第1圖係本發明一實施例所揭示之一發光元件1的結構俯視圖。
第2圖係沿著第1圖之切線X-X’的結構剖面圖。
第3A圖係依據本發明一實施例所揭示之發光元件1的局部剖面圖，並且是在第2圖用虛線表示的區域P的放大圖。
第3B圖係依據本發明另一實施例所揭示之發光元件1的局部剖面圖，並且是在第2圖用虛線表示的區域P的放大圖。
第4圖係第1圖用虛線表示的區域Ⅰ的放大圖。
第5圖係第4圖之切線Ⅰ-Ⅰ’的結構剖面圖。
第6圖係第1圖用虛線表示的區域Ⅱ的放大圖。
第7圖係第6圖之切線Ⅱ-Ⅱ’的結構剖面圖。
第8圖係第1圖用虛線表示的區域Ⅲ的放大圖。
第9圖係第8圖之切線Ⅲ-Ⅲ’的結構剖面圖。
第10圖係第1圖用虛線表示的區域Ⅳ的放大圖。
第11圖係第10圖之切線Ⅳ-Ⅳ’的結構剖面圖。
第12圖係為依本發明一實施例之發光裝置2之示意圖。
第13圖係為依本發明一實施例之發光裝置3之示意圖。
1:發光元件
10:基板
10d:切割道
10S:側邊
101:上表面
20:半導體疊層
20m:半導體台面
20S:邊緣
201:第一半導體層
202:第二半導體層
203:活性層
2000:孔穴
2006:凹陷部
2010:內側區域
2011:外周部
21S:側邊
30:鈍化層
301:第一鈍化層開口
302:第二鈍化層開口
40:接觸電極
50:絕緣層
500:絕緣層平台
502:第二絕緣層開口
5011:第一絕緣層外側開口
5012:第一絕緣層內側開口
61:第一電極
611:第一電極第一接觸區
612:第一電極第二接觸區
62:第二電極
70:第二電極
701:第一保護層開口
702:第二保護層開口
81:第一電極墊
82:第二電極墊

Claims (12)

  1. 一發光元件，包含： 一基板； 一半導體疊層包含一第一半導體層，一活性層及一第二半導體層位於該基板上，其中於一俯視圖下，該半導體疊層包含一外周部及一內側區域，該外周部露出該第一半導體層，該第二半導體層係設置於為該外周部所環繞的該內側區域； 一絕緣層包含複數個第一絕緣層外側開口位於該外周部及一第二絕緣層開口位於該內側區域； 一第一電極覆蓋該複數個第一絕緣層外側開口，藉由該複數個第一絕緣層外側開口於該外周部接觸該第一半導體層以形成複數個第一電極第一接觸區； 一第二電極覆蓋該第二絕緣層開口，並藉由該第二絕緣層開口電連接至該第二半導體層；以及 一保護層覆蓋該絕緣層，該第一電極，及該第二電極， 其中，該絕緣層及該保護層於該外周部相接觸之一部分包含一總厚度自該外周部向該內側區域漸減。
  2. 如申請專利範圍第1項所述的發光元件，其中自該發光元件之一俯視圖觀之，該半導體疊層包含四個角落及四個側壁，該複數個第一絕緣層外側開口係位於該四個角落以外的該四個側壁上。
  3. 如申請專利範圍第2項所述的發光元件，其中自該發光元件之該俯視圖觀之，該半導體疊層之該四個側壁包含直線，方波紋，波浪紋或前述任兩種之組合。
  4. 如申請專利範圍第2項所述的發光元件，包含一第一電極墊，及一第二電極墊，其中自該發光元件之該俯視圖觀之，該半導體疊層之該四個側壁包含一第一側壁，與該第一側壁相對之一第二側壁，一第三側壁，與該第三側壁相對之一第四側壁，且該第一電極墊鄰近該第一側壁及該第二電極墊鄰近該第二側壁。
  5. 如申請專利範圍第4項所述的發光元件，其中該第一電極墊與該第一側壁之間的一第一距離小於該第二電極墊與該第二側壁之間的一第二距離。
  6. 如申請專利範圍第4項所述的發光元件，其中該保護層包含一第一保護層開口位於該內側區域及一第二保護層開口位於該內側區域，且該第一保護層開口包含一第一開口寬度大於該第二保護層開口的一第二開口寬度。
  7. 如申請專利範圍第6項所述的發光元件，其中該第一電極墊藉由該第一保護層開口接觸該第一電極，且該第二電極墊藉由該第二保護層開口接觸該第二電極。
  8. 如申請專利範圍第4項所述的發光元件，更包含複數個孔穴位於該內側區域，其中該複數個孔穴穿過該活性層及該第二半導體層以露出該第一半導體層。
  9. 如申請專利範圍第8項所述的發光元件，其中該複數個孔穴之一個與該發光元件之一第一邊以一第一最短距離相間隔，該複數個孔穴之該個與該發光元件之一第二邊以一第二最短距離相間隔，該複數個孔穴之該個與該發光元件之一第三邊以一第三最短距離相間隔，且該第一最短距離大於或等於該第二最短距離，該第一最短距離大於該第三最短距離。
  10. 如申請專利範圍第8項所述的發光元件，其中該絕緣層更包含複數個第一絕緣層內側開口以對應該複數個孔穴，該第一電極覆蓋該複數個第一絕緣層內側開口，且藉由該複數個第一絕緣層內側開口接觸該第一半導體層以形成複數個第一電極第二接觸區。
  11. 如申請專利範圍第10項所述的發光元件，其中各該複數個第一電極第一接觸區包含一第一接觸面積小於各該複數個第一電極第二接觸區之一第二接觸面積。
  12. 如申請專利範圍第11項所述的發光元件，其中該複數個第一電極第一接觸區包含一第一接觸總面積大於該複數個第一電極第二接觸區之一第二接觸總面積。
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