TW202247165A - Sustainable dram having principle power supply voltage unified with logic circuit - Google Patents

Abstract

A DRAM chip configured to couple with an external logic circuit and to couple with a principle power supply voltage source includes a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator produces a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM chip. The DRAM core circuit with a DRAM cell includes an access transistor and a storage capacitor. The storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. A voltage level of the principle power supply voltage source to the DRAM chip is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.

Description

Dynamic random access memory with mains supply voltage source unified with logic circuits

The present invention relates to a dynamic random access memory, especially a dynamic random access memory with a main power supply voltage source that is unified or compatible with an external logic circuit.

In the prior art, the most widely used DRAM (Dynamic Random Access Memory, DRAM) unit (cell) includes an access transistor and a storage capacitor, wherein the source of the access transistor is connected to the storage capacitor, and The drain of the access transistor is connected to a bit line. The bit line is coupled to the first-stage sense amplifier, and the signal read out by the first-stage sense amplifier from the dynamic random access memory unit (READ out) is transmitted to a first stage after passing through column switches. A two-stage sense amplifier, wherein the second-stage sense amplifier is connected to the input/output line (that is, the data line). During the WRITE operation of the DRAM, the signal driven by the I/O buffer is stabilized on the data line, and the data line is further stabilized by the first-stage sense amplifier. The signal driven by the I/O buffer enables the correct signal to be written into the storage capacitor through the access transistor. During the active mode (active mode, that is, the period when the access transistor is turned on) of the access transistor, the access transistor is responsible for the read operation (READ operation) of the storage capacitor or the writing of the storage capacitor operation (WRITE operation), and in the inactive mode of the access transistor (that is, when the access transistor is turned off), the access transistor can prevent the data stored in the storage capacitor from being lost.

In the prior art, the access transistor is designed with a high threshold voltage to minimize the leakage current through the access transistor, but the attendant disadvantage is that when the access transistor is turned on, the memory The performance of the transistor is degraded. Therefore, the word line connected to the gate of the access transistor must be boosted or connected to a high voltage VPP (usually from a word line driver) to allow the access transistor to have a high drive capability to pass the signal Writing to the storage capacitor, wherein the voltage VPP is loaded to the word line or the gate of the access transistor through the word line driver. Because the voltage VPP is a high voltage stress applied to the access transistor, the dielectric material (for example, an oxide layer or a high dielectric constant material) of the gate of the access transistor must be higher than that applied to the DRAM. The dielectric material of the gate of other supporting circuits or peripheral circuits of the memory (such as command decoder, address decoder and other input/output circuits, etc.) is also thicker. Therefore, the design of the access transistor faces the challenge of maintaining high performance or high reliability, and a difficult trade-off must be made between the reliability and performance of the access transistor. However, in the prior art, the design of the access transistor is more focused on achieving high reliability of the access transistor, but the performance of the access transistor must be sacrificed at the same time.

In summary, regarding the design of the access transistor, the access transistor must have the high threshold voltage to reduce the leakage current of the access transistor (wherein reducing the leakage current of the access transistor helps to prolong The retention time of the charge stored in the storage capacitor), having a thick gate dielectric material to withstand high word line voltages (such as voltage VPP), and sacrificing the performance of the access transistor. Therefore, it will take a long time to write a high potential signal (that is, the signal "ONE", wherein the signal "ONE" usually corresponds to the voltage VCCSA shown in FIG. 1A ) to the storage capacitor through the access transistor. Or the voltage VCCSA corresponding to the signal "ONE" cannot be fully reached. That is to say, the writing time (WRITE time) consumed to completely write the voltage VCCSA corresponding to the signal “ONE” into the storage capacitor will be longer.

In addition, please refer to FIG. 1A again, wherein FIG. 1A is a schematic diagram illustrating the most common design of a DRAM unit, wherein the DRAM unit includes an access transistor 11 and a storage capacitor 12 . The gate of the access transistor 11 is coupled to a word line WL, and the sense amplifier 20 is coupled to the access transistor 11 through a bit line BL. The DRAM cell utilizes the access transistor 11 as a switch during the write mode (WRITE mode) to control the charge storage to the storage capacitor 12 through the bit line BL, or in the read mode (READ mode) ) period, transfer the charge stored in the storage capacitor 12 to the bit line BL, wherein a plurality of DRAM cells are respectively connected to the bit line BL. For example, sense amplifier 20 latches signal "ONE" (where signal "ONE" may be, for example, 1.2V, signal "ONE" is generally the voltage VCCSA provided by the sense amplifier 20) or a signal "ZERO" (wherein the signal "ZERO" may be, for example, 0V and the signal "ZERO" is generally the voltage VSS provided by the sense amplifier 20), or at During the write mode, the external writes a signal “ONE” or a signal “ZERO” to the sense amplifier 20 to store the correct signal to the storage capacitor 12 of the DRAM unit.

Please refer to FIG. 1B . FIG. 1B is a schematic diagram illustrating waveforms of related signals of a DRAM cell during an access (read or write) operation. For example, the design of the DRAM cell (25 nanometer (nm) process) generally has the following parameters related to the design of the DRAM cell array: the signal "ONE" on the bit line BL The voltage is 1.2V, the turn-on voltage on the word line WL is 2.7V (that is, the voltage VPP is 2.7V) and the standby voltage on the word line WL is about -0.3V, the critical The voltage range is between 0.7V and 0.9V, and the dielectric material of the gate electrode of the access transistor 11 must withstand a voltage strength of 2.7V (wherein under the condition of aging stress (burn-in stress), the access transistor The dielectric material of the gate electrode of 11 must withstand the voltage strength of 3.4V to maintain an acceptable reliability margin (reliability margin)), and the dielectric material of the gate electrode of the access transistor 11 must be thick, wherein the thick The dielectric material of the gate of the access transistor 11 will sacrifice the performance of the access transistor 11 .

As shown in FIG. 1B, the storage capacitor 12 is initially in a standby mode (standby made) or the non-start mode (that is to say, the access transistor 11 is turned off at this time), and the voltage on the word line WL is -0.3 V (standby voltage). The voltages on the bit lines BL and BLB are equalized to half the voltage VCCSA (ie 0.6V). When the storage capacitor 12 enters the active mode (that is, the access transistor 11 is turned on), the voltage on the word line WL is raised from the standby voltage (-0.3V) to a voltage VPP (for example, 2.7V), wherein the voltage VPP Far greater than the sum of the voltage VCCSA (1.2V) and the threshold voltage VT (which can be 0.7V or 0.8V) of the access transistor 11 to achieve a gate-source voltage of the access transistor 11 (for example, 2.7V - 1.2V - 0.8 V = 0.7V) to provide sufficient driving force. In addition, since the access transistor 11 is turned on, the bit line BL can be coupled to the storage capacitor 12 . As shown in FIG. 1B, during the access (reading or writing) operation, the voltage on the word line WL is continuously maintained at the voltage VPP, and the access operation is followed by a recovery phase (RESTORE phase ). During the recovery phase, the sense amplifier 20 will recharge the storage capacitor 12 according to the signal “ONE” or the signal “ZERO” stored in the storage capacitor 12 . After the recovery phase, the voltage on the word line WL will be pulled down from the voltage VPP to the standby voltage (-0.3V), causing the access transistor 11 to be in the inactive mode again.

Compared with the transistors applied to the peripheral circuits of the DRAM, the high voltage stress caused by the voltage VPP will make the access transistor 11 be designed to have a thicker gate oxide layer or gate insulating layer, However, the thicker gate oxide layer or gate insulating layer of the access transistor 11 will reduce the performance of the access transistor 11 (for example, the short channel effect of the access transistor 11 is more serious, and the opening/closing of the access transistor 11 The current ratio is smaller, and the swing slope (swing slope) to measure the turn-on/turn-off response capability of the access transistor 11 becomes worse, etc.). In addition, although the threshold voltage of the access transistor 11 is higher than that of the transistors used in the peripheral circuits of the DRAM unit, during the standby mode or the inactive mode, the memory The leakage current of the transistor 11 is still large enough to reduce the charge stored in the storage capacitor 12 for sensing. In the 12nm or 7nm fin field-effect transistor (fin field-effect transistor, FinFET) process technology, when the voltage VCCSA is low (for example, 0.6), the access transistor 11 is in the standby mode or the inactive The leakage current during mode becomes more severe. Therefore, the voltage level provided by a main power supply voltage source to the DRAM or the voltage VCCSA applied to the DRAM should be maintained at a certain voltage level.

On the other hand, an integrated circuit system for high-performance computing or artificial intelligence (AI) systems is composed of multiple DRAM chips and a logic chip. The logic chip can now be fabricated on silicon wafers using the 10nm process node, or the 7nm process node and the process node progressing towards 5nm. The above-mentioned process nodes basically follow Moore's law, and transistors can be increased by 2 times in a specific area of each process node through component scaling design. But the key to being able to follow Moore's Law lies in the invention and implementation of 3D transistor structures (eg: gate around, tri-gate or FinFET). Furthermore, transistors with 3D shapes or structures do offer advantages such as high performance, low leakage current, and high reliability.

However, after the 45nm process node, the scaling of DRAM technology slows down, especially after the 25nm process node, the introduction of more than a dozen nanometers requires more than the history of DRAM predicted by Moore's Law Each process node takes much longer than two years. A key reason is that 3D DRAM uses a stacked capacitor structure, which requires a high-temperature process step after the transistor structure is formed. Therefore, it is difficult to control the source and drain of transistors in the 3D DRAM to be as shallow as required by transistor scaling rules. As a result, most DRAM products do not use the same process technologies that are widely used at logic process nodes below 20nm.

To make matters worse, when logic/system on chip (SoC) performance can be rapidly advanced through sub-10nm process technology and design technology, especially due to the use of 3D tri-gate transistor structure and improvement, so slowing down the evolution of DRAM technology will make the well-known Memory-Wall effect (actually DRAM-Wall) worse, Among other things, the memory wall reduces the data transfer rate between the logic circuit and the memory. The performance gap between data bandwidth and random access time is getting bigger and bigger, so traditional DRAM cannot be used as a carrier for providing data or storing data to logic/single-chip systems.

In order to solve the problem of the memory wall, the development of DRAM technology leads to 3D-DRAM technology, that is, High Bandwidth Memory (HBM). However, in the high-bandwidth memory standard issued by the Joint Electron Device Engineering Council (JEDEC), the voltage Vdd provided by the main supply voltage source to the DRAM is defined as 1.2V, where The main supply voltage source is an external power source of the DRAM. On the other hand, the voltage provided by the main power supply voltage source applied to the tri-gate transistor in the logic chip is 0.6 to 0.7V. As shown in FIG. 1C, the DRAM circuit 100 includes an input/output circuit 110 (including a signal level conversion circuit, a driving impedance tuning circuit, etc.), a peripheral circuit 120 (including a command/address decoder, etc.) and a DRAM core circuit 130 (including a DRAM cell array, etc.). Between the dynamic random access memory circuit 100 and the logic circuit 300, there is a physical layer circuit (sometimes referred to as a physical layer) 200, wherein the physical layer circuit 200 also includes an input/output physical layer circuit 210 (also includes signal bits Quasi conversion circuit, and driving impedance tuning circuit, etc.) and a logical physical layer circuit 220. In addition, the logic physical layer circuit 220 is used for communicating with a logic circuit 300 . Due to the slowdown of the process technology evolution of the DRAM circuit 100 and the leakage current problem, the voltage Va provided by the external power supply voltage source of the DRAM circuit 100 can be between 2.5V~1.1V. , but the voltage Va' provided by the external power supply voltage source of the logic circuit 300 can be between 0.9V~0.6V. For example, the voltage Va is an external voltage of the DRAM circuit 100, and the voltage Va can be used by the DRAM circuit 100 to generate various voltages, such as the aforementioned voltage VCCSA, voltage 1/2VCCSA, and Voltage VPP, etc., wherein the voltage level of the voltage VCCSA may be the same as or different from the voltage level of the voltage Va

Due to the difference between the voltage Va and the voltage Va', as shown in FIG. 1D, in a conventional DRAM circuit, the input/output circuit 110 of the DRAM circuit 100 will include an output potential conversion circuit and an input comparator, wherein the output potential conversion circuit is used to increase or decrease the voltage level of the output signal of the dynamic random access memory circuit 100 to a predetermined level, and the predetermined level is an entity The input/output layer circuit 210 of the layer circuit 200 is acceptable. In addition, the input comparator can compare the input signal from the physical layer circuit 200 with the reference voltage Vref, and convert it into a corresponding signal DQ. Similarly, as shown in FIG. 1E , the input/output physical circuit 210 also includes an input comparator and an output potential conversion circuit, wherein the output potential conversion circuit of the input/output physical circuit 210 is used to convert the output potential from the physical layer circuit 200 The voltage level of the output signal is adjusted up or down to a predetermined level acceptable to the I/O circuit 110 of the DRAM circuit 100 . The input comparator of the input/output physical circuit 210 can compare the input signal from the DRAM circuit 100 with another reference voltage Vref' and convert it into a corresponding signal DQ'. Therefore, because of the incompatibility between the voltage Va' provided by the external power supply voltage source of the DRAM circuit 100 and the voltage Va' provided by the external power supply voltage source of the logic circuit 300, resulting in optimization of energy efficiency and Difficulty with performance synchronization.

In addition, please refer to FIG. 1F. FIG. 1F is a schematic diagram illustrating waveforms of related signals of a conventional low-power DRAM unit during a write operation, wherein a write data XIO (such as a signal "ONE" or a high Potential signal) will be received by a data input circuit DI, and then sent to a global input/output path GIO with a heavy load, and the voltage level of the write data XIO in the global input/output path GIO is 1.1V (for example, the application In the DRAM cell sense amplifier voltage VCCSA) for example. The write data XIO on the global input/output path GIO will then be transferred to a data line sense amplifier 70, wherein the data line sense amplifier 70 transfers the write data XIO to the main data line path (ie, a data line DL and a complementary data line DLB). However, the main data line path still has a heavy load, and the voltage level of the write data XIO on the data line DL is also 1.1V. Then the write data XIO on the data line DL will be transmitted to a memory array 75, wherein the write data XIO will be stored to an associated storage node in the memory array 75 through the bit line BL. As shown in FIG. 1F , the voltage level of the write data XIO on the bit line BL is usually 1.1V, and the global input/output path GIO and the data line DL are part of the data path. In order to meet low power consumption, the voltage level of the write data XIO on the global input/output path GIO, the voltage level of the write data XIO on the data line DL, and the voltage level of the write data XIO on the bit line BL should be As low as possible, eg 1.1V. However, lower voltages stored on the associated storage nodes suffer from serious leakage current problems and cause stored data to become invalid.

An embodiment of the present invention provides a DRAM coupled to an external logic circuit and a main supply voltage source. The DRAM includes a first sustain voltage source and a DRAM core circuit. The first maintaining voltage source is used to generate a first voltage, wherein the first voltage is higher than the voltage level of a high potential signal applied in the DRAM. The DRAM core circuit has a DRAM unit, wherein the DRAM unit includes an access transistor and a storage capacitor. The storage capacitor is selectively coupled to the first sustain voltage source. The voltage level provided by the main power supply voltage source to the DRAM is the same or substantially the same as the voltage level provided by another main power supply voltage source to the external logic circuit.

In an embodiment of the present invention, the DRAM further includes an input/output circuit and a peripheral circuit between the I/O circuit and the DRAM core circuit, wherein the application An operating supply voltage of a drain of a transistor in the peripheral circuit is the same as the voltage level provided to the DRAM by the main supply voltage source.

In one embodiment of the present invention, an operating supply voltage applied to the drain of a transistor in the DRAM core circuit and the main supply voltage source are provided to the DRAM The voltage levels are the same, and the transistor in the DRAM core circuit is different from the access transistor.

In an embodiment of the present invention, the voltage level of the high potential signal applied in the DRAM is the same as the voltage level provided to the DRAM by the main power supply voltage source.

In an embodiment of the present invention, the DRAM further includes an I/O circuit and a peripheral circuit between the I/O circuit and the DRAM core circuit, wherein the The input/output circuit does not have an input comparison circuit and an output potential conversion circuit.

In an embodiment of the invention, the voltage level provided by the main power supply voltage source to the DRAM is between 0.9V and 0.5V.

In an embodiment of the present invention, the DRAM further includes a word line, wherein the word line is coupled to the gate of the access transistor, and the word line is in a first time interval and a second time interval is selected to turn on the access transistor, the second time interval is located after the first time interval, and during the second time interval, the first sustain voltage source is electrically coupled to the storage capacitor .

In an embodiment of the present invention, the first time interval is an access operation interval, and the second time interval is a recovery phase.

In an embodiment of the present invention, a kicking charge source is electrically coupled to a bit line of the DRAM during the access operation period.

Another embodiment of the present invention provides a DRAM coupled to an external logic circuit and a main supply voltage source. The dynamic random access memory includes a dynamic random access memory core circuit, an input/output circuit and a peripheral circuit. The DRAM core circuit has a DRAM unit, wherein the DRAM unit includes an access transistor and a storage capacitor. The input/output circuit is coupled to the external logic circuit. The peripheral circuit is arranged between the I/O circuit and the DRAM core circuit. The voltage level provided by the main supply voltage source to the DRAM is the same or substantially the same as the voltage level provided by another main supply voltage source to the external logic circuit, and the main supply voltage source provides The voltage level for the DRAM is not greater than 0.9V.

In an embodiment of the present invention, an operating supply voltage applied to a drain of a transistor in the peripheral circuit is the same as the voltage level provided to the DRAM by the main supply voltage source.

In one embodiment of the present invention, an operating supply voltage applied to the drain of a transistor in the DRAM core circuit and the main supply voltage source are provided to the DRAM The voltage levels are the same, and the transistor in the DRAM core circuit is different from the access transistor.

In an embodiment of the present invention, the voltage level of the high potential signal applied in the DRAM is the same as the voltage level provided to the DRAM by the main power supply voltage source.

In an embodiment of the present invention, the input/output circuit does not have an input comparison circuit and an output level conversion circuit.

In an embodiment of the present invention, the DRAM further includes a first sustain voltage source and a word line. The first maintaining voltage source is used to generate a first voltage, wherein the first voltage is higher than the voltage level of a high potential signal applied in the DRAM. The word line is coupled to the gate of the access transistor, wherein the word line is selected to turn on the access transistor during a first time interval and a second time interval, the second time interval is located at the After the first time interval, and during the second time interval, the first maintaining voltage source is electrically coupled to the storage capacitor.

In an embodiment of the present invention, the first time interval is an access operation interval, and the second time interval is a recovery phase.

Another embodiment of the present invention provides a memory system. The memory system includes a DRAM chip and a logic chip. The logic chip is electrically coupled to the DRAM chip. The voltage level provided to the DRAM chip by a main supply voltage source is the same or substantially the same as the voltage level provided by another main supply voltage source to the logic chip, and the main supply voltage source provides The voltage level for the DRAM chip is not greater than 0.9V.

In one embodiment of the present invention, the DRAM chip includes a DRAM circuit, and the logic chip includes a logic circuit and a physical layer circuit, which are provided to the DRAM chip The main supply voltage source provided to the DRAM circuit is also provided to the DRAM circuit, and the other main supply voltage source provided to the logic chip is also provided to the logic circuit and the physical layer circuit.

In an embodiment of the present invention, the memory system further includes a base chip, wherein the base chip is electrically coupled to the DRAM chip, and the main power supply voltage source is provided to the dynamic random access memory chip. The voltage level of the random access memory chip is the same or substantially the same as the voltage level supplied to the base chip by another main power supply voltage source.

In one embodiment of the present invention, the DRAM chip includes a DRAM circuit, the logic chip includes a logic circuit, and the base chip includes a physical layer circuit; wherein the dynamic The main supply voltage source of the random access memory chip is also provided to the dynamic random access memory circuit, the other main supply voltage source provided to the logic chip is also provided to the logic circuit, and to the base chip The main supply voltage source is also provided to the physical layer circuit.

In one embodiment of the present invention, the DRAM chip includes a DRAM unit and a first sustain voltage source, and the DRAM unit includes a storage capacitor and an access Transistor, the first sustain voltage source generates a first voltage, and the first voltage is higher than the voltage level of a high potential signal applied in the dynamic random access memory, wherein the first sustain voltage source is in the The access transistor is coupled to the storage capacitor before it is turned off.

In an embodiment of the present invention, the DRAM further includes an I/O circuit and a peripheral circuit between the I/O circuit and the DRAM unit, and the The input/output circuit does not have an input comparison circuit and an output potential conversion circuit.

In an embodiment of the present invention, the memory system further includes a physical layer circuit, wherein the physical layer circuit includes an input/output physical layer circuit, and the input/output physical layer circuit does not have an input comparison circuit and an output Potential conversion circuit.

Another embodiment of the present invention provides a dynamic random access memory. The DRAM includes a DRAM unit, a sense amplifier and a data path. The DRAM unit includes an access transistor and a storage capacitor. The sense amplifier is coupled to the DRAM unit through a bit line. The data path is coupled to the sense amplifier. During the process of a high potential signal being written into the storage capacitor, the voltage level of the high potential signal on the data path is lower than the voltage level of the high potential signal stored in the storage capacitor, and during the data path The voltage level of the high potential signal on the path is between 0.9V and 0.5V.

In one embodiment of the present invention, only after a predetermined time defined by the double data rate memory specification of the Joint Electron Device Engineering Council (JEDEC), the voltage of the high potential signal The level will be stored in the storage capacitor.

In an embodiment of the present invention, the data path includes a global I/O path and a data line, and the high potential signal on the global I/O path or on the data line The voltage level is between 0.7V and 0.5V.

Another embodiment of the present invention provides a dynamic random access memory. The DRAM includes a DRAM unit, a sense amplifier and a data path. The DRAM unit includes an access transistor and a storage capacitor. The sense amplifier is coupled to the DRAM unit through a bit line. The data path is coupled to the sense amplifier. The voltage level of read data corresponding to a high potential signal on the data path is higher than the voltage level of write data corresponding to another high potential signal on the data path.

In an embodiment of the present invention, the written data is stored in the storage capacitor, and a voltage level of the written data stored in the storage capacitor is higher than that of the written data on the data path voltage level.

In an embodiment of the present invention, the voltage level of the read data corresponding to the high potential signal on the data path is between 1.2V and 1.0V, and the voltage level corresponding to the other high potential on the data path The voltage level of the write data of the signal is between 0.9V and 0.5V.

Another embodiment of the present invention provides a dynamic random access memory. The DRAM includes a DRAM unit, a sense amplifier and a data path. The DRAM unit includes an access transistor and a storage capacitor. The sense amplifier is coupled to the DRAM unit through a bit line. The data path is coupled to the sense amplifier. During a read operation, a voltage amplitude on a global I/O path or on a data line is greater than a voltage amplitude on the global I/O path or on the data line during a write operation.

In an embodiment of the present invention, during the read operation, the voltage amplitude on the global input/output path or the data line is between 1.2V and 1.0V, and during the write operation, The voltage amplitude on the global input/output path or the data line is between 0.8V and 0.6V.

In one embodiment of the present invention, a control signal and an address signal applied to the DRAM operation have a voltage amplitude greater than that on the global I/O path or on the data line during the write operation. the voltage amplitude.

The present invention discloses a dynamic random access memory (Dynamic Random Access Memory, DRAM) with sustaining access architecture, wherein the sustaining voltage source is electrically coupled before the access transistors included in the dynamic random access memory unit are turned off. connected to the storage capacitor included in the dynamic random access memory unit, and the voltage level provided by the sustain voltage source is higher than a conventional high potential signal (i.e. a signal "ONE") voltage value, or lower than a conventional low potential signal (ie, a signal "ZERO") voltage value applied to the DRAM. When the DRAM performs other specific operations (such as auto-precharge phase, recovery phase (RESTORE phase), refresh phase (refresh phase, and pre-charge phase) will make the dynamic random access memory Access transistors in random access memory cells are turned on. Therefore, during the turn-on period of the access transistor, the sustain voltage source will be electrically coupled to the storage capacitor of the DRAM cell, so there is still leakage current through the memory even after the access transistor is turned off. However, the charge stored in the storage capacitor can still be maintained for a longer period of time than the existing DRAM architecture.

First embodiment of the present invention:

FIG. 2 is a schematic diagram illustrating waveforms of related signals during an access (read or write) operation of the DRAM unit of the first embodiment, wherein the DRAM unit can refer to FIG. 1A . As shown in FIG. 2, the DRAM is in a standby mode at the beginning, and the word line WL is biased at a standby voltage (-0.3V) to completely turn off the access transistor 11. In the first embodiment, the voltage VCCSA is 1.2V, the voltage VSS is 0V, the signal "ONE" (that is, a high potential signal) is 1.2V, and the signal "ZERO" (that is, a low potential signal, equal to The potential of the ground terminal) is 0V. In addition, in the first embodiment, the voltages on the bit line BL and the bit line BLB are equalized at 0.6V, that is to say, the voltages on the bit line BL and the bit line BLB are equalized between the signal " ONE” (1.2V) and the signal “ZERO” (0V).

At a time T0, the voltage on the word line WL will be raised from the standby voltage (-0.3V) to the voltage VPP (2.7V) to turn on the access transistor 11, wherein the voltage VPP (2.7V) is much higher than the voltage VCCSA ( 1.2V) and the threshold voltage VT (0.8V) of the access transistor 11, that is to say, the voltage VPP (2.7V) can provide sufficient driving force for the turned-on access transistor 11 to turn the signal "ONE" or Signal "ZERO" is transmitted to bit line BL and bit line BLB. Sense amplifier 20 is then enabled to amplify the signal on bit line BL and bit line BLB until the signal on bit line BL and bit line BLB is developed to a certain level. After a time T1, the read operation (the signal read from the DRAM cell on the bit line BL and the bit line BLB is amplified by the sense amplifier 20), or the write operation (external Writing the signal “ONE” or the signal “ZERO” to the sense amplifier 20 stores the correct signal to the storage capacitor 12 of the DRAM cell). Of course, besides the read operation and the write operation, other DRAM operations can also be performed after the time T1. That is to say, the DRAM unit can perform the access operation between the time T1 and a time T2, wherein the time interval between the time T1 and the time T2 is a first time interval.

During the recovery phase after time T2, the voltage VPP is continuously loaded from the word line WL to the dielectric material of the gate of the access transistor 11 to reasonably shorten the recovery phase time. In the recovery phase, a first sustaining voltage source is electrically coupled to the storage capacitor 12 of the DRAM unit, wherein the first sustaining voltage source can provide a voltage higher than VCCSA (1.2V) or the signal “ONE” (1.2V) of the first voltage VCCSA+M1, the first sustaining voltage source can be electrically connected or coupled to the sense amplifier 20 to be coupled to the storage capacitor 12 by turning on the switch 13 shown in FIG. 3A , and FIG. 3A is A schematic diagram illustrating that the sense amplifier 20 is selectively coupled to the first sustain voltage source. Additionally, as shown in FIG. 3A, during the recovery phase, a normal voltage source (VCCSA) is disconnected from the sense amplifier 20 by closing switch 14, and the first sustaining voltage source (VCCSA+M1) is connected by opening switch 13. The sense amplifier 20 . In addition, the voltage M1 can be a positive number so that a first voltage VCCSA+M1 is higher than the voltage VCCSA. In an embodiment of the present invention, the voltage M1 may be between 1/3 of the voltage VCCSA (1.2V) and 2/3 of the voltage VCCSA (1.2V), such as 0.6V. For example, when the storage capacitor 12 initially stores the signal “ONE” (1.2V), in the recovery phase, the first voltage VCCSA+M1 (1.2V+0.6V) is passed from the first sustain voltage source through the sense amplifier 20 sent and stored in the storage capacitor 12. That is to say, as shown in FIG. 2, before the access transistor 11 is turned off at a time T3 (wherein when the access transistor 11 is turned off, the voltage on the word line WL will be gradually pulled down from the voltage VPP to the standby voltage ( −0.3V)), the storage capacitor 12 can be supplied with a first voltage VCCSA+M1 higher than the signal “ONE” (VCCSA) by the first sustaining voltage source. Therefore, even though there is still leakage current through the access transistor 11 after the access transistor 11 is turned off, the charge stored in the storage capacitor 12 can still be maintained for a longer period of time than the conventional DRAM architecture. In one embodiment of the present invention, the first sustain voltage source (VCCSA+M1) may turn off the sense amplifier 20 after turning off the access transistor 11 or after the recovery phase. In addition, after the access transistor 11 is turned off or after the recovery phase, the bit line BL and the bit line BLB can be coupled to a bit line voltage source for providing a voltage VB1, so the bit line BL and the bit line The voltage on bit line BLB can be reset to voltage VB1 after switching off access transistor 11 or after the recovery phase (as shown in FIG. 2 ).

Further, in another embodiment of the present invention, in the recovery phase, a second sustain voltage source is coupled to the storage capacitor 12 of the DRAM unit. As shown in FIG. 3B, the second sustaining voltage source can provide a second voltage VSS-M2 lower than the voltage VSS (0V) or the signal “ZERO” (0V) to the sense amplifier 20 by turning on a switch 23, wherein FIG. 3B is a schematic diagram illustrating that the sense amplifier 20 is selectively coupled to the second sustain voltage source, and the voltage M2 is a positive voltage. In an embodiment of the present invention, the voltage M2 may be between 0.4V and 0.8V, such as 0.6V. In addition, when the second sustaining voltage source is coupled to the sense amplifier 20 during the recovery phase, the sense amplifier 20 cannot receive the voltage VSS, for example by closing the switch 24 . When the storage capacitor 12 initially stores the signal “ZERO”, in the recovery phase, the second voltage VSS-M2 (−0.6V) is transmitted from the second sustain voltage source through the sense amplifier 20 and stored to the storage capacitor 12 . That is to say, as shown in FIG. 2, before the access transistor 11 is completely turned off after time T3 (wherein when the access transistor 11 is turned off, the voltage on the word line WL will be gradually pulled down from the voltage VPP to the word line WL is at the standby voltage of the standby mode), the storage capacitor 12 can be provided with the second voltage VSS-M2 by the second sustaining voltage source (that is to say, before the time T3 closes the access transistor 11, the storage capacitor 12 stores the second voltage VSS-M2), wherein the second voltage VSS-M2 is lower than the signal “ZERO” (that is, the normal low level signal). In an embodiment of the present invention, the second sustain voltage source may turn off the sense amplifier 20 after turning off the access transistor 11 or after the recovery phase.

Of course, in another embodiment of the present invention, in the recovery phase, both the first sustain voltage source and the second sustain voltage source are coupled to the storage capacitor 12 of the DRAM unit. Therefore, before the voltage on the word line WL is pulled down from the voltage VPP to the standby voltage where the word line WL is in the standby mode, when the storage capacitor 12 initially stores the signal “ONE”, the first voltage VCCSA+M1 (1.2 V+0.6V) is stored in the storage capacitor 12; or when the storage capacitor 12 initially stores the signal “ZERO”, the second voltage VSS-M2 (−0.6V) is stored in the storage capacitor 12 .

Second embodiment of the present invention:

In order to reduce the leakage current and keep the charge stored in the storage capacitor 12 from leaking out through the access transistor 11 , the access transistor 11 is generally designed to have a very high threshold voltage. When the voltage VCCSA drops to 0.6V, in the design of the dynamic random access memory, the 7nm or 5nm process tri-gate (Tri-gate) transistor or fin field effect transistor will be applied to The peripheral circuit of the DRAM unit, wherein the threshold voltage of the transistor applied to the peripheral circuit will be correspondingly reduced, for example, the threshold voltage of the transistor applied to the peripheral circuit is reduced to 0.3V. However, in the second embodiment of the present invention, the threshold voltage of the access transistor 11 can be intentionally increased to 0.5V-0.6V according to the above concept of reducing the leakage current. Therefore, the leakage current flowing from the storage capacitor 12 can be greatly reduced by at least 3 to 4 orders of magnitude (if the S factor used to measure the leakage current is 68mV/decade and the threshold voltage of the access transistor 11 is increased to 0.6V, the leakage current flowing from the storage capacitor 12 will be 4 orders of magnitude lower than the leakage current of the Tri-gate transistor applied to the peripheral circuit; if the critical voltage of the access transistor 11 is increased to 0.5V, the storage The leakage current flowing out of the capacitor 12 will be 2~3 orders of magnitude lower than the leakage current of the Tri-gate transistor applied to the peripheral circuit). Therefore, in the second embodiment of the present invention, the threshold voltage of the access transistor 11 will be increased to close to the voltage VCCSA or at least exceed 80% of 0.6V. In addition, in the second embodiment of the present invention, the thickness of the dielectric material of the gate of the access transistor 11 (such as a fin field effect transistor or a tri-gate transistor) is still applied to the peripheral The dielectric materials of the gates of the transistors of the circuit have the same or almost the same thickness, so the high performance advantage of using the Tri-gate structure for the access transistor 11 can still be maintained.

4 is a schematic diagram illustrating waveforms of related signals during the access (read or write) operation of the DRAM unit disclosed in the second embodiment, wherein in the second embodiment, the signal "ONE" is 0.6V and the signal "ZERO" is 0V (that is, the potential of the ground terminal). After time T2 in the recovery phase, a first sustain voltage source is coupled to the storage capacitor 12 of the DRAM cell. The first sustain voltage source can provide a first voltage VCCSA+K higher than the voltage VCCSA (0.6V) or the signal “ONE” (0.6V), wherein the first sustain voltage source can be sensed by an electrical connection or coupling The amplifier 20 is coupled to the storage capacitor 12, and the voltage K is a positive voltage. In an embodiment of the present invention, the voltage K may be between 1/3 of the voltage VCCSA (0.6V) and 2/3 of the voltage VCCSA (0.6V), such as 0.3V or 0.4V. In addition, in another embodiment of the present invention, the voltage K can also be any value between 0.05V~0.4V, such as 0.05V, 0.1V, 0.2V, 0.3V or 0.4V. Therefore, when the storage capacitor 12 initially stores the signal “ONE” (0.6V), the first voltage VCCSA+K (0.6V+0.4V) is provided to the storage capacitor 12 during the recovery phase. That is to say, as shown in FIG. 4 , before the access transistor 11 is completely turned off at time T3 (wherein when the access transistor 11 is turned off, the voltage on the word line WL will be pulled down from the voltage VPP to the word line WL at The standby voltage of the standby mode), the storage capacitor 12 can be provided with the first voltage VCCSA+K by the first sustaining voltage source, wherein the first voltage VCCSA+K is higher than the signal “ONE” (0.6V). Therefore, when the storage capacitor 12 initially stores the signal “ONE” (0.6V), after the voltage on the word line WL is pulled up to the voltage VPP and before being pulled down to the standby voltage, the first voltage VCCSA+K (1V) can be stored in the storage capacitor 12 . In addition, in an embodiment of the present invention, after the recovery phase, the bit line BL and the bit line BLB can be coupled to the bit line voltage source for providing the voltage VB1, so the bit line BL and the bit line The voltage level on the cell line BLB will be reset to the voltage VB1 (as shown in FIG. 4 ).

In addition, as mentioned above, when the storage capacitor 12 initially stores the signal “ZERO”, after the voltage on the word line WL is pulled up to the voltage VPP and before being pulled down to the standby voltage, the second sustain voltage The second voltage provided by the source can be stored in the storage capacitor 12 , wherein the second voltage provided by the second sustain voltage source is lower than the storage signal “ZERO”, for example −0.4V.

The third embodiment of the present invention:

5 is a schematic diagram of a circuit and functional blocks for a precharge operation disclosed in a third embodiment of the present invention, wherein in the third embodiment, the voltage VCCSA is 0.6V and the voltage VSS is 0V (also is the potential of the terminal). In this precharge operation, all the DRAM cells connected to the selected word line in the storage area 5 (Sec 5) (hereinafter called the first DRAM cell) will be precharged , and other DRAM units (hereinafter referred to as second DRAM units) connected to unselected word lines in the storage area (such as Sec4, Sec6, etc.) will be in an idle state (idle state).

The sense amplifiers 41, 42 (coupled to the first DRAM unit) are connected to a third sustain voltage source according to a precharge pulse signal 30, wherein the third sustain voltage source can provide a third voltage VHSA (0.6V+K), so a stronger drain-to-source electric field can speed up recovery of the signal of the first DRAM unit during the pre-charge operation. The third voltage VHSA is higher than the voltage VCCSA (0.6V) by about several hundred millivolts (mV), such as 0.3V or 0.4V. In addition, before the selected word line is turned off (that is, before the access transistor in the first DRAM unit is completely turned off), the third voltage VHSA (0.6V+ 0.4V) can then be stored in the storage capacitor. On the other hand, because the sense amplifier coupled to the second DRAM cell does not receive the pre-charge pulse signal 30, it is still coupled to the voltage VCCSA.

In addition, please refer to FIG. 6. FIG. 6 is a schematic diagram illustrating the sense amplifier coupled to the first DRAM unit in the precharge operation, wherein the symbols used to assist in explaining FIG. 6 are as follows:

LSLP: a node connected to the sense amplifier of the first DRAM unit for receiving high voltage;

LSLN: a node connected to the sense amplifier of the first DRAM unit for receiving a low voltage;

Vpl: Common voltage on the circuit board;

SN: storage node;

WL: word line;

BL: bit line;

Vsg1,2: connected to the source gate voltage of the P-type metal oxide semiconductor transistor P1, P2 in the sense amplifier of the first DRAM unit;

Vgs3,4: connected to the gate source voltage of the N-type metal oxide semiconductor transistor N3, N4 in the sense amplifier of the first DRAM unit;

Vsg5,6: connected to the source gate voltage of the P-type metal oxide semiconductor transistor P5, P6 in the sense amplifier of the first DRAM unit;

Vgs7,8 : connected to the gate-source voltage of the N-type metal-oxide-semiconductor transistors N7 and N8 in the sense amplifier of the first DRAM unit.

Referring to FIG. 6 again, the word line WL100 is coupled to a plurality of storage nodes, such as storage nodes SN1 and SN9 . When the signal "ONE" (0.6V) is stored in the storage node SN1 connected to the word line WL100, and after the precharge command is turned on and the word line WL100 is selected (that is, the word line WL100 is turned on), the node LSLP The voltage on the node LSLN is boosted from 0.6V to the third voltage VHSA (1.0V) and the voltage on the node LSLN remains at 0V. Therefore, the PMOS transistor P1 is turned off and the source-gate voltage Vsg1 is 0V. Similarly, the PMOS transistor P2 is turned on and the source-gate voltage Vsg2 is raised from 0.6V to 1.0V, and the voltage of 1.0V is fully charged to the storage node SN1 through the bit line BL1. At this time, the NMOS transistor N3 is turned on and the gate-source voltage Vgs3 is also increased from 0.6V to 1.0V. In addition, the NMOS transistor N4 is turned off and the gate-source voltage Vgs4 is 0V.

When the signal "ZERO" (0V) is stored at the storage node SN9 connected to the word line WL100, and after the precharge command is turned on and the word line WL100 is selected, the voltage on the node LSLP is raised from 0.6V to The third voltage VHSA (1.0V) and the voltage on the node LSLN still maintain 0V. Therefore, the PMOS transistor P5 is turned on and the source-gate voltage Vsg5 is raised from 0.6V to 1.0V. Similarly, the P-type MOSFET P6 is turned off and the source-gate voltage Vsg6 is 0V. At this time, the NMOS transistor N7 is turned off and the gate-source voltage Vgs7 is 0V. In addition, the NMOS transistor N8 is turned on and the gate-source voltage Vgs8 is raised from 0.6V to 1.0V, and the voltage of the storage node SN9 is strongly restored to 0V through the bit line BL9. Of course, as mentioned above, in the precharge operation, when the storage capacitor shown in FIG. 6 initially stores the signal “ZERO”, the node LSLN can receive a voltage VLSN(0V-K) provided by other sustaining voltage sources. , wherein the voltage VLSN is lower than the signal “ZERO”, and in the third embodiment of the present invention, the voltage VLSN may be -0.4V. Then, in this precharge operation, the voltage of the storage node SN9 is strongly restored to -0.4V through the bit line BL9.

The present invention's first Four Example :

In the fourth embodiment of the present invention, as shown in FIG. 7, after time T0, the voltage on the word line WL rises to turn on the access transistor 11 of the DRAM cell. Then, during the access (reading or writing) of the DRAM unit, the activation command ACM is executed, and during the execution of the activation command ACM, by closing the switch 14 and opening the switch 13 as shown in FIG. 3A Connecting the voltage source providing the voltage VCCSA+ΔN to the sense amplifier 20 reduces the time interval tRCD, where the time interval tRCD (defined by the Double Data Rate memory specification of the Joint Electron Device Engineering Council (JEDEC) Definition), and the voltage VCCSA+ΔN is slightly higher than the voltage VCCSA. Therefore, between time T1 and time T2 (that is to say during the access operation), the voltage on the bit line BL will be pumped (or kicked) at least to the voltage VCCSA+ΔN during the execution of the enable command ACM. This pumping (or kicking) of the voltage on the bit line BL may be referred to as an active kick, and the active kick will speed up signal sensing. After executing the enable command ACM or the enable kick, during the subsequent access (read or write), the voltage VCCSA is connected to the sense amplifier 20, and then the voltage on the bit line BL will return to the voltage VCCSA. Similarly, in the recovery phase (or the pre-charging phase) after time T2, the first sustaining voltage source (or a voltage source providing a different sustaining voltage higher than the voltage VCCSA) is coupled to the DRAM again The storage capacitor 12 of the body unit. That is to say, in the recovery phase (or the pre-charge phase), by closing the switch 14 and opening the switch 13 as shown in FIG. A voltage source (providing a first voltage VCCSA+M1 ) is connected to the sense amplifier 20 . At this time, the voltage on the bit line BL will be pumped (or kicked) at least to the first voltage VCCSA+M1. This pumping (or kicking) of the voltage on the bit line BL may be referred to as a restore kick. Thus, before the voltage on the word line WL is pulled down to completely turn off the access transistor 11 of the DRAM cell, the first voltage VCCSA+M1 higher than the signal “ONE” (voltage VCCSA) is provided For the storage capacitor 12 of the DRAM unit, so even after the access transistor 11 of the DRAM unit is turned off, there is still leakage current through the access transistor 11, the DRAM The charge stored in the storage capacitor 12 of the cell can still be maintained for a longer period of time than the conventional DRAM architecture.

In an embodiment of the present invention, the voltage VCCSA+ΔN applied to the start-up kick is lower than the first voltage VCCSA+M1 applied to the recovery kick. In another embodiment of the present invention, the voltage VCCSA+ΔN applied to the start-up kick is the same or substantially the same as the first voltage VCCSA+M1 applied to the recovery kick. The voltage VCCSA+ΔN and the first voltage VCCSA+M1 can be generated by two different voltage sources respectively, or the voltage VCCSA+ΔN applied to the starting kick can also be generated by the first sustaining voltage source, but the adjustment and connection of the The duration of the first sustain voltage source to the bit line BL so that the voltage on the bit line BL is pumped (or kicked) to the voltage VCCSA+ΔN instead of being pumped (or kicked) to the first voltage VCCSA+ M1. Certainly, in the present invention, the first voltage VCCSA+M1, the voltage VCCSA+ΔN, and the voltage VCCSA can be generated or converted inside the DRAM, or provided by other voltage sources outside the DRAM or The first voltage VCCSA+M1, the voltage VCCSA+ΔN, and the voltage VCCSA are converted. Additionally, during the start-up kick, the voltage on bit line BL can be pumped (or kicked) to the voltage VCCSA+ΔN by a bootstrap circuit in which a capacitor is coupled Connected to the bit line BL. Both the above-mentioned voltage source and the bootstrap circuit can be regarded as the charging source, so the voltage on the bit line BL can be pumped (or kicked) by the charging source to the voltage VCCSA+ΔN.

Fifth Embodiment of the Invention :

FIG. 8A is a schematic diagram of waveforms of related voltages during operation of the DRAM cell disclosed in the fifth embodiment of the present invention. Similar to the fourth embodiment shown in FIG. 7, between time T1 and time T2, the activation command ACM is executed, and during the execution of the activation command ACM, the first sustaining voltage source (providing the first voltage VCCSA+M1) Connect sense amplifier 20. Therefore, during the execution of the enable command ACM, the voltage on the bit line BL will be pumped (or kicked up) at least to the first voltage VCCSA+M1. After the start command ACM is executed, the voltage VCCSA is connected to the sense amplifier 20, and then the voltage on the bit line BL will return to the voltage VCCSA. After the start command ACM, one (or more) read commands RC can be executed before time T2, and during the execution of the read command RC, the first sustain voltage source (providing the first voltage VCCSA+M1) is connected to the sense again Amplifier 20. Therefore, during the execution of the read command RC, the voltage on the bit line BL will be pumped (or kicked) at least to the first voltage VCCSA+M1. After the execution of the read command RC is finished, the voltage VCCSA is connected to the sense amplifier 20 by turning on the switch 14 and closing the switch 13 as shown in FIG. 3A , and then the voltage on the bit line BL will return to the voltage VCCSA. This pumping (or kicking) of the bit line BL during the execution of the read command RC will improve the signal development time. For example, in this fifth embodiment, the voltage VCCSA is 1.1V and M1 is 0.2V, then during the execution of the read command RC, the signal development time with the pumping (or kicking) will be longer than without the pumping (or kick) signal development time is about 20%~30% faster.

Similarly, in the recovery phase after the time T2, the voltage source providing the voltage VCCSA is disconnected from the sense amplifier 20 and the first sustaining voltage source (providing the first voltage VCCSA+M1) is connected to the sense amplifier 20. At this time, the bit The voltage on the primary line BL will be pumped (or kicked) at least to the first voltage VCCSA+M1. Thus, the first voltage VCCSA+M1 higher than the signal “ONE” (voltage VCCSA) is provided to the storage capacitor 12 of the DRAM cell. However, in another embodiment of the present invention, as shown in FIG. 8B, during the recovery phase after time T2, the voltage source providing voltage VCCSA is still connected to the sense amplifier 20 instead of the first sustaining voltage source connected to the sense amplifier 20. Amplifier 20.

In addition, in another embodiment of the present invention, as shown in FIG. 8C, during the execution of the start command ACM, the voltage on the bit line BL will not be pumped (or kicked) to the first voltage VCCSA+M1, But during the execution of the read command RC, the voltage on the bit line BL will be pumped (or kicked) to the first voltage VCCSA+M1. During this recovery phase after time T2, the first sustain voltage source (providing the first voltage VCCSA+M1) is connected to the sense amplifier 20, at which point the voltage on the bit line BL is at least pumped (or kicked) to the first voltage VCCSA+M1.

Sixth embodiment of the present invention :

FIG. 8D is a schematic diagram of waveforms of relevant voltages during operation of the DRAM cell disclosed in the sixth embodiment of the present invention. Similar to the fifth embodiment shown in FIG. 8A, between time T1 and time T2, an activation command ACM and at least one read command RC following the activation command ACM are executed, and between the activation command ACM and the read command During RC execution, the first sustain voltage source (providing the first voltage VCCSA+M1 ) is connected to the sense amplifier 20 by turning on the switch 13 as shown in FIG. 3A . In addition, during the execution of the enable command ACM and the read command RC, the second sustain voltage source (VSS-M2) is connected to the sense amplifier 20 by turning on the switch 23 as shown in FIG. 3B . Therefore, during the execution of the start command ACM and the read command RC, the voltage on the bit line BL will be pumped (or kicked) at least to the first voltage VCCSA+M1 and the voltage on the bit line BLB will be pumped at least sent (or kicked) to the second voltage VSS-M2. After completing the execution of the start command ACM and the read command RC, the voltage VCCSA is connected to the sense amplifier 20 by opening the switch 14 and closing the switch 13 as shown in FIG. 3A and by opening the switch 24 and closing the switch as shown in FIG. 3B 23 to connect sense amplifier 20 to voltage VSS, then the voltage on bit line BL will return to voltage VCCSA and the voltage on bit line BLB will return to voltage VSS.

Similarly, in the recovery phase after the time T2, the voltage source providing the voltage VCCSA and the voltage source providing the voltage VSS are disconnected by turning off the switch 14 shown in FIG. 3A and the switch 24 shown in FIG. 3B respectively. amplifier 20, and the first sustain voltage source (providing the first voltage VCCSA+M1) is connected to sense amplifier 20 by opening switch 13 shown in FIG. The sustain voltage source (providing the second voltage VSS-M2 ) is connected to the sense amplifier 20 . Thus, the voltage on bit line BL is pumped (or kicked) at least to the first voltage VCCSA+M1 and the voltage on bit line BLB is pumped (or kicked) to at least the second voltage VSS- M2.

FIG. 8E is a diagram illustrating the relationship between the voltage on the bit line BL and the kick period during the operation of the DRAM cell. The length of the kicking period K4 corresponding to the voltage on the bit line BL of the recovery (or the pre-charging) stage is longer than the length of the kicking period K1 of the voltage on the bit line BL corresponding to the start command ACM, or the kicking The kick period K4 is longer than the kick periods K2 and K3 corresponding to the voltage on the bit line BL of the read command RC. In addition, the length of the kick period K1 corresponding to the voltage on the bit line BL of the start command ACM is equal to the lengths of the kick periods K2 and K3 corresponding to the voltage on the bit line BL of the read command RC. Of course, during the kick period K1~K3, the voltage on the bit line BL can be pumped (or kicked) to the first voltage VCCSA+M1 or other voltage levels higher than the voltage VCCSA through a bootstrap circuit (boostrap circuit). bit (for example, voltage VCCSA+ΔN, where 0<ΔN<M1), wherein a capacitor in the bootstrap circuit is coupled to the bit line BL, and the bootstrap circuit is also called a pumping voltage source. Both the above-mentioned voltage source and the bootstrap circuit can be regarded as the charging source, so the voltage on the bit line BL can be pumped (or kicked) by the charging source to the first voltage VCCSA+M1 or the voltage VCCSA+ΔN. Similarly, the voltage on the bit line BLB can also be pumped (or kicked) to the second voltage VSS-M2 (or voltage VSS-ΔN, where 0<ΔN<M2).

Of course, in another embodiment of the present invention, the voltage VCCSA can be in the range of 0.9V~0.5V (such as 0.9V, 0.8V, 0.7V or 0.6V) or lower, and the first voltage VCCSA+M1 is still It can be in the range of 1.1V~2.5V (such as 1.1V, 1.2V, 1.35V, 1.5V, 1.8V, or 2.5V, etc.) to overcome the leakage current problem and keep the DRAM cell acceptable charge retention time. Therefore, according to an embodiment of the present invention, since the leakage current problem of the DRAM circuit is alleviated, even under the condition of slowing DRAM technology migration, The voltage level provided by a main power supply voltage source to the DRAM can still be reduced to 1.0V-0.5V or lower. Therefore, the voltage level provided by the main power supply voltage source to the DRAM is the same or substantially the same as the voltage level provided by another main power supply voltage source to the logic chip.

Seventh embodiment of the present invention :

FIG. 9A is a schematic diagram of a DRAM circuit 500 disclosed in the seventh embodiment of the present invention. As shown in FIG. 9A , the DRAM circuit 500 includes an input/output circuit 510 , a peripheral circuit 520 and a DRAM core circuit 530 . A physical layer circuit (or physical layer) 400 is located between the DRAM circuit 500 and a logic circuit 300 . The physical layer circuit 400 further includes an input/output physical layer circuit 410 and a logical physical layer circuit 420 . Usually the DRAM circuit 500 will be in a DRAM chip, and the actual layer circuit 400 and the logic circuit 300 will be arranged in another chip (such as a logic circuit) separated from the DRAM chip. chip). For example, the logic chip includes a memory controller, where the memory controller is logic circuit 300, and also includes physical layer circuitry (or physical layer circuitry) that interacts with the DRAM chip and the memory controller. )400.

In another embodiment of the present invention, the physical layer circuit 400 and the logic circuit 300 may be respectively disposed in two independent chips. For example, DRAM circuit 500 may comprise a plurality of DRAM chips stacked together. The stacked DRAM die is then placed on a base die (or interposer) containing physical layer circuitry (or physical layer) 400 . The logic circuit 300 is a digital circuit or a memory controller, and the logic circuit 300 is provided in another logic die separate from the base die.

According to an embodiment of the present invention, the voltage Vnew provided by the main power supply voltage source of the DRAM circuit 500 may be between 1.0V and 0.5V (or between 0.9V and 0.5V) or lower , which is exactly the same as the range of the voltage Va' provided by the main supply voltage source of the logic circuit 3000, where the voltage Va' has already been between 1.0V and 0.5V (or 0.9V and 0 . 5V) or lower. In addition, the voltage Vnew is an external voltage of the DRAM circuit 500, and the voltage Vnew can be used by the DRAM circuit 500 to generate various voltages applied to the peripheral circuit 520 or the DRAM core circuit 530. Voltages, such as the aforementioned voltage VCCSA, the first voltage VCCSA+M1, the voltage 1/2VCCSA, and the voltage VPP. The voltage level of the voltage VCCSA may be the same as or different from that of the voltage Vnew. In addition, there may be another voltage source outside the DRAM circuit 500 for generating a voltage Vhigh, and the voltage Vhigh is higher than the voltage Vnew, wherein the voltage Vhigh may be used to generate the voltage Vpp or the first voltage VCCSA+M1 In order to achieve the purpose of improving the conversion efficiency.

In addition, since the voltage Vnew is the same or substantially the same as the voltage Va', the output level conversion circuit (adjusting the voltage level of the output signal up or down) and the input/output circuit in the conventional DRAM circuit 100 The input comparator within 110 can be removed. Therefore, according to an embodiment of the present invention, as shown in FIG. 9B, since the input/output circuit 510 of the DRAM circuit 500 does not include the aforementioned output potential conversion circuit and input comparator, the input to other Data from DRAM circuits (such as peripheral circuit 520 ) or data output from other DRAM circuits (such as peripheral circuit 520 ) do not need to be converted or compared by I/O circuit 510 . In addition, the amplitude of data input to or output from other DRAM circuits (eg, the peripheral circuit 520 ) can be set as the amplitude of the voltage Vnew.

As mentioned above, the DRAM circuit 500 includes an input/output circuit 510 , a peripheral circuit 520 , and a DRAM core circuit 530 . The peripheral circuit 520 includes at least a command/address decoder and/or other circuits including transistors, and the DRAM core circuit 530 includes at least a dynamic random access memory cell array and/or other related circuits including transistors . In an embodiment of the present invention, the voltage level of an operation supply voltage applied to the drain of a transistor in the peripheral circuit 520 may be the same as the voltage level of the voltage Vnew. In addition, the voltage level of an operating supply voltage applied to the drain of a transistor in the DRAM core circuit 530 may also be the same as the voltage level of the voltage Vnew, and the DRAM core circuit The transistor in 530 is different from the access transistor 11. Certainly, the voltage level of the signal “ONE” or the high potential signal applied in the DRAM can also be the same as the voltage level of the voltage Vnew.

Similarly, according to an embodiment of the present invention, as shown in FIG. 9C, because the input/output physical layer circuit 410 of the physical layer circuit 400 can also remove the aforementioned output potential conversion circuit (change the voltage level of the output signal turn up or turn down) and input comparators, so data input to or output from other physical layer circuits (such as logical physical layer circuit 420) does not have to pass through the physical layer circuit The input/output circuit 410 of 400 converts or compares. In addition, the amplitude of data input to or output from other physical layer circuits (such as the logical physical layer circuit 420) can be set as the amplitude of the voltage Va' (ie, the voltage Vnew). .

Therefore, in the present invention, the voltage levels of different main power supply voltage sources of the logic circuit 300 , the physical layer circuit 400 and the DRAM circuit 500 may all be the same. If the DRAM circuit 500 is disposed in a DRAM chip, the physical layer circuit 400 and the logic circuit 300 will be disposed in another logic chip that is separate from the DRAM chip wherein, the voltage level of the main power supply voltage source of the DRAM chip can be the same as the voltage level of the main power supply voltage source of the logic chip.

In addition, in another embodiment of the present invention, the input/output physical layer circuit 410 and the DRAM circuit 500 of the physical layer circuit 400 are arranged in a DRAM chip, and the physical layer circuit The logic physical layer circuit 420 and logic circuit 300 of 400 are disposed in another logic chip. Again, the voltage level of the main power supply voltage source of the DRAM chip can be the same as the voltage level of the main power supply voltage source of the logic chip.

In addition, in another embodiment of the present invention, when the logic circuit 300, the physical layer circuit 400 and the DRAM circuit 500 are respectively arranged on a logic chip, a base chip (or interposer) and a DRAM If the memory chip is taken, the voltage level of the main power supply voltage source of the dynamic random access memory chip is the same as that of the main power supply voltage source of the base chip, and is also the same as the voltage level of the main power supply voltage source of the logic chip. The voltage levels are the same.

As mentioned earlier, it is necessary to reduce the write data XIO on the data path (global input/output path GIO and data line DL), on the bit line BL (bit line BLB), and/or the DRAM The voltage level on the storage node of the memory cell is taken for low power applications. However, lower voltages stored in the associated storage nodes suffer from serious leakage current problems, resulting in invalidation of stored data. In an embodiment of the present invention, increasing the voltage level of the bit line BL during the recovery phase can be applied to the write operation to save power. FIG. 10 is a schematic diagram illustrating relevant signal waveforms during a write operation of the DRAM unit in an embodiment of the present invention, and FIG. A schematic diagram of a circuit for selectively coupling the sense amplifier to two separate voltages VCCSA, VCCSAh during a write operation, wherein the voltage level of the voltage VCCSAh is higher than that of the voltage VCCSA. When the write data XIO shown in FIG. 1F (such as a signal "ONE" or a high potential signal) is input to the global input/output path GIO through the data input circuit DI, the voltage of the write data XIO on the global input/output path GIO The level will be kept at VCCSA (eg 0.7V) to save power. However, the voltage level of the written data XIO corresponding to the signal “ONE” (or a high potential signal) may be higher than the voltage VCCSA, such as the voltage VSSCAh. Then the data XIO written on the global input/output path GIO will be passed to the data line DL through the data line sense amplifier 70 . As shown in FIG. 10, the voltage level of the data XIO written on the data line DL is also maintained at the voltage VCCSA by the data line sense amplifier 70. For the purpose of power saving, in the embodiment of FIG. 10, the voltage VCCSA is Set to (but not limited to) 0.7V. Then the write data XIO on the data line DL will be transferred to the bit line BL in the memory array 75 . As shown in FIG. 11, when a word line WL66 corresponding to the storage node SN is selected to turn on an access transistor 66, in the memory array 75, two separate voltages VCCSA (for example, 0.7V) and voltage VCCSAh (eg, 1.1V) can be selectively coupled to the sense amplifier 80 at different times. After word line WL66 is selected, voltage VCCSA is first coupled to sense amplifier 80, and bit switch BS100 is turned on to write data (ie, signal "ONE") to access transistor 66, causing bit The voltage level on line BL is also raised to voltage VCCSA. Meanwhile, those skilled in the art should know that the control signals EN1 and EN2 are enabled and the control signal EN3 is disabled. As shown in FIG. 10, the voltage level on the bit line BL is maintained at the voltage VCCSA for a period of time, but after a predetermined time (period tWR (write recovery time)) ends, in this recovery phase, the bit line BL The voltage level will be raised to the voltage VCCSAh (or called the restore kick (restore kick)), where the period tWR is specified by the double data rate memory specification of the Joint Electron Device Engineering Council (JEDEC) Definition, and the period tWR is the period between the rising edge of the last write clock and the precharge command. In addition, the period tWR can ensure that the restore kick can only start after the write cycle is completed.

Therefore, as shown in FIG. 10, after the period tWR ends, the voltage level on the bit line BL will be raised (that is, the restore kick) to the voltage VCCSAh, wherein in the embodiment of FIG. 10, The voltage VCCSAh is equal to (but not limited to) 1.1V and higher than the voltage VCCSA. At this time, please refer to FIG. 10 and FIG. 11 at the same time. Before the word line WL66 corresponding to the storage node SN is turned off, the voltage VCCSAh will be coupled to the sense amplifier 80 and the bit line BL, and then to the storage node SN, so The voltage level on bit line BL will be raised from voltage VCCSA to voltage VCCSAh. Therefore, based on the restore kick (restore kick) to the voltage VCCSAh, even if the voltage levels on the global input/output path GIO and the data line DL are all at the voltage VCCSA during the write operation, there will still be sufficient The charge of is stored in the storage node SN. In addition, the PRC shown in FIG. 10 is a precharge command.

Since the voltage level on the bit line BL is raised from the voltage VCCSA (0.7V or other voltages lower than 1.1V) to the voltage VCCSAh (1.1V), the present invention can obviously overcome the leakage current problem of the prior art. That is to say, even if the voltage level of the written data XIO on the global input/output path GIO, the data line DL and the bit line BL drops to 0.7V, 0.6V or lower, because based on the restore kick (restore kick) To the voltage VCCSAh, there is sufficient charge stored on the relevant storage nodes, so the present invention still does not have the problem of leakage current and data failure. As shown in FIG. 12, during the write operation, the voltage level of the write data XIO on the global input/output path GIO, the data line DL and the bit line BL can be reduced to 0.7V (or even 0.6V or lower ), so the operating current will also be reduced. For example, when the voltage level of the write data XIO on the global input/output path GIO, the data line DL and the bit line BL drops from 1.1V to 0.7 V (35% reduction), the operating current will be reduced from 141 mA It is reduced to 35 mA, and the operating current of 141 mA corresponds to the situation that the voltage level of the write data XIO on the global input/output path GIO, the data line DL and the bit line BL is kept at 1.1V.

On the other hand, during the read operation, when the read data corresponds to the signal “ONE” (or a high potential signal), in one embodiment of the present invention, the read data is transmitted between the global input/output paths GIO and The voltage level on the data line DL may be higher than the voltage VCCSA, such as the voltage VSSCAh. For example, as shown in FIG. 12, the voltage level of the read data (corresponding to the signal "ONE") on the global input/output path GIO and the data line DL is set to 1.1V, which is higher than that of the write data (corresponding to signal "ONE") on the global input/output path GIO and the voltage level on the data line DL, wherein the write data (corresponding to the signal "ONE") is on the global input/output path GIO and the voltage level on the data line DL It is set to voltage VCCSA (for example, 0.7V). Similarly, the voltage levels of a control signal and an address signal applied to the DRAM operation are also set to 1.1V (when corresponding to signal “ONE”), which is higher than the write data (corresponding to signal “ONE”) is the voltage level on the global input/output path GIO and the data line DL.

Therefore, in the read operation, the voltage amplitude on the global input/output path GIO and the data line DL (or the data path) will be different from that in the write operation on the global input/output path GIO and the data line DL ( or the voltage amplitude on the data path). In particular, the voltage amplitude of the read data set (comprising the signal "ONE" and the signal "ZERO") on the global input/output path GIO and/or the data line DL is higher than that of the global input/output path GIO and/or the data line DL The voltage amplitude of the write data set (including the signal "ONE" and the signal "ZERO") on . In addition, in an embodiment of the present invention, the voltage amplitudes of the control signal and the address signal applied to DRAM operations (such as the read operation, the write operation, or other operations) will be different from or higher than the voltage amplitude on the data path during the write operation.

In summary, the present invention discloses a sustainable DRAM with a unified main power supply voltage source for the logic circuit. Before the access transistor of the DRAM cell is turned off (or the word line coupled to the DRAM cell is turned off), the signal "ONE" (or high potential signal) restores or stores the first voltage of the voltage level to the DRAM unit. After the access transistor is turned off, even if there is a leakage current through the access transistor, the charge stored in the storage capacitor can still be maintained for a longer period of time than the existing DRAM architecture. Since the leakage current problem of the DRAM circuit is alleviated, the voltage provided by the main supply voltage source of the DRAM can be reduced even in the presence of slowing DRAM technology evolution to 1.0V~0.5V or lower. Therefore, the voltage level provided by the main power supply voltage source to the DRAM is the same or substantially the same as the voltage level provided by another main power supply voltage source to the external logic circuit. In addition, energy efficiency can be optimized simultaneously because of the compatibility between the voltage level provided by the main supply voltage source to the DRAM and the voltage level provided by the other main supply voltage source to the external logic circuit Synchronized with performance, it not only improves the operation speed, but also saves the area and power consumption of the chip. Furthermore, since the voltage amplitude of writing data on the data path is lower than that of reading data on the data path, the current or power consumption of the writing operation will be reduced. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

11, 66: access transistor 12: storage capacitor 13, 14, 23, 24: switch 20, 41, 42, 80: sense amplifier 21: Voltage equalization circuit 30: Precharge pulse signal 70: Data Line Sense Amplifier 75: Memory array 100, 500: Dynamic random access memory circuit 110, 210, 510: input/output circuit 120, 520: Peripheral circuits 130, 530: Dynamic random access memory core circuit 141: clear circuit 142: switch circuit 143: Comparator circuit 200, 400: physical layer circuit 210, 410: input/output physical layer circuit 220, 420: logical physical layer circuit 300: logic circuit ACM: start command BL, BLB, BL1, BL9, BL1B, BL9B: bit lines BS100: bit switch DQ, DQ': signal DL: data line DLB: complementary data line DI: data input circuit EN1, EN2, EN3: control signal GIO: global input/output path K1, K2, K3, K4: during kicking LSLP, LSLN: Node N3, N4, N7, N8: N-type metal oxide semiconductor P1, P2, P5, P6: P-type metal oxide semiconductor crystal RC: read command Sec: storage area SN1, SN9, SN: storage nodes T0, T1, T2, T3: time tWR: time period VREF, Vref': reference voltage VCCSA, VSS, VBl, VPP, M1, M2, K, ΔN, VCCSAh: Voltage VT: critical voltage Vpl: common voltage VHSA: third voltage WL, WL00, WL66: word line XIO: write data

FIG. 1A is a schematic diagram illustrating the most common design of the DRAM cell. FIG. 1B is a schematic diagram illustrating waveforms of related voltages of the DRAM cell during an access (read or write) operation. FIG. 1C is a schematic functional block diagram illustrating a logic circuit, a physical layer circuit and a DRAM circuit in the prior art. FIG. 1D is a functional block diagram illustrating the input/output circuit of the DRAM circuit in the prior art. FIG. 1E is a functional block diagram illustrating an input/output physical layer circuit of the physical layer circuit in the prior art. FIG. 1F is a schematic diagram illustrating waveforms of related signals of a conventional low power DRAM cell during a write operation. FIG. 2 is a schematic diagram of waveforms of relevant voltages during access (read or write) operations of the DRAM cell disclosed in the first embodiment of the present invention. FIG. 3A is a schematic diagram illustrating that the sense amplifier is selectively coupled to a first sustain voltage source. FIG. 3B is a schematic diagram illustrating that a sense amplifier is selectively coupled to the second sustain voltage source. FIG. 4 is a schematic diagram of waveforms of relevant voltages during access (read or write) operations of the DRAM cell disclosed in the second embodiment of the present invention. Fig. 5 is a schematic diagram of the circuit and functional blocks for the pre-charging operation disclosed in the third embodiment of the present invention FIG. 6 is a schematic diagram illustrating a sense amplifier coupled to the first DRAM cell during the precharge operation. FIG. 7 is a schematic diagram of waveforms of related voltages during operation of the DRAM cell disclosed in the fourth embodiment of the present invention. FIG. 8A is a schematic diagram of waveforms of related voltages during operation of the DRAM cell disclosed in the fifth embodiment of the present invention. 8B is a schematic diagram of waveforms of related voltages during operation of the DRAM cell disclosed in another embodiment of the present invention. FIG. 8C is a schematic diagram of waveforms of related voltages during operation of the DRAM cell disclosed in another embodiment of the present invention. FIG. 8D is a schematic diagram of waveforms of relevant voltages during operation of the DRAM cell disclosed in the sixth embodiment of the present invention. 8E is a schematic diagram illustrating the relationship between the voltage on the bit line and the kick period during the operation of the DRAM cell. FIG. 9A is a schematic functional block diagram of a logic circuit, a physical layer circuit and a DRAM circuit disclosed by an embodiment of the present invention. FIG. 9B is a functional block diagram of the input/output circuit of the DRAM circuit disclosed by an embodiment of the present invention. FIG. 9C is a functional block diagram of the input/output physical layer circuit of the physical layer circuit disclosed by an embodiment of the present invention. FIG. 10 is a schematic diagram illustrating related signal waveforms during a write operation of the DRAM cell according to an embodiment of the present invention. FIG. 11 is a schematic diagram illustrating a circuit for selectively coupling the sense amplifier to two separate voltages during a write operation of the DRAM cell. FIG. 12 is a schematic diagram illustrating voltage amplitudes on the data path during the read operation and during the write operation.

70: Data Line Sense Amplifier

75: Memory array

BL, BLB: bit line

DL: data line

DLB: complementary data line

DI: data input circuit

GIO: global input/output path

XIO: write data

Claims (32)

A dynamic random access memory coupled to an external logic circuit and a main supply voltage source, comprising: a first sustain voltage source for generating a first voltage, wherein the first voltage is higher than the voltage level of a high potential signal applied in the dynamic random access memory; and A dynamic random access memory core circuit has a dynamic random access memory unit, wherein the dynamic random access memory unit includes an access transistor and a storage capacitor; wherein the storage capacitor is selectively coupled to the first sustain voltage source; The voltage level provided by the main power supply voltage source to the DRAM is the same or substantially the same as the voltage level provided by another main power supply voltage source to the external logic circuit. The dynamic random access memory as described in claim 1 further comprises an input/output circuit and a peripheral circuit between the input/output circuit and the dynamic random access memory core circuit, wherein the An operating supply voltage of a drain of a transistor in the peripheral circuit is the same as the voltage level provided to the DRAM by the main supply voltage source. The dynamic random access memory as described in claim 2, wherein an operation supply voltage applied to the drain of a transistor in the core circuit of the dynamic random access memory and the main supply voltage source are provided to the dynamic random access memory The voltage levels for accessing memory are the same, and the transistor in the DRAM core circuit is different from the access transistor. The dynamic random access memory as described in claim 3, wherein the voltage level of the high potential signal applied in the dynamic random access memory and the voltage provided by the main power supply voltage source to the dynamic random access memory same level. The dynamic random access memory as described in claim 1 further comprises an input/output circuit and a peripheral circuit between the input/output circuit and the core circuit of the dynamic random access memory, wherein the input/output The output circuit does not have an input comparison circuit and an output potential conversion circuit. The DRAM according to claim 1, wherein the voltage level provided by the main power supply voltage source to the DRAM is between 0.9V and 0.5V. The dynamic random access memory as described in Claim 1, further comprising a word line, wherein the word line is coupled to the gate of the access transistor, and the word line is connected to a word line in a first time interval A second time interval is selected to turn on the access transistor, the second time interval is located after the first time interval, and in the second time interval, the first sustaining voltage source is electrically coupled to the storage capacitor. The DRAM according to claim 7, wherein the first time interval is an access operation interval, and the second time interval is a recovery phase. The DRAM according to claim 8, wherein during the access operation period, a kicking charge source is electrically coupled to a bit line of the DRAM. A dynamic random access memory coupled to an external logic circuit and a main supply voltage source, comprising: A dynamic random access memory core circuit has a dynamic random access memory unit, wherein the dynamic random access memory unit includes an access transistor and a storage capacitor; an input/output circuit coupled to the external logic circuit; and a peripheral circuit arranged between the input/output circuit and the dynamic random access memory core circuit; Wherein the voltage level provided by the main power supply voltage source to the DRAM is the same or substantially the same as the voltage level provided by another main power supply voltage source to the external logic circuit, and the main power supply voltage source The voltage level provided to the DRAM is not greater than 0.9V. The dynamic random access memory as described in claim 10, wherein an operating power supply voltage applied to a drain of a transistor in the peripheral circuit and the main power supply voltage source are provided to the dynamic random access memory The voltage levels are the same. The dynamic random access memory as described in claim 11, wherein an operation supply voltage applied to the drain of a transistor in the core circuit of the dynamic random access memory and the main supply voltage source are provided to the dynamic random access memory The voltage levels for accessing memory are the same, and the transistor in the DRAM core circuit is different from the access transistor. The dynamic random access memory as claimed in claim 12, wherein the voltage level of the high potential signal applied in the dynamic random access memory and the voltage provided by the main power supply voltage source to the dynamic random access memory same level. The DRAM according to claim 10, wherein the input/output circuit does not have an input comparison circuit and an output potential conversion circuit. The dynamic random access memory as described in claim item 10, further comprising: a first sustain voltage source for generating a first voltage, wherein the first voltage is higher than the voltage level of a high potential signal applied in the dynamic random access memory; and a word line coupled to the gate of the access transistor, wherein the word line is selected to turn on the access transistor during a first time interval and a second time interval, the second time interval is located at After the first time interval, and during the second time interval, the first sustain voltage source is electrically coupled to the storage capacitor. The DRAM according to claim 15, wherein the first time interval is an access operation interval, and the second time interval is a recovery phase. A memory system comprising: a dynamic random access memory chip; and a logic chip electrically coupled to the dynamic random access memory chip; The voltage level provided by one of the main power supply voltage sources to the DRAM chip is the same or substantially the same as the voltage level provided by the other main power supply voltage source to the logic chip, and the main power supply voltage source The voltage level provided to the DRAM chip is not greater than 0.9V. The memory system as claimed in claim 17, wherein the DRAM chip includes a DRAM circuit, and the logic chip includes a logic circuit and a physical layer circuit for providing the DRAM The main supply voltage source of the memory die is also provided to the DRAM circuit, and the other main supply voltage source provided to the logic die is also provided to the logic circuit and the physical layer circuit. The memory system as described in claim 17, further comprising a base chip (based chip), wherein the base chip is electrically coupled to the DRAM chip, and the main power supply voltage source is provided to the DRAM The voltage level of the memory chip is the same or substantially the same as the voltage level provided to the base chip by another main power supply voltage source. The memory system of claim 19, wherein the DRAM chip includes a DRAM circuit, the logic chip includes a logic circuit, and the base chip includes a physical layer circuit; wherein there is provided The main supply voltage source to the DRAM chip is also provided to the DRAM circuit, the other main supply voltage source provided to the logic chip is also provided to the logic circuit, and to the The main supply voltage source of the base die is also provided to the physical layer circuitry. The memory system according to claim 17, wherein the DRAM chip includes a DRAM unit and a first sustain voltage source, and the DRAM unit includes a storage capacitor and An access transistor, the first sustain voltage source generates a first voltage, and the first voltage is higher than the voltage level of a high potential signal applied in the dynamic random access memory, wherein the first sustain voltage A source is coupled to the storage capacitor before the access transistor is turned off. The memory system according to claim 21, wherein the DRAM further comprises an input/output circuit and a peripheral circuit between the I/O circuit and the DRAM unit , and the input/output circuit does not have an input comparison circuit and an output potential conversion circuit. The memory system as described in claim 17, further comprising a physical layer circuit, wherein the physical layer circuit includes an input/output physical layer circuit, and the input/output physical layer circuit does not have an input comparison circuit and an output potential conversion circuit. A dynamic random access memory comprising: A dynamic random access memory unit, including an access transistor and a storage capacitor; a sense amplifier coupled to the DRAM unit through a bit line; and a data path coupled to the sense amplifier; Wherein in the process of a high potential signal being written into the storage capacitor, the voltage level of the high potential signal on the data path is lower than the voltage level of the high potential signal stored in the storage capacitor, and in the The voltage level of the high potential signal on the data path is between 0.9V and 0.5V. The dynamic random access memory as claimed in claim 24, wherein only after a predetermined time defined by the double data rate memory specification of an Electronic Equipment Engineering Joint Committee (Joint Electron Device Engineering Council, JEDEC), The voltage level of the high potential signal is stored in the storage capacitor. The dynamic random access memory as described in claim 24, wherein the data path includes a global I/O path (global I/O path) and a data line, and on the global I/O path or on the data The voltage level of the high potential signal on the line is between 0.7V and 0.5V. A dynamic random access memory comprising: A dynamic random access memory unit, including an access transistor and a storage capacitor; a sense amplifier coupled to the DRAM unit through a bit line; and a data path coupled to the sense amplifier; Wherein the voltage level of read data corresponding to a high potential signal on the data path is higher than the voltage level of write data corresponding to another high potential signal on the data path. The dynamic random access memory as claimed in claim 27, wherein the write data is stored in the storage capacitor, and a voltage level of the write data stored in the storage capacitor is higher than that on the data path The voltage level of the written data. The dynamic random access memory as described in claim 27, wherein the voltage level of the read data corresponding to the high potential signal on the data path is between 1.2V and 1.0V, and on the data path The voltage level of the write data corresponding to the other high potential signal is between 0.9V and 0.5V. A dynamic random access memory comprising: A dynamic random access memory unit, including an access transistor and a storage capacitor; a sense amplifier coupled to the DRAM unit through a bit line; and a data path coupled to the sense amplifier; During a read operation, a voltage amplitude on a global I/O path or on a data line is greater than a voltage amplitude on the global I/O path or on the data line during a write operation. The dynamic random access memory as described in claim 30, wherein during the read operation, the voltage amplitude on the global input/output path or the data line is between 1.2V and 1.0V, and at During the write operation, the voltage amplitude on the global I/O path or the data line is between 0.8V and 0.6V. The dynamic random access memory of claim 30, wherein voltage amplitudes of a control signal and an address signal applied to the dynamic random access memory operation are greater than that of the global input/output path during the write operation the voltage amplitude on or on the data line.

Images