JP2022183131A - Sustainable dram having main power supply voltage unified with logic circuit - Google Patents

Abstract

To disclose a sustainable DRAM having a main power supply voltage unified with an external logic circuit.SOLUTION: A DRAM circuit is configured to be coupled to an external logic circuit and a main power supply voltage source. The DRAM circuit has a first maintenance voltage generator and a DRAM core circuit. The first maintenance voltage generator generates a first voltage level higher than a voltage level corresponding to a signal ONE used in the DRAM circuit. The DRAM core circuit has a DRAM cell having an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to be selectively coupled to the first maintenance voltage generator. The voltage level of the main power supply voltage source to the DRAM circuit is equal to or substantially equal to the voltage level of the main power supply voltage source to the external logic circuit.SELECTED DRAWING: Figure 2

Description

The present invention relates to dynamic memory, and more particularly to sustainable dynamic memory having a main power supply voltage that is uniform or compatible with external logic circuits.

Most commonly used DRAM cells have a single access transistor with its source connected to a storage capacitor and its drain connected to a bitline. The bitlines are connected to a first stage of cross-coupled sense amplifiers which, through column switches, couple signals read from the cell array to the I/O lines (also known as data lines). ) to the second stage sense amplifier connected to . In a WRITE operation, the signal is driven by the I/O buffer to keep it constant on the data line and the data line is further pulled to write the correct signal to the storage capacitor through the access transistor. , to keep the data constant on the first stage sense amplifier. While the access transistor is in active mode (i.e., the access transistor is ON), it is responsible for READ operations or WRITE operations of correct data to the storage capacitor, while the access transistor is in inactive mode (i.e., the access transistor is ON). OFF) also avoids loss of the stored signal.

Access transistors are designed with high threshold voltages to minimize leakage current in the transistors. However, it presents the drawback of impairing its performance when the access transistor is turned ON. As a result, the wordline is bootstrapped or connected to a high VPP (usually from the wordline voltage source) to allow the access transistor to have a high drive capability for WRITE of the signal to the storage capacitor. is required. Such a high VPP is loaded through the wordline driver to the gate of the wordline or access transistor. Since VPP is the high voltage stress on the access transistor, the dielectric material of the transistor (e.g., oxide layer or high-k material) is exposed to the DRAM's other support or peripheral circuits (e.g., command decoders, address decoders, and so on). It must be designed thicker than that used in transistors used in I/O circuits, etc.). Access transistor design is therefore faced with the challenge of maintaining either high performance or high reliability, presenting a difficult trade-off between reliability and performance. Widely used access transistor designs focus more on achieving high reliability, but at the expense of access transistor performance.

In brief summary, for a conventional access transistor design, it has a high threshold voltage to reduce leakage current to help long retention time of charge retention on the storage capacitor, and a high word line voltage such as VPP. have a thick gate dielectric material to withstand the , sacrificing the performance of the access transistor. As a result, a WRITE or READ of signal ONE(1), which normally points to the VCC level, may take longer, or signal ONE may not be fully restored. That is, the WRITE time is longer to satisfy writing the full signal VCC completely to the storage capacitor.

A commonly used design of a DRAM cell can be shown in FIG. 1A. A DRAM cell includes an access transistor 11 and a capacitor 12 . The gate of access transistor 11 is coupled to a wordline (WL) and a cross-coupled sense amplifier 20 is coupled to access transistor 11 through a bitline (BL). The DRAM cell uses the access transistor 11 as a switch to control the charge from the bitline (BL) to be stored in the capacitor in WRITE mode or transferred to the bitline in READ mode. of DRAM cells are each connected to a bit line. In this example, in READ mode, signal ONE (assumed to be 1.2V, signal ONE is typically the cross-coupled sense and signal ZERO (assumed to be 0V, signal ZERO typically corresponding to the voltage level of VSS provided by cross-coupled sense amplifier 20), or , these signals ONE and ZERO are written externally to twist the sense amplifiers to store the correct signals in the cell in WRITE mode.

FIG. 1B shows the signal waveforms involved in most current DRAM access (READ or WRITE) operations. As an example, a 25-nanometer DRAM cell typically has the following parameters (enclosed in it) that are relevant to array design: bitline ONE voltage is 1.2V, wordline ON is 2.7V. , the wordline OFF has a voltage of about -0.3V, the threshold voltage of the cell is in the range of about 0.7-0.9V, and the dielectric of the access transistor is 2.7V ( Under current test stress, for an acceptable reliability margin, this figure goes up to 3.4V), and the word line driver device also has a thick gate dielectric. must be used, thus sacrificing performance.

As shown in FIG. 1B, initially the storage capacitor of the DRAM is in standby or inactive mode (i.e., the access transistor is OFF) and the voltage level of the wordline coupled to the gate of the access transistor is Standby negative voltage (-0.3V). The bitline (BL) and bitline bar (BLB) are equalized at half the VCCSA voltage level between the ONE level at VCCSA=1.2V and the ZERO level at 0V. When the DRAM cell enters active mode (ie, the access transistor is turned ON), the voltage level of the wordline is raised from the standby negative voltage (-0.3V) to VCCSA (1.2V) and the access transistor. threshold voltage VT (which may be 0.7 or 0.8 V) and the threshold voltage VT (which may be 0.7 or 0.8 V) of the access transistor. Provide a sufficiently large drive (eg 2.7V-1.2V-0.8V=0.7V). A bitline is coupled to the storage capacitor. The word line is continuously ON at such high voltage VPP for access operations (such as READ or WRITE). The access operation is followed by a RESTORE phase. During the RESTORE phase, the cross-coupled sense amplifier will recharge the storage capacitor based on the signal ONE or ZERO in the storage capacitor. After the RESTORE phase, the wordline is pulled down from VPP to the voltage of the wordline in standby mode (-0.3V) and the access transistors are in inactive mode.

This high VPP voltage stress causes access transistors to be designed with thicker gate oxides or gate insulators than those used for transistors in peripheral circuits, which can lead to short channel effects, ON-OFF ratios of transistor currents, for example. , and deterioration of swing slope, etc., degrading access transistor performance. Furthermore, although the threshold voltage is designed to be higher than that used in the peripheral circuit transistors, the leakage current in the access transistor in standby mode or inactive mode is still high, and the amount of stored charge for sensing is lower the Lower VCCSA (eg, 0.6V) in 12 nm or 7 nm processes will exacerbate the leakage problem in standby or inactive mode. Therefore, the main power supply voltage to DRAM or the VCCSA voltage in transitional DRAM should be maintained at a certain voltage level.

On the other hand, IC systems for high performance computing or artificial intelligence (AI) systems consist of multiple DRAM chips and logic chips. Logic chips may now be fabricated in silicon dies using 10-nanometer process nodes or 7-nanometer process nodes, and are moving towards 5-nanometer process nodes. These process nodes essentially follow Moore's Law with a device scaling design that doubles the number of transistors in a given area per process node. However, a significant contribution to being able to follow Moore's Law is due to the invention and implementation of 3D transistor structures (eg gate-around, tri-gate, or FINFET). 3D shaped or 3D structured transistors deliver high performance, low leakage, high reliability, and so on.

However, DRAM technology scaling is slowing after the 45nm process node, and the introduction of 1Xnm after the 25nm process node has happened in the history of DRAM following predictions made by Moore's Law. It takes much longer than two years. An important reason is that DRAM uses a stacked capacitor structure that requires high temperature processing steps after the transistor structure is formed, and therefore the source and drain junctions of the transistor are scaled to such an extent that the scaling laws of the transistor require it. It is difficult to control the shallowness of the As a result, most DRAM products do not use the same process technology that is widely used in logic processes for sub-20 nanometer process nodes.

To make matters worse, the slowed transition of DRAM technology is expected to slow the transition to logic when logic/SOC performance can be highly accelerated by sub-10-nanometer processing and design technologies, especially through the use and refinement of 3D tri-gate transistor structures. It exacerbates the well-known Memory-Wall effect (actually a DRAM wall) that slows data transfer between and memory. Both data bandwidth and random access time result in an ever-larger performance gap, and conventional DRAM cannot serve as a memory vehicle for providing or storing data to logic/SOC chips.

In order to solve the memory wall problem, DRAM technology development has led to a 3D-DRAM technology called High-bandwidth DRAM (HBM). However, in the HBM standard issued by the Electronic Device Technology Coalition (JEDEC), the main power supply voltage or main supply voltage Vdd for DRAM chips is set at 1.2V. Such main power supply voltages are external to the DRAM chip. On the other hand, the main power supply voltage of tri-gate transistors used in logic chips is 0.6-0.7V. As shown in FIG. 1C, the DRAM circuit 100 includes an I/O circuit 110 (including a signal level conversion circuit, a drive impedance adjustment circuit, etc.), a peripheral circuit 120 (including a command/address decoder, etc.), and a DRAM core circuit. 130 (including cell arrays, etc.). A physical layer circuit (sometimes referred to as a PHY layer) 200 exists between the DRAM 100 and the logic circuit 300 to communicate with the logic circuit 300 (e.g., memory controller, etc.), and the physical layer circuit 200 further provides an I/ 0 physical circuitry 210 (which also includes signal level conversion circuitry, drive impedance adjustment circuitry, etc.) and logic physical circuitry 220 in communication with logic circuitry 300 . Due to slow DRAM technology migration and leakage problems in DRAM circuit 100, the external main power supply voltage Va to DRAM circuit 100 may be in the range of 2.5V-1.1V, but the external The mains voltage Va' may be in the range 0.9V-0.6V, for example. The main power supply voltage Va is external to the DRAM circuit 100 and can be used by the DRAM circuit 100 to generate various voltage sources, such as the aforementioned voltage sources VCCSA, 1/2VCCSA, VPP. The level of VCCSA may be the same as or different from the level of Va.

Due to the difference between the main power supply voltage Va to the DRAM circuit 100 and the main power supply voltage Va' to the logic circuit 300, in the transitional DRAM circuit, as shown in FIG. , an output level conversion circuit for leveling up or leveling down the voltage level of the output signal from the DRAM circuit 100 to a predetermined level allowed by the I/O physical circuit 210 of the physical layer circuit 200. become. I/O 110 also includes an input comparator that compares an input signal from physical layer circuit 200 with a reference voltage Vref and converts it to a corresponding signal. Similarly, as shown in FIG. 1E, the I/O physical circuit 210 of the physical layer circuit 200 also sets the voltage level of the output signal from the physical layer circuit 200 to the predetermined value allowed by the I/O circuit 110 of the DRAM circuit 100 . , and further compares the input signal from the DRAM circuit 100 with another reference voltage Vref' and converts it to a corresponding signal. Contains a comparator. These mismatches in main power supply voltages between DRAM chips and logic chips lead to difficulties in energy efficiency optimization and performance synchronization.

See also FIG. 1F, which shows a conventional low power DRAM circuit block. Input write data XIO (eg, signal ONE or signal High) is received by data input circuit DI and then passed to heavily loaded global I/O path GIO. The voltage level of write data on the global I/O path GIO is, for example, 1.1 V (eg, VCCSA used in sense amplifiers of DRAM arrays). The write data on global I/O path GIO is then sent to data line sense amplifiers 70 which transfer the write data to the main data line path (ie, data line DL). However, the main data line path still has a heavy load as well, and the voltage level of the write data on the data line DL can also be 1.1V. The write data on the data lines DL is then sent to the memory array 75 where the write data is stored in the corresponding storage nodes via the bit lines BL. Normally, the voltage level of the write data on the bitline BL is 1.1V, as shown in FIG. 1F. Here, global I/O path GIO and data line DL are part of the data path. To meet low power consumption, the voltage level of write data on global I/O path GIO, data line DL, and bit line BL should be as low as possible, eg, 1.1V. However, if the voltage stored on the corresponding storage node is low, it may suffer from severe leakage problems and cause data corruption.

Accordingly, the present invention introduces a sustainable DRAM chip with a unified main power supply voltage with external logic circuits. According to one aspect of the invention, a DRAM chip has a first sustain voltage generator and a DRAM core circuit. A first sustain voltage generator produces a first voltage level higher than the voltage level corresponding to signal ONE used in the DRAM chip. A DRAM core circuit has a DRAM cell having an access transistor and a storage capacitor, the storage capacitor of the DRAM cell configured to be selectively coupled to the first sustain voltage generator. The voltage level of the main power supply voltage supply to the DRAM chips is the same or substantially the same as the voltage level of the main power supply voltage supply to the external logic circuits.

According to one aspect of the invention, the voltage level of the external main power supply voltage source to the DRAM chip is less than or equal to 0.9V, for example, the voltage level of the external main power supply voltage source to the DRAM chip is 0.9V-0. .5V or lower.

According to one aspect of the invention, the DRAM chip further comprises an I/O circuit and peripheral circuits between the I/O circuit and the DRAM core circuit, the I/O circuit comprising an input comparison circuit and an output It does not have a level conversion circuit.

According to one aspect of the invention, the operating supply voltage to the drain side of the transistors in the peripheral circuitry is at the same voltage level as the main power supply voltage source to the DRAM chip. Also, the operating supply voltage to the drain side of the transistors in the DRAM core circuitry that are not access transistors is at the same voltage level as the main power supply voltage source to the DRAM chip. Additionally, the voltage level corresponding to signal ONE used in the DRAM chip is the same as the voltage level of the main power supply voltage source to the DRAM chip.

According to one aspect of the present invention, the DRAM chip further includes an I/O circuit and a peripheral circuit between the I/O circuit and the DRAM core circuit, output data from the peripheral circuit to the I/O circuit. Signals are not leveled up or down by the I/O circuitry, and input data signals from external logic circuitry to the DRAM chip are not compared with reference voltages to generate corresponding signals by the I/O circuitry.

According to one aspect of the invention, the DRAM chip further includes a word line coupled to the gate terminal of the access transistor, the word line activating the access transistor for a first period of time and a second period of time after the first period of time. Selected to turn on, the first sustain voltage generator is electrically coupled to the storage capacitor of the DRAM cell for the second time period. The first period is the access operation period, and the second period is the restoration phase period. In addition, a kicking charge source is electrically coupled to the bitlines of the DRAM chip during access operations.

According to another object of the present invention, the invention provides a DRAM chip configured for coupling with external logic circuitry and a mains voltage supply. A DRAM chip has a DRAM core circuit, an I/O circuit, and peripheral circuits between the I/O circuit and the DRAM core circuit. The DRAM core circuitry has DRAM cells with access transistors and storage capacitors, and the I/O circuitry is configured to couple to external logic circuitry. The voltage level of the main power voltage source to the DRAM chip is the same or substantially the same as the voltage level of the main power voltage source to the external logic circuit, and the voltage level of the main power voltage source to the DRAM chip is 0.9V. It is below.

According to one aspect of the invention, the operating supply voltage to the drain side of the transistors in the peripheral circuitry is at the same voltage level as the main power supply voltage source to the DRAM chip. Also, the operating supply voltage to the drain side of the transistors in the DRAM core circuitry that are not access transistors is at the same voltage level as the main power supply voltage source to the DRAM chip. Additionally, the voltage level corresponding to signal ONE used in the DRAM chip is the same as the voltage level of the main power supply voltage source to the DRAM chip. Also, the I/O circuitry eliminates or omits the input comparator circuitry and output level conversion circuitry.

According to one aspect of the invention, the DRAM chip further includes a first sustain voltage generator and a wordline coupled to the gate terminal of the access transistor. A first sustain voltage generator produces a first voltage level higher than the voltage level corresponding to signal ONE used in the DRAM chip. The word line is selected to turn on the access transistor for a first period of time and a second period of time after the first period of time, and the first sustain voltage generator is applied to the storage capacitor of the DRAM cell during the second period of time. electrically coupled. The first period is the access operation period, and the second period is the restoration phase period.

Another object of the present invention is to provide a memory system having a DRAM chip and a logic chip electrically coupled to the DRAM chip and having a unified power supply voltage. The voltage level of the main power voltage source to the DRAM chip is the same or substantially the same as the voltage level of the main power voltage source to the logic chip, and the voltage level of the main power voltage source to the DRAM chip is 0.9V or less. is.

According to one aspect of the invention, a DRAM chip includes a DRAM circuit, and a logic chip includes a logic circuit and a physical layer circuit. A main power supply voltage source to the DRAM chip is supplied to the DRAM circuit, and a main power supply voltage source to the logic chip is supplied to the logic circuit and the physical layer circuit.

According to one aspect of the present invention, the memory system with unified power supply voltage further includes a base chip electrically coupled to the DRAM chip. The voltage level of the main power supply voltage supply to the DRAM chips is the same or substantially the same as the voltage level of the main power supply voltage supply to the base chip.

According to one aspect of the invention, a DRAM chip includes DRAM circuitry, a logic chip includes logic circuitry, and a base chip includes physical layer circuitry. A main power supply voltage source to the DRAM chip is provided to the DRAM circuits, a main power supply voltage source to the logic chip is provided to the logic circuits, and a main power supply voltage source to the base chip is provided to the physical layer circuits.

According to one aspect of the invention, a DRAM chip has a DRAM cell and a first sustain voltage generator. A DRAM cell has a storage capacitor and an access transistor, and a first sustain voltage generator produces a first voltage level higher than the voltage level corresponding to signal ONE used in the DRAM chip. A first sustain voltage generator is coupled to the storage capacitor of the DRAM cell before the access transistor of the DRAM cell is turned off.

According to one aspect of the invention, the DRAM chip further comprises an I/O circuit and peripheral circuits between the I/O circuit and the DRAM cell, the I/O circuit comprising an input comparison circuit and an output level circuit. It does not have a conversion circuit.

According to one aspect of the invention, the physical layer circuitry of the memory system includes I/O physical circuitry, and the I/O physical circuitry does not include input comparison circuitry and output level conversion circuitry.

Another embodiment of the present invention provides a DRAM chip. A DRAM chip has a DRAM cell having an access transistor and a storage capacitor, a sense amplifier coupled to the DRAM cell via a bitline, and a data path coupled to the sense amplifier. In the process of writing signal ONE to the storage capacitor, the voltage level of signal ONE on the data path is different from the voltage level of signal ONE stored in the storage capacitor.

According to one aspect of the invention, the voltage level of signal ONE on the data path is lower than the voltage level of signal ONE stored on the storage capacitor.

According to one aspect of the invention, the voltage level of signal ONE on the data path is between 0.9-0.6V.

According to another aspect of the invention, the voltage level of signal ONE is stored in the storage capacitor only after the expiry of the period tWR defined by JEDEC.

According to another aspect of the invention, the data path includes a global I/O path and a data line, and the voltage level of signal ONE on the global I/O path or data line is 0.7-0. between 5V.

Another object of the present invention is to provide a DRAM chip comprising a DRAM cell having an access transistor and a storage capacitor, a sense amplifier coupled to the DRAM cell via a bitline, and a sense amplifier. and a data path coupled to. The voltage level of read data corresponding to a signal ONE on the data path is higher than the voltage level of write data corresponding to another signal ONE on the data path.

According to one aspect of the invention, the voltage level of the read data corresponding to signal ONE on the data path is between 1.2-1.0V and the voltage level of the write data corresponding to another signal ONE on the data path. is between 0.8-0.5V.

According to another aspect of the invention, write data is stored in a storage capacitor, and the voltage level of the write data stored in the storage capacitor is higher than the voltage level of the write data on the data path.

According to another aspect of the invention, the voltage level of signal ONE is stored in the storage capacitor only after the expiry of the period tWR defined by JEDEC.

The present invention further provides a DRAM chip having a DRAM cell having an access transistor and a storage capacitor, a sense amplifier coupled to the DRAM cell via a bitline, and a data path coupled to the sense amplifier. The voltage swing on the global I/O paths or data lines in read operations is larger than the voltage swing on the global I/O paths or data lines in write operations.

According to another aspect of the invention, the voltage swing on the global I/O paths or data lines in read operations is between 1.2-1.0V and the global I/O paths or data lines in write operations is between 1.2-1.0V. The voltage swing on the line is between 0.8-0.6V.

According to another aspect of the invention, the voltage swings of control and address signals for DRAM operations are greater than the voltage swings on global I/O paths or data lines in write operations. 31. The DRAM chip of Claim 30.

These and other objects of the present invention will become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments illustrated in the various figures and drawings.

A commonly used design of a DRAM cell and an array sense amplifier is shown. The relevant signal waveforms for most current DRAM access (READ or WRITE) operations are shown. 1 shows functional blocks for logic circuits, physical layer circuits and DRAM circuits in a traditional design. Fig. 3 shows part of a functional block for the I/O circuitry of a DRAM circuit in a traditional design; 1 shows a portion of functional blocks for an I/O physical circuit of a physical layer circuit in a traditional design; Fig. 2 shows voltage swings on the data path in a conventional low power DRAM write operation; 4 shows relevant signal waveforms in a DRAM cell access (READ or WRITE) operation according to one embodiment of the present invention. Fig. 3 shows a schematic circuit of a sense amplifier selectively coupled to a first sustain voltage source higher than VCCSA; Fig. 3 shows a schematic circuit of a sense amplifier selectively coupled to a second sustaining voltage source below VSS; 4 shows relevant signal waveforms for a DRAM cell according to another embodiment of the present invention; FIG. 4 shows a functional block diagram of one embodiment of the present invention for precharge operation; 4 illustrates the operation of the sense amplifier for precharge operation in accordance with the present invention; 4 shows relevant signal waveforms in the operation of a DRAM cell according to another embodiment of the invention; FIG. 4 shows relevant signal waveforms in the operation of a DRAM cell with three kicks according to another embodiment of the present invention; FIG. FIG. 4 shows relevant signal waveforms in the operation of a DRAM cell with two kicks according to another embodiment of the present invention; FIG. FIG. 4 shows relevant signal waveforms in the operation of another DRAM cell with two kicks according to another embodiment of the present invention; FIG. FIG. 4 shows relevant signal waveforms in the operation of another 3-kick DRAM cell in accordance with another embodiment of the present invention; FIG. FIG. 4 shows the relationship between the kick period and the bitline signals in the operation of a DRAM cell according to one embodiment of the present invention; FIG. 1 shows functional blocks for logic circuitry, physical layer circuitry and DRAM circuitry according to the present invention. Fig. 3 shows part of a functional block for the I/O circuitry of a DRAM circuit according to the present invention; Fig. 3 shows part of the functional blocks for the I/O physical circuit of the physical layer circuit according to the invention; Figure 4 shows relevant signal waveforms in a WRITE operation of a DRAM cell according to another embodiment of the present invention; Fig. 3 shows a schematic circuit of a sense amplifier selectively coupled to two separate voltage sources in a WRITE operation of a DRAM cell; 4 shows voltage swings on the data path during write and read operations according to the present invention.

Detailed descriptions of the following described embodiments of the disclosed apparatus and methods are presented herein by way of illustration and not limitation, with reference to the drawings. Although specific embodiments have been illustrated and described in detail, it is to be understood that various modifications and changes can be made without departing from the scope of the appended claims. The scope of the invention is not limited to the number, materials, shapes, relative arrangements, etc. of these constituent components, which are disclosed simply as examples of embodiments of the invention.

The present invention discloses a DRAM having a sustainable storage architecture, in which a sustain voltage source is electrically coupled to the storage capacitor of the DRAM cell prior to turn-off of the access transistor, and the voltage level of the sustain voltage source is is higher than the voltage level of the normal signal ONE, or the voltage level of the sustain voltage source is lower than the voltage level of the normal signal ZERO. A DRAM operation (eg, an auto-precharge operation, a RESTORE phase, a precharge phase, etc.) causes the selected DRAM cell to turn on its access transistor. Therefore, by coupling the sustain voltage source to the storage capacitor of the DRAM cell during the turn-on stage of the access transistor, the storage capacitor is conventionally maintained after the turn-off stage of the access transistor even if there is leakage current in the access transistor. can last for a long period of time compared to other DRAM structures.

FIG. 2 shows relevant signal waveforms for a DRAM cell access (READ or WRITE) operation according to one embodiment of the present invention. Starting from the standby mode of the DRAM, the wordline WL is biased to -0.3V to turn off the access transistor 11 completely. In this embodiment, VCCSA is set to 1.2V and VSS is set to 0V. In this example, the level of signal ONE is 1.2V and the level of signal ZERO is 0V (GND). The bitlines (BL and BLB) are equalized at a voltage level of 0.6V between the signal ONE level at VCCSA=1.2V and the signal ZERO level at VSS=0V.

At T0, the word line voltage is ramped up from -0.3V to 2.7V, which is well above the VCCSSA of 1.2V and the access transistor threshold voltage of 0.8V, with the access transistor turned on. 11 provide sufficient drive to transfer either signal ONE or ZERO to the bit lines. A sense amplifier 20 is activated to amplify the signal across the bitline (BL) and bitline bar (BLB) until the signal develops to a constant magnitude. After T1, a READ operation (by amplifying the signal carried by the cell signal onto the bitlines) or a WRITE operation (these signals ONE and ZERO are written externally to cause the sense amplifier 20 to twist, store the correct signal in the DRAM cell). Of course, besides READ or WRITE, other DRAM operations may be performed after T1. That is, the DRAM cell is accessible during the period between T1 and T2.

In the RESTORE phase after T2, the dielectric of access transistor 11 is still subject to VPP from the wordline for a reasonably short restore time. During this RESTORE phase, a first sustain voltage source is intentionally coupled to the capacitors of the DRAM cells. The voltage level of the first sustaining voltage source is higher than VCCSA of 1.2V (or the voltage level of signal ONE). This is shown in FIG. 3A, which shows a schematic circuit of sense amplifier 20 selectively coupled to a first sustain voltage source. It may be done by coupling (eg, by turning on switch 13, etc.). During this RESTORE phase, the original VCCSA voltage source is disconnected from the sense amplifiers (eg, by turning off switch 14) and the first sustaining voltage source (VCCSA+M1) is switched to the sense amplifiers 20, as shown in FIG. 3A. connected to M1 may be a positive number such that the first sustaining voltage source (VCCSA+M1) is higher than VCCSA. In one example, M1 may be in the range of 1/3 VCCSA to 2/3 VCCSA, such as 0.6V. For example, when signal ONE is originally in the storage capacitor, a voltage level of 1.2V+0.6V from the first sustain voltage source is supplied to storage capacitor 12 through sense amplifier 20 during this RESTORE phase. . That is, prior to the turn-off of access transistor 11 at T3 in FIG. , a voltage level of a first sustaining voltage source higher than the voltage level of the normal signal ONE (VCCSA). Therefore, even with leakage current in access transistor 11, after access transistor 11 is turned off, storage capacitor 12 can sustain for a longer period of time compared to conventional DRAM structures. In one embodiment, the first sustain voltage source (VCCSA+M1) may be disconnected from sense amplifier 20 after access transistor 11 is turned off, or after the RESTORE phase. Additionally, as shown in FIG. 2, the bitline (BL) can be coupled to a bitline voltage source having a voltage level of Vbl such that the voltage level of the bitline (BL) is reset to Vbl. The switches 13 and 14 shown in FIG. 3A are PMOS transistors and from a layout point of view it is necessary to provide an additional N-well to accommodate these PMOS transistors. To simplify the layout, switches 13 and 14 may be MNOS transistors, with these NMOS transistors located in the p-substrate. However, doing so requires a higher voltage to fully turn on the NMOS transistor.

In another embodiment, during the RESTORE phase after T2, a second sustain voltage source is intentionally coupled to the capacitors of the DRAM cells during the RESTORE phase. The voltage level of the second sustaining voltage source is lower than the voltage source VSS (0V or the voltage level of signal ZERO). This can be done by connecting a second sustaining voltage source (VSS-M2) to sense amplifier 20 (eg, by turning on switch 23, etc.), as shown in FIG. 3B. FIG. 3B shows a schematic circuit of a sense amplifier selectively coupled to a second sustaining voltage source (VSS-M2) below VSS, where M2 can be a positive number. In one example, M2 may be in the range of 0.4V-0.8V, such as 0.6V. Of course, when the second sustaining voltage source is coupled to sense amplifier 20 during the RESTORE phase, voltage source VSS is disconnected from sense amplifier 20 (eg, by turning off switch 24, etc.). When signal ZERO is originally in storage capacitor 12, a voltage level of -0.6V is provided to the storage capacitor during this RESTORE phase. That is, prior to the turn-off of access transistor 11 at T3 in FIG. 2 (i.e., wordline WL is pulled down from VPP to the wordline voltage in standby mode), storage capacitor 12 receives the normal voltage level of signal ZERO ( A voltage level of a second sustaining voltage source lower than VSS) is provided. In one embodiment, the second sustain voltage source (VSS-M2) may be disconnected from sense amplifier 20 after access transistor 11 is turned off, or after the RESTORE phase.

Of course, in another embodiment, both the first and second sustaining voltage sources may be intentionally coupled to the capacitors of the DRAM cells during the RESTORE phase. Thus, if signal ONE was originally on the storage capacitor before word line WL was pulled down from VPP to the word line voltage in standby mode, a voltage level of 1.2V+0.6V would be stored on the storage capacitor and signal ZERO would be stored. is originally on the storage capacitor, a voltage level of -0.6V is stored on the storage capacitor.

In order to maintain the stored charge without leakage through the access transistor, access transistors are typically designed with very high threshold voltages to reduce leakage current. When VCCSA is lowered to 0.6V, 7nm or 5nm process tri-gate or FinFET transistors are employed in the peripheral circuitry of the DRAM design, and accordingly the threshold voltage of these transistors is lowered to, for example, 0.3V. can be scaled such that In this embodiment, the threshold voltage of the access transistor can be intentionally raised to 0.5-0.6V. Then the leakage current from the storage capacitor drops sharply by at least 3 to 4 decades (=0.6-0.3 to 0.3V, if the S-factor is 68mV/decade, the leakage is reduced to the peripheral tri-gate It can be reduced 4 decades below that of the device, and if the threshold voltage is raised to 0.5 V, the leakage current should be 2 to 3 decades). It is proposed to raise the threshold voltage to near VCCSA or at least 80% above 0.6V. In embodiments, the gate dielectric thickness of the access transistor (such as a FinFET or tri-gate transistor) is still maintained to that of the peripheral transistor without increasing its thickness, which is the advantage of using a tri-gate structure. Performance benefits can be maintained.

FIG. 4 shows relevant signal waveforms for a DRAM cell according to another embodiment of the present invention. In this example, the level of signal ONE is 0.6V and the level of signal ZERO is 0V (GND). In the RESTORE phase after T2, the first sustain voltage source is intentionally coupled to the capacitors of the DRAM cells during the RESTORE phase. The voltage level of the first sustaining voltage source is higher than VCCSA of 0.6V (or the voltage level of signal ONE). This can be done by connecting a first sustain voltage source (VCCSA+K) to the sense amplifier, where K can be a positive number. In one example, K may be in the range of 1/3 VCCSA to 2/3 VCCSA, such as 0.3V or 0.4V. Thus, when the 0.6V signal ONE was originally in the storage capacitor, a voltage level of 0.6V+0.4V is provided to the storage capacitor during this RESTORE phase. That is, before the access transistor is turned off at T3 in FIG. 4 (i.e., the wordline WL is pulled down from VPP to the wordline voltage in standby mode), the storage capacitor is charged to the normal voltage level of signal ONE (0.6V). A voltage level of a first sustaining voltage source higher than (VCCSA) is provided. Therefore, after the word line WL is pulled to VPP and before the word line is pulled to standby mode or inactive mode, a voltage level of 1V is stored on the storage capacitor when signal ONE was originally on the storage capacitor. be done. In one embodiment, after the RESTORE phase, as shown in FIG. 4, the bitline (BL) and bitline bar (BLB) voltage levels are reset to Vbl such that the bitline (BL) voltage level and the bitline bar (BLB) voltage level are reset to Vbl. A line bar (BLB) may be coupled to a bitline voltage source having a voltage level of Vbl.

Of course, before the wordline WL is pulled down from VPP to the wordline voltage in standby mode, the voltage level of the second sustaining voltage source is stored if the signal ZERO was originally on the storage capacitor, as described above. It can be stored on a capacitor, and the voltage level of the second sustaining voltage source is lower than the voltage level of signal ZERO, eg, -0.4V.

FIG. 5 shows another embodiment of a circuit and functional block diagram for precharge operation. In this embodiment, VCCSA is set to 0.6V and VSS is set to 0V. In a precharge operation, all DRAM cells connected to the selected word line(s) in memory section 5 ("Sec5") are precharged and other memory sections (eg "Sec4", "Sec4", " Sec6'', etc.) are idled.

Sense amplifiers 41 and 42 coupled to the DRAM cells connected to the selected wordline(s) are kicked by precharge kicker 30 to a third sustaining voltage source VHSA (0.6V+K), As a result, a stronger drain-source electric field can accelerate signal restoration to the cell. A third sustaining voltage source VHSA is higher than VCCSA (0.6V) by about several hundred mV, for example 0.3V or 0.4V. Furthermore, before the selected word line(s) is turned OFF (i.e., the access transistors of the DRAM cells coupled to the selected word line(s) are turned OFF): A voltage level of 0.6V+0.4V, which is higher than the voltage level of the original signal ONE, can be stored on the storage capacitor. On the other hand, the sense amplifiers coupled to the DRAM cells connected to the unselected wordline(s) are not kicked up and are still coupled to VCCSA.

FIG. 6 describes the operation of the sense amplifier for the precharge phase, the meanings of the symbols used in FIG. 6 are as follows:
VCCSA: bit line sense amplifier voltage VHSA: third sustain voltage source LSLP: selected bit line sense amplifier high voltage LSLN: selected bit line sense amplifier low voltage Vpl: plate voltage SN: storage node WL: word line BL : bit lines Vsg1, Vsg2: source-gate voltages of P1, P2 Vgs3, Vgs4: gate-source voltages of N3, N4 Vsg5, Vsg6: source-gate voltages of P5, P6 Vgs7, Vgs8: gate-source of N7, N8 Voltage.

Referring to FIG. 6, wordline WL100 is coupled to a plurality of storage nodes, such as SN1 and SN9. After the precharge command is issued and the word line WL100 is selected (ie, the word line is turned ON) when the signal ONE (0.6V) is stored on the storage node SN1 connected to the word line WL100. , the LSLP of the sense amplifier is tied to VHSA (1.0V), so LSLP is kicked from 0.6V to 1.0V and LSLN remains at 0V. Therefore, transistor P1 of the sense amplifier is OFF and Vsg1=0V. Also, sense amplifier transistor P2 is ON, Vsg2 is kicked from 0.6V to 1.0V, and 1.0V is fully charged to storage node SN1 through bit line BL1. Meanwhile, the sense amplifier transistor N3 is ON and Vgs3 is also kicked from 0.6V to 1.0V. Also, the transistor N4 of the sense amplifier is OFF and Vgs4 is 0V.

When a signal ZERO (0V) is stored on storage node SN9 connected to word line WL100, the sense amplifier is coupled to VHSA (1.0V) after a precharge command is issued and word line WL100 is selected. , so LSLP is kicked from 0.6V to 1.0V and LSLN remains at 0V. Therefore, sense amplifier transistor P5 is ON and Vsg5 is kicked from 0.6V to 1.0V. Also, the transistor P6 of the sense amplifier is OFF and Vsg2 is 0V. On the other hand, the transistor N7 of the sense amplifier is OFF and Vgs7 is 0V. Also, sense amplifier transistor N8 is ON, Vgs8 is kicked from 0.6V to 1.0V, and 0V is strongly restored to storage node SN9 via bit line BL9. Of course, as mentioned above, when signal ZERO is originally on the storage capacitor, LSLN can be coupled to another sustain voltage source VLSN(0V−K) during the precharge phase. VLSN is lower than the voltage level of signal ZERO, in which case VLSN may be -0.4V. Then, in the precharge phase, -0.4V is strongly restored to storage node SN9 via bit line BL9.

In another embodiment, as shown in FIG. 7, after T0, the wordline voltage is ramped up to turn on the access transistor of the DRAM cell. And there are active commands to be executed on normal READ or WRITE accesses of the DRAM. To reduce tRCD as defined by JEDEC, a corresponding voltage slightly higher than VCCSA (such as VCCSA + ΔN) may be connected to the sense amplifier during execution of an active command (turning off switch 14 shown in FIG. 3A and by turning switch 13 on). Such a voltage level or voltage source is coupled to the bitlines during the period between T1 and T2 (ie, the access operation period). Accordingly, the corresponding voltage (VCCSA+ΔN) can be connected to the sense amplifier according to the active command. Therefore, the signal on the bitlines is pumped (or kicked) to at least VCCSA+ΔN during active command execution. Such a pump or kick in the bitline signal may be called an active kick. Such an active kick to the bitline speeds up signal sensing. After execution of an active command or active kick, the normal voltage source VCCSA is connected to the sense amplifiers and the signal on the bitlines returns to VCCSA on subsequent READ or WRITE operations. Similarly, in the RESTORE (or precharge) phase after T2, the first sustain voltage source VCCSA+M1 (or a different sustain voltage higher than VCCSA) is recoupled to the capacitors of the DRAM cells during this RESTORE phase. That is, during this RESTORE (or precharge) phase, the original VCCSA voltage source is disconnected from the sense amplifiers (eg, by turning off switch 14 shown in FIG. 3A), and the first sustaining voltage source VCCSA+M1 is turned off. It is connected to sense amplifier 20 (eg, by turning on switch 13 shown in FIG. 3A). Bitline signals are pumped (or kicked) to at least VCCSA+M1. Such a pump or kick in the bitline signal can be called a restore kick. Therefore, before the wordline WL is pulled down to completely turn off the access transistor of the DRAM cell, the storage capacitor of the DRAM cell is supplied with a first sustaining voltage source higher than the normal voltage level of signal ONE (VCCSA). , the storage capacitor of a DRAM cell can sustain a longer period of time compared to conventional DRAM structures, even if there is leakage current in the access transistor.

In one embodiment, the corresponding voltage (VCCSA+ΔN) used for the active kick is lower than the first sustain voltage (VCCSA+M1) used for the restore kick. In another embodiment, the corresponding voltage (VCCSA+ΔN) used for the active kick is the same or substantially the same as the first sustain voltage (VCCSA+M1) used for the restore kick. The corresponding voltage (VCCSA+ΔN) and the first sustain voltage (VCCSA+M1) can each be generated from two different voltage sources. Alternatively, the corresponding voltage (VCCSA+ΔN) used in the active kick to kick the bitline voltage can be generated from the first sustaining voltage source (VCCSA+M1), but the bitline is not (VCCSA+M1) The duration of connecting the first sustaining voltage source (VCCSA+M1) to the bitline is adjusted so that it is only pumped or kicked to the corresponding voltage (VCCSA+ΔN). Of course, in the present invention, voltage (VCCSA+M1), voltage (VCCSA+ΔN), and voltage (VCCSA) may be generated or converted inside the DRAM, or supplied or converted from other voltage sources external to the DRAM chip. may be Also, raising the bitline to the voltage level VCCSA+ΔN or VCCSA+M1 during an active kick can be done by a bootstrap circuit, where the charge on the capacitor in the bootstrap circuit is coupled to the bitline. A charge source, whether it be a voltage source or a bootstrap circuit, can be considered as a charge source, and thus a bitline can be kicked or pumped to the voltage level VCCSA+ΔN or VCCSA+M1 during an active kick.

FIG. 8A shows relevant signal waveforms for the operation of a DRAM cell according to another embodiment of the invention. During the period between T1 and T2, there is an active command to execute and the corresponding first sustain voltage source (VCCSA+M1) can be connected to the sense amplifier during active operation. Therefore, the bitline signal is pumped (or kicked) to at least VCCSA+M1 during an active command. After execution of the active command, the normal voltage source VCCSA is connected to the sense amplifiers and the signal on the bitlines returns to VCCSA. After the active command, one (or more) read commands can be executed before T2, and the signal on the bitlines is pumped (or kicked) to at least VCCSA+M1 during the read command. A sustain voltage source of 1 (VCCSA+M1) may be connected back to the sense amplifier during a read command. After execution of the read command, the normal voltage source VCCSA is again connected to the sense amplifier (by turning off switch 13 and turning on switch 14 shown in FIG. 3A), and the signal on the bitline returns to VCCSA.
Such a kick to the bitlines during read commands improves signal development time. For example, if VCCSA is 1.1V and M1 is 0.2V, the signal development time with kick during a read command is about 20%-30% faster than without kick.

Similarly, in the RESTORE phase after T2, the original VCCSA voltage source is disconnected from the sense amplifier, the first sustain voltage source VCCSA+M1 is connected to sense amplifier 20, and the signal on the bitlines is pumped (or kicked) to at least VCCSA+M1. be done. Thus, the storage capacitor of the DRAM cell is supplied with the voltage level of the first sustaining voltage source, which is higher than the voltage level of the normal signal ONE (VCCSA). However, in another embodiment, the original VCCSA voltage source (instead of VCCSA+M1) is still connected to the sense amplifiers in the RESTORE phase after T2, as shown in FIG. 8B.

In another embodiment, the signal on the bitlines is not kicked to VCCSA+M1 during an active command and the signal on the bitlines is kicked to VCCSA+M1 during a read command. As shown in FIG. 8C, in the RESTORE phase after T2, the first sustaining voltage source VCCSA+M1 is connected to the sense amplifier so that the signal on the bitlines is pumped (or kicked) to at least VCCSA+M1.

FIG. 8D shows relevant signal waveforms for operation of a DRAM cell according to another embodiment of the present invention. Similar to FIG. 8A, in the period between T1 and T2, there is an active command to be executed and at least one read command following the active command, and during the active operation and during the read command, the corresponding first A sustain voltage source (VCCSA+M1) may be connected to the sense amplifier (by turning on switch 13 shown in FIG. 3A). Additionally, during active operations and during read commands, a corresponding second sustain voltage source (VSS-M2) can be connected to the sense amplifier (by turning on switch 23 shown in FIG. 3B). Thus, during active commands and read commands, the signal on bitline (BL) is pumped (or kicked) to at least VCCSA+M1 and the signal on bitline bar (BLB) is pumped (or kicked) to at least VSS-M2. be done. After execution of the ACTIVE and READ commands, the normal voltage source VCCSA is connected to the sense amplifier (by turning off switch 13 and turning on switch 14 shown in FIG. 3A) and the normal voltage source VSS is connected to the sense amplifier. (by turning off switch 23 and turning on switch 24 shown in FIG. 3B), and the signal on bitline returns to VCCSA and the signal on bitline bar returns to VSS.

Similarly, in the RESTORE phase after T2, the original VCCSA and VSS voltage sources are disconnected from the sense amplifiers (eg, by turning off switches 14 and 24 in FIGS. 3A and 3B, respectively) to restore the first sustain. Voltage source VCCSA+M1 is connected to sense amplifier 20 (by turning on switch 13 in FIG. 3A) and a second sustaining voltage source VSS-M2 is connected to sense amplifier 20 (by turning on switch 23 in FIG. 3B). ), and the signal on bitline is pumped (or kicked) to at least VCCSA+M1 and the signal on bitline bar is pumped (or kicked) to at least VSS-M2.

FIG. 8E shows the relationship between the kick period and the signal on the bitline in DRAM cell operation. The kick period of the bit line signal corresponding to the RESTORE phase (or precharge) K4 may be longer than that corresponding to the active command K1 or longer than that corresponding to the read command K2 or K3. Also, the kick period of the bit line signal corresponding to the active command K1 is equal to that corresponding to the read command K2 or K3. Of course, raising the signal on the bitline to a voltage level VCCSA+M1 or some other voltage level (such as VCCSA+ΔN, where ΔN<M1, etc.) during the period K1-K3 can be done by a bootstrap circuit. , and the charge on the capacitor in the bootstrap circuit is coupled to the bitline. Either a voltage source or a bootstrap circuit can be considered a charge source, so the signal on the bitline can be kicked or pumped to the voltage level VCCSA+M1 or VCCSA+ΔN by the charge source. So is the signal on the bitline that is kicked to VSS-M2 (or VSS-ΔN, where ΔN<M2).

Of course, in another embodiment, VCCSA is in the range of 0.9V-0.5V (eg, 0.9V, 0.8V, 0.7V, or 0.6V, etc.) or lower. and the kick voltage VCCSA+M1 is still within the range of 1.1V-2.5V (eg, 1.1V, 1.1V, 1.5V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V, 1.1V) 2V, 1.35V, 1.5V, 1.8V, or 2.5V). Therefore, leakage problems in DRAM circuits are mitigated in accordance with the present invention so that the main power supply voltage to a DRAM chip can be reduced to 1.0V-0.5V or less even in the presence of a slowdown in DRAM technology migration. . Therefore, the main power supply voltage to the DRAM chips can be the same or substantially the same as the main power supply voltage to the logic circuit chips.

As shown in FIG. 9A, DRAM circuitry 500 includes I/O circuitry 510 , peripheral circuitry 520 , and DRAM core circuitry 530 . Between DRAM 500 and logic circuit 300 is physical layer circuit 400 . Physical layer circuitry 400 further includes I/O physical circuitry 410 and logic physical circuitry 420 . Typically, the DRAM circuit 500 is in a DRAM chip, and the physical layer circuit 400 and logic circuit 300 are in another chip (eg, logic chip, etc.) separate from the DRAM chip. For example, the logic chip includes a memory controller, logic circuit 300, and also physical layer circuitry (or PHY circuitry) 400 that interacts with the DRAM chip and memory controller.

In another embodiment, physical layer circuitry 400 and logic circuitry 300 may each be located in two separate chips. For example, DRAM circuit 500 may include multiple DRAM chips stacked together. The stacked DRAM chips are then positioned on a base chip (or interposer) containing physical layer circuitry (or PHY layer) 400 . Logic circuit 300 is a digital circuit or memory controller located in a logic chip separate from the base chip.

In accordance with the present invention, the main power supply voltage Vnew to DRAM circuit 500 can be in the range of 1.0V-0.5V (or 0.9V-0.5V) or less, which is a high speed Just the same as the main power supply voltage Va' to the logic chip or circuit 300, which is already within or below 1.0V-0.5V (or 0.9V-0.5V) due to scaled-down logic technology migration. is. The main power supply voltage Vnew is external to the DRAM circuit 500 and generates various voltage sources used in the peripheral circuits 520 or the DRAM core circuit 530, such as the voltage sources VCCSA, VCCSA+M1, 1/2VCCSA, VPP, etc. previously described. can be used by DRAM circuit 500 for The level of VCCSA may be the same as or different from the level of the main power supply voltage Vnew to the DRAM circuit. There may also be another supply voltage _{V high} external to the DRAM circuit 100, which is higher than the main power supply voltage Vnew and produces a voltage source Vpp or VCCSA+M1 for conversion efficiency purposes. can be used for

Also, since the value of the main power supply voltage Vnew to the DRAM circuit 500 is the same or substantially the same as the value of the main power supply voltage Va' to the logic circuit 300, the I/O circuit 110 of the traditional DRAM circuit 100 The output level conversion circuitry (to level up or level down the voltage level of the output signal) and the input comparators within may be removed or omitted. Therefore, according to the present invention shown in FIG. 9B, the I/O circuit 510 of the DRAM circuit 500 does not include the aforementioned output level conversion circuit and input comparator, and provides a connection to other DRAM circuits (such as peripheral circuits 520, etc.). Input/output data signals from or are not necessarily converted or compared by I/O circuitry 510 . Also, the signal swing of input/output data to or from other DRAM circuits can be set to the level of the main power supply voltage Vnew.

As previously mentioned, DRAM circuit 500 includes I/O circuitry 510 , peripheral circuitry 520 , and DRAM core circuitry 530 . Peripheral circuitry 520 includes at least command/address decoders and/or other circuitry including transistors, and DRAM core circuitry 530 includes at least cell arrays and/or other associated circuitry including transistors. In accordance with the present invention, the operating supply voltage to the drain side of the transistors in the peripheral circuitry can be the same as the voltage level of the main power supply voltage source Vnew to the DRAM chip. Also, the operating supply voltage to the drain side of transistors in the DRAM core circuitry that are not access transistors may be the same voltage level as the main power supply voltage source to the DRAM chip. Of course, the voltage level corresponding to signal ONE or signal High used in a DRAM chip can be the same as the voltage level of the main power supply voltage source Vnew to the DRAM chip.

Similarly, in accordance with the present invention shown in FIG. 9C, the I/O physical circuit 410 of the physical layer circuit 400 also includes the aforementioned output level conversion circuit (to level up or level down the voltage level of the output signal) and the input comparison circuit. vessel can be removed. Input/output data signals to or from other physical layer circuits (such as logic physical circuit 420 ) are not necessarily converted or compared by I/O circuit 410 of physical layer circuit 400 . Also, the signal swing of input/output data to/from other physical layer circuits may be set to the level of the main power supply voltage Va' (ie, Vnew).

Therefore, in accordance with the present invention, the main power supply voltage levels to logic circuit 300, physical layer circuit 400, and DRAM circuit 500 may all be the same. If the DRAM circuit 500 is located in a DRAM chip, and the physical layer circuit 400 and logic circuit 300 are located in another logic chip separate from the DRAM chip, the level of the main power supply voltage to the DRAM chip is the same as that of the logic chip. is the same as the level of the mains voltage to

The I/O physical circuit 410 and the DRAM circuit 500 of the physical layer circuit 400 can be located in a DRAM chip, and the logic physical circuit 420 and the logic circuit 300 of the physical layer circuit 400 can be located in another logic chip. be. Again, the level of the main power supply voltage to the DRAM chip is the same as the level of the main power supply voltage to the logic chip.

In another case, when logic circuit 300, physical layer circuit 400, and DRAM circuit 500 are located in a logic chip, base chip (or interposer), and DRAM chip, respectively, the main power supply voltage to the DRAM chip is The level is the same as the level of the main power supply voltage to the base chip and the same as the level of the main power supply voltage to the logic chip.

As previously mentioned, low power applications require lower voltage levels for write data on the data paths, bitlines, and/or storage nodes of DRAM cells. However, if the voltage stored on the corresponding storage node is low, it may suffer from severe leakage problems and cause data corruption. Kicking up the voltage level of the bitlines during the restore phase according to the present invention can be applied to data write operations for power saving. FIG. 10 shows the relevant signal waveforms in the WRITE operation of a DRAM cell according to another embodiment of the present invention, and FIG. Figure 2 shows a schematic circuit of a selectively coupled sense amplifier, where the voltage level of VCCSAh is higher than the voltage level of VCCSA. When the write data XIO (eg, signal ONE or signal High) shown in FIG. 1F is input to the global I/O path GIO through the data input circuit DI, the voltage level of the write data on the global I/O path GIO is is kept as VCCSA (eg, 0.7V, etc.) for power saving. However, the voltage level of write data XIO corresponding to signal ONE (or signal High) may be higher than VCCSA, eg, VSSCAh. Write data on the global I/O path GIO is then passed to the data line DL via the data line sense amplifier. As shown in FIG. 10, the voltage level of write data on data line DL is also maintained at voltage level VCCSA by data line sense amplifier 70, and in this embodiment of FIG. The level is set to 0.7V (but not limited to this). The write data on the data lines DL are then passed to the corresponding bit lines BL in the memory array. As shown in FIG. 11, within memory array 75, when word line WL 66 corresponding to storage node SN is selected to turn on access transistor 66, VCCSA (eg, 0.7V) and VCCSA, which is higher than VCCSA, are selected to turn on access transistor 66. Two separate voltage sources, VCCSAh (eg, 1.1V), are selectively coupled to cross-coupled sense amplifier 80 at different times. After word line WL66 is selected, voltage source VCCSA is first coupled to cross-coupled sense amplifier 80, and bit switch BS100 is turned on to write data (i.e., signal ONE) to access transistor 66, thus The voltage level of the bitline BL is also raised to VCCSA. On the other hand, as will be appreciated by those skilled in the art, signals EN1 and EN2 are enabled and signal EN3 is disabled. As shown in FIG. 10 with respect to signal waveforms, the voltage level on the bit line BL is maintained at VCCSA for some time, but after the period tWR (write recovery time) ends, the voltage level on the bit line rises to VCCSAh during the restore phase. Kicked up (or called a "recovery kick"). The period tWR can refer to the DRAM specification defined by JEDEC (Electronic Device Engineering Coalition), which is the Last Write CLK rising edge for the precharge command. This tWR (write recovery time) ensures that the restore kick from precharge command can only start after the write cycle is completed.

Thus, as shown in FIG. 10, after the end of time period tWR, the voltage level of bitline BL is kicked up (ie, kicked back) to VCCSAh, and in this embodiment of FIG. is also equal to high 1.1V (but not limited to this). 10 and 11, voltage source VCCSAh is coupled to cross-coupled sense amplifier 80, bit line BL, and storage node SN before word line WL 66 corresponding to storage node SN is turned off. As a result, even if the voltage level of global I/O path GIO and data line DL during a WRITE operation is VCCSA, the voltage level of bitline BL is kicked up from VCCSA to VCCSAh and back to VCCSAh. Sufficient charges are stored in storage node SN based on the above.

Since the voltage level of the bitline BL is kicked up from VCCSA (0.7V, or other voltage level lower than 1.1V) to VCCSAh (1.1V), the present invention clearly overcomes the leakage problem of the prior art. can be resolved. That is, even if the voltage levels of write data on global I/O path GIO, data lines DL, and bit lines BL are lowered to 0.7V, 0.6V, or lower, VCCSAh is applied to the corresponding storage nodes. The present invention will still not suffer from leakage problems and data corruption, since sufficient charge can be stored based on the restore kick to . As shown in FIG. 12, in a write operation, the voltage level of write data on global I/O path GIO, data lines DL, and bit lines BL is lowered to 0.7V (or even 0.6V or lower). , resulting in lower operating currents. For example, when the voltage level of write data on global I/O path GIO, data line DL, and bit line BL is reduced from 1.1V to 0.7V (35% reduction), the operating current is reduced from 141mA to 35mA. will be reduced, where the operating current of 141 mA corresponds to the case where the voltage level of write data on the global I/O path GIO, data lines DL and bit lines BL is maintained at 1.1V.

On the other hand, in a read operation, if read data corresponds to signal ONE (or signal High), in one embodiment of the present invention, the voltage level of read data on global I/O path GIO and data line DL is set to VSSCAh, for example. etc., can be higher than VCCSA. For example, as shown in FIG. 12, the voltage level of read data (corresponding to signal ONE) on global I/O path GIO and data line DL is set to VCCSA (eg, 0.7 V). It is set to 1.1V, which is higher than the voltage level of the write data (corresponding to signal ONE) on path GIO and data line DL. Similarly, the voltage level of control signals and/or address signals for DRAM operation is set to 1.1V, which is higher than the voltage level of write data (corresponding to signal ONE) on global I/O path GIO and data line DL. Set (if corresponding to signal ONE).

Therefore, the voltage swing on global I/O path GIO and data line DL (or data path) in a read operation is different from the voltage swing on global I/O path GIO and data line DL (or data path) in a write operation. Differently, in particular, the voltage swing of the read data set (including signal ONE and signal ZERO) on global I/O path GIO and/or data lines DL may vary from the write data set on global I/O path GIO and/or data lines DL. Higher than the voltage swing of the data set (including signal ONE and signal ZERO). Also, the voltage swings of the control and address signals for DRAM operations (such as read, write, or other operations) in accordance with the present invention may be different or different than the voltage swings on the data path in write operations. higher than

Summarizing the above description, the present invention discloses a sustainable DRAM with a unified main power supply voltage that is unified with logic circuits. Before the access transistor of the DRAM storage cell is turned OFF (or the word line coupled to the DRAM storage cell is turned OFF), a first voltage level higher than the voltage level of signal ONE (or signal high) is applied to the DRAM storage cell. A sustain voltage of 1 can be restored or stored. After turning off the access transistor, the storage capacitor can last for a longer period of time compared to conventional DRAM structures, even if there is leakage current in the access transistor. Leakage problems in DRAM circuits are mitigated so that the main power supply voltage to DRAM chips can be reduced to 1.0V-0.5V or even lower, even in the presence of a slowdown in DRAM technology migration. Therefore, the main power supply voltage to the DRAM chips can be the same or substantially the same as the main power supply voltage to the logic circuit chips. Also, power supply voltage compatibility between DRAM chips and logic chips leads to optimization of energy efficiency and performance synchronization, which not only increases operating speed but also saves die area and power. Furthermore, the voltage swing of write data on the data path is lower than the voltage swing of read data on the data path, thus reducing current or power for write operations.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (32)

A DRAM chip coupled to external logic circuitry and configured to couple to a mains voltage source, comprising:
a first sustain voltage generator for generating a first voltage level higher than a voltage level corresponding to signal ONE used in the DRAM chip;
a DRAM core circuit having DRAM cells with access transistors and storage capacitors;
has
the storage capacitor of the DRAM cell is configured to be selectively coupled to the first sustain voltage generator;
the voltage level of the main power supply voltage source to the DRAM chip is the same or substantially the same as the voltage level of the main power supply voltage source to the external logic circuit;
DRAM chips. The DRAM chip further includes I/O circuitry and peripheral circuitry between the I/O circuitry and the DRAM core circuitry, wherein an operating supply voltage to the drain side of transistors in the peripheral circuitry is controlled by the DRAM. 2. The DRAM chip of claim 1, which is the same as said voltage level of said main power supply voltage source to the chip. 3. The DRAM chip of claim 2, wherein an operating supply voltage to the drain side of a transistor in said DRAM core circuitry that is not said access transistor is the same as said voltage level of said main power supply voltage source to said DRAM chip. 4. The DRAM chip of claim 3, wherein said voltage level corresponding to said signal ONE used in said DRAM chip is the same as said voltage level of said main power supply voltage source to said DRAM chip. The DRAM chip further includes an I/O circuit and a peripheral circuit between the I/O circuit and the DRAM core circuit, the I/O circuit including an input comparison circuit and an output level conversion circuit. The DRAM chip of claim 1, wherein no. 2. The DRAM chip of claim 1, wherein said voltage level of said main power supply voltage source to said DRAM chip is between 0.9V-0.5V. The DRAM chip further includes a word line coupled to the gate terminal of the access transistor, the word line turning on the access transistor for a first period of time and a second period of time after the first period of time. 2. The DRAM chip of claim 1, wherein selected, said first sustain voltage generator is electrically coupled to said storage capacitor of said DRAM cell during said second time period. 8. The DRAM chip of claim 7, wherein said first period is an access operation period and said second period is a restore phase period. 9. The DRAM chip of claim 8, wherein a kicking charge source is electrically coupled to a bitline of the DRAM chip during said access operation. A DRAM chip configured for coupling with external logic circuitry and a mains voltage supply, comprising:
a DRAM core circuit having DRAM cells with access transistors and storage capacitors;
an I/O circuit configured to couple to the external logic circuit;
a peripheral circuit between the I/O circuit and the DRAM core circuit;
has
The voltage level of the main power supply voltage source to the DRAM chip is the same or substantially the same as the voltage level of the main power supply voltage source to the external logic circuit, and the voltage level of the main power supply voltage source to the DRAM chip is the same or substantially the same. the voltage level is less than or equal to 0.9V;
DRAM chips. 11. The DRAM chip of claim 10, wherein an operating supply voltage to the drain side of transistors in said peripheral circuitry is the same as said voltage level of said main power supply voltage source to said DRAM chip. 12. The DRAM chip of claim 11, wherein an operating supply voltage to the drain side of a transistor in said DRAM core circuitry that is not said access transistor is the same as said voltage level of said main power supply voltage source to said DRAM chip. 13. The DRAM chip of claim 12, wherein a voltage level corresponding to signal ONE used in said DRAM chip is the same as said voltage level of said main power supply voltage source to said DRAM chip. 11. The DRAM chip of claim 10, wherein said I/O circuitry does not have input comparison circuitry and output level conversion circuitry. a first sustain voltage generator for generating a first voltage level higher than a voltage level corresponding to signal ONE used in the DRAM chip;
a word line coupled to the gate terminal of the access transistor, the word line selected to turn on the access transistor for a first period of time and a second period of time after the first period; 11. The DRAM chip of claim 10, wherein a sustain voltage generator is electrically coupled to said storage capacitor of said DRAM cell during said second time period. 16. The DRAM chip of claim 15, wherein said first period is an access operation period and said second period is a restore phase period. a DRAM chip;
a logic chip electrically coupled to the DRAM chip;
has
The voltage level of the main power supply voltage source to the DRAM chip is the same or substantially the same as the voltage level of the main power supply voltage source to the logic chip, and the voltage level of the main power supply voltage source to the DRAM chip. is less than or equal to 0.9 V,
memory system. The DRAM chip includes a DRAM circuit, the logic chip includes a logic circuit and a physical layer circuit, the main power supply voltage source to the DRAM chip is supplied to the DRAM circuit, and the main power supply to the logic chip is supplied to the DRAM circuit. 18. The memory system of claim 17, wherein a voltage source is supplied to said logic circuit and said physical layer circuit. The memory system further includes a base chip electrically coupled to the DRAM chip, wherein the voltage level of the main power supply voltage source to the DRAM chip is the voltage level of the main power supply voltage source to the base chip. 18. The memory system of claim 17, which is the same or substantially the same as . The DRAM chip includes a DRAM circuit, the logic chip includes a logic circuit, the base chip includes a physical layer circuit, the main power supply voltage source to the DRAM chip is supplied to the DRAM circuit, and the 20. The memory system of claim 19, wherein the main power supply voltage source to logic chip is supplied to the logic circuitry and the main power supply voltage supply to the base chip is supplied to the physical layer circuitry. The DRAM chip has a DRAM cell and a first sustain voltage generator, the DRAM cell has a storage capacitor and an access transistor, and the first sustain voltage generator is used in the DRAM chip. Generating a first voltage level higher than a voltage level corresponding to signal ONE, the first sustain voltage generator applies to the storage capacitor of the DRAM cell before the access transistor of the DRAM cell is turned off. 18. The memory system of claim 17, combined. said DRAM chip further comprising an I/O circuit and peripheral circuits between said I/O circuit and said DRAM cell, said I/O circuit not having an input comparison circuit and an output level conversion circuit; 22. The memory system of claim 21. 18. The memory system of claim 17, further comprising a physical layer circuit comprising an I/O physical circuit, said I/O physical circuit having no input comparison circuit and output level conversion circuit. a DRAM cell having an access transistor and a storage capacitor;
a sense amplifier coupled to the DRAM cell via a bitline;
a data path coupled to the sense amplifier;
has
In the process of writing the signal ONE to the storage capacitor, the voltage level of the signal ONE on the data path is lower than the voltage level of the signal ONE stored on the storage capacitor, and the signal ONE on the data path is less than the voltage level of the signal ONE stored on the storage capacitor. the voltage level of is between 0.9-0.5V;
DRAM chips. 25. The DRAM chip of claim 24, wherein said voltage level of said signal ONE is stored in said storage capacitor only after expiration of a period of time tWR defined by JEDEC. the data path includes a global I/O path and a data line, wherein the voltage level of the signal ONE on the global I/O path or the data line is between 0.7-0.5V; 25. The DRAM chip of claim 24. a DRAM cell having an access transistor and a storage capacitor;
a sense amplifier coupled to the DRAM cell via a bitline;
a data path coupled to the sense amplifier;
has
read data corresponding to a signal ONE on the data path has a higher voltage level than write data corresponding to another signal ONE on the data path;
DRAM chips. 28. The DRAM chip of claim 27, wherein said write data is stored on said storage capacitor, and wherein a voltage level of said write data stored on said storage capacitor is higher than said voltage level of said write data on said data path. . The voltage level of the read data corresponding to the signal ONE on the data path is between 1.2-1.0 V, and the voltage level of the write data corresponding to the another signal ONE on the data path. 28. The DRAM chip of claim 27, wherein the voltage level is between 0.9-0.5V. a DRAM cell having an access transistor and a storage capacitor;
a sense amplifier coupled to the DRAM cell via a bitline;
a data path coupled to the sense amplifier;
has
a voltage swing on a global I/O path or data line of the data path in a read operation is greater than a voltage swing on the global I/O path or data line of the data path in a write operation;
DRAM chips. The voltage swing on the global I/O path or the data line in the read operation is between 1.2-1.0V and the voltage swing on the global I/O path or the data line in the write operation is 31. The DRAM chip of claim 30, wherein the voltage swing is between 0.8-0.6V. 31. The DRAM chip of claim 30, wherein voltage swings of control and address signals for DRAM operations are greater than said voltage swings on said global I/O paths or said data lines in said write operations.

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