TW202246992A - Rs-485 circuit and communication system - Google Patents

Abstract

Disclosed is an RS-485 circuit, which is arranged in an electronic device including a processing module. The RS-485 circuit includes an RS-485 interface chip, a start detector, an inter-integrated circuit and a counter. A default state of the RS-485 interface chip is a data receiving state, and the RS-485 interface chip includes a data input terminal and an enable terminal, wherein the data input terminal is configured to receive a data signal from the processing module, and the enable terminal is configured to receive a start signal or a switching signal to make the RS-485 interface chip in a data transmitting state or the data receiving state. The start detector is configured to detect the first signal edge of the data signal to generate the start signal to the enable terminal. A count value from the processing module is stored in a register through the inter-integrated circuit, so that the counter performs counting based on the count value, and outputs the switching signal to the enable terminal when the count of the counter is expired.

Description

RS-485 circuit and communication system

This application relates to a communication interface circuit, and in particular to an RS-485 circuit and communication system.

RS-485 is a common serial communication standard. It is a communication method between two devices through balanced transmission and differential reception.

The electrical characteristics based on RS-485 are half-duplex mode (Half Duplex), so that two devices communicating through the RS-485 interface cannot simultaneously transmit and receive data. Therefore, only one device can transmit data at the same time. If another device needs to transmit data, it needs to wait for the device that is transmitting data to finish sending the data before proceeding.

Generally speaking, it is necessary to output a control signal to the RS-485 interface chip through the processing module (for example: microprocessor, central processing unit or single chip) of the device, so as to realize the switching of the data sending and receiving state of the RS-485 interface chip. However, the above method has the problem of increasing the workload of software development and wasting human resources for research and development because additional software codes need to be added to the processing module of the device to realize the control of state switching.

The main purpose of this application is to provide an RS-485 circuit and communication system, which solves the problem of increasing the workload of software development due to the need to add additional software codes to the processing module of the device to realize the control of state switching in the prior art , the problem of wasting human resources for research and development.

In order to achieve the above object, the application is implemented as follows:

In a first aspect, an RS-485 circuit is provided, which is disposed in an electronic device including a processing module. The RS-485 circuit includes: RS-485 interface chip, start detector, integrated bus circuit and counter. Wherein, the default state of the RS-485 interface chip is the data receiving state and includes: a data input terminal and an enabling terminal, the data input terminal is used to receive the data signal from the processing module; the enabling terminal is used to receive the start signal, Make the RS-485 interface chip in the data sending state; and after receiving the switching signal, make the RS-485 interface chip in the data receiving state. The start detector is used for detecting the first signal edge of the data signal to generate a start signal to the enable terminal. The integrated bus circuit is connected to the processing module, and the counter is connected to the integrated bus circuit and the enabling terminal. The counter includes a temporary register, and the count value from the processing module is stored in the temporary register through the integrated bus circuit, so that the counter counts based on the count value, and outputs a switching signal to the enabling terminal when the count expires, wherein, the processing The module generates a count value based on the data length and baud rate of the data signal.

In a second aspect, a communication system is provided, which includes: a processing module, a communication bus and an RS-485 circuit, wherein the RS-485 circuit is connected to the processing module through the communication bus. The processing module is used to generate a count value based on the data length and baud rate of the data signal; the RS-485 circuit includes: an RS-485 interface chip, a start detector, an integrated bus circuit and a counter. Wherein, the default state of the RS-485 interface chip is the data receiving state and includes: a data input terminal and an enabling terminal, the data input terminal is used to receive the data signal from the processing module; the enabling terminal is used to receive the start signal, Make the RS-485 interface chip in the data sending state; and after receiving the switching signal, make the RS-485 interface chip in the data receiving state. The start detector is used for detecting the first signal edge of the data signal to generate a start signal to the enable terminal. The integrated bus circuit is connected to the processing module, and the counter is connected to the integrated bus circuit and the enabling terminal. The counter includes a temporary register, and the count value from the processing module is stored in the temporary register through the integrated bus circuit, so that the counter counts based on the count value, and outputs a switching signal to the enabling terminal when the count expires.

In this application, by setting up the detector, the control module and the counter, the RS-485 circuit can automatically judge the data transmission direction and transmission time of the RS-485 interface chip by means of hardware, so as to avoid the problem that the data has not been completely transmitted Then the transmission direction is switched or the data transmission is completed but the transmission direction is not switched in time, resulting in errors in data transmission, and it can also solve the problem in the prior art that additional software codes need to be added to the processing module of the device to achieve state switching control, resulting in increased workload of software development, waste of human resources for research and development.

Embodiments of the present invention will be described below in conjunction with related figures. In these drawings, the same reference numerals indicate the same or similar components or method flows.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, components and/or components, but do not exclude possible Add more technical characteristics, values, method steps, operation processes, components, components, or any combination of the above.

It must be understood that when a component is described as being "connected" or "coupled" to another component, it may be directly linked, or coupled to the other component, and intervening components may be present. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components present.

Please refer to FIG. 1 , which is a block diagram of an embodiment of an RS-485 circuit according to the present application. As shown in Figure 1, in this embodiment, the RS-485 circuit 100 is set in an electronic device (not shown) including a processing module (not shown), and the RS-485 circuit 100 includes: an RS-485 interface chip 110 , start the detector 120, the integrated bus bar circuit 130 and the counter 140, the integrated bus bar circuit 130 is connected to the processing module and the counter 140, the start detector 120 and the counter 140 are respectively connected to the RS-485 interface chip 110; The RS-485 interface chip 110 can be connected with other RS-485 interface chips (not shown) through the RS-485 bus bar 50, so that the electronic device configured with the RS-485 interface chip 110 can be connected with the RS-485 bus bar 50 and configured with The electronic devices (not shown) of the other RS-485 interface chips carry out data transmission and reception. Wherein, because the integrated busbar circuit 130 has the advantage of occupying a very small space, the space of the printed circuit board of the electronic device can be reduced, and the interconnection cost is reduced; in addition, the integrated busbar circuit 130 only has two signal lines , for the user, the operation is more simple and convenient, and the number of pins of the processing module connected thereto can be reduced, so as to avoid wasting the I/O resources of the processing module.

In this embodiment, the default state of the RS-485 interface chip 110 is the data receiving state and includes: a data input terminal 111 and an enabling terminal 112, the data input terminal 111 is used for receiving data signals; the enabling terminal 112 is used for receiving After the start signal, the RS-485 interface chip 110 is in the data sending state; and after receiving the switching signal, the RS-485 interface chip 110 is in the data receiving state. It should be noted that when the RS-485 interface chip 110 is preset to receive data, the data signal can be preset but not limited to a high-level signal, and the signal received by the enable terminal 112 can be preset but not limited to Micro Motion bit signal; when the data signal begins to undergo a signal state transition (that is, the data signal includes a signal edge), it means that the device equipped with the RS-485 interface chip 110 will start to transmit data, and the RS-485 interface chip 110 needs to switch to The data sending status, but this embodiment is not intended to limit the present invention. For example, when the RS-485 interface chip 110 is preset to receive data, the data signal can also be preset as a low-level signal, and the signal received by the enabling terminal 112 can also be preset as a low-level signal.

In one embodiment, when the RS-485 interface chip 110 is preset to the data receiving state and the signal received by the enabling terminal 112 can be preset as a high level signal, the start signal can be a low level signal, so The switching signal can be a high level signal. In another embodiment, when the RS-485 interface chip 110 is preset to the data receiving state and the signal received by the enabling terminal 112 can be preset as a low-level signal, the start signal can be a high-level signal, The switching signal can be a low level signal.

In one embodiment, the RS-485 interface chip 110 may further include: a differential signal transceiver terminal 113. When the RS-485 interface chip 110 is in the state of data transmission, the RS-485 interface chip 110 receives the signal based on the data input terminal 111. The data signal outputs a differential signal to the RS-485 bus 50 through the differential signal transceiver terminal 113; Another differential signal for row 50. In more detail, the differential signal transceiver 113 may include a differential signal pin 113a and a differential signal pin 113b. The received data signal outputs the differential signal to the RS-485 bus bar 50 through the differential signal pin 113a and the differential signal pin 113b; The pin 113 a and the differential signal pin 113 b receive another differential signal from the RS-485 bus 50 .

In one embodiment, the RS-485 interface chip 110 may further include: a data output terminal 114. When the RS-485 interface chip 110 is in the data receiving state, the RS-485 interface chip 110 receives another signal based on the differential signal transceiver terminal 113. A differential signal outputs another data signal through the data output terminal 114 .

In one embodiment, the RS-485 interface chip 110 includes a transmission logic unit 60 and a reception logic unit 70, wherein the input terminal of the transmission logic unit 60 is connected to the data input terminal 111, and the output terminal of the transmission logic unit 60 is connected to the differential signal transceiver terminal. 113, the control terminal of the transmission logic unit 60 is connected to the enabling terminal 112; the input terminal of the receiving logic unit 70 is connected to the differential signal transceiver terminal 113, the output terminal of the receiving logic unit 70 is connected to the data output terminal 114, and the control terminal of the receiving logic unit 70 is connected to Enable terminal 112 . It should be noted that when the RS-485 interface chip 110 is preset to the data receiving state, the transmitting logic unit 60 will not operate, but the receiving logic unit 70 will operate; when the RS-485 interface chip 110 is preset to the data sending state When , the transmitting logic unit 60 will operate, and the receiving logic unit 70 will not operate.

In this embodiment, the enable detector 120 is used to detect the first signal edge of the data signal and generate the enable signal to the enable terminal 112 . In other words, when the data signal starts to undergo a signal state transition (that is, the data signal includes a signal edge), it means that the device configured with the RS-485 interface chip 110 will start to transmit data, so the start detector 120 detects When the first signal edge of the data signal is detected, the start signal is generated and transmitted to the enabling terminal 112, so that the RS-485 interface chip 110 is switched to the data sending state. Wherein, when the data signal is preset as a high-level signal, the first signal edge may be a falling edge; when the data signal is preset as a low-level signal, the first signal edge may be It can be adjusted according to actual needs.

In one embodiment, when the enable detector 120 detects the first signal edge of the data signal, another enable signal is generated to the counter 140 to enable the counter 140 .

In one embodiment, the activation detector 120 can also be used to continuously detect the signal edge of the data signal. When the activation detector 120 does not detect the signal edge within a preset time, then after the preset time A start signal is generated when a signal edge is detected for the first time. In other words, the first signal edge of the data signal may be but not limited to the first detected signal edge after the preset time. Wherein, the preset time can be adjusted according to actual needs.

In this embodiment, the counter 140 includes a temporary register 142, and the count value from the processing module is stored in the temporary register 142 through the integrated bus circuit 130, so that the counter 140 counts based on the count value, and counts to Periodically output the switching signal to the enabling terminal 112 . Wherein, when the counter 140 counts to the count value, it means that the count of the counter 140 expires, and it also means that the data transmission is completed (because the processing module generates the count value based on the data length and baud rate of the data signal). Wherein, the data length of the data signal may be, but not limited to, the length between the first signal edge and the last signal edge of the data signal, and the baud rate is the transmission rate of the data signal. It should be noted that the timing difference between the penultimate signal edge and the last signal edge of the data signal cannot be greater than the aforementioned preset time.

In one embodiment, the integrated bus circuit 130 and the counter 140 have a corresponding baud rate, that is, at the corresponding baud rate, when the count of the counter 140 expires, the enabling terminal 112 is notified, so that the enabling terminal 112 Control the RS-485 interface chip 110 to switch to the data receiving state. In addition, since the integrated bus circuit 130 and the counter 140 have corresponding baud rates, the counter 140 does not only count one baud rate, but needs to have the function of counting different baud rates.

Please refer to FIG. 2 , which is a block diagram of an embodiment of a communication system according to the present application. In this embodiment, the communication system 200 includes: a processing module 210 , a communication bus 220 and an RS-485 circuit 100 , wherein the RS-485 circuit 100 is connected to the processing module 210 through the communication bus 220 . Wherein, the data input terminal 111 receives the data signal from the processing module 210 through the communication bus 220, and the data output terminal 114 outputs another data signal to the processing module 210 through the communication bus 220; the processing module 210 can be but not limited to A microprocessor, a central processing unit or a single chip generates the count value based on the data length and baud rate of the data signal; the communication bus 220 can be but not limited to a Universal Asynchronous Receiver Transmitter (UART) bus.

Therefore, when data is sent and received between a plurality of electronic devices configured with the RS-485 circuit 100 or the communication system 200 of the embodiment of the present application, the RS-485 interface chip 110 of the electronic device that transmits the data can be connected by its data input terminal. 111 has a signal state transition and switches to the data sending state, while the RS-485 interface chip 110 of other electronic devices receiving data remains in the data receiving state (because the data input terminal 111 has no signal state transition and remains in the default state ), so that the transmission and reception of data can be successfully completed between these electronic devices; and when the electronic device that transmits data completes the transmission of data, the RS-485 interface that it has can be based on the expiration of the counter 140 it has. The chip 110 is switched to a preset data receiving state.

In summary, the RS-485 circuit of the embodiment of the present application can automatically determine the direction of data transmission of the RS-485 interface chip and the Transmission time, to avoid errors in data transmission caused by switching the transmission direction before the data is completely transmitted or not switching the transmission direction in time after the data transmission is completed, and can also solve the existing problems in the prior art due to the need for processing modules in the device Adding additional software codes on the computer to realize the control of state switching will increase the workload of software development and waste human resources for research and development.

Although the above-described components are included in the drawings of the present application, it is not excluded to use more other additional components to achieve better technical effects without violating the spirit of the invention.

While the invention has been described using the above examples, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the claims must be construed in the broadest manner to include all obvious modifications and similar arrangements.

50: RS-485 bus 60:Transfer logic unit 70: Receive logic unit 100: RS-485 circuit 110: RS-485 interface chip 111: data input terminal 112: enable end 113: Differential signal transceiver 113a, 113b: differential signal pins 114: data output terminal 120:Start detector 130: Integrated busbar circuit 140: Counter 142: Temporary register 200: Communication system 210: Processing module 220: communication bus

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The schematic embodiments and descriptions of the application are used to explain the application and do not constitute an improper limitation to the application. In the schema: Fig. 1 is an embodiment block diagram according to the RS-485 circuit of the present application; And FIG. 2 is a block diagram of an embodiment of a communication system according to the present application.

50: RS-485 bus

60:Transfer logic unit

70: Receive logic unit

100: RS-485 circuit

110: RS-485 interface chip

111: data input terminal

112: enable end

113: Differential signal transceiver

113a, 113b: differential signal pins

114: data output terminal

120:Start detector

130: Integrated busbar circuit

140: counter

142: Temporary register

Claims (10)

An RS-485 circuit, set in an electronic device including a processing module, the RS-485 circuit includes: an RS-485 interface chip, a default state of the RS-485 interface chip is a data receiving state, The RS-485 interface chip includes: a data input terminal for receiving a data signal from the processing module; state; and after receiving a switch signal, make the RS-485 interface chip in the data receiving state; a start detector, connected to the data input end and the enabling end, for detecting the data signal The start signal is generated to the enabling terminal by the first signal edge; an integrated bus circuit (Inter-Integrated Circuit, I ² C) is connected to the processing module; and a counter is connected to the integrated bus circuit and the enable end, including a temporary register, a count value from the processing module is stored in the temporary register through the integrated bus circuit, so that the counter counts based on the count value, and when the count expires Outputting the switching signal to the enabling terminal at the same time, wherein the processing module generates the count value based on a data length and a baud rate of the data signal. The RS-485 circuit as described in claim 1, wherein the RS-485 interface chip also includes: a differential signal transceiver, when the RS-485 interface chip is in the data transmission state, the RS-485 interface chip is based on The data signal outputs a differential signal to an RS-485 bus through the differential signal transceiver end; and when the RS-485 interface chip is in the data receiving state, the RS-485 interface chip receives the signal from Another differential signal for the RS-485 bus. The RS-485 circuit as described in claim 2, wherein, the RS-485 interface chip also includes: a data output terminal, when the RS-485 interface chip is in the data receiving state, the RS-485 interface chip is based on the Another differential signal outputs another data signal through the data output terminal. The RS-485 circuit as claimed in claim 1, wherein when the enable detector detects the first signal edge of the data signal, it generates another enable signal to the counter to activate the counter. The RS-485 circuit according to claim 1, wherein the first signal edge is a falling edge or a rising edge. The RS-485 circuit as described in claim 1, wherein, the start detector is also used to continuously detect a signal edge of the data signal, when the start detector does not detect the signal edge within a preset time When the signal edge is detected, the start signal is generated when the signal edge is detected for the first time after the preset time. The RS-485 circuit according to claim 1, wherein the start signal is a high level signal, and the switching signal is a low level signal. The RS-485 circuit according to claim 1, wherein the start signal is a low level signal, and the switching signal is a high level signal. The RS-485 circuit according to claim 1, wherein the integrated bus circuit and the counter have corresponding baud rates. A communication system comprising: a processing module for generating a count value based on a data length and a baud rate of a data signal; a communication bus; and An RS-485 circuit, connected to the processing module through the communication bus, the RS-485 circuit includes: An RS-485 interface chip, a default state of the RS-485 interface chip is a data receiving state, and the RS-485 interface chip includes: a data input terminal for receiving the data signal from the processing module; and An enabling terminal is used to make the RS-485 interface chip in a data sending state after receiving a start signal; and is used to make the RS-485 interface chip in the data receiving state after receiving a switching signal; an enable detector, connected to the data input terminal and the enable terminal, for detecting the first signal edge of the data signal and generating the enable signal to the enable terminal; an integrated bus circuit connected to the processing module; and A counter, connected to the integrated bus circuit and the enable terminal, includes a temporary register, the count value from the processing module is stored in the temporary register through the integrated bus circuit, so that the counter is based on the The count value is counted, and the switching signal is output to the enabling terminal when the count expires.

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