JPH0675904A - Ic for arbitration and bi-directional signal mutual converter - Google Patents

Abstract

PURPOSE:To realize a high speed data transfer conformed to the specification of an SCSI with reduced space and inexpensively, regarding an IC for bus arbitration for SCSI interface and bi-directional signal mutual converter. CONSTITUTION:These devices are provided with pulse preparation parts 1, 3, a decision part 2 deciding the priority order of bus use right requests and a driver for unbalanced signal as an IC for bus arbitration for SCSI 10 and provided with the IC and the mutual converting means of balanced and unbalanced signals which converts a balance type signal into an unbalanced signal and outputs it, and converts the unbalanced signal into the balanced signal and outputs it an a bi-direction signal mutual converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention realizes high-speed data transfer in a space-saving and inexpensive manner in conformity with the SCSI2 standard which is an extended SCSI among the SCSI standards which are means for transmitting information between a small computer and peripheral devices. The present invention relates to a possible bus arbitration IC and a bidirectional signal mutual converter using the same.

[0002]

2. Description of the Related Art The SCSI standard is ANSI X3.
It is a standard interface standard for small computers established as 131-1986, and is currently widely used mainly as an interface for data transfer mainly between a computer and peripheral devices such as a disk device. Up to 8 peripheral devices can be connected on this SCSI bus, and 8 data lines and 1
There are two data parity lines and nine control lines, and two types of electrical conditions of the transmission system are used, an unbalanced type and a balanced type. The unbalanced type has an open collector output and active Low, that is, a Low signal is true, while the balanced type uses two plus and minus signals for one signal, and the plus signal level is the minus signal level. It is recognized as true when it becomes higher than. In the unbalanced type, considering the influence of external noise,
The maximum cable length is limited to 6 meters, and the balanced type is limited to 25 meters in maximum cable length because it is difficult to be affected by external noise because it takes a differential signal as described above. However, in the actual system configuration, the unbalanced type is widely used for ordinary disk devices. Therefore, a method of configuring the bus line in the balanced type and converting it to the unbalanced type before each peripheral device is adopted. .

When the SCSI network is constructed as described above, the unbalanced signal of the general disk device is converted into a highly reliable balanced signal for data transfer as described above. A bidirectional signal converter capable of mutually converting an unbalanced type signal from the side and a balanced type signal from the data bus side is used. As such a signal converter, for example, JP-A-3-255515
, A so-called synchronous logic circuit provided with a sampling circuit for reading an input signal by using a control clock signal of a specific cycle in a bus arbitration circuit and a special control for a bus arbitration circuit. There is one using an asynchronous logic circuit that does not use a clock signal.

FIG. 3 is a block diagram showing an example of a balanced / unbalanced bidirectional signal mutual converter in the prior art. When the unbalanced signal is input first and the converted output to the balanced signal is obtained, the unbalanced signal is the unbalanced input SI.
When input from O to the bus arbitration circuit 4 via the receiver 5, and the bus arbitration circuit 4 is a synchronous logic circuit, data is sent to the balanced signal output driver 8 in response to the control clock signal, The driver 8 is turned on and output to the balanced line DO side. On the other hand, when the balanced signal is input first, the bus arbitration circuit 4 responding to the control clock signal receives the data of the balanced signal input from the balanced input DI through the balanced signal input receiver 7. The reading is performed, the driver 6 is turned on, and the data is output to the unbalanced line SIO side. That is, the priority of the bus use right request is determined by using a control clock signal separately provided as a means for recognizing the input signal.

On the other hand, in the case of the asynchronous logic circuit, the configuration of the signal converter is the same as the example shown in FIG.
As a means for recognizing an input signal, for example, a method of capturing a change in input signal level is used.

[0006]

The use of the control clock signal in the synchronous logic circuit as described above is excellent in that the effect of a hazard in which the output is temporarily disturbed can be avoided, as is well known. A problem is that the operating speed of the system cannot be increased to the operating speed of the device. Further, regardless of whether it is a synchronous type or an asynchronous type, since the signal detection unit of the bus arbitration circuit and the determination unit that determines the priority order of signals are conventionally implemented as separate ICs and mounted on the board, As a result of the increased wiring length, the operating speed of the system could not be increased to the operating speed of the device even in the asynchronous system. For these reasons, the maximum data transfer rate in the prior art is about 5 megabytes / second (hereinafter referred to as MB / s) with a 1-byte wide data bus regardless of whether the logic circuit is synchronous or asynchronous. there were.

On the other hand, SCSI2 is an extended specification of SCSI.
Has been developed, and two methods have been introduced: WIDE SCSI that expands the data bus to enable high-speed data transfer and FAST SCSI that enables data transfer up to 10 MB / s with a 1-byte wide data bus. Has been done. However, with the conventional signal converter, 10 MB / s
Data transfer is not possible at all, and WIDE SC
In SI, 9 control lines and 32 data lines are required, and the current signal converters must be installed in 3 parallels. Since they are mounted on the board, a large volume is required and the number of parts is large. However, there is a problem in that the cost is high due to the large number of components.

That is, in the conventional signal converter, the SCSI
There is a serious drawback in that it is extremely difficult to completely comply with the SCSI2 standard as an extended specification due to the performance problem and the signal converter size problem.

[0009]

In order to solve the above-mentioned problems, the present inventor has conducted extensive studies and realized 10 MB / s data transfer by using an asynchronous logic circuit as a bus arbitration circuit. That is, the present invention provides a bus arbitration IC capable of realizing high-speed data transfer conforming to the SCSI2 standard in a space-saving and inexpensive manner, and a bidirectional signal mutual converter using the same. Where to do is SCSI2
As a bus arbitration IC using an asynchronous logic circuit that selects bidirectional signals in accordance with the standard of 1), a pulse generation unit that generates positive and negative pulses according to a change in input signal level, and a bus by the pulse. There is a determination unit that determines the priority of the usage right request and a driver for unbalanced signal output, and as a bidirectional signal mutual converter,
The IC and the balanced and unbalanced signal mutual conversion means for converting a balanced signal into an unbalanced signal for output and for converting the unbalanced signal into a balanced signal for output It is in.

[0010]

In the first invention, as described above, the SCSI is used.
As the bus arbitration IC, the pulse generation unit and the determination unit are integrated into one chip by using the asynchronous logic circuit, so that the control clock signal is not required and the wiring is not required, and the circuit operation is performed. The speed can be increased to the operating speed of the device. In addition, in the second aspect of the present invention, by simply adding a mutual conversion means for balanced and unbalanced signals to this IC,
It becomes a bidirectional signal mutual converter for SCSI2.

[0011]

Next, details of the first invention will be described based on embodiments. FIG. 1 is a block diagram showing a main part of a bus arbitration IC according to the present invention. In the figure, reference numerals 1 and 3 are a pulse generating section that generates positive and negative pulses according to a change in the input signal level, 2 is a determining section that determines the priority of the bus use right request by the pulse, and DI is a balanced type. Signal input, DO indicates a balanced signal output, SIO indicates an unbalanced signal input / output, and RS indicates a reset signal input. This circuit detects Low level (hereinafter referred to as L level) signals from the SIO and DI terminals, and outputs DO and SI
The signal is output to O, and the signal has a two-system flow of SIO to DO and DI to SIO, and transmits the earlier of the L level of each, and at the same time performs control to suppress the other signal. Moreover, since an asynchronous logic circuit is used in this circuit, a hazard prevention circuit is added.

The pulse generators 1 and 3 are a combination of a logical product, a logical sum, and a negation circuit, and with respect to the input signal, from High (hereinafter referred to as H) to Low (hereinafter referred to as L) of the signal.
It has a two-system output section that generates a positive pulse at the edge of and a negative pulse at the edges of L to H, respectively. The determination unit 2 is composed of an AND circuit and a flip-flop that is a sequential circuit, and the pulse generation units 1 and 3 are provided.
From the input of the AND circuit, the output of which is supplied to the trigger input of one flip-flop, the negative pulse of which is supplied to the reset of the flip-flop, and the output of the other flip-flop. One of them is combined so as to be supplied to one input of the AND circuit, and the pulse generators 1, 3 are combined.
It operates to detect the earlier of the positive pulses from each.

Next, the determination operation for determining the priority of the bus use right request by this IC will be described. In the initial state, one of the outputs of the flip-flop is in the H state and the other is in the L state, and the H output is supplied to one of the inputs of the AND circuit which receives the outputs from the pulse creating sections 1 and 3. Therefore, the positive pulse from the pulse generators 1 and 3 is supplied to the trigger input of the flip-flop. When a positive pulse is input, that is, when either SIO or DI goes to L level, a positive pulse is input from any of the pulse generators 1 and 3, so that the flip-flop on the input side is Invert. At this time, since one of the inputs of the AND circuit at the preceding stage of the trigger input of the flip-flop having no input becomes L, the signal to the trigger input is suppressed and only the output of the inverted flip-flop is DO,
Reflected in SIO. Next, when a negative pulse is input, that is, SI
When either O or DI goes high, a negative pulse is input from any of the pulse generators 1 and 3, so that the flip-flop on the input side is reset to reset the initial state. Then, the process waits for a signal input. Here, the state in which SIO and DI are simultaneously at the L level makes the operation of the circuit indefinite, but it is not possible as a SCSI interface, so it need not be considered.

The bus arbitration circuit as described above, to which an unbalanced signal output driver is added, is integrated into 18 circuits to be a single chip as a bus arbitration IC, together with a mutual conversion means for balanced and unbalanced signals. It was mounted on a board to make a bidirectional signal mutual converter. As for the IC shape, for bus arbitration, it is a square with a side of 23 mm and a thickness of 3
mm and a surface mount type using a plastic package. As the signal mutual conversion means, three hybrid ICs each having 6 circuits were used.

Further, a bidirectional signal mutual converter as a second invention will be described. FIG. 2 is a schematic diagram showing the circuit configuration of the signal converter according to the second invention.
However, 18 circuits are actually required. In the figure, 10 is the bus arbitration IC in the first invention, D and R are balanced signal drivers and receivers, R1 and R2 are unbalanced termination resistors, and R3 to R5 are balanced termination resistors. R6 represents a pull-down resistor for impedance matching. For example, when an unbalanced signal is first input and converted to a balanced signal, the unbalanced signal is input from the SIO to the bus arbitration IC 10 so that the input from the balanced signal side is suppressed and for the balanced signal. The signal is output to the balanced signal line DO side via the driver D. On the other hand, when the balanced signal is first input, the bus arbitration IC1 is input from the DI via the balanced signal receiver R.
0, the input from the unbalanced type signal line is suppressed and output to the unbalanced type signal line SIO side as described above. As the power supply voltage V, 5 V was supplied from the terminal side.

When a SCSI network is constructed using the bidirectional signal mutual converter as described above and data transfer is performed, a data bus of 1 byte has a capacity of 10 MB.
The data transfer rate of / s was confirmed.

[0017]

As described above, in the present invention, the SCS
Since the I bus arbitration circuit was integrated into one chip as an IC using an asynchronous logic circuit, the operating speed was increased to the operating speed of the device itself, resulting in a 1-byte wide data bus
A data transfer rate of 0 MB / s, which was impossible with the conventional technology, was realized. Further, since a bidirectional signal mutual converter can be obtained only by adding a balanced type / unbalanced type signal mutual conversion means to the present IC, the signal converter can be constructed with an extremely small volume. These effects cannot be obtained by the conventional technology, and the FA as SCSI2
It is possible to realize ST SCSI and WIDE SCSI in a small space and at low cost.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an operation of a bus arbitration IC of the present invention.

FIG. 2 is an explanatory diagram for showing the operation of the bidirectional signal mutual converter of the present invention.

FIG. 3 is an explanatory diagram showing the operation of a conventional bidirectional signal mutual converter.

[Explanation of symbols]

 1, 3 Pulse creation unit 2 Judgment unit 4 Conventional bus arbitration circuit 5 Unbalanced signal input receiver 6 Unbalanced signal output driver 7 Balanced signal input receiver 8 Balanced signal output driver 10 Bus arbitration IC D Balanced signal output driver R Balanced signal input receiver R1, R2 Unbalanced termination resistor R3, R4, R5 Balanced termination resistor R6 Pulldown resistor DI Balanced input DO Balanced output SIO Unbalanced input / output RS reset V power supply voltage

Claims (2)

[Claims] 1. A bus arbitration IC using an asynchronous logic circuit that selects bidirectional signals in accordance with the SCSI2 standard at any time, and a pulse that generates positive and negative pulses according to a change in input signal level. A bus arbitration IC provided with a creation unit, a determination unit that determines the priority of a bus usage right request by the pulse, and an unbalanced signal output driver. 2. A bus arbitration IC using an asynchronous logic circuit that selects bidirectional signals compliant with the SCSI2 standard at any time, the pulse generating positive and negative pulses according to a change in input signal level. A bus arbitration IC provided with a creation unit, a determination unit that determines the priority of the bus use right request by the pulse, and an unbalanced signal output driver, and outputs a balanced signal to an unbalanced signal And a mutual conversion means for converting an unbalanced signal into a balanced signal and outputting the converted balanced signal, the bidirectional signal mutual converter.