TW202246729A - Three-motors configuration for adjusting wafer tilt and focus - Google Patents
Three-motors configuration for adjusting wafer tilt and focus Download PDFInfo
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- G01B9/00—Measuring instruments characterised by the use of optical techniques
- G01B9/02—Interferometers
- G01B9/02015—Interferometers characterised by the beam path configuration
- G01B9/02017—Interferometers characterised by the beam path configuration with multiple interactions between the target object and light beams, e.g. beam reflections occurring from different locations
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- G01B11/00—Measuring arrangements characterised by the use of optical techniques
- G01B11/24—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
- G01B11/2441—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures using interferometry
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- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
- G01B11/30—Measuring arrangements characterised by the use of optical techniques for measuring roughness or irregularity of surfaces
- G01B11/306—Measuring arrangements characterised by the use of optical techniques for measuring roughness or irregularity of surfaces for measuring evenness
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Abstract
Description
本發明係關於調節一晶圓量測工具中之晶圓傾斜及聚焦。The present invention relates to adjusting wafer tilt and focus in a wafer metrology tool.
半導體製造包含在一半導體晶圓上沈積膜層並圖案化該等層。此沈積對晶圓施加應力以導致晶圓翹曲。隨著膜層之數目增加,翹曲增加。對於可具有超過100個層之現代三維(3D)半導體記憶體,翹曲可為500微米至1毫米或更大。干涉量測術可用於量測此翹曲。然而,對於高翹曲,干涉儀可能無法聚焦至整個晶圓上。即使晶圓傾斜以容許單獨量測不同區域中晶圓之形狀,然量測整個晶圓之形狀仍可能係不可行的。Semiconductor manufacturing involves depositing layers on a semiconductor wafer and patterning the layers. This deposition stresses the wafer causing warping of the wafer. As the number of layers increases, warpage increases. For modern three-dimensional (3D) semiconductor memories, which can have more than 100 layers, warpage can range from 500 microns to 1 mm or more. Interferometry can be used to measure this warpage. However, for high warpage, the interferometer may not be able to focus over the entire wafer. Even if the wafer is tilted to allow separate measurement of the shape of the wafer in different regions, measuring the shape of the entire wafer may not be feasible.
因此,需要系統及方法來容許有效地量測半導體晶圓之形狀。Therefore, systems and methods are needed to allow efficient measurement of the shape of semiconductor wafers.
在一些實施例中,一種系統包含:一第一干涉儀,其用於量測一半導體晶圓之一第一側之形狀;一托盤,其用於固持該半導體晶圓並將該半導體晶圓之該第一側暴露於該第一干涉儀;及三個馬達,其等耦合至該托盤。該三個馬達包含在一第一位置耦合至該托盤之一第一馬達、在一第二位置耦合至該托盤之一第二馬達及在一第三位置耦合至該托盤之一第三馬達。In some embodiments, a system includes: a first interferometer for measuring the shape of a first side of a semiconductor wafer; a tray for holding the semiconductor wafer and placing the semiconductor wafer the first side exposed to the first interferometer; and three motors coupled to the tray. The three motors include a first motor coupled to the tray at a first location, a second motor coupled to the tray at a second location, and a third motor coupled to the tray at a third location.
該系統可進一步包含用於量測該半導體晶圓之一第二側之形狀之一第二干涉儀,且該托盤可具有將該半導體晶圓之該第二側暴露於第二干涉儀之一孔。該托盤將該半導體晶圓固持在該第一干涉儀與該第二干涉儀之間。The system can further include a second interferometer for measuring the shape of a second side of the semiconductor wafer, and the tray can have a hole. The tray holds the semiconductor wafer between the first interferometer and the second interferometer.
在一些實施例中,一種方法包含將一半導體晶圓固持在一第一干涉儀與一第二干涉儀之間的一托盤中。該半導體晶圓之一第一側暴露於該第一干涉儀,且該半導體晶圓之一第二側暴露於該第二干涉儀。一第一馬達在一第一位置耦合至該托盤,一第二馬達在一第二位置耦合至該托盤,且一第三馬達在一第三位置耦合至該托盤。該方法亦包含平移該第一馬達及該第二馬達以使該半導體晶圓之一傾斜為零,且在該半導體晶圓之該傾斜為零之情況下,使該半導體晶圓在該第一干涉儀與該第二干涉儀之間居中。使該半導體晶圓居中包含平移該第一馬達、該第二馬達及該第三馬達。In some embodiments, a method includes holding a semiconductor wafer in a tray between a first interferometer and a second interferometer. A first side of the semiconductor wafer is exposed to the first interferometer, and a second side of the semiconductor wafer is exposed to the second interferometer. A first motor is coupled to the tray at a first position, a second motor is coupled to the tray at a second position, and a third motor is coupled to the tray at a third position. The method also includes translating the first motor and the second motor so that a tilt of the semiconductor wafer is zero, and if the tilt of the semiconductor wafer is zero, causing the semiconductor wafer to rotate on the first The interferometer is centered with the second interferometer. Centering the semiconductor wafer includes translating the first motor, the second motor, and the third motor.
該方法可進一步包含在使該半導體晶圓在該第一干涉儀與該第二干涉儀之間居中之後,計算用於量測複數個各自區域中該半導體晶圓之形狀之複數個傾斜。對於該複數個傾斜,計算該第一馬達、該第二馬達及該第三馬達之複數組目標位置。該複數組目標位置之各組目標位置對應於該複數個傾斜之一各自傾斜。平移該第一馬達、該第二馬達及該第三馬達至該複數組目標位置之各組目標位置,以在將該半導體晶圓連續地定位為具有該複數個傾斜之各傾斜。在該半導體晶圓連續地定位為具有該複數個傾斜之各傾斜之情況下,在該複數個各自區域之每一各自區域中量測該半導體晶圓之形狀。The method may further include calculating a plurality of tilts for measuring the shape of the semiconductor wafer in a plurality of respective regions after centering the semiconductor wafer between the first interferometer and the second interferometer. For the plurality of tilts, a plurality of sets of target positions for the first motor, the second motor, and the third motor are calculated. Each set of target positions of the plurality of sets of target positions corresponds to a respective one of the plurality of tilts. Translating the first motor, the second motor, and the third motor to each set of target positions of the plurality of sets of target positions to continuously position the semiconductor wafer with each of the plurality of tilts. The shape of the semiconductor wafer is measured in each respective area of the plurality of respective areas with the semiconductor wafer positioned consecutively with each of the plurality of inclinations.
在一些實施例中,一種系統包含:一第一干涉儀;一第二干涉儀;一托盤,其用於將一半導體晶圓固持在該第一干涉儀與該第二干涉儀之間,其中該半導體晶圓之一第一側暴露於第一干涉儀且該半導體晶圓之一第二側暴露於該第二干涉儀;及三個馬達,其等耦合至該托盤。該三個馬達包含在一第一位置耦合至該托盤之一第一馬達、在一第二位置耦合至該托盤之一第二馬達及在一第三位置耦合至該托盤之一第三馬達。該系統亦包含一或多個處理器及儲存一或多個程式以供該一或多個處理器執行之記憶體。該一或多個程式包含用於執行上述方法之指令。In some embodiments, a system includes: a first interferometer; a second interferometer; a tray for holding a semiconductor wafer between the first interferometer and the second interferometer, wherein a first side of the semiconductor wafer exposed to the first interferometer and a second side of the semiconductor wafer exposed to the second interferometer; and three motors coupled to the tray. The three motors include a first motor coupled to the tray at a first location, a second motor coupled to the tray at a second location, and a third motor coupled to the tray at a third location. The system also includes one or more processors and memory storing one or more programs for execution by the one or more processors. The one or more programs include instructions for performing the methods described above.
在一些實施例中,一種非暫時性電腦可讀儲存媒體儲存一或多個程式以供一干涉量測系統之一或多個處理器執行。該一或多個程式包含用於執行上述方法之指令。In some embodiments, a non-transitory computer readable storage medium stores one or more programs for execution by one or more processors of an interferometric system. The one or more programs include instructions for performing the methods described above.
現在將詳細地參考各種實施例,其等之實例在附圖中繪示。在以下詳細描述中,闡述諸多具體細節,以便提供對所描述之各種實施例之一透徹理解。然而,對於一般技術者而言顯而易見的係,可在沒有此等具體細節之情況下實踐所描述之各種實施例。在其他例項中,尚未詳細描述熟知方法、程式、組件、電路及網路,以避免不必要地模糊實施例之態樣。Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments described. It will be apparent, however, to one of ordinary skill that the various embodiments described may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring aspects of the embodiments.
圖1展示根據一些實施例之用於量測半導體晶圓102之形狀之一干涉量測系統100。干涉量測系統100可位於一晶圓量測工具中(例如,半導體晶圓量測工具730,圖7)。半導體晶圓102可為已在其上沈積並圖案化膜層之一圖案化晶圓(例如,對於其圖案化及由此進行之晶圓製造已完成或正在進行中)。例如,半導體晶圓102可為一三維(3D)記憶體晶圓(即,具有複數個3D記憶體裸片之一晶圓)(例如,一3D快閃記憶體晶圓)。半導體晶圓102固持在一托盤104上之干涉量測系統100中。在一些實施例中,托盤104將半導體晶圓102垂直地固持在干涉量測系統100中,以最小化重力對半導體晶圓102翹曲之影響。FIG. 1 shows an
干涉量測系統100包含用於量測半導體晶圓102之一第一側(例如,頂側,或替代地,底側)之一第一干涉儀106-1,及用於量測半導體晶圓102之一第二側(例如,底側,或替代地,頂側)之一第二干涉儀106-2。第一側與第二側相對。在一些實施例中,干涉儀106-1及106-2係斐索(Fizeau)干涉儀:第一干涉儀106-1係一第一斐索干涉儀,且第二干涉儀106-2係一第二斐索干涉儀。各斐索干涉儀包含:一參考平面108;一透鏡110,其用於將一各自雷射光束124-1或124-2聚焦至參考平面108及半導體晶圓102上;一分束器,其用於將各自雷射光束124-1或124-2引導至透鏡110並傳輸由參考平面108及半導體晶圓102反射之各自雷射光束124-1或124-2;一透鏡114,其用於聚焦經反射各自雷射光束124-1或124-2;一數位攝影機116,其用於接收由透鏡114聚焦之經反射各自雷射光束124-1或124-2;及一電腦118,其用於處理來自數位攝影機116之資料。雷射光束124-1及124-2由一雷射120產生,並藉由各自光纖122-1及122-2提供至各自干涉儀106-1及106-2之分束器112。
在各干涉儀106-1及106-2中,由參考平面108經反射各自雷射光束124-1或124-2之部分與由半導體晶圓102反射之各自雷射光束124-1或124-2之部分干涉,從而產生由攝影機116捕獲之一干涉圖。使用干涉圖分析,量測半導體晶圓102上之點與參考平面108之距離,從而量測點之高度。經量測點高度指示半導體晶圓102之形狀(例如,由於膜沈積導致之半導體晶圓102之翹曲)。藉由使用兩個干涉儀106-1及106-2,量測半導體晶圓102之兩側(即頂側及底側)之高度及因此量測形狀。各干涉儀106-1及106-2之攝影機116可具有一專用電腦118來處理其干涉圖資料,使得干涉量測系統100總共具有兩台電腦118來處理干涉圖資料。在一些實施例中,各攝影機116係一90百萬像素攝影機。In each interferometer 106-1 and 106-2, the portion of the respective laser beam 124-1 or 124-2 reflected by the
圖2A及圖2B展示根據一些實施例之用於固持一半導體晶圓102 (圖2B)之一托盤200。托盤200可為托盤104 (圖1)之一實例。在圖2B中,展示托盤200固持半導體晶圓102,而在圖2A中,展示不具有半導體晶圓102之托盤200。在一些實施例中,托盤200具有一孔202 (圖2A) (例如,一圓孔),半導體晶圓102可固持在其上,以容許半導體晶圓102之兩側(即頂側及底側)暴露於各自干涉儀(例如,干涉儀106-1及106-2,圖1),使得可量測半導體晶圓102之兩側之形狀。半導體晶圓102之一側面向托盤200之外側,且因此暴露於一第一干涉儀(例如,干涉儀106-1,或替代地,干涉儀106-2),而半導體晶圓102之另一側通過孔202暴露於一第二干涉儀(例如,干涉儀106-2,或替代地,干涉儀106-1)。在一些實施例中,托盤具有用於固持半導體晶圓102之夾具218 (例如,三個夾具218)。夾具218可使用最小力來避免或最小化在量測期間半導體晶圓102之形狀之變形。2A and 2B show a
三個馬達(一第一馬達204、一第二馬達208及一第三馬達212)耦合至托盤200以傾斜並平移托盤200。第一馬達204在一第一位置耦合至托盤200,第二馬達208在一第二位置耦合至托盤200,且第三馬達212在一第三位置耦合至托盤200。在一些實施例中,第一位置係沿托盤200之一第一側206,第二位置處於托盤200之一第一角210,且第三位置處於托盤200之一第二角214。第一角210及第二角214處於托盤200之一第二側216之相對端,該第二側216與第一側206相對。Three motors (a
在一些實施例中,第一馬達204、第二馬達208及第三馬達212可在實質上相同方向220 (例如,在製造容限內之相同方向)上平移。例如,第一馬達204、第二馬達208及第三馬達212各自可具有一單一自由度,使得其等僅在方向220上前後移動。方向220可實質上平行於(例如,在製造容限內平行於)第一干涉儀106-1及/或第二干涉儀106-2之光軸111 (圖1)。馬達(例如,馬達之一或兩者) 204、208及/或212可用於達成托盤200及因此達成半導體晶圓102之一期望傾斜。馬達204、208及212之所有三者可用於(例如,同時)平移托盤200及半導體晶圓102之位置,同時保持一期望傾斜。在一些實施例中,馬達204、208及212具有50 nm之一最小運動,重複性為2微米。在一些實施例中,馬達204、208及212各自具有+/-4至5微米範圍內之一行程(即,最大可能平移)。馬達204、208及212之不同者可具有不同行程(例如,各自在+/-4微米至5微米之一範圍內)。In some embodiments, the
圖3A至圖3C係半導體晶圓102之橫截面側視圖,為了達到效果而放大了半導體晶圓102之翹曲。圖3A至圖3C展示根據一些實施例之可使用托盤200及馬達204、208及/或212 (圖2A至圖2B)達成之各自傾斜300A、300B及300C。圖3A展示一零傾斜300A:馬達204、208及/或212已用於使半導體晶圓102之一傾斜為零(由托盤200固持),使得半導體晶圓102之一中心部分之一切線不傾斜(例如,係垂直的,使得半導體晶圓102垂直定位)。在零傾斜300A (例如,及干涉儀106-1與106-2之間的一中心位置)之情況下,干涉儀106-1及/或106-2 (圖1)能夠聚焦至半導體晶圓102之一中心區域302上並因此量測半導體晶圓102之一中心區域302之形狀。在零傾斜300A (及適當平移定位)之情況下,中心區域302因此可在干涉儀106-1及/或106-2之聚焦深度內。然而,在傾斜300A之情況下,半導體晶圓102之高度翹曲阻礙干涉儀106-1及/或106-2聚焦在半導體晶圓102之一頂部區域304及一底部區域306上。在傾斜300A之情況下,區域304及306因此散焦,使得干涉儀106-1及/或106-2不能量測區域304及306之形狀。即,在零傾斜300A之情況下,區域304及306在干涉儀106-1及/或106-2之聚焦深度之外。3A to 3C are cross-sectional side views of the
圖3B展示一傾斜300B,其中馬達204、208及/或212已被用於使半導體晶圓102向前傾斜(由托盤200固持),以容許干涉儀106-1及/或106-2聚焦至區域304上。傾斜300B (連同適當平移定位)容許干涉儀106-1及/或106-2量測頂部區域304之形狀。在傾斜300B (及適當平移定位)之情況下,頂部區域304在干涉儀106-1及/或106-2之聚焦深度內。圖3C展示一傾斜300C,其中馬達204、208及/或212已被用於使半導體晶圓102向後傾斜(由托盤200固持),以容許干涉儀106-1及/或106-2聚焦至區域306上。傾斜300C (連同適當平移定位)容許干涉儀106-1及/或106-2量測底部區域306之形狀。在傾斜300C (及適當平移定位)之情況下,底部區域306在干涉儀106-1及/或106-2之聚焦深度內。3B shows a
圖4展示根據一些實施例之半導體晶圓102之一晶圓圖400之一模擬實例。晶圓圖400展示共同覆蓋半導體晶圓102之一中心區域402及複數個區域404。複數個區域404之各區域404對應於半導體晶圓102 (由托盤200固持)之一各自傾斜(即,非零傾斜),該傾斜可使用馬達204、208及/或212達成(圖2A至圖2B)。例如,區域404之兩者對應於各自傾斜300B及300C (圖3B至圖3C),因此係區域304及306之實例。中心區域402對應於由托盤200固持之半導體晶圓102之一零傾斜(例如,零傾斜300A,圖3A),因此係中心區域302之一實例。各區域404中之半導體晶圓102之形狀可由干涉儀106-1及/或106-2 (圖1)量測,其中半導體晶圓102 (由托盤200固持)使用馬達204、208及/或212定位為具有對應於區域404之各自傾斜(及適當平移定位)。中心區域402中之半導體晶圓102之形狀可由干涉儀106-1及/或106-2 (圖1)量測,其中半導體晶圓102 (由托盤200固持)使用馬達204、208及/或212定位為具有零傾斜(及適當平移定位)。FIG. 4 shows a simulated example of a
為了進行比較,圖5展示對於其中省略了馬達212 (圖2A至圖2B)並用一樞轉接頭替換使得只有兩個馬達可用於傾斜托盤200之一方案中之半導體晶圓102之一晶圓圖500之一模擬實例。在此方案中,可對中心區域402及各自區域504達成傾斜。干涉儀106-1及/或106-2 (圖1)可在中心區域402及各自區域504中量測半導體晶圓102之形狀,但不在各自區域504及中心區域402之外之區域中量測。各自區域504及中心區域402不共同覆蓋半導體晶圓102。因此,在沒有第三馬達212之情況下,干涉儀106-1及/或106-2 (圖1)不能量測整個半導體晶圓102之形狀。For comparison, FIG. 5 shows one of the
圖6A係展示根據一些實施例之在一干涉量測系統(例如,干涉量測系統100,圖1)中定位一半導體晶圓(例如,半導體晶圓102,圖1至圖4)以準備量測半導體晶圓之形狀(例如,翹曲)之一方法600A之一流程圖。在方法600A中,將半導體晶圓固持(602)在一第一干涉儀與一第二干涉儀之間的一托盤中。半導體晶圓之一第一側暴露於第一干涉儀。半導體晶圓之一第二側暴露於第二干涉儀。一第一馬達(例如,馬達204,圖2A至圖2B)在一第一位置耦合至托盤。一第二馬達(例如,馬達208,圖2A至圖2B)在一第二位置耦合至托盤。一第三馬達(例如,馬達212,圖2A至圖2B)在一第三位置耦合至托盤。在一些實施例中,第一干涉儀(例如,干涉儀106-1,圖1)係(604)一第一斐索干涉儀,且第二干涉儀(例如,干涉儀106-2,圖1)係一第二斐索干涉儀。FIG. 6A illustrates positioning a semiconductor wafer (eg,
平移第一馬達及第二馬達(606)以使半導體晶圓之一傾斜為零(例如,以具有一零傾斜300A,圖3A)。使半導體晶圓之傾斜為零可係關於將第一馬達及第二馬達平移不同的量,以使托盤傾斜一定量,使得半導體晶圓之傾斜為零。The first and second motors are translated ( 606 ) to zero one of the semiconductor wafer tilts (eg, to have a zero
在半導體晶圓之一傾斜為零之情況下,半導體晶圓在第一干涉儀與第二干涉儀之間居中(608)。為了使半導體晶圓居中,將第一馬達、第二馬達及第三馬達平移(例如,將所有三個馬達平移相同距離)。在一些實施例中,平移第一馬達、第二馬達及第三馬達(610)以使半導體晶圓在第一斐索干涉儀之一第一參考平面108 (圖1)與第二斐索干涉儀之一第二參考平面108 (圖1)之間居中,同時保持半導體晶圓之零傾斜。使半導體晶圓居中使得半導體晶圓(例如,半導體晶圓之一中心區域402,圖4)對第一干涉儀及第二干涉儀兩者皆聚焦。With one of the semiconductor wafers tilted to zero, the semiconductor wafer is centered between the first interferometer and the second interferometer (608). To center the semiconductor wafer, the first motor, the second motor, and the third motor are translated (eg, all three motors are translated the same distance). In some embodiments, the first motor, the second motor, and the third motor are translated (610) to cause the semiconductor wafer to interfere with the second Fizeau interferometer at one of the first reference planes 108 (FIG. 1) of the first Fizeau interferometer. centered between a second reference plane 108 (FIG. 1) of the instrument while maintaining zero tilt of the semiconductor wafer. Centering the semiconductor wafer brings the semiconductor wafer (eg, a
圖6B係展示根據一些實施例之在一干涉量測系統(例如,干涉量測系統100,圖1)中量測一半導體晶圓(例如,半導體晶圓102,圖1至圖4)之形狀(例如,翹曲)之一方法600B之一流程圖。方法600B可作為方法600A之一延續來執行。6B illustrates measuring the shape of a semiconductor wafer (eg,
在方法600B中,計算(612)用於量測複數個各自區域(例如,複數個區域404及中心區域402,圖4)中半導體晶圓之形狀之複數個傾斜(例如,包含傾斜300B及300C (圖3B至圖3C)連同其他傾斜)。在一些實施例中,複數個各自區域共同覆蓋(614)整個半導體晶圓(例如,如圖4所示)。In
在一些實施例中,為了計算複數個傾斜,使用一第一干涉儀或一第二干涉儀(例如,方法600A之步驟602之第一及/或第二干涉儀,圖6A)(例如,干涉儀106-1及/或106-2,圖1)之至少一者來量測(616)半導體晶圓之一中心區域(例如,中心區域302,圖3A;中心區域402,圖4)之形狀。使用所量測之中心區域之形狀來預測(618)半導體晶圓之晶圓圖。晶圓圖展示一所預測晶圓形狀(即,晶圓在晶圓上之各自位置處之預測高度)。可假定半導體晶圓具有一指定形狀(例如,半導體晶圓之形狀係抛物線形)來預測晶圓圖。例如,可基於假定整個晶圓之形狀係如指定的(例如,抛物線形),藉由自中心區域之形狀推斷來預測晶圓圖。使用預測晶圓圖來判定(620)複數個傾斜。In some embodiments, to calculate the plurality of tilts, a first interferometer or a second interferometer (eg, the first and/or second interferometer of step 602 of
對於複數個傾斜,計算第一馬達、第二馬達及第三馬達馬達之複數組目標位置(622)。複數組目標位置之各組目標位置對應於複數個傾斜之一各自傾斜。For the plurality of tilts, a plurality of sets of target positions for the first motor, the second motor, and the third motor are calculated (622). Each set of target positions of the plurality of sets of target positions corresponds to a respective one of the plurality of tilts.
將第一馬達、第二馬達及第三馬達(例如,馬達204、208及212,圖2A至圖2B)平移(624)至複數組目標位置之一組目標位置,以將半導體晶圓定位為具有複數個傾斜之一傾斜。在半導體晶圓被定位為具有此傾斜之情況下,在複數個各自區域之一各自區域中量測(626)半導體晶圓之形狀。若在量測各自區域中之半導體晶圓之形狀之後存在第一馬達、第二馬達及第三馬達尚未經平移至容許量測任何各自區域之任何剩餘組目標位置(628-是),則選擇下一組目標位置(630),並再次執行步驟624、626及628。若沒有剩餘組目標位置(628-否),則方法600B結束(632)。Translating (624) the first, second, and third motors (e.g.,
步驟624、626、628及630之環路導致平移第一馬達、第二馬達及第三馬達至複數組目標位置之各組目標位置,以將半導體晶圓連續地定位為具有複數個傾斜之各傾斜。且在半導體晶圓連續地定位為具有複數個傾斜之各傾斜之情況下,可在複數個各自區域之每一各自區域中量測半導體晶圓之形狀。因此,藉由編譯各區域(即,對於複數個各自區域)之形狀量測,可獲得半導體晶圓形狀之一完整量測。The loop of
藉由方法600B產生之形狀量測資料可用於程序控制。例如,所量測之半導體晶圓102之翹曲可用於回饋程序控制,以識別對先前處理步驟之改變以減少後續處理晶圓之翹曲或翹曲之變化。在另一實例中,所量測之半導體晶圓102之翹曲可用於前饋程序控制,以識別將對後續處理步驟作出之改變以適應所量測翹曲。形狀量測資料亦可用於處置半導體晶圓102 (例如,判定是否繼續加工、返工或報廢半導體晶圓102)。The shape measurement data generated by
圖7係根據一些實施例之一半導體晶圓量測系統700之一方塊圖。半導體晶圓量測系統700具有一半導體晶圓量測工具730,其包含一或多個(例如,兩個)干涉儀732 (例如,干涉儀106-1及106-2,圖1)及一三馬達托盤734 (例如,具有馬達204、208及212之托盤200,圖2A至圖2B)。FIG. 7 is a block diagram of a semiconductor
半導體晶圓量測系統700亦包含一電腦系統709 (例如一本端主機),電腦系統709具有一或多個處理器702 (例如,CPU)、選用使用者介面706、記憶體710及將此類組件與半導體晶圓量測工具730互連之一或多個通信匯流排704。使用者介面706可包含一顯示器707及一或多個輸入裝置708 (例如,一鍵盤、滑鼠、顯示器707之觸敏表面等)。顯示器可展示來自半導體晶圓量測系統700之結果及其狀態(例如,方法600A及/或600B之狀態及量測結果,圖6A至圖6B)。Semiconductor
記憶體710包含揮發性及/或非揮發性記憶體。記憶體710 (例如,記憶體710內之非揮發性記憶體)包含一非暫時性電腦可讀儲存媒體。記憶體710視情況包含遠離處理器702定位之一或多個儲存裝置及/或可移除地插入電腦系統709中之一非暫時性電腦可讀儲存媒體。在一些實施例中,記憶體710 (例如,記憶體710之非暫時性電腦可讀儲存媒體)儲存以下模組及資料或其等之子集或超集:一作業系統712,其包含用於處理各種基本系統服務及用於執行硬體相關任務之程式;一馬達控制模組714,其用於控制三馬達托盤734之馬達(例如,用於控制馬達204、208及212,圖2A至圖2B)(例如,用於根據方法600A平移馬達,圖6A;用於執行方法600B之步驟624,圖6B);一照明模組716,其用於控制干涉儀732中之照明(例如,用於控制雷射120,圖1);一傾斜計算模組718 (例如,用於計算方法600A之步驟606之零傾斜,圖6A;用於執行方法600B之步驟612,圖6B);一目標位置計算模組720 (例如,用於執行方法600B之步驟622,圖6B),及一晶圓量測模組722(例如,用於執行方法600B之步驟626,圖6B)。Memory 710 includes volatile and/or non-volatile memory. Memory 710 (eg, non-volatile memory within memory 710 ) includes a non-transitory computer-readable storage medium. Memory 710 optionally includes one or more storage devices located remotely from processor 702 and/or a non-transitory computer-readable storage medium removably inserted into computer system 709 . In some embodiments, memory 710 (e.g., the non-transitory computer-readable storage medium of memory 710) stores the following modules and data, or a subset or superset thereof: an operating system 712, which includes Various basic system services and programs for performing hardware-related tasks; a motor control module 714 for controlling the motors of the three-motor tray 734 (eg, for controlling the
記憶體710 (例如,記憶體710之非暫時性電腦可讀儲存媒體)包含用於執行方法600A及/或600B之全部或一部分之指令(圖6A至圖6B)。儲存在記憶體710中之模組之各者對應於用於執行本文所述之一或多個功能之指令集。單獨模組不需要作為單獨軟體程式來實施。模組及模組之各種子集可被組合或以其他方式重新佈置。在一些實施例中,記憶體710儲存上述模組及/或資料結構之一子集或超集。Memory 710 (eg, a non-transitory computer-readable storage medium of memory 710 ) includes instructions for performing all or a portion of
圖7較意欲作為半導體晶圓量測系統700中可能存在之各種特徵之一功能描述,而非作為一結構示意圖。例如,可在多個裝置之間分割電腦系統709之功能性。儲存在記憶體710中之模組之全部或一部分可替換地儲存在透過一或多個網路與半導體晶圓量測系統700通信地耦合之一或多個其他電腦系統中。FIG. 7 is intended to be a functional description of various features that may exist in the semiconductor
為了解釋目的,已參考具體實施例描述前述描述。然而,上述繪示性討論並非希望詳盡無遺或將發明申請專利範圍之範疇限制為所公開之確切形式。鑑於上述教示,諸多修改及變化係可行的。選擇實施例係為了最好地解釋發明申請專利範圍之基本原理及其等之實際應用,從而使熟習此項技術者能夠以適合於考慮之特定用途之各種修改來最佳地使用實施例。The foregoing description, for purposes of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of patentable inventions to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen in order to best explain the basic principles of the claimed invention and their practical application, thereby enabling others skilled in the art to best utilize the embodiments with various modifications as are suited to the particular use contemplated.
100:干涉量測系統 102:半導體晶圓 104:托盤 106-1:第一干涉儀 106-2:第二干涉儀 108:參考平面 110:透鏡 111:光軸 112:分束器 114:透鏡 116:數位攝影機 118:電腦 120:雷射 122-1:光纖 122-2:光纖 124-1:雷射光束 124-2:雷射光束 200:托盤 202:孔 204:第一馬達 206:第一側 208:第二馬達 210:第一角 212:第三馬達 214:第二角 216:第二側 218:夾具 220:方向 300A:傾斜 300B:傾斜 300C:傾斜 302:中心區域 304:頂部區域 306:底部區域 400:晶圓圖 402:中心區域 404:區域 500:晶圓圖 504:區域 600A:方法 600B:方法 602:步驟 604:步驟 606:步驟 608:步驟 610:步驟 612:步驟 614:步驟 616:步驟 618:步驟 620:步驟 622:步驟 624:步驟 626:步驟 628:步驟 630:步驟 632:結束 700:半導體晶圓量測系統 702:處理器 704:通信匯流排 706:使用者介面 707:顯示器 708:輸入裝置 709:電腦系統 710:記憶體 712:作業系統 714:馬達控制模組 716:照明模組 718:傾斜計算模組 720:目標位置計算模組 722:晶圓量測模組 730:半導體晶圓量測工具 732:干涉儀 734:三馬達托盤 100:Interferometric measurement system 102: Semiconductor wafer 104: tray 106-1: The first interferometer 106-2: The second interferometer 108: Reference plane 110: lens 111: optical axis 112: beam splitter 114: lens 116: Digital video camera 118: computer 120:Laser 122-1: Optical fiber 122-2: Optical fiber 124-1: Laser Beam 124-2: Laser Beam 200: tray 202: hole 204: The first motor 206: First side 208:Second motor 210: first angle 212: The third motor 214: second angle 216: second side 218: Fixture 220: direction 300A: inclined 300B: Tilt 300C: inclined 302: central area 304: top area 306: Bottom area 400:Wafer map 402: central area 404: area 500:Wafer map 504: area 600A: Method 600B: Method 602: Step 604: Step 606: Step 608: Step 610: Step 612: Step 614:Step 616: Step 618:Step 620: Step 622: Step 624: step 626: step 628:step 630: step 632: end 700:Semiconductor Wafer Measurement System 702: Processor 704: communication bus 706: user interface 707: display 708: input device 709:Computer systems 710: Memory 712: operating system 714:Motor control module 716: Lighting module 718: Tilt calculation module 720: Target position calculation module 722: Wafer measurement module 730:Semiconductor Wafer Measurement Tools 732:Interferometer 734: Three motor tray
為了更好地理解所描述之各種實施方案,應結合以下附圖,參考以下[實施方式]。For a better understanding of the various embodiments described, reference should be made to the following [Embodiments] in conjunction with the following figures.
圖1展示根據一些實施例之用於量測一半導體晶圓形狀之一干涉量測系統。FIG. 1 shows an interferometric metrology system for measuring the shape of a semiconductor wafer according to some embodiments.
圖2A及圖2B展示根據一些實施例之用於固持一半導體晶圓之一托盤。2A and 2B show a tray for holding a semiconductor wafer according to some embodiments.
圖3A至圖3C係根據一些實施例之展示可使用圖2A及圖2B之托盤及三個馬達達成之各自傾斜之一翹曲半導體晶圓之橫截面側視圖。3A-3C are cross-sectional side views of a warped semiconductor wafer showing respective tilts that can be achieved using the tray and three motors of FIGS. 2A and 2B , according to some embodiments.
圖4展示根據一些實施例之一半導體晶圓之一晶圓圖之一模擬實例,其中一中心區域及複數個區域共同覆蓋半導體晶圓。4 shows a simulated example of a wafer map of a semiconductor wafer in which a central region and a plurality of regions collectively cover the semiconductor wafer, according to some embodiments.
圖5展示對於其中省略圖2A及圖2B之第三馬達並用一樞轉接頭代替之一方案中之一半導體晶圓之一晶圓圖之一模擬實例。5 shows a simulated example of a wafer map of a semiconductor wafer for a scenario in which the third motor of FIGS. 2A and 2B is omitted and replaced with a pivot joint.
圖6A係根據一些實施例之展示在一干涉量測系統中定位一半導體晶圓以準備量測半導體晶圓之形狀之一方法之一流程圖。6A is a flowchart showing a method of positioning a semiconductor wafer in an interferometric metrology system in preparation for measuring the shape of the semiconductor wafer, according to some embodiments.
圖6B係根據一些實施例之展示在一干涉量測系統中量測半導體晶圓之形狀之一方法之一流程圖。6B is a flowchart showing a method of measuring the shape of a semiconductor wafer in an interferometric metrology system, according to some embodiments.
圖7係根據一些實施例之一半導體晶圓量測系統之一方塊圖。FIG. 7 is a block diagram of a semiconductor wafer metrology system according to some embodiments.
相同元件符號係指貫穿整個圖式及說明書之對應部分。The same reference numerals refer to corresponding parts throughout the drawings and the specification.
102:半導體晶圓 102: Semiconductor wafer
200:托盤 200: tray
204:第一馬達 204: The first motor
206:第一側 206: First side
208:第二馬達 208:Second motor
210:第一角 210: first corner
212:第三馬達 212: The third motor
214:第二角 214: second corner
216:第二側 216: second side
218:夾具 218: Fixture
220:方向 220: direction
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