TW202243039A - Method for forming wire - Google Patents

Abstract

The invention provides a method for forming a wire, the method includes providing a first dielectric layer, forming a trench in the first dielectric layer, forming a conductive layer in the trench and covering the first dielectric layer, flattening the conductive layer, forming a wire in the trench, forming a second dielectric layer covering the wire and the first dielectric layer, heating the wire, and thinning the second dielectric layer to reduce the second dielectric layer.

Description

method of forming wires

The invention relates to the field of semiconductor manufacturing process, in particular to a method for making a wire.

In the semiconductor manufacturing process, in order to save the area used by the wafer, a multi-layer stacked electronic component structure is often formed in the vertical direction in a stacked manner, which can effectively reduce the total area and facilitate the miniaturization of the wafer.

In addition, the required electronic components can also be formed on different wafers, and then the different wafers can be bonded together to achieve the same effect of stacking. Therefore, the quality of the bonding between the wafers will affect the yield of the final semiconductor device. Improving the bonding quality between wafers is also one of the development goals in this field.

The invention provides a method for forming wires, comprising providing a first dielectric layer, forming a groove in the first dielectric layer, forming a conductive layer in the groove and covering the first dielectric layer , planarizing the conductive layer, forming a wire in the trench, forming a second dielectric layer covering the wire and the first dielectric layer, performing a heating step on the wire, and thinning the second dielectric layer electrical layer to reduce a thickness of the second dielectric layer.

A feature of the present invention is that applicants have discovered that it is necessary to form a second dielectric layer covering the wires before performing the HPA heating step, thus avoiding the possibility of the holes in the wires expanding during the heating step. However, the applicant has found that when a thinner second dielectric layer is used to cover the wire, and then the heating step is performed, the wire will easily expand or even break through the second dielectric layer. Therefore, in the present invention, a thicker second dielectric layer is firstly used to cover the wire to prevent the metal wire from expanding and breaking through the second dielectric layer during the heating step, and then the second dielectric layer is thinned after the heating step is completed. to meet actual needs. With the method provided by the present invention, a higher quality semiconductor wire structure can be produced.

In order to enable those who are familiar with the general skills in the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, the composition of the present invention and the desired effects are described in detail. .

For the convenience of description, the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As for the up-down relationship of relative elements in the figures described in the text, those skilled in the art should understand that they refer to the relative positions of objects, so they can be reversed to present the same components, which should all belong to this specification. The scope of disclosure is described here first.

Please refer to FIG. 1 to FIG. 7 . FIG. 1 to FIG. 7 are cross-sectional schematic diagrams illustrating the manufacturing process of forming a semiconductor structure containing wires and bonding the structure with another structure according to the present invention. First, as shown in FIG. 1 , a first dielectric layer 10 is provided, and a trench 12 is formed in the first dielectric layer 10 . The material of the first dielectric layer 10 is, for example, silicon oxide, which may be the topmost layer of a multi-layer stacked dielectric layer on a substrate (not shown in the figure), where a wiring layer is formed. In other words, a wire will be formed in the first dielectric layer 10 later, and the wire may be connected with another wire layer on another substrate (not shown) to form a silicon via (Through Silicon Via, TSV). way of electrical connection. The trench 12 is a predetermined position for forming the wire, and the trench 12 can be formed by etching, etc., and the present invention does not limit its fabrication method. In addition, it is understandable that other dielectric layers or wires may be included under the first dielectric layer 10 , which are not shown here for the sake of brevity. Next, a conductive layer 14 is formed to cover the first dielectric layer 10 and fill the trench 12 . The conductive layer 14 is, for example, copper or other metals with good conductivity. The conductive layer 14 can be used as a subsequent wire.

Subsequently, as shown in FIG. 2 , a planarization step (such as chemical mechanical polishing) is used to remove the excess conductive layer 14 , and the remaining conductive layer 14 in the trench is defined as a wire 16 .

As shown in FIG. 3 , a second dielectric layer 18 is formed to cover the wire 16 and the first dielectric layer 10 . The material of the second dielectric layer 18 is, for example, silicon carbide nitride (SiCN), and the thickness is above 400 angstroms. The second dielectric layer 18 is formed, for example, by chemical vapor deposition (CVD), but not limited thereto. The second dielectric layer 18 in this embodiment can serve as a function of protecting the wire 16 to prevent voids from being generated inside the wire 16 due to heating in a subsequent heating step.

As shown in FIG. 4 , a heating step is performed, such as a high pressure anneal (HPA) step P1, and the HPA step P1 is performed in an environment fed with hydrogen gas. It is worth noting that the purpose of performing this HPA step P1 is that in the previous process, some charges may remain in the wire 16 or other components. When performing the HPA step P1, hydrogen ions can be introduced into the wire by high temperature. and other components, and remove the original residual charges to reduce the impact of charges on semiconductor components.

As shown in FIG. 5, a thinning step P2 is performed to thin the second dielectric layer 18, for example, a part of the second dielectric layer 18 is removed by chemical mechanical polishing (CMP) or etch back, A part of the second dielectric layer 18 is left to cover the wire 16 and the first dielectric layer 10 . In this embodiment, the original thickness of the second dielectric layer 18 is greater than 400 angstroms, while the thickness of the thinned second dielectric layer 18 is less than 360 angstroms. In other words, the thickness of the second dielectric layer 18 is reduced by more than about 10%. It is worth noting that in a general CVD process, the thickness of one standard deviation of variation is about plus or minus 10 angstroms, so a thickness reduction of more than 40 angstroms has exceeded the thickness of several standard deviations of variation, that is, for the entire second dielectric layer The thickness of 18 has changed significantly.

The applicant found that if the HPA step P1 is directly performed on the wire 16 without forming the above-mentioned second dielectric layer 18 , the void during deposition inside the wire 16 may be enlarged and the performance of the wire 16 may be affected. The HPA step P1 is performed after covering the second dielectric layer 18 , which can effectively reduce the occurrence of holes in the above-mentioned wires.

However, the applicant has found another problem, that is, when the thickness of the second dielectric layer 18 is relatively thin (less than 360 angstroms), when the HPA step P1 is performed, protrusions (protrusions) may occur due to thermal expansion of the metal wire 16 ( hillock), may even break through the second dielectric layer 18, exposing the wire 16 to the air or other dielectric layers formed subsequently. Therefore, in this embodiment, the thickness of the second dielectric layer 18 deposited at the beginning needs to be controlled to be greater than 400 angstroms, and a thicker second dielectric layer 18 is used to cover the wires 16, so as to prevent the above-mentioned heating protrusion from penetrating through the second dielectric layer. Layer 18 happens. And in the subsequent steps, an additional thinning step P2 is performed to reduce the thickness of the second dielectric layer 18 to meet the actual use requirements.

Subsequently, as shown in FIG. 6 , a third dielectric layer 20 and a fourth dielectric layer 22 are formed on the second dielectric layer 18 . The third dielectric layer 20 and the fourth dielectric layer 22 can be used as planar layers bonded to another substrate. In this embodiment, the third dielectric layer 20 is, for example, tetraethoxysilane (TEOS), and the fourth dielectric layer 22 is, for example, silicon carbonitride (SiCN), but not limited thereto.

Finally, as shown in Figure 7, the above structure is bonded to another substrate. For example, the first dielectric layer 110, the wire 116, the second dielectric layer 118, the third dielectric layer 120 and the fourth dielectric layer 122 are formed on another substrate (not shown) in a similar manner, and then Bond the structure shown in Figure 6 to another substrate. Finally, a via structure 30 is formed to penetrate the second dielectric layer 18 , the third dielectric layer 20 and the fourth dielectric layer 22 , and electrically connect the wire 16 and the wire 116 to complete the bonding of the two substrates. In this embodiment, the via structure 30 is, for example, a through-silicon via (TSV), and the material of the TSV is, for example, a metal with good conductivity such as copper, but it is not limited thereto.

Based on the above paragraphs and drawings, the present invention provides a method for forming wires, including providing a first dielectric layer 10, forming a trench 12 in the first dielectric layer 10; forming a conductive layer 14 in the trench 12 Center and cover on the first dielectric layer 10, planarize the conductive layer 14, form a wire 16 in the trench 12, form a second dielectric layer 18, cover the wire 16 and the first dielectric layer 10, and conduct the wire 16 perform a heating step (HPA step P1 ), and thin the second dielectric layer 18 to reduce a thickness of the second dielectric layer 18 .

In some embodiments, the heating step comprises heating in a hydrogen environment.

In some embodiments, the thickness of the second dielectric layer 18 before being thinned is greater than 400 angstroms.

In some embodiments, the thickness of the second dielectric layer 18 after being thinned is less than 360 angstroms.

In some embodiments, the conductive layer 14 includes copper.

In some embodiments, the material of the second dielectric layer 18 includes silicon carbonitride (SiCN).

In some embodiments, after the second dielectric layer 18 is thinned, a third dielectric layer 20 and a fourth dielectric layer 22 are formed on the second dielectric layer 18, and the fourth The dielectric layer 22 contacts the other dielectric layer 122 to bond the fourth dielectric layer 22 and the other dielectric layer 122 .

In some embodiments, the third dielectric layer 20 includes tetraethoxysilane (TEOS).

In some embodiments, the fourth dielectric layer 22 includes silicon carbon nitride (SiCN).

In some embodiments, it further includes forming a via structure 30 , penetrating through the second dielectric layer 18 , the third dielectric layer 20 and the fourth dielectric layer 22 , and electrically connecting with the wire 16 .

A feature of the present invention is that applicants have discovered that it is necessary to form a second dielectric layer covering the wires before performing the HPA heating step, thus avoiding the possibility of the holes in the wires expanding during the heating step. However, the applicant has found that when a thinner second dielectric layer is used to cover the wire, and then the heating step is performed, the wire will easily expand or even break through the second dielectric layer. Therefore, in the present invention, a thicker second dielectric layer is firstly used to cover the wire to prevent the metal wire from expanding and breaking through the second dielectric layer during the heating step, and then the second dielectric layer is thinned after the heating step is completed. to meet actual needs. With the method provided by the present invention, a higher quality semiconductor wire structure can be produced. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: The first dielectric layer 12: Groove 14: Conductive layer 16: wire 18: Second dielectric layer 20: The third dielectric layer 22: The fourth dielectric layer 30: Through hole structure 110: the first dielectric layer 116: wire 118: second dielectric layer 120: the third dielectric layer 122: The fourth dielectric layer P1: heating step P2: Thinning step

FIG. 1 to FIG. 7 are cross-sectional schematic diagrams illustrating the manufacturing process of forming a semiconductor structure containing wires and bonding the structure with another structure according to the present invention.

10: The first dielectric layer

16: wire

18: Second dielectric layer

20: The third dielectric layer

22: The fourth dielectric layer

30: Through hole structure

110: the first dielectric layer

116: wire

118: second dielectric layer

120: the third dielectric layer

122: The fourth dielectric layer

Claims (10)

A method of forming a wire, comprising: providing a first dielectric layer; forming a trench in the first dielectric layer; forming a conductive layer in the trench and covering the first dielectric layer; planarizing the conductive layer to form a wire in the trench; forming a second dielectric layer covering the wire and the first dielectric layer; subjecting the wire to a heating step; and Thinning the second dielectric layer to reduce a thickness of the second dielectric layer. The method as described in claim 1, wherein the heating step includes heating in a hydrogen environment. The method of claim 1, wherein the thickness of the second dielectric layer before being thinned is greater than 400 angstroms. The method according to claim 1, wherein the thickness of the second dielectric layer is less than 360 angstroms after being thinned. The method described in claim 1, wherein the conductive layer includes copper. The method described in claim 1, wherein the material of the second dielectric layer includes silicon carbonitride (SiCN). The method described in item 1 of the scope of the patent application, which further includes: After the second dielectric layer is thinned, forming a third dielectric layer and a fourth dielectric layer on the second dielectric layer; and The fourth dielectric layer is in contact with another dielectric layer to bond the fourth dielectric layer and the other dielectric layer. The method according to claim 7, wherein the third dielectric layer comprises tetraethoxysilane (TEOS). The method according to claim 7, wherein the fourth dielectric layer comprises silicon carbonitride (SiCN). The method described in claim 7 of the patent application further includes forming a via structure, penetrating through the second dielectric layer, the third dielectric layer and the fourth dielectric layer, and electrically connecting with the wire.

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