TW202242558A - Method for manufacturing semiconductor integrated circuit, method for manufacturing semiconductor device, and exposure apparatus - Google Patents

Abstract

A method for manufacturing a semiconductor integrated circuit in each of a plurality of regions on a substrate comprises: forming an electronic circuit as a portion of the semiconductor integrated circuit in each of the plurality of regions using a mask pattern affixed to a mask substrate; and forming a specific circuit indicating specific information specific to each semiconductor integrated circuit in a portion of each of the plurality of regions using a variable shaping exposure apparatus having a variable shaping mask. The specific circuits respectively formed in the plurality of regions are different from each other.

Description

Manufacturing method of semiconductor integrated circuit, manufacturing method of semiconductor element, and exposure apparatus

The present invention relates to a manufacturing method of a semiconductor integrated circuit, a manufacturing method of a semiconductor element and an exposure device. This application claims priority based on Japanese Patent Application No. 2020-217784 filed on December 25, 2020, the contents of which are incorporated herein.

Among semiconductor elements used for communication purposes, a semiconductor integrated circuit is proposed, which forms a unique circuit for memorizing some inherent information in a plurality of semiconductor integrated circuits including most common circuits, respectively. , and improve the confidentiality of communication (Non-Patent Document 1). [Prior art literature] [Non-patent literature]

[Non-Patent Document 1] Isabelle Servin, 10 others, "Process development of a maskless N40 via level for security application with multi-beam lithography", SPIE Proceedings Vol. 10584, SPIE (USA), March 19, 2018

According to the first aspect, the method of manufacturing a semiconductor integrated circuit is a method of manufacturing a semiconductor integrated circuit in a plurality of regions on a substrate, including: forming an electronic circuit which is a part of said semiconductor integrated circuit, respectively; and using a variable-shaping exposure apparatus including a variable-shaping mask, forming, on a portion of each of said plurality of regions, an electronic circuit representing each of said semiconductor integrated circuits. The specific circuit of the specific information, the specific circuit formed in each of the plurality of regions is different from each other. According to the second aspect, the method for manufacturing a semiconductor element includes: separately packaging a plurality of semiconductor integrated circuits manufactured by the method for manufacturing a semiconductor integrated circuit of the first aspect to form a plurality of semiconductor elements; relational data, generating second interrelationship data, the second interrelationship data representing the packaged plurality of semiconductor elements and the inherent circuits of the semiconductor integrated circuits included in the plurality of semiconductor elements The corresponding relationship of the inherent information of . According to a third aspect, the exposure device includes: a substrate holding unit for holding the substrate; a variable shaping mask for setting the shape of a bright and dark pattern irradiated on the substrate; The correlation data of the mutual relationship is determined by the shapes of the light and dark patterns respectively exposed to a plurality of regions corresponding to a plurality of the semiconductor integrated circuits formed on the substrate. According to the fourth aspect, the exposure device includes: a substrate holding unit for holding the substrate; a variable shaping mask for setting the shape of the bright and dark pattern irradiated on the substrate; The integrated circuits are respectively formed, and inherent information including multi-bit digital information is determined by the shapes of the light and dark patterns respectively exposed to a plurality of specific regions corresponding to the plurality of semiconductor integrated circuits formed on the substrate.

(Method of Manufacturing Semiconductor Integrated Circuit of First Embodiment) FIG. 1 is a diagram schematically showing a plurality of semiconductor integrated circuits 1 manufactured on a substrate 10 by a method of manufacturing a semiconductor integrated circuit according to a first embodiment.

The X direction, Y direction, and Z direction indicated by arrows in FIG. 1 and in each figure referred to below are respectively orthogonal directions, and the X direction, Y direction, and Z direction represent the same direction in each figure. Hereinafter, the directions indicated by the respective arrows are respectively referred to as +X direction, +Y direction, and +Z direction. Also, the position in the X direction is referred to as an X position, the position in the Y direction is referred to as a Y position, and the position in the Z direction is referred to as a Z position.

In the method of manufacturing the semiconductor integrated circuit 1 according to the first embodiment, as an example, the semiconductor integrated circuits 1 are respectively manufactured in the plurality of regions 11 on the substrate 10 including silicon. The plurality of semiconductor integrated circuits 1 formed on the substrate 10 form a common circuit 2 , which is an electronic circuit common to each semiconductor integrated circuit 1 , and a unique circuit 3 representing unique information unique to each semiconductor integrated circuit 1 . In other words, each semiconductor integrated circuit 1 includes a common circuit 2 and a specific circuit 3 .

As shown in FIG. 1 , as an example, the shape of the semiconductor integrated circuit 1 in the XY plane is a rectangle, and a plurality of semiconductor integrated circuits 1 are two-dimensionally arranged on the substrate 10 along the X direction and the Y direction. Hereinafter, each semiconductor integrated circuit 1 may be identified according to the arrangement positions in the X direction as columns ( R1 to R7 ) and the arrangement positions in the Y direction as rows ( C1 to C6 ).

FIG. 2 is an enlarged view showing an enlarged semiconductor integrated circuit 1 manufactured by the method for manufacturing a semiconductor integrated circuit according to the first embodiment. In the semiconductor integrated circuit 1 , various circuits including an encryption circuit 22 , a decoding circuit 23 , and a communication circuit 24 described below are formed in the portion of the above-mentioned common circuit 2 . A part of the unique information memory circuit 21 is included in the common circuit 2, and the other part is included in the unique circuit 3 indicated by the dotted line.

FIG. 3 is a diagram showing a circuit diagram of an example of the unique information memory circuit 21 . As an example, the inherent information memory circuit 21 is a common NAND (Not-And, NAND) mask read only memory (read only memory, ROM) circuit, a plurality of which are arranged along the data line DL extending in the Y direction A metal-oxide-semiconductor (MOS) transistor TR is connected to a gate of each MOS transistor TR with a selection line SL extending along the X direction. A voltage applying part 26 and a voltage detecting part 27 are respectively arranged at both ends of each data line DL. A voltage application unit 28 for applying a voltage to the gate of each MOS transistor TR via the selection line SL is arranged at an end of each selection line SL.

In the unique information memory circuit 21, a plurality of MOS transistors TR constituting the memory area of the mask ROM circuit are included in the unique circuit 3 indicated by a dotted line. On the other hand, the voltage application unit 26 , the voltage application unit 28 , and the voltage detection unit 27 are not included in the specific circuit 3 but are included in the common circuit 2 shown in FIG. 2 . Furthermore, as mentioned above, since the unique information storage circuit 21 is a normal mask ROM circuit, its detailed description will be omitted. Furthermore, in this specification, a circuit includes not only a completed electrical circuit that performs a function, but also a part of a completed electrical circuit to some extent.

FIG. 4A is a plan view showing the structure of a partial region 25 surrounded by a dotted line in FIG. 3 in the intrinsic circuit 3 serving as a mask ROM circuit viewed from the +Z direction. FIG. 4B is a diagram showing a cross-section of a portion along line AA in FIG. 4A . A plurality of n-type MOS transistors TR (TR1, TR2) including a source/drain region SD and a gate electrode serving as a selection line SL are formed inside the specific circuit 3 as an example. , gate oxide film GO, and channel part Ch0 and channel part Ch1. The source/drain region SD is doped with impurity ions such as phosphorus or arsenic at a high concentration.

The source/drain regions SD of the plurality of MOS transistors TR1 and TR2 arranged at the same X position and arranged along the Y direction are formed continuously along the Y direction. Thereby, the source/drain regions SD of the plurality of MOS transistors TR1 and TR2 , and the channel portions Ch0 and Ch1 form a data line DL as a whole (see FIG. 3 ).

The channel portion Ch0 of several MOS transistors such as MOS transistor TR1 is made into an intrinsic semiconductor state in which the concentration of impurity ions is low. On the other hand, channel portions Ch1 of several MOS transistors such as MOS transistor TR2 are set in an n-type semiconductor state having a high concentration of impurity ions such as phosphorus or arsenic.

The MOS transistor TR2 including the channel portion Ch1 having a high concentration of impurity ions is turned on even when a potential of either positive or 0 [V] is applied to the selection line SL serving as a gate. Therefore, the channel Ch1 included in the MOS transistor TR2 memorizes, for example, a state corresponding to data "1".

On the other hand, the MOS transistor TR1 including the channel portion Ch0 having a low concentration of impurity ions is turned on only when a positive potential is applied to the selection line SL serving as a gate. Therefore, the channel part Ch0 included in the MOS transistor TR1 memorizes, for example, a state corresponding to data "0". Furthermore, the data stored in the channel Ch0 having a low concentration of impurity ions may be set to "1", and the data stored in the channel Ch1 having a high concentration of impurity ions may be set to "0".

The plurality of semiconductor integrated circuits 1 formed on the substrate 10 respectively include the above-mentioned common circuit 2 and specific circuit 3 . In addition, the concentration distribution of impurity ions in a part of the intrinsic circuit 3 , for example, the above-mentioned channel portion Ch0 and channel portion Ch1 is different among the plurality of semiconductor integrated circuits 1 .

In the manufacturing method of the first embodiment, in the semiconductor integrated circuit 1, the circuit portion and the common circuit 2 common to a plurality of semiconductor integrated circuits 1 in the specific circuit 3 are formed by using a mask fixed to the mask substrate. The pattern (the combination of the mask substrate and the mask pattern will also be referred to as "fixed mask" hereinafter) is formed by exposure. As an example, the fixed mask may be a light-transmissive mask in which a light-shielding film such as chrome as a mask pattern or a transparent film of a dielectric body as a phase shifter are formed on a light-transmitting mask substrate. Alternatively, a light-absorbing film serving as a mask pattern or a reflective mask having a step shape serving as a phase shifter may be formed on the surface of a reflective mask substrate.

On the other hand, the different circuit portions of the plurality of semiconductor integrated circuits 1 in the intrinsic circuit 3 are formed by exposure using a variable reshaping mask. Variable shaping masks are so-called spatial light modulators. The reflective variable shaping mask can be used, for example, in a reflective surface in which a plurality of movable micromirrors are formed, or a reflective liquid crystal display element. As the transmissive variable shaping mask, for example, a transmissive liquid crystal display element can be used. Furthermore, the details of the exposure apparatus using the variable shaping mask will be described below.

Hereinafter, the flow of the manufacturing method of the first embodiment will be described with reference to FIG. 6 . In the same way as in the production of general semiconductor integrated circuits, the semiconductor integrated circuit 1 is produced by performing a plurality of lithography steps on the substrate 10 in the production method of the first embodiment. Therefore, step S100 is a step at the beginning of a cycle including all N lithography steps. Furthermore, the substrate 10 is not limited to one substrate, and may also be an aggregate of multiple substrates.

Furthermore, in this specification, the lithography step refers to forming a photosensitive film (photoresist) on the substrate 10, patterning the photosensitive film through exposure and development, and using the patterned photosensitive film to process the substrate 10. step. The lithography step may include the step of forming a specific film on the substrate 10 before forming the photosensitive film. In addition, the processing of the substrate 10 may be etching, oxidation, nitriding, or ion implantation for the substrate 10 or a specific film formed on the substrate 10 .

In step S110, it is determined whether the jth lithography step is an exposure step using a variable shaping mask. When it is judged as negative (No), go to step S120 and perform a lithography step including exposure using a fixed mask. In step S120, the fixed mask on which the circuit pattern of the common circuit 2 including the encryption circuit 22, the decoding circuit 23, and the communication circuit 24 constituting the semiconductor integrated circuit 1 is formed is used. Therefore, in step S120 , a circuit pattern constituting a part of the common circuit 2 including the encryption circuit 22 , the decoding circuit 23 , and the communication circuit 24 is formed on the substrate 10 . A lithography step including exposure using a fixed mask is the same as a lithography step generally used in the manufacture of a semiconductor integrated circuit, and thus a detailed description thereof is omitted.

Furthermore, the fixed mask used in step S120 may include a mask pattern corresponding to a circuit pattern of a portion common to a plurality of semiconductor integrated circuits 1 in the intrinsic circuit 3 . In this case, in step S120 , on the substrate 10 , in addition to the various circuit patterns described above, part of the circuit pattern of the portion common to the plurality of semiconductor integrated circuits 1 in the specific circuit 3 is also formed together.

In step S120 , a method of forming a circuit pattern of a portion common to a plurality of semiconductor integrated circuits 1 in the inherent circuit 3 will be described with reference to FIGS. 7A and 7B . FIG. 7A is a diagram showing an example of a fixed mask 30 for forming a circuit pattern of a portion common to a plurality of semiconductor integrated circuits 1 . The fixed mask 30 includes a light-transmitting mask substrate 31 and a mask pattern 32 formed on the surface of the mask substrate 31 for forming the source/drain region SD in the unique information memory circuit 21 as an example. The mask pattern 32 includes a light-transmitting portion 33 and a light-shielding portion 34 .

Furthermore, FIG. 7A shows a mask pattern 32 corresponding to a portion 25M corresponding to the partial region 25 shown in FIGS. 3 and 5 in the source/drain region SD in the unique information memory circuit 21 . The AA line in FIG. 7A is shown at a position on the mask pattern 32 corresponding to the AA line shown in FIG. 5 . Furthermore, the mask pattern 32 may include a portion other than the partial area 25 of the inherent information memory circuit 21 , and mask patterns corresponding to other circuits such as the encryption circuit 22 , the decoding circuit 23 , and the communication circuit 24 . Or the mask pattern 32 may not include patterns in the partial area 25 of the inherent information memory circuit 21, but only include mask patterns corresponding to other circuits such as the encryption circuit 22, the decoding circuit 23, and the communication circuit 24.

FIG. 7B is a diagram showing a step of forming source/drain regions SD in portions corresponding to specific circuits 3 in each region 11 on the substrate 10 using the fixed mask 30 shown in FIG. 7A . FIG. 7B is a cross-sectional view of the substrate 10 on line AA shown in FIG. 5 .

First, a photosensitive film 26 such as a photoresist is formed on the substrate 10 , and the photosensitive film 26 is exposed using the fixed mask 30 to expose the photosensitive film 26 corresponding to the light-transmitting portion 33 . Then, the photosensitive portion of the photosensitive film 26 is removed by development to form an opening 26 o, and the surface of the substrate 10 is exposed from the opening 26 o.

Thereafter, by using the remaining photosensitive film 26 , that is, the patterned photosensitive film 26 as a mask, arsenic or phosphorus, for example, is ion-implanted on the substrate 10 to form source/drain regions SD. Moreover, at the same time, it is also possible to form source/drain regions in parts other than the partial region 25 of the inherent information memory circuit 21, and specific parts in other circuits such as the encryption circuit 22, the decoding circuit 23, and the communication circuit 24. .

After the steps of step S120 are completed, go to step S160 and repeat the cycle from step S110 to step S160 until N times of processes are completed.

When the determination in step S110 is affirmative (Yes), proceed to step S130. In step S130 , it is judged whether the jth lithography step is not only the exposure using the variable shaping mask, but also the exposure using the fixed mask. If the judgment is negative (No), go to step S140 to perform a lithography step including exposure using a variable shaping mask.

In step S140 , for the unique circuit 3 of the unique information memory circuit 21 , different circuit patterns among the plurality of semiconductor integrated circuits 1 are formed. However, as will be described later with reference to FIG. 12 , a part of the semiconductor integrated circuit 1 may be formed in the same pattern as the specific circuit 3 .

FIG. 8A is a diagram showing the shape (shading distribution) of the light and dark pattern 35 formed on the substrate 10 using a variable shaping mask. Line AA in FIG. 8A is shown at a position corresponding to line AA shown in FIG. 5 . FIG. 8A only shows the pattern in the small area 25E corresponding to the partial area 25 in the light and dark pattern 35 , and the light and dark pattern 35 may also include the area corresponding to all the intrinsic circuits 3 .

8B is a diagram illustrating a method of implanting ions of specific impurity concentrations into the channel portions Ch0 and channel portions Ch1 of the plurality of MOS transistors TR included in the specific circuit 3 using the light and dark pattern 35 shown in FIG. 8A . FIG. 8B is a cross-sectional view of the substrate 10 on line AA shown in FIG. 5 .

In step S140 , a photosensitive film 27 such as photoresist is formed on the substrate 10 , and the light and dark pattern 35 formed by the variable shaping mask is exposed to the photosensitive film 27 . At this time, the shape (light and dark distribution) of the light and dark pattern 35 is set so that the portion corresponding to the channel portion Ch1 becomes the bright portion 36 and the other portion becomes the dark portion 37 . That is, the variable shaping mask is set so that the portion 38 corresponding to the channel portion Ch0 becomes the dark portion 37 in the same manner as the portion 39 corresponding to the channel portion Ch0 and other than the channel portion Ch1. The light and dark pattern 35 may be different for each semiconductor integrated circuit 1 formed in each region 11 in the substrate 10 .

The portion of the photosensitive film 27 exposed by the bright portion 36 is removed by subsequent development to form the opening 27 o, and the surface of the substrate 10 is exposed from the opening 27 o. Thereafter, using the remaining photosensitive film 27 , that is, the patterned photosensitive film 27 as a mask, the substrate 10 is ion-implanted with arsenic or phosphorus as an example, and impurity ions of a specific concentration are implanted into the channel Ch1 .

At this time, since the portion corresponding to the channel portion Ch0 is covered with the photosensitive film 27 , ions are not implanted. Therefore, by step S140 , a specific concentration distribution of impurity ions can be formed in each channel portion of a plurality of MOS transistors constituting a NAND-type mask ROM as an example of the unique information memory circuit 21 . As described above, for example, 1-bit data "1" is stored in the channel part Ch1 doped with impurity ions at a high concentration, and 1-bit data is stored in the channel part Ch0 not doped with impurity ions (low concentration). "0". Therefore, if there are M MOS transistors TR each including a channel portion in the dedicated circuit 3 , M bits of information can be stored in the dedicated circuit 3 . The number of MOS transistors TR included in the inherent circuit 3 is not limited to 8×8=64 as shown in FIG. 3 , but can be any number.

Thereby, unique information different from each other can be stored in each unique information memory circuit 21 of the semiconductor integrated circuit 1 formed in the plurality of regions 11 on the substrate 10 . In other words, the unique circuit 3 representing the unique information unique to each semiconductor integrated circuit 1 and having at least a part of each circuit pattern different can be formed in a part of each of the plurality of regions 11 on the substrate 10 . In addition, it can be considered that the distribution of the concentration of impurity ions in the channel portion Ch0 and the channel portion Ch1 is also a circuit pattern.

After the steps of step S140 are completed, go to step S160 and repeat the cycle from step S110 to step S160 until N times of processes are completed.

When the determination in step S130 is affirmative (Yes), go to step S150. 9, 10A, 10B, and 10C are diagrams illustrating the lithography step in step S150. Step S150 is a lithography step in which exposure using a variable shaping mask is also performed in addition to exposure using a fixed mask. .

In step S150 , as shown in the flow chart of FIG. 9 , first in step S151 , a thin film is formed on the substrate 10 . Furthermore, when it is not necessary to form a thin film, step S151 can also be omitted.

Next, in step S152 , a photosensitive film 26 such as a photoresist is formed on the substrate 10 . Then, in step S153 , the photosensitive film 26 is exposed using the fixed mask 30 shown in FIG. 7A . A cross-sectional view of the substrate 10 and the photosensitive film 26 after exposure using the fixed mask 30 is shown in FIG. 10A . In addition, FIG. 10A is a cross-sectional view of the substrate 10 taken along line AA in FIG. 5 , similarly to FIG. 7B and FIG. 8B . By exposure using the fixed mask 30 , a photosensitive portion 26E is formed on the photosensitive film 26 . A portion not exposed to light by exposure using the fixed mask 30 remains as a non-light-sensitive portion 26N.

Then, in step S154 , the photosensitive film 26 is developed. The photosensitive film 26 after development is in the same state as the photosensitive film 26 shown in FIG. 7B . Thereafter, in step S155 , for the remaining photosensitive film 26 , the light and dark pattern 35 as shown in FIG. 8A formed by the variable shaping mask is exposed. Then, in step S156, the photosensitive film 26 is developed again. In the photosensitive film 26 after development, as shown in FIG. 10C , only the non-photosensitive portion 26N left unsensitized by the exposure using the fixed mask 30 in step S153 and the exposure using the variable shaping mask in step S155 remains. on the substrate 10.

In this state, the process proceeds to step S157, and the substrate 10 is processed using the photosensitive film 26 of the remaining non-photosensitive portion 26N as shown in FIG. 10C , that is, the patterned photosensitive film 26 . In the example shown in FIG. 10C , as an example, the treatment of the substrate 10 is ion implantation of arsenic or phosphorus on the substrate 10 , and the source/drain region SD and the channel portion are simultaneously formed by the ion implantation. Ch1. On the other hand, since the channel portion Ch0 is covered by the photosensitive film 26 , ion implantation is not performed.

Furthermore, in step S151 , when a thin film is formed on the substrate 10 , the ion implantation may also be performed on the thin film formed on the substrate 10 instead of on the substrate 10 .

Furthermore, in the above steps, the development of the photosensitive film 26 is performed after the exposure using the fixed mask and the exposure using the variable shaping mask respectively, but the development after exposure using the fixed mask (step development of S154). In this case, as shown in the cross-sectional view of FIG. 10B , the photosensitive film 26 after performing step S155 forms the photosensitive portion 26E formed by exposure using the fixed mask 30 , and the photosensitive portion 26E formed by exposure using the variable shaping mask. The photosensitive part 26F formed, and the non-photosensitive part 26N which was not photosensitive by any exposure. In step S156 , the photosensitive film 26 in this state can be developed to form the photosensitive film 26 (non-photosensitive portion 26N) in the state shown in FIG. 10C . In addition, in the above steps, the exposure using the variable shaping mask is performed after the exposure using the fixed mask, but the exposure using the fixed mask may be performed after the exposure using the variable shaping mask.

Based on the above, in step S150, similar to the above-mentioned step S140, a variable shaping mask can be used to form the inherent information, In addition, at least a part of each circuit pattern is different from the original circuit 3 .

After the steps of step S150 are completed, go to step S160 and repeat the cycle from step S110 to step S160 until N times of processes are completed. Furthermore, after step S160 is completed, each semiconductor integrated circuit 1 may be cut (singulated) from the substrate 10 as described below.

As shown in FIG. 4A and FIG. 4B , through subsequent steps, a selection line SL serving as a gate is formed on the ion-implanted channel portion Ch1 and the ion-implanted channel portion Ch0 . Therefore, it is difficult to analyze the concentration of impurity ions in the channel portions Ch0 and Ch1 only by observing the completed semiconductor integrated circuit 1 or the like from the upper surface. Therefore, in the above method, it is possible to reduce the worry that the inherent information stored in the inherent circuit 3 will be restored.

Furthermore, in step S120 , step S140 , and step S150 , the processing of the substrate 10 using the patterned photosensitive film 26 and photosensitive film 27 is not limited to the above-mentioned ion implantation. That is, the processing of the substrate 10 may be other processing such as etching, oxidation, and nitridation for the substrate 10 or a specific film formed on the substrate 10 . In addition, after forming grooves or holes in the substrate 10 or a specific film formed on the substrate 10 by performing specific etching, conductors such as metals may be partially buried in the grooves or holes.

Also, in step S120 and step S140 , like step S150 , a step of forming a specific film on the substrate 10 may be included before forming the photosensitive film 26 and the photosensitive film 27 on the substrate 10 . In addition, after the exposure using the fixed mask 30 or the exposure using the variable shaping mask, and before the development, a post exposure bake (Post Exposure Bake, PEB) process of heating the photosensitive film 26 and the photosensitive film 27 may also be included.

Furthermore, the unique circuit 3 representing unique information unique to each semiconductor integrated circuit 1 and at least partly different for each circuit pattern, and the unique information storage circuit 21 including the unique circuit 3 are not limited to the above-mentioned NAND-type mask ROM. Therefore, the pattern specific to each semiconductor integrated circuit 1 in the specific circuit 3 is not limited to the above-mentioned concentration distribution of impurity ions.

The specific pattern of the semiconductor integrated circuit 1 in the specific circuit 3 may be the presence or absence of a specific transistor in the circuit constituting the electronic device, a difference in gate length, or a difference in gate width. Alternatively, it may be the presence or absence of connection parts such as specific via holes in the circuit constituting the electronic component or a difference in size. In addition, depending on the difference in operating characteristics of electronic components caused by the presence or absence of these or the difference in size, it may also be a circuit that memorizes a signal "1" or a signal "0".

Formation of these transistors, via holes, and the like can also be performed by two or more lithography steps including exposure using a variable shaping exposure device. Furthermore, in the above-mentioned step S140 and step S150, the inherent pattern representing the inherent information inherent in the semiconductor integrated circuit 1 in the inherent circuit 3 can be performed by one lithography step including exposure using a variable shaping exposure device. That is, the formation of the channel part Ch0 and the channel part Ch1. Therefore, it is possible to reduce the necessary number of exposures using the variable shaping exposure device, which takes a processing time compared with exposure using the fixed mask 30 , and improve the productivity of the semiconductor integrated circuit 1 .

In addition, the exposure using the variable shaping exposure device is not limited to the above-mentioned exposure using light including ultraviolet rays, and may be exposure using charged particle beams such as electron beams. In this case, a so-called blanking hole array can be used, for example, as a variable shaping mask.

Next, an example of a method of exposing a bright and dark pattern on the substrate 10 in order to form the intrinsic circuit 3 using the variable shaping mask will be described with reference to FIG. 11 . As shown in FIG. 1 , a plurality of semiconductor integrated circuits 1 are formed in each region 11 two-dimensionally arranged on a substrate 10 along the X direction and the Y direction. Therefore, by arranging the specific circuits 3 at common positions inside the respective semiconductor integrated circuits 1, the plurality of specific circuits 3 are two-dimensionally arranged along the X direction and the Y direction.

Therefore, as shown in FIG. 11 , a plurality of intrinsic circuits 3 can be exposed by, for example, one scanning exposure along the Y direction using an exposure apparatus including a variable shaping mask. That is, the plurality of intrinsic circuits 3 included in the semiconductor integrated circuit 1 arranged in the plurality of regions 11 of the row R1 can be exposed by scanning exposure along the scanning path SP1 shown by the dotted line. Similarly, the plurality of intrinsic circuits 3 included in the semiconductor integrated circuits 1 arranged in the plurality of regions 11 of the rows R2 to R7 can be exposed by each scanning exposure along the scanning path SP2 to the scanning path SP7.

The X-direction width AW of the intrinsic circuit 3 may be, for example, about 100 μm or less. Therefore, the X-direction exposure field of view of an exposure device including a variable shaping mask may also be about 100 μm or less. Hereinafter, an exposure apparatus including a variable shaping mask will be described with reference to FIG. 13 . By performing such scanning exposure, the time required for acceleration or deceleration of the substrate 10 required before and after the exposure of each specific circuit 3 can be reduced, so that the processing time required for exposure can be shortened and the throughput can be improved.

Furthermore, as shown in FIG. 11 , in each scanning path SP1 to scanning path SP7 adjacent along the X direction, the scanning direction (moving direction of the substrate 10 during exposure) can be reversed to each other, thereby reducing the number of scans. The moving distance of the substrate 10 between the path SP1 to the scanning path SP7. Thereby, the yield can be further increased.

Furthermore, scanning exposure using an exposure device including a variable shaping mask is not limited to along the Y direction, and can also be along the X direction. The Y direction (or X direction) may be referred to as a first direction, and the X direction (or Y direction) may be referred to as a second direction intersecting the first direction, that is, the Y direction (or X direction).

Next, an example in which a cryptographic key (Cryptographic key) is stored in the unique circuit 3 as an example of unique information will be described with reference to FIG. 12 . The encryption key is an encryption key used when encrypting a signal transmitted or received by the semiconductor integrated circuit 1 by the encryption circuit 22 or decoding it by the decoding circuit 23 . As the encryption key, for example, a 4-byte hexadecimal value such as 0x34F23E1A is used. Therefore, in the unique circuit 3 of the unique information storage circuit 21 of the semiconductor integrated circuit 1 formed in each region 11 on the substrate 10, a password of a value corresponding to the purpose of use of the semiconductor integrated circuit 1 formed in each region 11 is memorized. key.

Based on the interrelationship data (INTERRELATIONSHIP DATA) shown in FIG. 12 , it is determined which encryption key is memorized in the semiconductor integrated circuit 1 formed in each region 11 . The correlation data is data showing the relationship between one and another or a plurality of manufactured semiconductor integrated circuits 1 . In other words, the correlation data represent the substrate number W of the substrate 10 on which each semiconductor integrated circuit 1 is formed, the arrangement position (row) C in the Y direction on the substrate 10, and the arrangement position (column) R specified by the X direction. Relational information of the respective semiconductor integrated circuits 1 of the other semiconductor integrated circuits 1. A management number (IC NO.) of IC (W, C, R) is assigned to the semiconductor integrated circuit 1 disposed at the position of row C and column R of the substrate number W, that is, the Wth substrate.

As an example, in the correlation data, the semiconductor integrated circuit 1 of the management number IC (1, 1, 2) is allocated to the semiconductor integrated circuit 1 that should be the main chip among the plurality of semiconductor integrated circuits 1 in the first group The symbol of Master-1 (INDEX). Accordingly, a password key for functioning as a master chip among the plurality of semiconductor integrated circuits 1 of the first group is memorized in the unique information memory circuit 21 of the semiconductor integrated circuit 1 with the management number IC (1, 1, 2) 0x34F23E1A.

Moreover, Slave-1 of the semiconductor integrated circuit 1 that should be the first slave chip among the plurality of semiconductor integrated circuits 1 in the first group is allocated to the semiconductor integrated circuit 1 with the management number IC (1, 1, 3). -1 sign. Accordingly, it is stored in the unique information memory circuit 21 of the semiconductor integrated circuit 1 of the management number IC (1, 1, 3) so that it functions as the first slave chip among the plurality of semiconductor integrated circuits 1 in the first group. The password key is 0xAB56BD23.

Similarly, the symbol corresponding to the allocated Slave-1-2 is memorized in the semiconductor integrated circuit 1 of the management number IC (1, 1, 4) so that it is used in the first plurality of semiconductor integrated circuits 1 as Code key 0x7EA843BC that functions from chip No. 2.

As another example, the symbol corresponding to the assigned Master-2 is stored in the semiconductor integrated circuit 1 with the management number IC (1, 2, 5) to be the master among the plurality of semiconductor integrated circuits 1 in the second group. Chip function code key 0x7EA843BC. And, corresponding to the assigned Slave-2 symbol, it is memorized in the semiconductor integrated circuit 1 of the management number IC (1, 2, 6) and the management number IC (1, 2, 7) so that it is included in the second group. The same password key 0x59C6AF32 as the slave chip in 1 semiconductor integrated circuit.

As yet another example, corresponding to the assigned symbols of Group-1, management numbers IC (1, 4, 4), management numbers IC (1, 4, 5), and management numbers IC (1, 4, 6) In the semiconductor integrated circuit 1 of , the password key 0xBA5CFE4D common to a plurality of semiconductor integrated circuits 1 belonging to Group-1 is stored.

Similarly, the management number IC (2, 2, 7), the management number IC (2, 3, 1), and the management number IC formed on the second substrate 10 correspond to the allocated symbols of Group-2. The semiconductor integrated circuit 1 of (2, 3, 2) stores the password key 0xC4A25D3B common to the plurality of semiconductor integrated circuits 1 belonging to Group-2.

Furthermore, the password key is not limited to the above-mentioned 4-byte hexadecimal code, but can be digital data with any number of bits. Also, instead of the encryption key itself, it may be digital data obtained by performing a specific operation on the encryption key, for example. Hereinafter, the encryption key itself and the digital data obtained by performing specific operations on the encryption key are also referred to as "information related to the encryption key".

A plurality of semiconductor integrated circuits 1 manufactured by the manufacturing method of the first embodiment can associate only one or more of the symbols corresponding to the information related to the encryption key stored in each unique circuit 3 . other semiconductor integrated circuits 1 for communication with encryption and decoding. Conversely, by forming a plurality of semiconductor integrated circuits 1 using a substantially common circuit pattern, and respectively changing a part of the circuit patterns in the inherent circuit 3, it is possible to manufacture only one or more specific semiconductor integrated circuits. The circuit 1 communicates with the semiconductor integrated circuit 1 . Furthermore, the intrinsic information stored in the intrinsic circuit 3 is not limited to the above-mentioned password key, and may be, for example, identification information representing each semiconductor integrated circuit 1 .

The unique information such as the password key stored in the unique circuit 3 can be specified by the semiconductor manufacturer who implements the manufacturing method of the semiconductor integrated circuit 1 according to the first embodiment. Furthermore, it is also possible for the semiconductor manufacturer to determine the correspondence between the inherent information and the symbols included in the correlation data. Alternatively, the consignor who consigns the manufacture of the semiconductor integrated circuit 1 to the semiconductor manufacturer may specify the unique information or the correspondence between each unique information and symbols.

When the semiconductor manufacturer determines the correspondence between the inherent information and the symbols included in the correlation data, or the inherent information, only the semiconductor manufacturer can grasp the inherent information actually stored in the semiconductor integrated circuit 1 . Therefore, in this case, since the information related to the unique information is not known to anyone other than the semiconductor manufacturer, the secrecy of the unique information such as an encryption key can be maintained at a high level.

Also, as described below, the correspondence relationship between inherent information and symbols included in the correlation data may be determined (generated) by a variable shaping exposure device used in exposure using a variable shaping mask as described below, or inherent information. In this case, the inherent information actually stored in the semiconductor integrated circuit 1 is grasped only by the variable shaping exposure device and cannot be known by others. Therefore, in this case, the secrecy related to the inherent information can be maintained at a higher level.

The correlation data may also be generated by a semiconductor manufacturer who implements the method for manufacturing the semiconductor integrated circuit 1 according to the first embodiment, or by a variable shaping exposure device used in exposure using a variable shaping mask as described below. . Alternatively, the correlation data may be specified by a consignor who consigns the manufacture of the semiconductor integrated circuit 1 to the semiconductor manufacturer.

When the correlation data is generated by a semiconductor manufacturer or by a variable shaping exposure device, it is possible to transfer a plurality of semiconductor integrated circuits 1 manufactured together with the correlation data to the use of the semiconductor integrated circuit 1 The person (consignor of the manufacture of the semiconductor integrated circuit 1). A user using the semiconductor integrated circuit 1 may select a semiconductor integrated circuit 1 suitable for the purpose of use from among a plurality of semiconductor integrated circuits 1 based on the correlation data transferred from the manufacturer.

(Effects of the Manufacturing Method of the Semiconductor Integrated Circuit of the First Embodiment) (1) The method of manufacturing the semiconductor integrated circuit 1 according to the first embodiment described above is a method of manufacturing the semiconductor integrated circuit 1 in the plurality of regions 11 on the substrate 10 , including the use of a mask fixed to the mask substrate 31 . The mask pattern 32 forms an electronic circuit (common circuit 2) as a part of the semiconductor integrated circuit 1 in the plurality of regions 11; Some of the unique circuits 3 representing unique information inherent to each semiconductor integrated circuit 1 are formed, and the unique circuits 3 formed in the plurality of regions 11 are different from each other. With this configuration, a plurality of semiconductor integrated circuits 1 each including a unique circuit 3 can be manufactured at low cost.

(2) The electronic circuit as the common circuit 2 includes at least a part of the circuit for encrypting or decoding information (encryption circuit 22, decoding circuit 23), and the inherent information may be related to the encryption key used when encrypting or decoding information. Information. With this structure, by forming a plurality of semiconductor integrated circuits 1 using a substantially common circuit pattern and changing a part of the circuit pattern in the unique circuit 3, it is possible to manufacture one or more semiconductor circuits that can only be combined with other specific ones. The integrated circuit 1 communicates with the semiconductor integrated circuit 1 .

(3) An electronic circuit (common circuit 2 ) can be formed respectively in a plurality of said regions arranged along the first direction on the substrate 10 and the second direction intersecting with the first direction, and the formation of the intrinsic circuit 3 includes The substrate 10 on which the photosensitive film 26 is formed is relatively scanned along the first direction (Y direction) relative to the variable shaping exposure device, and a plurality of regions 11 arranged along the first direction (Y direction) are scanned during scanning. Area 11 is exposed. With this structure, the specific circuit 3 can be formed in a shorter time, and the productivity of the semiconductor integrated circuit 1 can be further improved.

(4) The unique pattern (channel part Ch0, channel part Ch1) in the unique circuit 3 representing the unique information inherent in the semiconductor integrated circuit 1 can be formed by one microscopic process including exposure using a variable shaping exposure device. shadow step. Thereby, the number of times of exposure using the variable shaping exposure device can be reduced, and the productivity of the semiconductor integrated circuit 1 can be further improved. (5) The electronic circuit (common circuit 2) may include a NAND-type mask ROM (inherent information memory circuit 21), and the inherent circuit 3 may include channel parts Ch0, Concentration distribution of impurity ions implanted in the channel portion Ch1. With this structure, the number of exposures using the variable shaping exposure device can be reduced, and the productivity of the semiconductor integrated circuit 1 can be further improved.

(Exposure apparatus of the second embodiment) FIG. 13 is a diagram schematically showing the configuration of an exposure apparatus 50 according to the second embodiment. The exposure device 50 of the second embodiment is a variable-shaping exposure device that includes a variable-shaping mask 54 and exposes a shape-variable light and dark pattern 35 on a substrate 10 . The variable shaping mask 54 can be any one of the above-mentioned spatial light modulators, and in this embodiment, a reflective spatial light modulator in which a plurality of tiny reflection surfaces are arranged on the variable mask surface DP is adopted. . The exposure device 50 further includes a light transmission optical system 52 , a branching element 53 , an imaging optical system 55 , a substrate holding unit 56 , a platen 57 , a control unit 60 , and the like.

The substrate 10 is placed on the substrate holding portion 56 arranged on the platen 57 . The substrate 10 can move along the X direction and the Y direction on the platen 57 by the substrate holding part 56 . In addition, the substrate 10 can also be moved by a small distance along the Z direction by the substrate holding portion 56 , and can be rotated (tilted) by a small angle by using the X direction and the Y direction as rotation axes.

The positions of the substrate 10 in the X direction and the Y direction are measured by the position measurement unit 59 through the position of the scale plate 58 provided on the substrate holding unit 56 , and are sent to the control unit 60 as a measurement signal S3 . The control part 60 performs control by sending the position control signal S4 to the board|substrate holding part 56 based on the measurement signal S3, and arrange|positions the board|substrate 10 in a specific X position and a Y position. The control unit 60 sends an exposure control signal S2 to the light source 51 to control the timing and amount of light emission of the light source 51 .

The exposure device 50 may be a scanning type exposure device that scans the substrate 10 and the substrate holder 56 relative to the projection optical system 55 along the XY in-plane direction to perform exposure. In this case, the exposure apparatus 50 can shorten the processing time required for the exposure of the board|substrate 10 by performing scanning exposure along scanning path SP1 - scanning path SP7 shown in FIG.

Alternatively, it may be a step-and-repeat type exposure device, that is, exposure is performed in a state where the substrate 10 and the substrate holding part 56 are fixed relative to the projection optical system 55, and after the exposure is completed, the substrate 10 and the substrate holding part 56 are positioned relative to the projection optical system 55. The projection optical system 55 moves sequentially. In both the scanning type exposure apparatus and the step-and-repeat type exposure apparatus, in order to avoid unnecessary exposure of a part of the common circuit 2 on the substrate 10, the control unit 60 stops the light source 51 at a time other than the timing for exposing the specific circuit 3. glow.

As an example, the wavelength of the illumination light emitted from the light source 51 is 450 [nm] or less. As a further example, the wavelength of the illumination light may be 193 [nm] or less. The light source 51 can be incorporated inside the exposure device 50 , and can also be arranged outside the exposure device 50 . Illumination light can be guided from the light source 51 to the exposure device 50 using a light guide member such as an optical fiber.

The illumination light emitted from the light source 51 is shaped by the light transmission optical system 52, enters the branching element 53 such as a beam splitter, is reflected by the branching surface 53s of the branching element 53, and irradiates the variable masking surface of the variable shaping mask 54. DP. In addition, a part of the illumination light is reflected by a plurality of microreflective surfaces (not shown) arranged on the variable mask surface DP, enters the branch element 53 again, passes through the branch surface 53s of the branch element 53, and enters the imaging optical system. 55.

The variable shaping mask 54 directs a part of the reflected light in a direction that cannot pass through the imaging optical system 55 by changing the angle of each reflection surface of a plurality of micro reflection members (not shown) arranged on the variable mask surface DP. reflection. Or, by making the Z-direction positions of the reflecting surfaces of a plurality of adjacent tiny reflecting members different from each other, the effect of canceling the phase of the light is produced, so that the reflection from a specific part of the variable mask surface DP toward the imaging optical system 55 light extinction. Thereby, the light and dark pattern 35 formed by the variable shaping mask 54 is projected onto the surface of the substrate 10 .

The control unit 60 sends the control signal S1 to the variable shaping mask 54, and displaces a specific micro-reflecting member in the variable mask surface DP by a specific amount of displacement, thereby determining the light and dark pattern 35 formed on the surface of the substrate 10. Shape (light and dark distribution). The control unit 60 may include a pattern determination unit 61 and a correlation data generation unit 62 . Moreover, the control part 60 communicates with the external server 70 provided outside the exposure apparatus 50 via the network line NW.

The pattern specifying unit 61 specifies a light and dark pattern 35 for exposing parts of the inherent circuits 3 in the plurality of regions 11 corresponding to the plurality of semiconductor integrated circuits 1 formed on the substrate 10 based on the correlation data shown in FIG. 12 described above. shape (light and dark distribution). Specifically, as shown in FIG. 12 , for example, the index (INDEX) for each semiconductor integrated circuit 1 on the substrate 10 is assigned to the correlation data received from the external server 70 . The pattern specifying unit 61 specifies the unique information to be stored in the unique circuit 3 (for example, the numerical value of the encryption key including the above-mentioned hexadecimal code) based on the symbols shown in the correlation data.

Furthermore, the pattern determination unit 61 determines the shape (light and dark distribution) of the light and dark pattern 35 for exposing and transferring the circuit pattern corresponding to the unique information to the substrate 10 based on the identified unique information. Then, the control unit 60 controls the variable shaping mask 54 through the control signal S1 in such a way that the light and dark pattern 35 determined by the pattern determination unit 61 is projected onto the substrate 10 .

An example of the shape of the light and shade pattern 35 is the shape (light and shade distribution) shown in FIG. 8A described above. Furthermore, when the exposure device 50 is the above-mentioned scanning type exposure device, the dynamic control is variable in such a way that the bright and dark pattern 35 projected on the substrate 10 moves along the X direction or the Y direction in synchronization with the scanning on the substrate 10 . Shaping mask54.

The pattern determination unit 61 may include a storage unit 63 that stores shape data of the light and dark patterns 35 respectively corresponding to a plurality of intrinsic information. In this case, the pattern identifying unit 61 may read and use one piece of shape data corresponding to the identified unique information from the memory unit 63 . Therefore, compared with the case where the shape data of the light and dark pattern 35 is generated every time the unique information is determined, the shape data of the light and dark pattern 35 can be determined in a short time.

Also, the memory unit 63 of the pattern specifying unit 61 may store shape data of the light and dark patterns 35 respectively corresponding to the divided unique information obtained by dividing the unique information by a specific number of bits (1 to 16, for example). In this case, the pattern determining unit 61 may read a plurality of shape data corresponding to the determined inherent information from the memory unit 63 , and combine the shape data to obtain the shape data of the light and dark pattern 35 .

The shape data memorized by the memory unit 63 can be, for example, bitmap data or tagged image file (Tagged Image File, TIF) data, etc. representing images, and can also be Graphic Data System (Graphic Data System, GDS) II, etc. Data that typically represents masked data. In addition, the shape data memorized by the memory unit 63 may be sent from the external server 70 or may be generated by the control unit 60 .

In addition, the exposure device 50 as the variable shaping exposure device is not limited to the above-mentioned exposure device using light including ultraviolet rays, and may be an exposure device using charged particle beams such as electron beams. In this case, as the variable shaping mask 54, for example, a transmissive mask including a so-called blanking hole array can be used.

As described in the method of manufacturing a semiconductor integrated circuit according to the first embodiment, the exposure apparatus 50 may include a correlation data generation unit 62 that generates the correlation data shown in FIG. 12 . In this case, the exposure device 50 determines the intrinsic information to be memorized in the intrinsic circuit 3 (for example, the numerical value of the encryption key including the above-mentioned hexadecimal code) based on the correlation data generated by itself.

(Effects of Exposure Device of Second Embodiment) (6) The exposure device 50 of the second embodiment includes: a substrate holding unit 56 for holding the substrate 10; a variable shaping mask 54 for setting the shape of the bright and dark pattern 35 irradiated on the substrate 10; The correlation data of the mutual relationship of the plurality of semiconductor integrated circuits 1 determines the shape of the bright and dark pattern 35 to be exposed to the plurality of regions 11 corresponding to the plurality of semiconductor integrated circuits 1 formed on the substrate 10 . With this configuration, a plurality of semiconductor integrated circuits 1 each including a unique circuit 3 can be manufactured at low cost.

(7) The pattern determination unit 61 may determine the unique information to be formed in each of the plurality of specific regions 11 based on the correlation data, and determine the shape of the light and dark pattern 35 based on the determined unique information. With this structure, it is possible to flexibly form the unique circuit 3 in which different unique information is memorized for each of the plurality of semiconductor integrated circuits 1 .

(8) The pattern determination unit 61 includes a memory unit 63 that memorizes the shape data of the light and dark patterns 35 respectively corresponding to a plurality of inherent information, and reads the shape corresponding to the identified inherent information from the memory unit 63 . material. Thereby, the shape data of the light and dark pattern 35 can be determined in a shorter time.

(Exposure device of a modified example) In the exposure device 50 of the second embodiment described above, the specific circuits 3 specified in the plurality of regions 11 are respectively exposed by the pattern determination unit 61 based on the correlation data indicating the mutual relationship of the plurality of semiconductor integrated circuits 1. The shape of the chiaroscuro pattern 35 .

In the exposure device of the modified example, the pattern determination unit 61 determines the specific information for the inherent circuit 3 based on the inherent information including the multi-bit digital information that should be memorized in the inherent circuit 3 (for example, the value of the above-mentioned encryption key including the hexadecimal code). 3 Shapes of light and dark patterns 35 exposed separately. However, since the configuration of the exposure apparatus of the modified example is the same as that of the exposure apparatus 50 of the second embodiment described above, a detailed description of the exposure apparatus of the modified example will be omitted. The intrinsic information to be stored in the intrinsic circuit 3 can be received from the external server 70 via the network line NW.

Furthermore, in the exposure apparatus of the modified example, the pattern determination part 61 may also include the memory part 63 which memorize|stores the shape data of the light and dark pattern 35 respectively corresponding to several inherent information. Then, the pattern specifying unit 61 may read and use one piece of shape data corresponding to specific unique information from the memory unit 63 .

(Effect of the exposure device of the modified example) (9) The exposure device 50 of the modified example includes: a substrate holding part 56, which holds the substrate 10; a variable shaping mask 54, which sets the shape of the light and dark pattern 35 irradiated on the substrate 10; Inherent information including multi-bit digital information in a plurality of semiconductor integrated circuits 1 is determined in light and dark patterns 35 respectively exposed to a plurality of specific regions 11 corresponding to a plurality of semiconductor integrated circuits 1 formed on a substrate 10 shape. With this configuration, a plurality of semiconductor integrated circuits 1 each including a unique circuit 3 can be manufactured at low cost.

(10) The pattern determination unit 61 may include a memory unit 63 that stores shape data of the light and dark patterns 35 respectively corresponding to a plurality of unique pieces of information. Thereby, the shape data of the light and dark pattern 35 can be determined in a shorter time.

(Method for Manufacturing Semiconductor Element of Third Embodiment) A method of manufacturing a semiconductor element according to a third embodiment will be described with reference to FIGS. 14A , 14B, and 15 . In the method of manufacturing a semiconductor element of the third embodiment, the semiconductor integrated circuit 1 manufactured by the method of manufacturing a semiconductor integrated circuit of the first embodiment is individually packaged to form a plurality of semiconductor elements DD1 to DD4. Furthermore, based on the above-mentioned correlation data shown in FIG. 12 , a second correlation data is generated, and the second correlation data represents the inherent relationship between the packaged plurality of semiconductor elements DD1 to DD4 and the semiconductor integrated circuits 1 included in each of them. The corresponding relationship of the inherent information represented by the circuit 3.

FIG. 14A is a diagram illustrating a step of cutting a substrate 10 on which semiconductor integrated circuits 1 manufactured by the method of manufacturing a semiconductor integrated circuit according to the first embodiment is cut for each semiconductor integrated circuit 1 . FIG. 14A shows a state where the five semiconductor integrated circuits 1 arranged in the row C1 are cut (singulated) from the substrate 10 . Hereinafter, the singulated semiconductor integrated circuits 1 are also referred to as semiconductor wafer D01 to semiconductor wafer D05 , respectively.

Then, as shown in FIG. 14B , the singulated semiconductor wafers D01 - D04 are packaged by the packaging members P01 - P04 , respectively, thereby completing the semiconductor elements DD1 - DD4 . Any method can be used for the packaging method of the semiconductor wafer D01 - the semiconductor wafer D04.

As described above in the method of manufacturing a semiconductor integrated circuit in the first embodiment, the semiconductor integrated circuit 1 on the substrate 10 is assigned the substrate number W of the substrate, the arrangement position (row) C on the substrate 10 in the Y direction, and the X The arrangement position (column) R of the direction constitutes the management number IC (W, C, R). And, the characteristics of each semiconductor integrated circuit 1 specified by the management number IC (W, C, R) are specified by the interrelationship data (INTERRELATIONSHIP DATA) shown in FIG. 12 .

However, if the semiconductor integrated circuit 1 is singulated, it becomes difficult to manage the singulated semiconductor integrated circuit 1 by the correlation data. Therefore, based on the correlation data, a second data table indicating the correspondence between the packaged plurality of semiconductor elements DD1 to DD4 and the inherent information 3 of the semiconductor integrated circuit 1 included in the plurality of semiconductor elements DD1 to DD4 is generated. interrelationship data.

FIG. 15 is a diagram showing an example of the second interrelationship data (2ND INTERRELATIONSHIP DATA). The second correlation data shows the device numbers (DEVICE NO.) of the plurality of semiconductor devices DD1 to DD4 and the unique circuit 3 of the semiconductor integrated circuit 1 included in the semiconductor device DD1 to DD4 with the device number. Correspondence between symbols (INDEX) corresponding to information.

The management number (IC No.) shown on the left end of FIG. 15 is a management number assigned to each semiconductor integrated circuit 1 on the substrate 10 in the correlation data shown in FIG. 12 . As shown in FIG. 15, in the second correlation data, the management number (IC NO.) of the semiconductor integrated circuit 1 in the correlation data shown in FIG. The device number D0001, the device number D0002, etc. of the device DD1 - the semiconductor device DD4 are.

The symbols (INDEX) in the second correlation data may be the same as those in the correlation data shown in FIG. 12 . Alternatively, the symbols in the second correlation data may have the same meaning as the symbols in the correlation data shown in FIG. 12 but different symbols. For example, when the symbol in the interrelationship data is "Master1", the symbol in the second interrelationship data can be "M1".

When the semiconductor integrated circuit 1 is packaged into the semiconductor element DD1 to the semiconductor element DD4, the surface of the packaging member P01 to the packaging member P04 or the surface of the semiconductor integrated circuit 1 that is not covered by the packaging member P01 to the packaging member P04 can be marked. Component number D0001, component number D0002, etc.

When the manufacturer of the semiconductor device DD1 - the semiconductor device DD4 transfers the semiconductor device DD1 - the semiconductor device DD4 , the second correlation data is transferred to the purchaser together with the semiconductor device DD1 - the semiconductor device DD4 . The user who uses the semiconductor devices DD1 - DD4 may select and use the semiconductor devices DD1 - DD4 that meet the purpose of use from the plurality of semiconductor devices DD1 - DD4 based on the second correlation data transferred from the manufacturer. Therefore, management of the plurality of semiconductor elements DD1 to DD4 can be easily performed.

(Effects of the method for manufacturing a semiconductor element according to the third embodiment) (11) The manufacturing method of the semiconductor device DD1 to the semiconductor device DD4 according to the third embodiment described above includes: a plurality of semiconductor integrated circuits 1 manufactured by the manufacturing method of the semiconductor integrated circuit according to the first embodiment described above. Separately package and manufacture a plurality of semiconductor elements DD1-DD4; and generate a specific circuit representing the packaged plurality of semiconductor elements DD1-DD4 and the semiconductor integrated circuit 1 included in the plurality of semiconductor elements DD1-DD4 based on the correlation data 3 represents the second correlation data of the correspondence relation of the inherent information. With this configuration, a plurality of semiconductor elements DD1 to DD4 including the semiconductor integrated circuit 1 each including a unique circuit 3 can be inexpensively manufactured, and management of the plurality of semiconductor elements DD1 to DD4 can be easily performed.

Various embodiments and modified examples have been described above, but the present invention is not limited to these contents. In addition, each embodiment and modification can be applied individually or in combination. Other forms considered within the scope of the technical idea of the present invention are also included in the scope of the present invention.

1: Semiconductor integrated circuit 2: common circuit 3: Inherent circuit 10: Substrate 11: area 21: Inherent information memory circuit 22: encryption circuit 23: decoding circuit 24: Communication circuit 25: Some areas 25E: small area 25M: Equivalent to the portion of Partial Area 25 26, 27: photosensitive film 26E, 26F: photosensitive part 26N: Non-photosensitive part 26o, 27o: opening 28: Voltage application part 30: Fixed mask 31: Mask substrate 32: Mask pattern 33: Translucent part 34: shading part 35: Light and dark patterns 36: Ming Department 37: Anbu 38: The part corresponding to channel part Ch0 39: Corresponds to parts other than channel part Ch0 and channel part Ch1 50: Variable shaping exposure device (exposure device) 51: light source 52: Sending optical system 53: branch element 53s: branch surface 54: Variable shaping mask 55: Imaging optical system 56: Substrate holding part 57: pressure plate 58: Scale plate 59: Position measurement department 60: Control Department 61: Pattern Determination Department 62:Correlation data generation department 63: memory department 70:External server AW: width C1～C6: row Ch0, Ch1: channel part D01～D05: Semiconductor wafer DD1～DD4: semiconductor components DL: data line DP: variable masking surface GO: gate oxide film NW: Network Route P01～P04: Packaging components R1～R7: column S1: Control signal S2: exposure control signal S3: Measurement signal S4: Position control signal SD: source/drain region SL: selection line SP1～SP7: Scan path TR, TR1, TR2: MOS transistors

FIG. 1 is a diagram schematically showing a plurality of semiconductor integrated circuits manufactured by a method of manufacturing a semiconductor integrated circuit according to a first embodiment. FIG. 2 is a diagram showing one semiconductor integrated circuit manufactured by the method of manufacturing a semiconductor integrated circuit according to the first embodiment. 3 is a diagram showing a circuit diagram of an example of a unique information memory circuit in a semiconductor integrated circuit. FIG. 4A is an enlarged view of a portion of the intrinsic circuit. FIG. 4B is an enlarged view of a portion of the intrinsic circuit. FIG. 5 is a diagram illustrating the concentration distribution of impurity ions in a part of the intrinsic circuit. FIG. 6 is a diagram illustrating the flow of the method of manufacturing the semiconductor integrated circuit according to the first embodiment. 7A is a diagram illustrating a step of forming a circuit pattern of a portion common to a plurality of semiconductor integrated circuits using a fixed mask. FIG. 7B is a diagram illustrating a step of forming a circuit pattern of a portion common to a plurality of semiconductor integrated circuits using a fixed mask. FIG. 8A is a diagram for explaining a procedure of forming an intrinsic circuit using a variable reshaping mask. FIG. 8B is a diagram for explaining the steps of forming an intrinsic circuit using a variable reshaping mask. FIG. 9 is a diagram illustrating a part of the flow of a method of manufacturing a semiconductor integrated circuit. FIG. 10A is a diagram illustrating an exposure step using a fixed mask and a variable shaping mask. FIG. 10B is a diagram illustrating an exposure step using a fixed mask and a variable shaping mask. FIG. 10C is a diagram illustrating an exposure step using a fixed mask and a variable shaping mask. FIG. 11 is a diagram showing an example of a method of exposing a substrate to form a specific circuit using a variable shaping mask. FIG. 12 is a diagram showing an outline of a correlation data showing a relationship among a plurality of semiconductor integrated circuits. FIG. 13 is a diagram showing an outline of an exposure apparatus according to a second embodiment. 14A is a diagram showing an outline of a method of manufacturing a semiconductor element according to a third embodiment. 14B is a diagram showing an outline of a method of manufacturing a semiconductor element according to the third embodiment. FIG. 15 is a diagram showing an outline of a second correlation data showing the mutual relationship of a plurality of semiconductor elements.

1: Semiconductor integrated circuit

2: common circuit

3: Inherent circuit

10: Substrate

11: area

C1~C6: row

R1~R7: column

Claims (21)

A method of manufacturing a semiconductor integrated circuit, which is a method of manufacturing a semiconductor integrated circuit in a plurality of regions on a substrate, comprising: forming an electronic circuit as a part of the semiconductor integrated circuit in each of the plurality of regions using a mask pattern fixed to the mask substrate; and using a variable-shaping exposure device including a variable-shaping mask, forming an inherent circuit representing inherent information inherent in each of the semiconductor integrated circuits in a part of each of the plurality of regions, The specific circuits formed in each of the plurality of regions are different from each other. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the electronic circuit includes at least a part of a circuit for encrypting or decoding information, The inherent information is information related to a cryptographic key used when encrypting or decoding the information. The method of manufacturing a semiconductor integrated circuit according to claim 1 or claim 2, wherein the plurality of said regions respectively form the electronic circuits, The forming of the inherent circuit includes relative scanning the substrate on which the photosensitive film is formed along the first direction relative to the variable shaping exposure device, and performing the scanning along the plurality of regions in the scanning. exposing a plurality of areas arranged in the first direction. The method for manufacturing a semiconductor integrated circuit according to any one of claim 1 to claim 3, wherein the inherent pattern in the inherent circuit and representing the inherent information inherent in the semiconductor integrated circuit is formed by Performed by 1 lithography step including exposure using the variable shaping exposure device. The method for manufacturing a semiconductor integrated circuit according to any one of claim 1 to claim 4, wherein the electronic circuit includes an NAND mask read-only memory, The intrinsic circuit includes a concentration distribution of impurity ions implanted into respective channel portions of a plurality of metal oxide semiconductor transistors constituting the NAND mask ROM. The method for manufacturing a semiconductor integrated circuit according to any one of claim 1 to claim 5, wherein the generation represents at least one of the manufactured plurality of semiconductor integrated circuits and a plurality of the semiconductor integrated circuits The interrelationship data of at least one of the interrelationships, Based on the correlation data, the shape of the unique pattern representing the unique information formed in the unique circuits of the plurality of semiconductor integrated circuits is determined. The method of manufacturing a semiconductor integrated circuit according to claim 6, wherein the inherent information is generated by the variable shaping exposure device. The method of manufacturing a semiconductor integrated circuit according to claim 7, wherein the correlation data is generated by the variable shaping exposure device. A method of manufacturing a semiconductor device, comprising: Separately package a plurality of semiconductor integrated circuits manufactured by the method for manufacturing semiconductor integrated circuits according to any one of claim 6 to claim 8 to form a plurality of semiconductor elements; and Based on the correlation data, second correlation data is generated, and the second correlation data represents the relationship between the plurality of packaged semiconductor elements and the semiconductor integrated circuits included in the plurality of semiconductor elements. The corresponding relationship of the inherent information represented by the inherent circuit. An exposure device, comprising: The substrate holding part holds the substrate; a variable shaping mask for setting the shape of the light and dark pattern irradiated onto the substrate; and The pattern specifying unit determines, on the basis of correlation data representing a mutual relationship between a plurality of semiconductor integrated circuits, the plurality of regions respectively exposed to the plurality of semiconductor integrated circuits formed on the substrate. Shades of light and dark patterns. The exposure device according to claim 10, wherein the pattern determination unit determines inherent information to be formed in a plurality of specific regions based on the correlation data, and determines the light and dark pattern based on the determined inherent information. shape. The exposure device according to claim 11, wherein the pattern determination unit determines a correspondence between the inherent information and the correlation data. The exposure apparatus according to claim 11 or claim 12, wherein the pattern determination unit does not output the inherent information to the outside. The exposure apparatus according to any one of claim 11 to claim 13, wherein the pattern determination unit including a memory unit that memorizes shape data of the light and dark patterns respectively corresponding to a plurality of the inherent information, The shape data corresponding to the determined inherent information is read from the memory unit. The exposure device according to any one of claim 10 to claim 14, further comprising: The correlation data generating unit generates the correlation data. An exposure device, comprising: The substrate holding part holds the substrate; a variable shaping mask for setting the shape of the light and dark pattern irradiated onto the substrate; and The pattern specifying unit determines a plurality of specific patterns corresponding to the plurality of semiconductor integrated circuits formed on the substrate based on inherent information including multi-bit digital information that should be formed respectively in the plurality of semiconductor integrated circuits. Areas are exposed separately to the shape of the light and dark pattern. The exposure apparatus according to claim 16, wherein the pattern determination unit A memory unit is included, and the memory unit memorizes shape data of the light and dark patterns respectively corresponding to a plurality of the inherent information. The exposure device according to claim 16 or claim 17, wherein the pattern determination unit generates the inherent information. The exposure device according to claim 18, wherein the pattern specifying unit does not output the inherent information to the outside. The exposure apparatus according to any one of claim 10 to claim 19, wherein the substrate holding part moves along a first direction and a second direction intersecting the first direction, the first direction moves along touching the surface of the substrate, The substrate holding part is moved along the first direction, and the bright and dark patterns are respectively irradiated to a part of the plurality of specific regions on the substrate discretely arranged along the first direction. The exposure apparatus according to claim 20, wherein a part of the plurality of specific regions is discrete along the second direction.

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