TW202240686A - Chip cutting channel process method - Google Patents

Chip cutting channel process method Download PDF

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TW202240686A
TW202240686A TW111112948A TW111112948A TW202240686A TW 202240686 A TW202240686 A TW 202240686A TW 111112948 A TW111112948 A TW 111112948A TW 111112948 A TW111112948 A TW 111112948A TW 202240686 A TW202240686 A TW 202240686A
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wafer
etching
dicing
cutting
zone
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TW111112948A
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Chinese (zh)
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方照詒
李承遠
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大陸商深圳市德明利光電有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention relates to a chip cutting channel process method. The chip cutting channel process method comprises the following steps of: carrying out chemical etching on a cutting channel region to form an etching belt, wherein the side wall of the etching belt is a non-vertical side wall; and using a mechanical grinding wheel for aligning the etching belt for cutting, wherein cutting edge traces fall in the etching belt, the outline, located on the surface of the wafer, of the etching belt is a straight line without mechanical damage, and a highlight reflection region with a flat edge outline is formed on the upper surface of the wafer.

Description

晶片切割道工藝方法wafer dicing line process

本發明涉及晶片製造工藝技術領域，尤其涉及一種晶片切割道工藝方法。The invention relates to the technical field of wafer manufacturing technology, in particular to a wafer cutting line processing method.

現有的晶片製造工藝中將晶圓切割成一個一個晶片時，所採用的方法一般是鐳射切割或者砂輪鋸片切斷。其中，鐳射切割一般並非一次切斷，通常需要後續的劈裂工藝配合，且鐳射切割高溫灼燒的過程會產生有害的含砷元素的氣體，會對人體造成傷害，甚至導致中毒死亡，故其工藝複雜、成本較高並具有安全隱患。而使用砂輪將晶圓直接切斷的方式，會造成晶片出現鋸齒狀邊緣輪廓的外觀不良，及外觀尺寸不一致的問題，並且在使用自動光學檢測的時候，誤判率非常高。In the existing wafer manufacturing process, when the wafer is cut into individual wafers, the method generally adopted is laser cutting or grinding wheel saw blade cutting. Among them, laser cutting is generally not a one-time cutting, and usually requires the cooperation of the subsequent splitting process, and the high-temperature burning process of laser cutting will produce harmful arsenic-containing gas, which will cause harm to the human body and even lead to poisoning death, so its The process is complicated, the cost is high and there are potential safety hazards. The method of directly cutting the wafer with a grinding wheel will cause poor appearance of the wafer with a jagged edge profile and inconsistent appearance and size, and when automatic optical inspection is used, the misjudgment rate is very high.

鑒於上述狀況，有必要提出一種提高顯示品質的晶片切割道工藝方法。In view of the above situation, it is necessary to propose a wafer dicing line process method for improving display quality.

為了解決上述技術問題，本發明採用的技術方案為：一種晶片切割道工藝方法，其特徵在於，包括以下步驟：對一切割道區域進行化學蝕刻，形成一蝕刻帶，該蝕刻帶的側壁為非垂直面側壁；及用機械砂輪對準該蝕刻帶進行切割，切割邊緣痕跡落在該蝕刻帶內，且該蝕刻帶位於晶圓表面的輪廓為無機械損傷的平直直線，使晶圓上表面形成具有平整邊緣輪廓的高光反射區域。In order to solve the above technical problems, the technical solution adopted by the present invention is: a wafer dicing line process method, which is characterized in that it includes the following steps: chemically etching a dicing line area to form an etching zone, the sidewall of the etching zone is non- vertical sidewall; and use a mechanical grinding wheel to align the etching band for cutting, the cutting edge traces fall in the etching band, and the contour of the etching band on the wafer surface is a straight line without mechanical damage, so that the upper surface of the wafer Creates specular areas with flat edge contours.

進一步的，該蝕刻帶的深度為10-20μm，寬度為20-40μm。Further, the etching zone has a depth of 10-20 μm and a width of 20-40 μm.

進一步的，在化學蝕刻之前，用光刻定義該切割道區域。Further, photolithography is used to define the scribe line region before chemical etching.

進一步的，在化學蝕刻後切割工藝前，用機械研磨減薄該切割道區域背向光刻膠的一側。Further, before the dicing process after the chemical etching, the side of the dicing line region facing away from the photoresist is thinned by mechanical grinding.

進一步的，減薄後的晶圓剩餘厚度為50-200μm。Further, the remaining thickness of the thinned wafer is 50-200 μm.

進一步的，該切割工藝為機械切割或鐳射切割。Further, the cutting process is mechanical cutting or laser cutting.

進一步的，在切割工藝後去除光刻膠。Further, the photoresist is removed after the cutting process.

進一步的，該蝕刻帶的側壁為弧形側壁，其寬度向下逐漸減小。Further, the sidewall of the etching zone is an arc-shaped sidewall, and its width gradually decreases downwards.

進一步的，化學蝕刻所使用的蝕刻液包含 H 3PO 4/H 2SO 4/HCl/H 2O 2/H 2O中的至少一種。 Further, the etching solution used for chemical etching includes at least one of H 3 PO 4 /H 2 SO 4 /HCl/H 2 O 2 /H 2 O.

本發明的有益效果在於：利用濕法蝕刻在晶圓上表面形成具有平整邊緣輪廓的高光反射區域，與側壁區域形成光學強度高對比，由於該蝕刻帶為非垂直側壁，該蝕刻帶與切割痕跡的交界處形成的焦平面與高光反射區域的焦平面不在一個焦平面上，在顯微鏡下晶片外觀視覺上平整，在自動光學檢測時不容易出現誤判，提高了自動光學檢測的準確率。The beneficial effect of the present invention is that: wet etching is used to form a high-light reflection region with a smooth edge profile on the upper surface of the wafer, which forms a high contrast in optical intensity with the sidewall region. Since the etching zone is a non-vertical sidewall, the etching zone and the cutting trace The focal plane formed at the junction of the wafer and the focal plane of the high-light reflection area are not on the same focal plane. Under the microscope, the appearance of the wafer is visually flat, and it is not easy to misjudgment during automatic optical inspection, which improves the accuracy of automatic optical inspection.

為了使本發明的目的、技術方案及優點更加清楚明白，以下結合附圖及實施例，對本發明一種晶片切割道工藝方法進行進一步詳細說明。應當理解，此處所描述的具體實施例僅用以解釋本發明，並不用於限定本發明。In order to make the object, technical solution and advantages of the present invention clearer, a wafer dicing line processing method of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

請參照圖3和圖4，一種晶片切割道工藝方法，包括以下步驟：對一切割道區域200進行化學蝕刻，形成一蝕刻帶210，該蝕刻帶210的側壁為非垂直面側壁；及用機械砂輪對準該蝕刻帶210進行切割，切割邊緣痕跡220落在該蝕刻帶210內，且該蝕刻帶210位於晶圓表面的輪廓為無機械損傷的平直直線，使晶圓上表面形成具有平整邊緣輪廓的高光反射區300域。Please refer to Fig. 3 and Fig. 4, a kind of wafer dicing line processing method, comprises the following steps: carry out chemical etching to a dicing line area 200, form an etching zone 210, the sidewall of this etching zone 210 is non-vertical sidewall; The grinding wheel is aligned with the etching band 210 for cutting, the cutting edge marks 220 fall in the etching band 210, and the contour of the etching band 210 on the surface of the wafer is a straight line without mechanical damage, so that the upper surface of the wafer is formed with a flat surface. The specular region 300 domain of the edge profile.

利用濕法蝕刻在晶圓上表面形成具有平整邊緣輪廓的高光反射區300域，與側壁區域形成光學強度高對比，由於該蝕刻帶210為非垂直側壁211，該蝕刻帶210與切割痕跡的交界處形成的焦平面與高光反射區300域的焦平面不在一個焦平面上，在顯微鏡下晶片100外觀視覺上平整，在自動光學檢測時不容易出現誤判，提高了自動光學檢測的準確率。A high-light reflective region 300 with a flat edge profile is formed on the upper surface of the wafer by wet etching, which forms a high optical intensity contrast with the sidewall region. Since the etched zone 210 is a non-vertical sidewall 211, the junction of the etched zone 210 and the cutting trace The focal plane formed at the center and the focal plane of the high-light reflection area 300 are not on the same focal plane, and the appearance of the wafer 100 under the microscope is visually smooth, and it is not easy to misjudgment during the automatic optical inspection, which improves the accuracy of the automatic optical inspection.

可以理解的，化學蝕刻即為濕法蝕刻。Understandably, chemical etching is wet etching.

優選的，該蝕刻帶210的深度為10-20μm，寬度為20-40μm。Preferably, the etching zone 210 has a depth of 10-20 μm and a width of 20-40 μm.

一般的，請參照圖3，在化學蝕刻之前，用光刻定義該切割道區域200。Generally, referring to FIG. 3 , the scribe line region 200 is defined by photolithography prior to chemical etching.

優選的，請參照圖3，在化學蝕刻後切割工藝前，用機械研磨減薄該切割道區域200背向光刻膠400的一側。Preferably, please refer to FIG. 3 , before the dicing process after the chemical etching, the side of the scribe line region 200 facing away from the photoresist 400 is thinned by mechanical grinding.

優選的，減薄後的晶圓剩餘厚度為50-200μm。Preferably, the remaining thickness of the thinned wafer is 50-200 μm.

簡單的，切割工藝為機械切割或鐳射切割。可以理解的，機械切割即採用砂輪切割。Simple, the cutting process is mechanical cutting or laser cutting. It can be understood that mechanical cutting means cutting with grinding wheels.

一般的，請參照圖3，在切割工藝後去除光刻膠400。Generally, referring to FIG. 3 , the photoresist 400 is removed after the dicing process.

特別的，請參照圖3和圖4，該蝕刻帶210的側壁為弧形側壁，其寬度向下逐漸減小。In particular, please refer to FIG. 3 and FIG. 4 , the sidewall of the etching zone 210 is an arc-shaped sidewall, and its width gradually decreases downwards.

優選的，化學蝕刻所使用的蝕刻液包含 H 3PO 4/H 2SO 4/HCl/H 2O 2/H 2O中的至少一種，即包括上述材料的任一比例混合液。 Preferably, the etching solution used for chemical etching contains at least one of H 3 PO 4 /H 2 SO 4 /HCl/H 2 O 2 /H 2 O, that is, a mixed solution including any ratio of the above materials.

具體的，請參照圖3和圖4，準備尚未切割的、晶面襯底為（100）或者（110）的VSCEL（垂直腔面雷射器）晶圓；通過光刻工藝定義該切割道區域200；採用濕法工藝蝕刻切割道形成側壁區域為非垂直側壁211的蝕刻帶210；通過機械研磨減薄工藝減薄晶圓，其減薄部位為背向光刻膠400的一側，剩餘的晶圓厚度為50-200μm；採用鐳射或機械方式的物理切割工藝進行切割，切割邊緣痕跡220落在該蝕刻帶210內，且該蝕刻帶210位於晶圓表面的輪廓為無機械損傷的平直直線，使晶圓上表面形成具有平整邊緣輪廓的高光反射區300；及去除光刻膠400。Specifically, please refer to Figure 3 and Figure 4 to prepare a VSCEL (Vertical Cavity Surface Laser) wafer that has not been cut and whose crystal plane substrate is (100) or (110); define the scribe area by photolithography 200; using a wet process to etch the dicing line to form an etching zone 210 with a non-vertical sidewall 211 in the sidewall region; thinning the wafer through a mechanical grinding thinning process, the thinned part is the side facing away from the photoresist 400, and the remaining The thickness of the wafer is 50-200 μm; laser or mechanical physical cutting process is used for cutting, the cutting edge marks 220 fall in the etching zone 210, and the contour of the etching zone 210 on the wafer surface is straight without mechanical damage a straight line to form a high-light reflection region 300 with a smooth edge profile on the upper surface of the wafer; and remove the photoresist 400 .

請參照圖1、圖2和圖5、圖6，使用砂輪將晶圓直接切斷的方式，該蝕刻帶210是垂直的，粗糙面邊緣與晶圓上表面處在同一焦平面上，顯微鏡觀察時光線返回觀察者會看到明顯顯示的粗糙邊緣，既影響產品外觀，又容易引起缺陷誤判。請參照圖3、圖4和圖7，而採用本申請的晶片100切割道工藝，產品的邊緣輪廓平滑，既可以使產品外觀美觀，又可以提高自動光學檢測的準確性。Please refer to Fig. 1, Fig. 2 and Fig. 5, Fig. 6, using the grinding wheel to cut the wafer directly, the etching zone 210 is vertical, and the edge of the rough surface is on the same focal plane as the upper surface of the wafer, observed under a microscope When the light returns to the observer, the obvious rough edges will be seen, which not only affects the appearance of the product, but also easily leads to misjudgment of defects. Please refer to FIG. 3 , FIG. 4 and FIG. 7 , but using the wafer 100 dicing process of the present application, the edge profile of the product is smooth, which can not only make the product appearance beautiful, but also improve the accuracy of automatic optical inspection.

需要說明，若本發明實施例中有涉及方向性指示（諸如上、下、左、右、前、後……），則該方向性指示僅用於解釋在某一特定姿態（如附圖所示）下各部件之間的相對位置關係、運動情況等，如果該特定姿態發生改變時，則該方向性指示也相應地隨之改變。It should be noted that if there are directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention, the directional indications are only used to explain how to move in a certain posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

綜上所述，本發明提供的一種晶片切割道工藝方法，利用濕法蝕刻在晶圓上表面形成具有平整邊緣輪廓的高光反射區域，與側壁區域形成光學強度高對比，由於該蝕刻帶為非垂直側壁，該蝕刻帶與切割痕跡的交界處形成的焦平面與高光反射區域的焦平面不在一個焦平面上，在顯微鏡下晶片外觀視覺上平整，在自動光學檢測時不容易出現誤判，提高了自動光學檢測的準確率。In summary, the present invention provides a wafer dicing line process method, which uses wet etching to form a high light reflection area with a flat edge profile on the upper surface of the wafer, and forms a high optical intensity contrast with the sidewall area. The vertical side wall, the focal plane formed at the junction of the etching zone and the cutting trace is not on the same focal plane as the focal plane of the high-light reflection area. The appearance of the wafer under the microscope is visually smooth, and it is not easy to misjudgment during automatic optical inspection, which improves the quality of the wafer. The accuracy rate of automatic optical inspection.

以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本專業的技術人員，在不脫離本發明技術方案範圍內，當可利用上述揭示的技術內容做出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but as long as they do not depart from the content of the technical solution of the present invention, the Technical Essence Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

100:晶片 200:切割道區域 210:蝕刻帶 211:非垂直側壁 220:切割邊緣痕跡 300:高光反射區域 400:光刻膠 100: chip 200: cutting lane area 210: Etched belt 211: Non-vertical side walls 220: Cut edge marks 300: high light reflection area 400: photoresist

圖1，為現有技術的流程示意圖。 圖2，為現有技術的自動光學檢測的光路示意圖。 圖3，為本發明實施例一種晶片切割道工藝方法的流程示意圖。 圖4，是本發明實施例自動光學檢測的光路示意圖。 圖5，是現有技術的產品的切割道邊緣痕跡示意圖。 圖6，是現有技術的產品圖的切割道邊緣痕跡示意圖。 圖7，是本發明的產品的切割道邊緣痕跡示意圖。 Fig. 1 is a schematic flow chart of the prior art. Fig. 2 is a schematic diagram of the optical path of the automatic optical detection in the prior art. FIG. 3 is a schematic flowchart of a wafer dicing line processing method according to an embodiment of the present invention. Fig. 4 is a schematic diagram of an optical path of an automatic optical detection embodiment of the present invention. Fig. 5 is a schematic diagram of the edge marks of the cutting line of the product in the prior art. Fig. 6 is a schematic diagram of the edge traces of the cutting line in the product map of the prior art. Fig. 7 is a schematic diagram of the edge marks of the cutting line of the product of the present invention.

100:晶片 100: chip

200:切割道區域 200: cutting lane area

210:蝕刻帶 210: Etched belt

211:非垂直側壁 211: Non-vertical side walls

220:切割邊緣痕跡 220: Cut edge marks

300:高光反射區 300: high light reflection area

400:光刻膠 400: Photoresist

Claims (9)

一種晶片切割道工藝方法，其特徵在於，包括以下步驟： 對一切割道區域進行化學蝕刻，形成一蝕刻帶，該蝕刻帶的側壁為非垂直面側壁；及 用機械砂輪對準該蝕刻帶進行切割，切割邊緣痕跡落在該蝕刻帶內，且該蝕刻帶位於晶圓表面的輪廓為無機械損傷的平直直線，使晶圓上表面形成具有平整邊緣輪廓的高光反射區域。 A wafer dicing process method, characterized in that it comprises the following steps: chemically etching a scribe line region to form an etched zone with sidewalls that are non-vertical sidewalls; and Align the etched strip with a mechanical grinding wheel for cutting, the cutting edge traces fall in the etched strip, and the contour of the etched strip on the wafer surface is a straight line without mechanical damage, so that the upper surface of the wafer forms a flat edge profile of highly reflective areas. 如請求項1所述之晶片切割道工藝方法，其中，該蝕刻帶的深度為10-20μm，寬度為20-40μm。The wafer dicing line processing method according to claim 1, wherein the etching zone has a depth of 10-20 μm and a width of 20-40 μm. 如請求項1所述之晶片切割道工藝方法，其中，在化學蝕刻之前，用光刻定義該切割道區域。The wafer dicing line processing method as claimed in claim 1, wherein the dicing line area is defined by photolithography before chemical etching. 如請求項1所述之晶片切割道工藝方法，其中，在化學蝕刻後切割工藝前，用機械研磨減薄該切割道區域背向光刻膠的一側。The wafer dicing line processing method as claimed in claim 1, wherein, before the dicing process after the chemical etching, the side of the dicing line area facing away from the photoresist is thinned by mechanical grinding. 如請求項4所述之晶片切割道工藝方法，其中，減薄後的晶圓剩餘厚度為50-200μm。The wafer dicing method according to claim 4, wherein the remaining thickness of the thinned wafer is 50-200 μm. 如請求項1所述之晶片切割道工藝方法，其中，該切割工藝為機械切割或鐳射切割。The wafer dicing process method as described in Claim 1, wherein the dicing process is mechanical dicing or laser dicing. 如請求項1所述之晶片切割道工藝方法，其中，在切割工藝後去除光刻膠。The wafer dicing process method as claimed in claim 1, wherein the photoresist is removed after the dicing process. 如請求項1所述之晶片切割道工藝方法，其中，該蝕刻帶的側壁為弧形側壁，其寬度向下逐漸減小。The wafer dicing line processing method as claimed in claim 1, wherein the sidewall of the etching zone is an arc-shaped sidewall, and its width gradually decreases downwards. 如請求項1所述之晶片切割道工藝方法，其中，化學蝕刻所使用的蝕刻液包含 H 3PO 4/H 2SO 4/HCl/H 2O 2/H 2O中的至少一種。 The wafer dicing line process method according to claim 1, wherein the etching solution used for chemical etching contains at least one of H 3 PO 4 /H 2 SO 4 /HCl/H 2 O 2 /H 2 O.
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JPS613428A (en) * 1984-06-15 1986-01-09 New Japan Radio Co Ltd Method for cutting semiconductor substrate
JPH08222529A (en) * 1995-02-14 1996-08-30 Oki Electric Ind Co Ltd Dicing mark, method of forming dicing mark, dicing method and dicing inspection method
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US6955989B2 (en) * 2001-11-30 2005-10-18 Xerox Corporation Use of a U-groove as an alternative to using a V-groove for protection against dicing induced damage in silicon
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US20140151841A1 (en) * 2012-12-01 2014-06-05 North Carolina State University Semiconductor devices having a positive-bevel termination or a negative-bevel termination and their manufacture
US10008472B2 (en) * 2015-06-29 2018-06-26 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices
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