JPH08222529A - Dicing mark, method of forming dicing mark, dicing method and dicing inspection method - Google Patents

Abstract

PURPOSE: To perform a dicing operation precisely even when the light-emitting edge of an LED is formed by a wet etching operation by a method wherein intersecting points in which contours for a first mark region and a second mark region which are continued to each other in the partial section of a straight line are crossed at an acute angle are situated in one end or both ends of the partial section of the straight line. CONSTITUTION: A dicing mark 27a is provided, on both sides of a straight line 31, with a first mark region 32 and a second mark region 34 whose size and shape are nearly identical and which are trapezoids, and both regions are formed to be a mutually continued shape in the partial section 33 of the straight line 31 in such a way that one side each of the respective trapezoids are overlapped exactly. Then, respective contours for the first and second mark regions 32, 34 form intersecting points 35a, 35b respectively so as to be crossed at an acute angle on both ends of the partial section 33 of the straight line 31. The dicing mark uses an impurity diffusion region formed in a substratum as a model for the dicing mark, and a recessed part is formed in a wafer. Then, the dicing mark which protrudes from the bottom face of the recessed part can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to an edge emitting LED.
A dicing mark used when dicing a wafer on which (Light Emitting Diode: Light emitting diode) is formed and separating into individual LEDs, a dicing mark forming method, a dicing method using the dicing mark, and a dicing quality inspection method. It is about.

[0002]

2. Description of the Related Art Edge emitting LED arrays are used as light sources for electrophotographic printers. The structure and the manufacturing method thereof are disclosed in, for example, Japanese Patent Application Laid-Open No. 2-125765 (hereinafter referred to as Publication 1) and Japanese Patent Application Laid-Open No. 5-31955 (hereinafter referred to as Publication 2). In the upper left column on page 3 of Publication 1,
N electrode, N-GaAs buffer layer, N-AlGaAs
It is described that individual edge emitting LED arrays can be obtained by dicing a semiconductor wafer having a structure in which layers, P-AlGaAs layers, and P electrodes are laminated. According to this method, 5 to 10 μm from the cut surface of the LED array
There is a problem that cracks and cracks are likely to occur in the portion up to m, and if the occurrence of these cracks and cracks extends to the light emitting layer, the production yield is deteriorated. Further, in the second column of page 5, right column, lines 31 to 32, it is described that a light emitting end face is formed on a semiconductor wafer having a double hetero structure by a dry etching method using a chlorine-based gas. ing. According to this method, since a fine pattern and deep etching are required, there is a problem that high manufacturing processing accuracy is required to eliminate etching defects.

In order to solve these problems, there has been proposed a method of using a wet etching method when manufacturing a light emitting end surface of an edge emitting LED array on a semiconductor wafer.

[0004]

However, if the wet etching method is used when the light emitting end face of the edge emitting LED array is formed on the semiconductor wafer, then when the wafer is diced to obtain individual LED arrays. In addition, a new problem arises in that the dicing mark used as a mark cannot be directly formed at the dicing position.

LE is applied to the wafer by wet etching.
When the light emitting end face of D is manufactured, a groove-shaped recess is formed in this wafer, and the wafer in the portion corresponding to the recess is removed.
Since it is the part below the bottom of the recess that is diced,
Even if the dicing mark is formed in advance at the dicing position, it is removed when the recess is formed. For this reason, it has been necessary to determine the dicing position based on the dicing marks provided on the portion other than the concave portion and perform the dicing.

If dicing is performed by such a method, the dicing position is likely to shift. For this reason, there is a possibility that the shape of each LED array may vary, and that the amount of light emitted from the light emitting elements (LEDs) forming the LED array may vary.

In addition, the inspection for determining the quality of dicing (determination of overcutting or uncutting) requires a complicated method of measuring the distance from the cut portion to the dicing mark provided on the portion other than the concave portion. there were.

Therefore, the LED is wet-etched.
It has been desired to provide a dicing mark, a method for forming the dicing mark, and a method for dicing the dicing mark, which enable accurate dicing even when the light emitting end face is manufactured. In addition, similarly, the appearance of an inspection method that can easily determine the quality of dicing has been desired.

[0009]

Therefore, the dicing mark of the invention of claim 1 of this application has the following features. That is, on both sides of the straight line, the first and second mark areas having the same or different shapes, which are continuous with each other in the straight line sub-section, are provided, and the first and second mark areas are provided at one or both ends of the straight line sub-section. It is characterized in that the intersections where the respective contour lines of the first and second mark areas intersect at an acute angle are located.

Further, according to the invention of claim 2 of this application, dicing marks for dicing the wafer are formed on a wafer on which a large number of edge emitting light emitting diodes are arranged in a matrix. In this regard, it is characterized in that a dicing mark is formed on the bottom surface of the recess formed in the wafer by the wet etching process for forming the light emitting end face of the light emitting diode.

Further, according to the invention of claim 3 of this application, this wafer is used as a wafer on which a large number of edge emitting type light emitting diodes are formed with the light emitting direction oriented in the column direction. In forming a dicing mark for dicing, the following (a),
The method is characterized by including steps (b) and (c) in this order.

(A) The same impurity is alternately applied to the base along the column direction so that the first impurity diffusion regions for light emitting regions and the second impurity diffusion regions for forming dicing marks are alternately exposed to the surface of the base. It is formed by using.

(B) Of the adjacent first and second impurity regions, a surface of a part of the first impurity region on the second impurity region side and the entire surface of the second impurity region are exposed with an etching mask as a base. Be provided on the entire surface of.

(C) By using the etching mask to wet-etch the base to form a recess, a light emitting end face is formed on the etching surface of the first impurity region, and a flat surface of the second impurity region is formed on the bottom of the recess. A dicing mark having a transferred shape is formed.

Further, according to the invention of claim 4 of this application, first and second mark regions having the same or different shapes from each other, which are continuous with each other in a partial section of the straight line, are provided on both sides of the straight line. A wafer having dicing marks and edge emitting type light emitting diodes formed at intersections where the respective contour lines of the first and second mark regions intersect at an acute angle is diced at one end or both ends of the partial section. On the above-mentioned straight line, and
It is characterized in that dicing is performed so that either one of the second mark area and the second mark area remains.

Further, according to the invention of claim 5 of the present application, first and second mark areas having the same or different shapes from each other, which are continuous with each other in a partial section of the straight line, are provided on both sides of the straight line. A wafer having a dicing mark and an edge emitting light emitting diode in which an intersection point where the contour lines of the first and second mark regions intersect at an acute angle is located at one end or both ends of the partial section is diced. Later, when inspecting the quality of dicing,
The dicing is performed according to the contour line 2 of the dicing mark described above.
It is characterized in that the quality of dicing is determined by observing the quality of the shape of the remaining dicing marks after dicing, performed along a straight line passing through one intersection.

[0017]

According to the dicing mark of the invention of claim 1 of this application, there are two intersection points of the contours of the first and second mark areas forming the dicing mark, and the line connecting these two intersection points is diced. Since it can be used as a reference line for the dicing, the dicing position can be determined by using these two intersections as a mark, and therefore dicing can be performed easily and accurately.

According to the invention of claim 2 of this application, the light emitting end face is formed by wet etching, and
Since the dicing marks are formed on the bottoms of the grooves or recesses dug by this wet etching, the dicing marks can be formed on the wafer at the dicing positions between the light emitting diodes or the light emitting diode arrays to be cut out.

Further, according to the invention of claim 3 of this application, a second impurity diffusion region for forming a dicing mark is previously formed between the first impurity diffusion regions for the light emitting regions for each light emitting diode on the wafer. The first impurity diffusion region is partially etched to form a light emitting end face, which is formed as a prototype of a dicing mark, and the second impurity diffusion region and its peripheral region are etched by wet etching to form a groove (or (Recess) is formed. Due to the difference in etching rate between the second impurity diffusion region and the wafer material in the peripheral region in this wet etching, the second impurity diffusion region is substantially transferred as a protruding or dented region to the bottom surface of the groove dug by etching. Formed, and this transferred and formed area becomes a dicing mark. Therefore, if the second impurity diffusion region is formed in advance at the dicing position of the wafer as a prototype having a plane shape that matches the shape of the die sigmark to be finally obtained, the wet etching process for forming the light emitting end face is used. The dicing mark can be accurately and easily formed at the dicing position.

According to the invention of claim 4 of this application, since dicing can be performed at an accurate position,
There is no risk of variations in the shapes of individual LED arrays and variations in the amount of light emitted by the light emitting elements (LEDs) that make up the LED arrays.

Furthermore, according to the invention of claim 5 of this application, the quality of the dicing can be inspected by observing the quality of the shape of the residual dicing marks after dicing, so that the inspection can be performed accurately and easily. It can be carried out.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of each invention of this application will be described below with reference to the drawings. Each drawing schematically shows the size, shape, and arrangement relationship of each component so that the invention can be understood. Further, in the following description, specific materials, conditions, etc. may be used, but these materials, conditions, etc. are merely one of the preferred examples, and are not limited thereto.

FIGS. 1 to 3 are diagrams for explaining the structure of an edge-emitting LED array 10 according to an embodiment of the invention of this application. FIG. 1 shows a case in which a plurality of LED arrays arranged in a matrix are formed on a wafer, and among the plurality of edge-emitting LED arrays 10 before dicing, the direction in which the light-emitting edge is formed is the column direction. 2 lined up in the row direction
FIG. 3 is a partial schematic plan view showing the area where the row LED arrays 10a and 10b are built, as seen from above. 2 is a view when FIG. 1 is viewed in a direction of an arrow from a cross section taken along line α-α, and FIG. 3 is a cross-sectional view taken along line β-β in FIG. In FIG. 3, hatching and the like showing the cross section are partially omitted.

In FIGS. 1 to 3, reference numeral 11 denotes an N-type semiconductor base forming a wafer. Specifically, an N-type gallium arsenide (GaAs) substrate 11a and epitaxially grown on this GaAs substrate 11a. N-type gallium
It is composed of an arsenic / phosphorus (GaAsP) layer 11b (FIGS. 2 and 3). 13 is an N-type semiconductor base 11,
P-type GaA formed at intervals according to the LED arrangement pitch
It is the sP layer. The P-type GaAsP layer 13 serves as a light emitting region, that is, a light emitting layer. Further, 15 is a P-side electrode, 17 is N
The side electrode 19 is an insulating film that electrically insulates the P-side electrode 15 from the N-type semiconductor base 11. In addition, in FIG.
What is indicated by 1 is a diffusion prevention film. Diffusion prevention film 21
Is necessary for manufacturing, and has a function of preventing P-type impurities used when forming the P-type GaAsP layer (light emitting layer) 13 from diffusing into a region other than a predetermined region of the N-type semiconductor underlayer 11. However, the structure of the LED is not always necessary. Reference numeral 23 denotes a groove or a recess formed on the wafer at the time of wet etching for forming a light emitting end face and a dicing mark, which are side surfaces 26a and 26b of the recess 23, on which the P-type GaAsP layer 13 is exposed. Is the light emitting end face 25. The side surfaces 26a, 26b may be vertical or inclined in either direction. In the illustrated example, the inclined side surface is opened upward from the bottom surface of the recess 23. Although the bottom portion 26c of the recess 23 is normally a flat surface, the dicing mark 27 is formed in a convex or concave shape on the bottom portion (bottom surface) 26c. In the illustrated example, a convex dicing mark is shown. There is. In this example,
The dicing marks are provided at positions corresponding to between the two adjacent LEDs at the positions forming the LED arrays 10a and 10b, respectively. Reference numeral 29 is a dicing area for separating the two LED arrays 10a and 10b, which are determined based on the dicing mark 27. This dicing area 2
The width of 9 is determined by the width of the dicing blade used for dicing. In this embodiment, the dicing area 2
9 is set as a region in which one end of this region 29 passes through the dicing mark 27 and is further away from the light emitting end face 25 of the LED.

1. Example of dicing mark FIGS. 4A to 4D and FIG. 5 are explanatory views for explaining an example of the dicing mark, and are schematic plan views when the wafer surface side is viewed from above the wafer. It is shown.

FIGS. 4A to 4D show diffusion windows 28a,
28b, 28c, 28d, dicing mark prototype 41
a, 41b, 41c, 41d and dicing mark 2
7a, 27b, 27c, 27d are examples of plane shapes.
The broken line represents the contour of the impurity diffusion region for forming the dicing mark, and the entire region surrounded by the broken line forms the prototype of the dicing mark. In the drawings, the regions that are also hatched and emphasized are shown together with the dicing mark prototypes 41a, 41b, 41c, and 41d by, for example, diffusing impurities into the base.
Windows 28a, 28b, 28c, 28 for forming
Indicates d. Actually, for example, a diffusion window 28 having a shape to be the source of the dicing mark 27 is formed in a diffusion prevention film provided on a semiconductor wafer, and impurities are introduced into the underlayer 11 through the diffusion window 28 to diffuse the impurities. A prototype of a dicing mark having a shape spread in a region indicated by a broken line shown in (A) to (D) of 4 is obtained. Since the dicing mark is formed as a shape in which this master is substantially transferred, the shape of this master may be considered as the shape of the dicing mark. Therefore, here, this prototype is used as the dicing mark 27a,
27b, 27c, and 27d will be described instead. In addition,
In that case, P ₁ and P ₂ in the drawing are reference points for determining the dicing position. A detailed description thereof will be given in an example of a method for forming a dicing mark described later. Here, the dicing mark 27a of FIG. 4A will be described as the dicing mark of the embodiment. Further, FIG. 5 is a plan view for explaining the shape of the dicing mark 27a. In the following description, the dicing mark may be represented by 27, the diffusion window may be represented by 28, and the dicing mark prototype may be represented by 41.

According to the dicing mark 27 of the present invention, on both sides of the straight line, the first and second mark areas having the same or different shapes from each other and continuous with each other in the straight line partial section are provided, and the partial section is provided. An intersection point where the respective contour lines of the first and second mark areas intersect at an acute angle is located at one end or both ends of.

The dicing mark 27a of this embodiment is
As shown in FIG. 5, both sides of the straight line 31 (in the illustrated example, the straight line 3
1 above and below 1) and the first and second mark areas 32 and 3 having trapezoidal shapes having substantially the same size and shape.
In the partial section 33 of the straight line 31, both regions are continuous with each other so that the sides of the trapezoids are exactly overlapped. Then, the respective contour lines of the first and second mark areas 32 and 34 intersect with each other at both ends of the partial section 33 of the straight line 31 at an acute angle and form an intersection point 35.
a and 35b are formed respectively. These intersections are also reference points for determining the dicing position, and therefore, these intersections are represented by P ₁ and P ₂ as representatives.

Although a detailed method of forming the dicing mark will be described later, for example, an impurity diffusion region is formed in a base and the impurity diffusion region is used as a prototype of the dicing mark 27, and thereafter, this prototype of the wafer and When the peripheral area is wet-etched to form the concave portion 23 in the wafer, the original planar shape of the dicing mark 27 is transferred to the bottom surface of the concave portion 23 due to the difference in the etching rate between the base and the impurity, and from the bottom surface of the concave portion 23. It can be formed as a protruding dicing mark 27.

At this time, if the shape of the dicing mark satisfies the characteristics of the present invention described above, that is, 2
If the intersections P ₁ and P ₂ of the contour lines of the two mark areas are located on a predetermined straight line, even if the impurities diffuse and spread to the shape shown by the broken line, the two intersections P ₁ and P 2 Since the straight line connecting P ₂ can be used as a reference line for dicing, the position for determining dicing is set to one,
Dicing can be performed accurately and easily.

The dicing mark 27b shown in FIG.
Is a shape in which a rhombus having the same center as the rectangle is provided in the rectangle. In this example, the straight line connecting the reference points P ₁ and P ₂ , which are the intersections, may be used as the reference line for dicing. When dicing a wafer to obtain individual LED arrays, it is necessary to dice not only the LED arrays adjacent to each other in the row direction (direction forming side surfaces of the LED arrays) but also in the column direction forming the light emitting end faces of the LED arrays. There is. Therefore, although not shown, it is conceivable to form dicing marks in the row direction as well. At this time, for example, in the case of the dicing marks having the shapes as shown in FIGS. 4A, 4C, and 4D, since there is only one set of reference points P ₁ P ₂ , this mark is rotated by 90 °. As a result, it can be used as a dicing mark in the row direction. However, like a dicing mark having a shape as shown in FIG. 4B, there are two sets of reference points P ₁ and P ₂ and P ₃ and P ₄ , and a straight line connecting P ₁ and P ₂ If the straight line connecting ₃ and P ₄ is 90 °, the dicing mark itself is 9
Even if it is not rotated by 0 °, it can be used as it is as a dicing mark in the row direction.

The dicing mark 2 shown in FIG.
7c is the dicing mark 27 of FIG.
It is similar to the shape of a, but has a shape in which the bases of trapezoids facing each other are stretched, and the intersection of the contours of the marks at an acute angle, that is, the dicing reference point P.
_The shape is such that the portions ₁ and P ₂ are more prominent.

As can be understood from FIGS. 4A to 4C, the dicing marks satisfying the features of the present invention are:
In both cases, the dicing position is easily determined without the shape of the dicing mark prototype, which is formed by diffusion, affecting the portion indicating the dicing position.

All of the dicing mark shapes 27a to 27c in FIGS. 4A to 4C are intersections (P ₁ and P ₂ , P _{2) at which} the contour lines of the first mark area and the second mark area intersect. _Although it is symmetrical with respect to the straight line connecting ₃ and P ₄ ), it may have a shape in which trapezoids of different sizes are joined, as in the dicing mark 27d shown in FIG. In addition, the shape is not limited to these as long as the characteristics of the invention are satisfied.

2. Example of Method of Forming Dicing Marks (A) to (E) of FIG. 6, (A) to (D) of FIG. 7, and FIG.
FIG. 11 is a process diagram according to an embodiment of the method for forming a dicing mark of this application. 6A to 6E and FIG.
8A to 8D show steps in a cross section of a portion similar to the cross section along the line α-α in the plan view of FIG. 1.
1 is a plan view showing the steps in the middle of these steps, following FIG. 6 and 7, hatching showing a cross section is partially omitted.

According to the method of forming the dicing marks of the present invention, when the dicing marks 27 for dicing the wafer are formed on the wafer on which a large number of the edge emitting type light emitting diodes are arranged in the matrix form. In the wet etching process for forming the light emitting end face 25 of the light emitting diode, the dicing mark 27 is formed on the bottom surface of the recess 23 formed in the wafer by this wet etching.

Specifically, for example, a large number of end face types L are arranged in a matrix and the light emission direction is directed in the column direction.
To form the dicing marks 27 for dicing the wafer on the wafer on which the ED is formed, first,
The first impurity diffusion regions 39 for light emitting regions and the second impurity diffusion regions 41 for forming dicing marks are alternately formed on the base 11 along the column direction, and are formed using impurities so as to be exposed on the surface of the base. The impurities may be common to the first and second impurity diffusion regions 39 and 41, or different regions may be formed by using different impurities.

Therefore, in this embodiment, the semiconductor base 1
The diffusion preventive film 21 is formed on the entire surface of No. 1 by a known film forming method, for example, a sputtering method or a vapor phase growth method, for example, 50 to 500 nm.
It is provided with a film thickness of about the same (see FIG. 6A). The diffusion prevention film 21 is selected from materials such as alumina, silicon nitride, and silicon oxide. Then, the first diffusion window 3 is formed on the diffusion prevention film 21.
7a and the second diffusion window 37b are formed ((A) of FIG. 6).
reference). FIG. 8 is a plan view at this time. The first diffusion window 37a and the second diffusion window 37b are for forming a first impurity diffusion region 39 for a light emitting region and a second impurity diffusion region 41 for forming a dicing mark, which will be described later.
Further, the second diffusion window 37b is a window corresponding to the diffusion windows 28a, 28b, 28c and 28d already described with reference to FIG. 4, but in the embodiment here, when the shape is similar to the diffusion window 28a. Is shown. These first diffusion windows 37
Although the layout relationship such as the size and shape of the a and the second diffusion window 37b and the distance between the two is determined by the design, the first impurity region 39 and the second impurity region 41 are continuous due to mutual diffusion later, In order to avoid causing a short circuit or the like, it is preferable to form them so as to be spaced apart by diffusion so as not to be continuous. For example, in order to obtain the structure shown in FIG. 1 described above, when the arrangement direction of the individual LEDs of the LED array is the column direction, the light emitting layer (also referred to as the light emitting region) 13 and the light emitting layer 13 are most suitable. The first and second diffusion windows 3 are arranged such that the respective arrays of the close dicing marks 27 are shifted in the row direction, and the light emitting layer 13 and the dicing marks 27 are arranged in a staggered pattern as a whole.
7a and 37b are provided. In this embodiment, the size of the first diffusion window 37a in plan view is about 30 μm in length and width,
The size of the diffusion window 37b was about 20 μm in length and width, and the distance between the two was about 15 μm in a straight line.

Next, a diffusion control film 43 is formed on the entire upper surface of the base 11 which has been subjected to the above-mentioned treatment by a known film forming method.
A structure having a film thickness of about 0 to 300 nm is obtained as shown in FIG. The diffusion control film 43 is preferably made of, for example, alumina, silicon nitride, silicon oxide, PSG (Ph).
It is better to use a film selected from materials such as ospho-Silicate Glass).

Next, through the diffusion control film 43, from the first and second diffusion windows 37a and 37b into the underlayer 11,
A P-type impurity is introduced, and the introduced impurity is diffused by a vapor phase diffusion method or the like, and the first impurity diffusion region 39 is formed on the base 11.
And the second impurity diffusion region 41 is formed. At this time,
First impurity diffusion region 39 and second impurity diffusion region 41
Is about 5 μm, for example. After that, the diffusion control film 4 is formed by immersing the wafer in a hydrofluoric acid-based etching solution.
3 is removed to obtain a structure as shown in FIGS. 6B and 9. Here, in the drawing, the first impurity diffusion region 39
And the second impurity diffusion region 41 is clearly shown,
These first and second impurity diffusion regions 39 and 41
Can't be confirmed with the naked eye. However, in order to facilitate understanding of the invention, these are clearly shown here.

Next, according to the forming method of the present invention, the second impurity diffusion region 4 of the first impurity diffusion region 39 among the first and second impurity diffusion regions 39 and 41 adjacent to each other is formed.
An etching mask 45 exposing a part of the surface on the first side and the entire surface of the second impurity region 41 is provided on the upper side of the underlayer 11. This is because the etching groove, that is, the concave portion 23 is formed in the exposed portion. Therefore, in this embodiment, first, the diffusion prevention film 21 in the portion corresponding to the formation planned region 44 of the recess 23 is removed by a suitable method ((C) of FIG. 6). The region 44 where the recess 23 is to be formed takes into consideration the width of the dicing region 29, the dicing alignment accuracy margin including the repeat accuracy, and the chipping margin, and the sum of these is at least the minimum dimension. The width of the minimum dimension is determined by having it. The chipping margin is a margin to be taken into consideration so that even if chipping occurs, it does not affect the light emitting layer (light emitting region). Next, in this embodiment, the wafer other than the region where the recess 23 is to be formed is covered with the etching mask 45 ((D) in FIG. 6).
And FIG. 10). The etching mask 45 is formed using, for example, photoresist. In FIG. 10, the wafer portion covered with the etching mask 45 is hidden and cannot be actually seen.

Further, according to the forming method of the present invention, the light emitting end face 25 is formed on the etching surface of the first impurity region 39 by wet etching the base 11 to form the recess 23 using the etching mask 45. At the same time, the dicing mark 27 to which the planar shape of the second impurity region 41 is transferred is formed on the bottom of the recess 23. For this reason,
In this embodiment, the recesses 23 are formed by wet etching the base 11 using the etching mask 45. The etching solution used for wet etching can be selected from phosphoric acid-based, citric acid-based, sulfuric acid-based etching solutions, and the like. At this time, the speed of etching the P-type first and second impurity diffusion regions 39 and 41 is slower than the speed of etching the surrounding N-type GaAsP layer 11a, so that these regions 39 and 41 are etched.
The area around is quickly etched. Therefore, the first and second impurity diffusion regions 39 and 41 are gradually separated from the surrounding N
It protrudes beyond the type GaAsP layer 11a. Even if a part of the P-type first impurity diffusion region 39 and the P-type second impurity diffusion region 41 are entirely removed by further etching, the protruding portion caused by the difference in etching rate remains.
This protruding portion becomes the dicing mark 27 to which the planar shape of the second impurity diffusion region 41 is transferred. In addition, recess 2
By forming 3, the part of the first impurity diffusion region 39 remains and becomes the light emitting region (P-type GaAsP layer) 13, and the etching surface of this region 13 is formed as the light emitting end face 25 (see FIG. 6). (E)).

Now, let us say that the bottom surface of the concave portion 23 is indicated by 26c, the side surface on the light emitting end surface side is 26a, and the side surface on the side facing the light emitting end surface is 26b. The recess 23 is formed to have a depth exceeding the PN junction surface formed by the first impurity diffusion region 39 and the base 11. In this case, since it is the base 11 below the bottom portion 26c of the recess 23 that is diced, the light emitting layer 13 is not adversely affected. In this embodiment, the depth of the recess 23 is about 10 μm, and the dicing mark 2 protruding from the bottom 26 c of the recess 23.
The height of 7 is about 0.3 μm. Bottom 26 of recess 23
c is in the N-type GaAsP layer 11b and does not reach the boundary surface with the N-type GaAs substrate 11a.

In this wet etching, etching is performed more uniformly on any part of the wafer than dry etching. Further, throughput can be improved because a plurality of wafers can be simultaneously processed by one wet etching. Further, even if the recess 23 is formed by wet etching, the dicing mark 27 can be directly formed at the dicing position, so that dicing can be performed accurately and easily.

Next, an example of steps after the recess 23 is formed and before the LED arrays 10a and 10b before dicing are manufactured will be briefly described. Etching mask 45
Is removed by a stripper (FIG. 7 (A) and FIG. 11),
After that, the entire surface of the wafer is covered with the alumina film 47 or the like. The film thickness of the alumina film 47 can be, for example, about 50 to 500 nm ((B) of FIG. 7). This alumina film 47
Is an N-type semiconductor substrate 11 and a P-side electrode 1 to be formed later.
5 (see FIGS. 1 to 3), an insulating film 19 for insulation.
And a silicon nitride film, a silicon oxide film, or the like can be used instead of the alumina film.

Next, the alumina film 47 is processed and shaped by a known photolithography technique and etching technique to obtain an insulating film 19 having a predetermined shape (FIG. 7C).
Next, P connected to the P-type GaAsP layer (light emitting layer) 13
The side electrode 15 is formed by a known film forming method and fine processing technique, and the N side electrode 17 is formed on the back surface of the N-type semiconductor base 11 ((D) of FIG. 7). At this time, if the back surface of the underlayer 11 is polished to remove contaminants, oxide films, etc. adhering to the back surface of the underlayer 11 before the N-side electrode 17 is formed, the characteristics of the LED are likely to be stable. . Thus, the LED array (before dicing) in the state shown in FIGS. 1 to 3 is obtained.

As can be understood from the above description, one of the features of the forming method of the present invention is that the portion which becomes the light emitting layer 13 and the portion where the dicing marks 27 are formed later can be formed at the same time. is there. Therefore, the distance between the two can be positioned very accurately in advance, and as a result, the shapes of the individual LED arrays may vary, and the amount of light emitted from the light emitting elements forming the LED arrays may vary. Absent.

Alternatively, these first impurity diffusion regions 39
A prototype of the dicing mark may be formed in a state where the second impurity diffusion region 41 and the second impurity diffusion region 41 are joined together without being separated from each other. This will be described in detail in the following description as a modified example.

12 to 14 are explanatory views of modified examples of the method for forming a dicing mark according to the present invention. FIG. 12A is a plan view of a modified example, which is shown in a manner similar to FIG. That is, when the direction in which the light emitting end faces 250 are formed is the row direction among the plurality of edge emitting LED arrays 100 before dicing that are manufactured in a matrix on the wafer, two rows of LEDs arranged in the row direction are arranged. Array 10
The area around 0a and 100b is shown from above. Further, FIG. 12B is a plan view of a diffusion window for a dicing mark and a prototype of the dicing mark according to the modified example. In addition, FIG. 13A is a diagram when FIG. 12A is viewed in a direction of an arrow from a cross section taken along line XX, and FIG. 13B is a YY sectional view. is there. 14 is a process drawing of the modified example, which is shown following the process drawing of the embodiment of FIG.

Such a planar dicing mark 2
In order to obtain 70, a base 110 (N-type GaAs substrate 110
a and the N-type GaAsP layer 110b), the first diffusion window 370a and the second diffusion window 370a are formed in the diffusion prevention film 210 provided on the diffusion prevention film 210
The diffusion windows 370b are arranged as a single window that is aligned in the row direction when the LEDs are arranged on the LED array in the column direction and is joined together without being separated. Then, the diffusion window 370 having the shape shown by the solid line in FIG. 12B is formed ((A) in FIG. 14). Next, impurities are diffused, and the impurity diffused region 40 is diffused to the region shown by the broken line in FIG.
0 is formed ((B) of FIG. 14). This region 400 is a first impurity diffusion region 400a for forming a light emitting region and a second impurity diffusion region 400 for forming a dicing mark.
and b are connected and formed as one region.
The boundary between the two areas 400a and 400b is indicated by a one-dot chain line a. Since the planar shape of this area b corresponds to the shape of the dicing mark, the area indicated by the broken line will be described as a dicing mark 270. In addition, in order to emphasize the diffusion window 370 in FIG.
It is shown with hatching.

After that, the same processes as those in the embodiment already described with reference to FIGS. 6 to 7 are sequentially performed. Therefore,
When the description is duplicated, the description is omitted. The diffusion prevention film 210 at the portion corresponding to the recess formation planned region 440 is removed (FIG. 14C), and similarly, the region other than the recess formation planned region 440 is covered with the etching mask 450 (FIG. 14D), and thereafter. The recess 230 is formed in the recess formation-scheduled region 440 by wet etching. By this wet etching, the entire second impurity diffusion region 400b and a part of the first impurity diffusion region 400a are removed by etching, and an etching groove 230 as a recess is formed. Therefore, a part of the impurity diffusion region 400a remains, and the remaining region is the light emitting region, that is, the light emitting layer 13.
The surface exposed to the recess 230 of the light emitting layer 130 becomes the light emitting end face 250. This recess 230
When the concave portion 230 is formed so that the depth of the concave portion is deeper than the boundary between the light emitting layer 130 and the base 110, the side surface 230a is separated from the light emitting layer 130 by one side surface 230a of the concave portion 230. And the recess 23
0 dicing mark 270 projected by bottom surface 230
Is formed. The dicing marks 270 are formed on the bottom surface 2
It is formed away from the other side surface 230b of the concave portion 230 via 30c. Then, the etching mask 450
Are removed by a suitable method ((E) in FIG. 14). Since the light emitting layer (also referred to as a light emitting region) 130 also serves as a part of the dicing mark 270 of the modified example, the recess 230 is formed.
The portion protruding from the bottom of the is connected to the light emitting end face 250 ((A) and (B) of FIG. 12 and (B) of FIG. 13). After that, the insulating film 190, the P-side electrode 150, and the N-side electrode 170 are formed by a known film forming method and fine processing technique, and are shown in FIGS. 12A, 13A, and 13B. LED array 100a before dicing
Multiple LED arrays can be formed on the wafer, such as and 100b. After that, other parts are the same as those in the embodiment already described with reference to FIGS. 6 to 7, and therefore the description thereof will be omitted.

When the dicing mark is provided in contact with the region of the light emitting layer as in this modification, the following effects are obtained. First, when the prototype of the dicing mark and the light emitting layer are formed by diffusing the same impurities, the light emitting layer 13 and the dicing mark 27 are formed with a certain interval as in the above-described embodiment (see FIG. 1) When the LED array becomes high-definition and the pitch between the LEDs arranged side by side in the LED array becomes narrow, it becomes difficult to form dicing marks due to lack of space. If formed forcibly, the individual L's arranged side by side in the LED array
The diffused light emitting layers 13 of the LEDs adjacent to each other in the vicinity of the dicing mark in the ED are short-circuited through the similarly diffused dicing mark.

Therefore, as in this modification, the first
If the prototype 400 of the dicing mark is formed in a state where the impurity diffusion region and the second impurity diffusion region are joined, LE
Even if the D arrays 100a and 100b have high definition,
The dicing mark 270 can be directly formed at the dicing position.

3. Example of Dicing Method Next, according to the dicing method of the present invention, first and second mark regions having the same or different shapes, which are continuous with each other in a partial section of the straight line, are provided on both sides of the straight line. A wafer having dicing marks and edge emitting type light emitting diodes formed at intersections where the respective contour lines of the first and second mark regions intersect at an acute angle is diced at one end or both ends of the partial section. At this time, dicing is performed along the above-mentioned straight line so that either one of the first and second mark areas remains. In this embodiment, for example, the wafer shown in FIG. 1 is diced according to the dicing marks as a part of the wafer on which the dicing marks having the shape satisfying the above-described conditions and the edge emitting LEDs are formed.

Referring to FIG. 5, the first mark area 32
The edge of the dicing blade so that
Along the straight line 31 connecting the _two intersections P ₁ and P ₂ , dicing is performed from the bottom surface of the recess 23 formed in the wafer toward the back surface of the wafer. As a result, a region substantially the same as the dicing region 29 as shown in FIGS. 1 and 3 is cut. Therefore, since the dicing can be performed very accurately, there is no possibility that the shapes of the individual LED arrays will vary and that the light emission amount of the light emitting elements that form the LED array will vary.

4. Example of Inspection Method of Pass / Fail of Dicing Further, according to the inspection method of pass / fail of the dicing of the present invention, on both sides of a straight line, continuous with each other in a partial section of the straight line, having the same or different shapes from each other. The first and second mark areas are provided, and a dicing mark and an edge emitting light emitting diode, in which an intersection point where the respective contour lines of the first and second mark areas intersect at an acute angle is located at one end or both ends of the partial section, is formed. After inspecting the quality of dicing after dicing the wafer
The dicing is performed according to the contour line 2 of the dicing mark described above.
The quality of the dicing is judged by observing the quality of the shape of the residual dicing marks after dicing by performing along a straight line passing through the two intersections. In this embodiment, a dicing mark and an edge emitting LED having a shape satisfying the above-mentioned conditions are used.
As a part of the wafer on which is formed, for example, the wafer shown in FIG. 1 is diced according to dicing marks. As an example of the dicing marks, FIG.
A case of overcutting or uncutting by the dicing inspection method of the present invention will be described as an example in FIGS. 15A to 15E using a mark of the dicing mark type shown in FIG. The first mark area on one side of the straight line 31 passing through the two intersections P ₁ and P ₂ of the contour lines of the dicing marks is 32, and the second mark area on the other side is 34. Dicing is performed along the straight line 31 (see FIG. 5) from the bottom of the recess 23 toward the back surface, and the shape of the remaining dicing marks that remain is observed. In FIGS. 15A to 15E, the residual dicing marks are shown by solid lines and the diced portions are shown by dotted lines. At this time,
As shown in FIG. 15A, the second mark area 34
Is completely diced and the shape of the remaining dicing mark is the first mark area 32 itself on one side of the straight line 31, that is, if the area 32 is almost completely left, it is the best. Further, when the entire second mark area 34 and a part of the first mark area 32 are diced and the first mark area 32 remains small (FIG. 15 (B)), or 1 mark area 3
Up to the case where all 2 are left and the second mark area 34 is even missing (FIG. 15C), the dicing result is acceptable. However, when the mark does not remain at all ((D) of FIG. 15)
Is determined to be overcut, and when all the marks remain ((E) in FIG. 15), it is determined to be uncut.

If the dicing mark has the above-mentioned shape, the light emitting end face 2 is formed by the wet etching method.
Even if No. 5 is formed, the dicing mark can be directly formed at the dicing position. Therefore, dicing is performed according to the dicing mark directly provided at the dicing position, and the shape of the remaining dicing mark is observed to inspect the quality of dicing. You can As a result, it becomes possible to accurately and easily perform the inspection for overcutting and uncutting.

It is obvious that these inventions are not limited to the above-mentioned embodiments. For example, in the embodiment, the case where the wafer on which the LED array is formed is diced has been described.
Can also be applied when dicing in the row and column directions. In particular, the embodiment has been described as a suitable method for forming an LED array. In each of the embodiments, the case where the light emitting end faces 25 of the LED array are formed so as to face the same direction on the wafer has been described. However, in the wafer provided so that the light emitting end faces 25 face each other. Also, each invention described above can be applied.

The cross-sectional shape of the recess 23 (or the recess 230) is not limited to the tapered shape, but may be an inverse tapered shape or a vertical wall shape. It is possible to change the cross-sectional shape of the recess 23 by changing the crystal orientation of the wafer.

[0060]

As is apparent from the above description, according to the dicing mark of the present invention, even if the prototype of the dicing mark is formed by diffusing impurities into the base wafer, the dicing position is kept constant. It is possible to obtain a dicing mark having a unique shape.

Further, according to the method of forming a dicing mark of the present invention, even if the light emitting end face of the LED array is formed by wet etching, the dicing mark can be directly formed at the dicing position. As a result, subsequent dicing and dicing inspection are accurate and easy, and it is possible to shorten the process time and improve the yield.

Further, according to the dicing method of the present invention, since dicing can be performed at an accurate position,
The shape of each LED array may vary,
There is no risk of variations in the amount of light emitted by the light emitting elements forming the D array. Therefore, it is possible to reduce the occurrence of defective products, which also leads to an improvement in yield.

Further, according to the inspection method of quality of dicing of the present invention, the quality of dicing can be inspected by observing the quality of the shape of the residual dicing marks after dicing. As a result, the inspection can be performed accurately and easily in a short inspection time as compared with the method of performing the dicing inspection based on the dicing marks provided at positions other than the dicing position. This also improves the reliability of the inspection.

[Brief description of drawings]

FIG. 1 is a partial plan view according to an embodiment of each invention.

FIG. 2 is a cross-sectional view taken along the line α-α of FIG.

FIG. 3 is a sectional view taken along line β-β of FIG.

4A to 4D are examples of a diffusion window, a dicing mark prototype, and a dicing mark.

FIG. 5 is an explanatory diagram of dicing marks according to the embodiment.

FIG. 6 is a process drawing of a method for forming a dicing mark.

FIG. 7 is a process diagram of the dicing mark forming method following FIG. 6;

FIG. 8 is a plan view (No. 1) for explaining the dicing mark forming method.

FIG. 9 is a plan view (No. 2) for explaining the dicing mark forming method.

FIG. 10 is a plan view (No. 3) for explaining the dicing mark forming method.

FIG. 11 is a plan view (No. 4) for explaining the dicing mark forming method.

FIG. 12A is a partial plan view of a modification of the dicing mark forming method, and FIG. 12B is a diffusion window of the modification.
It is an explanatory view of a prototype of a dicing mark and a dicing mark.

13A is a sectional view taken along line XX of FIG. 12A, and FIG. 13B is a sectional view taken along line YY of FIG.

14A to 14E are process diagrams of a modified example of the dicing mark forming method.

FIG. 15 is an explanatory diagram related to an example of an inspection method of quality of a dicing mark.

[Explanation of symbols]

 10a, 10b: Edge emitting LED array 11: Semiconductor base 11a: N-type GaAs substrate 11b: N-type GaAsP layer 13: P-type GaAsP layer (light-emitting region or light-emitting layer) 15: P-side electrode 17: N-side electrode 19: Insulating film 21: Diffusion prevention film 23: Recessed portion 25: Light emitting end surface 26a, 26b: Side surface 26c: Bottom surface 27: Dicing mark 28: Diffusion window 29: Dicing area 31: Straight line 32: First mark area 33: Partial section 34: Section 2 mark area | region 37a: 1st diffusion window 37b: 2nd diffusion window 39: 1st impurity diffusion area 41: 2nd impurity diffusion area 43: diffusion control film 44: recessed part formation area 45: etching mask

Front page continued (72) Inventor Masumi Koizumi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (5)

[Claims] 1. A first and a second mark area having the same or different shapes from each other, which are continuous with each other in a partial section of the straight line, are provided on both sides of the straight line, and the first and second mark areas are provided at one or both ends of the partial section. A dicing mark, characterized in that the intersections where the respective contour lines of the first and second mark areas intersect at an acute angle are located. 2. Wet etching for forming a light emitting end face of a light emitting diode when forming dicing marks for dicing the wafer on a wafer on which a large number of end face light emitting type light emitting diodes are arranged in a matrix. A method for forming a dicing mark, characterized in that a dicing mark is formed on the bottom surface of the recess formed in the wafer by the wet etching. 3. A dicing mark for dicing the wafer is formed on a wafer which is arranged in a matrix matrix and in which a large number of edge emitting light emitting diodes are formed with the light emitting direction oriented in the column direction. a) The first impurity diffusion regions for the light emitting regions and the second impurity diffusion regions for forming the dicing marks are alternately formed on the base along the column direction and are formed by using the same impurity so as to be exposed on the surface of the base. And (b) an etching mask that exposes a surface of a part of the first and second impurity regions adjacent to each other on the second impurity region side of the first and second impurity regions and an entire surface of the second impurity region. Is provided on the entire surface of the base, and (c) the base is wet-etched using the etching mask to form a recess, thereby forming a recess of the first impurity region. While forming a light emitting end face on the etching surface,
A method of forming a dicing mark, comprising: a step of forming a dicing mark, in which the planar shape of the second impurity region is transferred, on the bottom of the concave portion, in this order. 4. A first and a second mark area, which have the same or different shapes from each other and are continuous with each other on both sides of the straight line, in the partial sections of the straight line, and the first and second mark areas are provided at one or both ends of the partial section. When dicing a wafer on which the edge-emitting light-emitting diode and the dicing mark in which the respective intersections of the contour lines of the first and second mark regions intersect at an acute angle are located, along the straight line, and A dicing method, characterized in that dicing is performed so that one of the first mark region and the second mark region remains. 5. On both sides of the straight line, there are provided first and second mark areas having the same or different shapes, which are continuous with each other in the straight line sub-sections, and the first and second mark areas are provided at one or both ends of the sub-sections. When dicing a wafer on which a dicing mark having an intersection point where the respective contour lines of the first and second mark regions intersect at an acute angle and an edge emitting light emitting diode are formed, and then inspecting the quality of the dicing, An inspection method, wherein dicing is performed along a straight line that passes through two intersections of the contour lines of the dicing marks, and the quality of the shape of the remaining dicing marks after the dicing is observed to determine the quality of the dicing.