JPH1012919A - Light-receiving/emitting device, light-receiving/emitting device array, and manufacture of light-receiving/ emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable realization of a desired light emission quantity or light receiving quantity even in the case where the plane area of a lightreceiving/ emitting portion is reduced in comparison with the conventional technique, by constituting the light-receiving/emitting portion using a P-N junction having an uneven junction interface. SOLUTION: In a P-N junction 15, PN junction portions 15ya, 15yb on both sides of a band-shaped shallow junction portion 15x are regions having a greater junction depth than other regions. Therefore, the PN junction 15 having an uneven junction interface formed by the regions 15ya, 15x and 15yb is constituted. Thus, the junction area per unit plane area is increased. Accordingly, when a light emission quantity similar to that of the conventional technique is to be obtained, the plane area of the lightemitting portion may be reduced in comparison to the conventional technique. Therefore, light-emitting portions may be arrayed at a high density in constituting a LED array, and a desired light emission quantity may be obtained without increasing the dimension in a second direction of the LED.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting / receiving element, a light emitting / receiving element array, and a method for manufacturing the light emitting / receiving element. Here, the light receiving / emitting element means an element that can be used as a light receiving element and can also be used as a light emitting element depending on the direction of application of an electric signal to the element.

[0002]

2. Description of the Related Art As one kind of light receiving / emitting element array, for example, a light emitting diode array (hereinafter, also referred to as an LED array).
There is. The LED array is used, for example, as a light source for an electrophotographic printer. Focusing on the light emitting direction, LED arrays can be broadly classified into a top emission type and an edge emission type. The top emission type is, for example, an N-type G
An N-type semiconductor base formed by growing an N-type AlGaAs layer on an aAs substrate, P-type impurity diffusion regions formed in each of the bases scattered in an array, and N- and P-side electrodes. And emits light vertically and upward with respect to the semiconductor base surface. Here, each PN junction formed by the N-type semiconductor base and each P-type impurity diffusion region becomes an individual light-emitting portion in the LED array. On the other hand, the edge emitting type is, in short, a top emitting type that is cut along a direction perpendicular to the semiconductor base surface to produce an end face with an exposed PN junction. The type emits light in a direction parallel to the semiconductor base surface (for example, Japanese Patent Application Laid-Open No. 2-125765).
In the case of either type, a diffusion prevention mask having openings in an array is formed on an N-type semiconductor base during its manufacture. Then, a P-type impurity is introduced into the base through the diffusion prevention mask to form the P-type diffusion region.

[0003]

By the way, for an electrophotographic printer, for example, it is desired to improve the performance so that a higher-resolution image can be formed. For that purpose, it is necessary to reduce the pitch of each light emitting unit in the LED array. However, in such a case, it is necessary to reduce the size of each light emitting unit along the direction in which the light emitting units are arranged, which causes a problem that the amount of light emitted from the light emitting unit is reduced. In order to avoid this, the light emitting part, that is, PN
It is also conceivable to increase the dimension of the joining portion along a direction orthogonal to the direction in which the light emitting portions are arranged. However, when doing so, the size of the LED array along the direction orthogonal to the direction in which the light emitting units are lined up increases accordingly. This reduces the number of chips when each LED array chip is formed on a semiconductor wafer, which leads to an increase in the cost of the LED array.

[0004] Even if the plane area of the light emitting / receiving section is made smaller than before, the light receiving quantity of the light emitting / receiving section (in the case of a light receiving element, the amount of electric signal to be photoelectrically converted) can be as desired. A light emitting element, a light receiving / emitting element array, and a manufacturing method suitable for manufacturing these are desired.

[0005]

According to the present invention, there is provided a light emitting / receiving element comprising a light emitting / receiving section constituted by a PN junction having an uneven bonding interface.

According to the light emitting and receiving element of the present invention, the junction interface of the PN junction forming the light emitting and receiving section is uneven, so that the general PN junction (the junction interface on the bottom side of the PN junction is not formed). A light-emitting / emitting element having a larger junction area per unit area can be configured than when the light-emitting / receiving section is constituted by a substantially flat PN junction. The same effect as described above can be obtained in the light receiving / emitting element array. Therefore, a light receiving / emitting element (light receiving / emitting element array) having a light receiving area or a light emitting area larger than that of the related art can be obtained. Therefore, for example, even if the plane area of the light emitting unit is made smaller than that of the conventional light emitting unit, it is possible to realize a light emitting unit having the same light emission amount as the conventional one.

In the practice of the present invention, it is preferable that the PN junction having an uneven junction interface has the following structure. : PN having a shallow junction having a shallower junction depth than other portions and having at least one strip-shaped shallow junction traversing the region where the PN junction is formed along the first direction.
Joint. : The region where the junction depth is shallower than other portions and where the PN junction is formed is moved in the first direction and in the first direction.
A PN junction comprising at least one intersecting shallow junction traversing along a second direction intersecting the direction of. With these PN junctions, a light emitting and receiving element and a light emitting and receiving element array having a large junction area per unit area are realized.

[0008] In addition, the structure according to claim 7, namely, (a).
The bonding interface is uneven and includes two or more projections, and the diffusion depths of these projections are different from each other.
In the case of an end face light emitting / receiving light emitting / receiving element array in which each light emitting / receiving section is constituted by an N junction, or (b) the junction depth is smaller than other portions and a PN junction is formed. An end face receiving device having two or more strip-shaped shallow junctions traversing the region along the first direction, and each light-receiving / emitting unit formed by a PN junction having a different junction depth between the shallow junctions. In each of the light emitting and receiving light emitting and receiving element arrays, in addition to the effect of increasing the bonding area due to the unevenness of the bonding interface, there is also obtained the effect that a portion where the height of the bonding interface differs when viewed from the light emitting end face is generated. .

According to the method for manufacturing a light emitting / receiving element of the present invention, a diffusion prevention mask having an opening exposing a region where a light emitting / receiving portion is to be formed in the semiconductor base is formed on a first conductive type semiconductor base. And a step of introducing a second conductivity type impurity into the semiconductor base through the opening to form a second conductivity type impurity diffusion region in the semiconductor base to obtain a PN junction for forming a light emitting / receiving section. In the method for manufacturing a light receiving and emitting element, the method further comprises using, as the diffusion preventing mask, a diffusion preventing mask in which the opening for forming one light emitting and receiving unit is composed of two or more openings. And

According to the invention of this manufacturing method, a junction of a predetermined depth is formed in the semiconductor base portion below each opening, while the semiconductor base portion between two or more openings is introduced from these openings. A junction resulting from the lateral diffusion of the impurity, that is, a junction having a shallow junction depth is formed. Where 2
In the case of using a diffusion prevention mask in which the above-described openings are arranged in a one-dimensional direction, a strip-shaped shallow junction can be formed in a semiconductor base portion between two or more openings. In the case of using a diffusion prevention mask in which three or more openings are two-dimensionally arranged, a shallow junction is formed in a semiconductor base portion between the openings, so that a cross-shaped shallow junction can be eventually formed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a light emitting / receiving element, a light emitting / receiving element array, and a method for manufacturing a light receiving / emitting element array according to the present invention will be described with reference to the drawings. However, the drawings used in the description schematically show the dimensions, shapes, and arrangements of the components so that the present invention can be understood. Also, in each of the drawings, the same components are denoted by the same reference numerals, and redundant description will be omitted. Here, an example in which the present invention is applied to an LED array, which is a type of light emitting / receiving element array, will be described.

1. First Embodiment First, an example in which the present invention is applied to a top emission type LED array will be described. Moreover, the P having one strip-shaped shallow junction portion
An example in which individual light emitting units are configured by N junctions will be described. First, the structure will be described. This will be described with reference to FIGS. Here, FIG.
FIG. 1A is a plan view showing a part of the LED array 10 according to the first embodiment, and FIG. 1B is a sectional view taken along a line II in FIG.
Line cross-sectional view (however, a view showing the cut end; the same applies hereinafter), FIG. 1
1C is a sectional view taken along line II-II in FIG.
FIG. 2D is an enlarged cross-sectional view of a portion Q in FIG. However, in each cross-sectional view, hatching indicating a cross-section is partially omitted in order to avoid complicating the drawing (the same applies to other cross-sectional views below).

In FIG. 1, reference numeral 11 denotes a semiconductor substrate of the first conductivity type. In this embodiment, an N-type semiconductor underlayer 1 is used.
It is set to 1. In detail, N-type gallium arsenide (Ga
An As-type substrate 11a and an N-type gallium-arsenic-phosphorus (N-type GaAsP) layer 11b epitaxially grown on the N-type GaAs substrate 11a form an N-type semiconductor underlayer 11.
Is composed. Reference numeral 13 denotes P formed on the N-type semiconductor base 11 at a predetermined interval (an interval corresponding to the arrangement pitch of the LEDs).
Type GaAsP layer. 13a is a P-type GaAsP
The outline of the lateral diffusion region generated by the lateral diffusion of impurities when forming the layer 13 is shown. This P-type GaAsP layer 1
3 and the N-type GaAsP layer 11b constitute a PN junction 15 (see FIG. 1D). And this PN junction 15
Each of the individual light emitting units of the LED array 10 is configured. However, the PN junction 15 has a band-shaped shallow junction 15x whose junction depth is shallower than other portions and crosses the region where the PN junction is formed along the first direction.
Is provided. In particular, the PN junction 15 in this example passes through the center point of the region where the PN junction is formed and the direction in which the light emitting units are arranged (in this example, this direction corresponds to the first direction in the present invention. (D) is a PN having a strip-shaped shallow junction 15x along the direction perpendicular to the paper surface))).
It is a joint. Therefore, in the PN junction portion 15, the PN junction portions 15y on both sides of the strip-shaped shallow junction portion 15x.
Since a and 15yb are regions where the junction depth is deeper than the others, these regions 15ya, 15x and 15yb
PN junction 15 whose junction interface is uneven due to yb
Is configured.

In FIG. 1, reference numeral 17 denotes a P-side electrode, and 19 denotes an N-side electrode. The P-side electrode 17 is made of a corresponding P-type GaAs
It is provided on the P layer 13 such that one end is in contact therewith. Moreover,
The P-side electrode 17 is connected to the two regions 15ya and 15yb.
It is provided on the P-type GaAsP layer 13 so as to be in contact with both surfaces. The N-side electrode 19 is provided on the back surface of the semiconductor base 11.

In FIG. 1, reference numeral 21 denotes an insulating film. The insulating film 21 functions as a diffusion prevention mask for selectively introducing a P-type impurity into the N-type GaAsP layer 11b to form the P-type GaAsP layer 13 at the stage of manufacturing the LED array (for details, see FIG. L)
After the ED array is completed, the P-side electrode 17 and the N-type semiconductor base 11
And a film that electrically separates the above. This insulating film 21 is also referred to as a diffusion prevention mask 21 particularly in the description of the manufacturing method later. Also, in FIG.
What is indicated by 1 b is an opening provided in the insulating film 21. These openings 21a and 21b function as impurity introduction windows for forming the P-type GaAsP layer 13 at the stage of manufacturing the LED array.
It functions as a connection window between the side electrode 17 and the light emitting unit. In addition, an insulating film may be further provided on the insulating film 21 to further enhance the reliability of the insulating property between the P-side electrode 17 and the N-type semiconductor base 11.

The LED array 10 according to the first embodiment
In the figure, the light emitting section is constituted by the PN junction 15 which is partially a strip-shaped shallow junction 15x. The portion indicated by 15x in FIG. 1D as a conventional PN junction is 15ya,
Although it was almost a flat surface connected to 15yb,
In the present invention, it is convex. As a result, the bonding interface becomes uneven, so that the bonding area per unit flat area increases accordingly. Therefore, for example, if a light emission amount similar to that of the related art is obtained, the plane area of the light emitting unit can be smaller than that of the related art. For this reason, when forming the LED array, each light emitting section can be arranged at a higher density, and
A desired light emission amount can be obtained without increasing the dimension in the second direction.

Next, a preferred method of manufacturing the LED array according to the first embodiment will be described with reference to FIGS. Here, FIG. 2 and FIG.
FIG. 4 is a process diagram showing a state of a wafer in a main process in a manufacturing process by a partial cross section thereof. Just a partial cross section,
FIG. 2 is a cross-sectional view corresponding to a cutting position similar to FIG. 1C, and is a cross-sectional view of a portion where two rows of LED arrays are to be formed on a wafer. FIG. 4 is a plan view for further explaining the step of FIG. It should be noted that hatching shown in FIG. 4 indicates that the relevant area is clearly separated from other areas, and does not mean a cross section.

First, on the N-type semiconductor base 11, the base 11
A diffusion prevention mask 21 having an opening exposing a portion where a light emitting portion (PN junction) is to be formed is formed (FIG. 2).
(A)). However, the diffusion prevention mask 21 in this embodiment has two openings for forming one light emitting part.
This is a mask constituted by two independent openings 21a and 21b. Moreover, the diffusion prevention mask 21 is formed so that these two openings 21a and 21b are arranged in a direction (horizontal direction in FIG. 2A) orthogonal to the direction in which the light emitting units are arranged. Moreover, these two openings 21a,
The distance d between the ends of the sides 21b adjacent to each other (FIG. 2
(Refer to the enlarged view in (A)).
These openings 21a and 21b are arranged so as to fall within twice the lateral diffusion distance of the P-type impurity introduced into the N-type semiconductor base 11 through the base 21b. When the distance d is defined in this manner, the lateral diffusion regions of the P-type impurity diffusion regions formed below these openings 21a and 21b come into contact with each other in the subsequent impurity diffusion region formation step. Therefore, the semiconductor base portions below the openings 21a and 21b are respectively provided in the regions 15ya and 15ya shown in FIG.
5yb can be formed, and a band-shaped shallow junction 15x can be formed in the semiconductor base portion between the openings 21a and 21b, and these regions 15ya, 15yb, and 15x are continuous. In forming the diffusion prevention mask 21, an opening for forming one light emitting / receiving section is formed by one.
The openings 21a and 21b are preferably arranged such that the openings 21a and 21b are accommodated in a range smaller than the area that is expected when the openings 21a and 21b are configured with one opening. In a specific example, if it is assumed that one opening having an area A is used when forming one light emitting unit in the related art, in the present application, the openings 21a and 21b fall within a range smaller than the area A. , The openings 21a and 21b are arranged. This is because a PN junction having a smaller plane area can be formed as compared with the related art. Even so, already
As described with reference to (D), the PN according to the present invention is used.
This is because the bonding area 15s of the bonding portion 15 becomes uneven, so that the bonding area itself can be made equal to that of the conventional PN bonding portion. Of course, if the areas of the openings 21a and 21b are too small, a desired bonding area cannot be obtained no matter how much the bonding interface 15s of the PN junction 15 becomes uneven. This point is also taken into account. The diffusion prevention mask 21 can be formed by a known film forming method, for example, a film forming method such as a sputtering method or a CVD method, and a photolithography technique and an etching technique. The diffusion preventing mask 21 can be formed of a film selected from, for example, an alumina film, a silicon nitride film, a silicon oxide film, a PSG (Phospho-Silicate Glass) film, and the like. Further, the film thickness can be set to a suitable film thickness in the range of, for example, 50 to 500 nm.

Next, a diffusion control film 23 is formed on the N-type semiconductor base 11 on which the diffusion prevention mask 21 has been formed (FIG. 2A). The diffusion control film 23 can be formed by a known film forming method, for example, a sputtering method, a CVD method, or the like. The diffusion control film 23 includes, for example, an alumina film, a silicon nitride film,
It can be composed of a film selected from a silicon oxide film, a PSG (Phospho-Silicate Glass) film and the like. Further, the film thickness can be a suitable film thickness in the range of, for example, 10 to 300 nm. The diffusion control film 23 is used to reduce damage due to the introduction of impurities into the N-type semiconductor base during diffusion, and a process without using the diffusion control film is also possible.

Next, for example, zinc (Z
n) is introduced into the N-type GaAsP layer 11b through each opening of the diffusion control film 23 and the diffusion prevention mask 21. This impurity introduction is performed by, for example, a vapor phase diffusion method or a solid phase diffusion method. As a result, part of the N-type GaAsP layer 11b becomes P-type.
GaAsP layer 13. In the diffusion step, as described above, an opening for forming one light emitting portion is formed as two diffusion openings 21a and 2a as a diffusion prevention mask.
1D, the regions 15ya and 15yb shown in FIG. 1D can be formed in the N-type GaAsP layer below the openings 21a and 21b, respectively. A strip-shaped shallow junction 15x can be formed in the N-type GaAsP layer (FIG. 2B). Therefore, P described with reference to FIG.
The N junction 15 can be easily formed.

Next, the diffusion control film 23 is removed by a known etching method, for example, a wet etching method or a dry etching method (FIG. 2B).

Next, a P-side electrode 17 connected to the P-type GaAsP layer 13 is formed by a suitable film forming method such as an evaporation method or a sputtering method and a fine processing technique (FIG. 3).
(A)). The P-side electrode 17 of this embodiment is formed so as to pass from above the diffusion prevention mask 21 to the P-type GaAsP layer below the two openings 21a and 21b and then to reach the diffusion prevention mask 21 again. is there. This P-side electrode 1
7 is a P-type GaAsP under the two openings 21a and 21b.
It is preferable to form the layers so as to be in contact with the respective layers. PN
This is because electrical connection between each of the regions 15ya and 15yb in the joint 15 and the P-side electrode 17 is further ensured. However, the portion of the P-side electrode 17 formed on the diffusion prevention mask 21 may be only on the bonding pad side. The constituent material of the P-side electrode 17 is not particularly limited as long as an ohmic contact is made between the P-side electrode 17 and the P-type GaAsP layer 13. For example, aluminum is cited as a material forming the P-side electrode 17.

Next, an N-side electrode 19 is formed on the back surface of the N-type semiconductor base 11 (FIG. 3B). To improve the characteristics, the N-side electrode 1 is polished after polishing the back surface of the N-type semiconductor 11.
9 may be formed. Also, the P-side electrode 17 and the N-side electrode 1
The order of forming 9 may be reversed.

Further, a protective film may be formed on each light emitting section. After the impurity diffusion step is completed, the portion 31 of the diffusion mask 21 which corresponds to the planned dicing region is removed in order to further reduce the risk of the peeling of the diffusion prevention mask 21 occurring in the dicing step performed later. It is also possible. This embodiment shows an example (FIG. 3B). FIG. 4 is a plan view for making this easier to understand. A cross-sectional view along a line YY in FIG. 4A corresponds to FIG.

Next, the light emission characteristics and electrical characteristics of each light emitting unit are inspected by probing. Next, the individual LED arrays 10 are separated from the wafer using a dicing saw (FIG. 3C).

Thereafter, only non-defective LED arrays are selected on the basis of the inspection results obtained by the above-described probing, and are used, for example, for assembling an electrophotographic printer head.

In the above-described example, the mask opening for forming one light emitting section is shown as an example in which the openings are formed of two openings 21a and 21b. However, the mask opening may be formed of three or more openings. . When three or more (for example, n) openings for forming one light emitting portion are formed, a PN junction having n-1 strip-shaped shallow junctions 15x can be easily formed. . In the above example, two or more openings are arranged along a direction orthogonal to the direction in which the light emitting units are arranged.
Two or more openings may be arranged along the direction in which the light emitting units are arranged. In such a case, a strip-shaped shallow junction that crosses the region where the PN junction is formed along the direction orthogonal to the direction in which the light emitting units are arranged can be easily formed.

2. Second Embodiment Next, as a second embodiment, in a top-emission type LED array, each light-emitting portion is constituted by a PN junction having a cross-shaped shallow junction. An example of an LED array will be described. This will be described with reference to FIGS. Here, FIG. 5A is a plan view showing a part of the LED array 40 according to the second embodiment, FIG. 5B is a sectional view taken along line II in FIG. 5A, and FIG. C) is FIG.
FIG. 2A is a sectional view taken along line II-II in FIG.

The LED array 40 according to the second embodiment
The main differences from the first embodiment are the structure of the junction interface at the PN junction 41 and the arrangement of the openings in the insulating film 43 (particularly also referred to as a diffusion prevention mask in manufacturing). Thus, hereinafter, these differences will be mainly described.

Also in the second embodiment, the LED
The PN junction 41 constituting each light emitting unit of the array 40 is composed of an N-type GaAsP layer 11b and a P-type GaAsP layer 13. However, in the second embodiment, each of the PN junctions 41 has a junction depth smaller than that of the other portion and passes through the center point of the region where the PN junction is formed in the first direction and the PN junction. A shallow junction (cross-shaped shallow junction 41x; here, a cross-shaped shallow junction 41x) crossing the region in the direction of No. 2 is provided. Therefore, in the PN junction 41, four regions having junctions deeper than the others are formed around the cross-shaped shallow junction 41x. Three regions 41ya to 41yc of these four regions are shown in FIGS.

The LED array 40 according to the second embodiment
In the embodiment, each light-emitting portion is constituted by a PN junction portion 41 having a cross-shaped shallow junction portion 41x having a reduced junction depth.
Therefore, as compared with the first embodiment, the unevenness of the junction interface at the PN junction is further increased, so that the junction area per unit flat area can be made wider than that of the first embodiment.

Next, a preferred method of manufacturing the LED array according to the second embodiment will be described with reference to FIG.
This will be described with reference to FIG. Note that this manufacturing method is different from the manufacturing method described in the first embodiment in the arrangement of the openings in the diffusion prevention mask 43. When forming the diffusion prevention mask 43, four openings 43a to 43d are two-dimensionally arranged with one opening for forming one light emitting unit, and more specifically, the four openings 43a to 43d are formed in a substantially square shape. Deploy. 2 and 3 in the first embodiment.
The manufacturing procedure described with reference to FIG.

In forming the four openings 43a to 43d, the concept of forming the openings 21a and 21 in the first embodiment is applied to the interval and the area thereof.

According to the manufacturing method of the second embodiment, the PN junction 41 having the cross-shaped shallow junction 41x having a cross shape can be easily formed. Therefore, the LED array according to the second embodiment can be easily manufactured.

Here, an example in which a total of four openings are arranged two by two in the two-dimensional direction has been described, but the number of arrangements is not limited to this and may be larger. Also, the number of openings in each direction may be different.

3. Third Embodiment The first and second embodiments described above are examples in which the present invention is applied to a top emission type LED array. But,
The present invention can be applied to an edge emitting type LED array. First, as a third embodiment, an example in which the concept of the first embodiment is applied to an edge emission type will be described. This description will be made with reference to FIGS. here,
FIG. 6A is a plan view showing a part of the LED array 50 according to the third embodiment, and FIG.
FIG. 6C is a sectional view taken along line II-II in FIG.
It is a line sectional view.

In FIG. 6, reference numeral 50a denotes a light emitting end face.
Since the structure of the light emitting end face 50a has many parts related to the manufacturing method, it will be described later in the description of the manufacturing method. Also in the case of the LED array of the third embodiment, similar to the first embodiment,
Each PN junction constituting each light emitting unit is constituted by a PN junction 15 having a strip-shaped shallow junction 15x (see FIG. 6C). Therefore, as in the case of the first embodiment, the bonding area per unit flat area can be made wider than in the conventional case.

The characteristic process for manufacturing the LED array of the third embodiment is the same as that of the manufacturing method of the first and second embodiments. The point is that the opening for forming a portion is constituted by two or more openings. That is, the opening for forming one light emitting portion in the diffusion prevention mask 21 is
Also in the case of the embodiment, two openings 21a and 21b are formed in the same manner as in the manufacturing method of the first embodiment. However, the size of the opening corresponding to the light emitting end face side is taken into consideration so that a part of the PN junction formed under the semiconductor base below this is exposed to the end face. Otherwise, the manufacturing may be performed according to the manufacturing procedure described with reference to FIGS. However, a step for forming the light emitting end face is added. The added step will be briefly described below with reference to FIG.

First, each of the steps is performed in the same procedure as that described with reference to FIGS. 2A to 3B to remove a portion of the diffusion preventing film 21 corresponding to a dicing area. A body is obtained (FIG. 7 (A)).

Next, on the structure shown in FIG. 7A, an etching mask 53 for exposing only a dicing area 51 between two adjacent LED arrays in the structure is formed (FIG. 7 (A)). B)). This etching mask 51 can be composed of, for example, a photoresist.

Next, the semiconductor layer 1 is formed by a wet etching method using, for example, a phosphoric acid: hydrogen peroxide-based etching solution, a citric acid-based etching solution, a hydrofluoric acid-based etching solution, or a sulfuric acid-based etching solution.
The portion of 1b that is not covered with the etching mask 51 is etched. At the time of this etching, P-type GaAs
PN composed of a P layer 13 and an N-type GaAsP layer 11b
Etch to a depth beyond the junction interface. This is because the later dicing is started from below the PN junction interface. This is because it is possible to prevent the impact at the time of dicing from reaching the PN junction interface. By this etching, a concave portion 55 can be formed in a predetermined portion of the N-type GaAsp layer 11b. In addition, the light emitting end face 50a can be formed (FIG. 7C). In the example shown in FIG. 7C, a concave portion having a reverse tapered cross section is formed as the concave portion 55. Even if the concave portion 55 has a forward tapered cross section, the side wall is perpendicular to the semiconductor base surface. It may be a concave part. Further, the etching for forming the concave portion may be performed by a dry etching method.

Next, an N-side electrode 19 is formed on the back surface of the semiconductor underlayer 11.
(Not shown). Next, the light emission characteristics and electrical characteristics of each light emitting unit are inspected by probing. Next, the individual LED arrays are separated from the wafer using a dicing saw.

Thereafter, only non-defective LED arrays are selected based on the inspection results obtained by the above-described probing, and are used, for example, for assembling an electrophotographic printer head.

4. Fourth Embodiment As a fourth embodiment, an example will be described in which the idea of the second embodiment is applied to an edge emission type. This explanation is shown in FIG.
This is performed with reference to (A) to (C). Here, FIG. 8A is a plan view showing a part of the LED array 60 according to the fourth embodiment, FIG. 8B is a cross-sectional view taken along the line II in FIG. FIG. 8C is a sectional view taken along line II-II in FIG.

In FIG. 8, reference numeral 60a denotes a light emitting end face.
In the case of the LED array 60 according to the fourth embodiment, as in the second embodiment, each PN constituting each light-emitting unit is used.
The junction is a cross-shaped (here, cross-shaped) shallow junction 41x
PN junction 41 having Therefore, as in the case of the second embodiment, the bonding area per unit flat area can be made wider than in the conventional case.

The characteristic steps in manufacturing the LED array according to the fourth embodiment are the same as those in the manufacturing method according to the first and second embodiments. The point is that the formation opening is constituted by two or more openings. That is, the diffusion prevention mask 4
In the third embodiment, one opening for forming a light emitting unit in 3 is formed of four openings 43a to 43d in the same manner as in the manufacturing method of the second embodiment. However,
The size of the openings 43c and 43d corresponding to the light emitting end face side is taken into consideration so that a part of the PN junction formed below the semiconductor base is exposed to the end face. Otherwise, the manufacturing may be performed according to the manufacturing procedure described with reference to FIGS. 2 to 4 and FIG. 7, and a detailed description of the manufacturing method will be omitted here.

5. Fifth Embodiment Next, an LED array according to a fifth embodiment will be described. The fifth embodiment is an example of a particularly preferable structure and a manufacturing method thereof when the present invention is applied to an end face light emitting / receiving element array (here, an edge emitting type LED array).

First, the structure will be described with reference to FIGS. 9 (A) to 9 (C). Here, FIG. 9A is a plan view showing a part of the LED array 70 according to the fifth embodiment, and FIG.
9B is a cross-sectional view taken along the line II in FIG.
FIG. 10C is a sectional view taken along line II-II in FIG.

In FIG. 9, reference numeral 70a denotes a light emitting end face. Further, reference numeral 71 denotes an insulating film. The insulating film 71 is the same as the insulating film 21. At the stage of manufacturing the LED array, a P-type impurity is selectively introduced into the N-type GaAsP layer 11b to prevent diffusion for forming the P-type GaAsP layer 13. Functions as a mask, and after the LED array is completed, the P-side electrode 17
It functions as a film that electrically separates the N-type semiconductor base 11 from the N-type semiconductor base 11. This insulating film 71 is also referred to as a diffusion prevention mask 71 in the description of the manufacturing method in particular. Also,
In FIG. 9, reference numerals 71a to 71c denote openings provided in the insulating film 71. These openings 71
a to 71c are P-type G at the stage of manufacturing the LED array.
It functions as an impurity introduction window for forming the aAsP layer 13, and functions as a connection window between the P-side electrode 17 and the light emitting unit and a light extraction window after the LED array is completed.

The LED array 70 according to the fifth embodiment
The main difference from the first to fourth embodiments is that P
At the N junction 73. In the fifth embodiment, the junction interface is uneven and includes two or more convex portions, and the diffusion depths of these convex portions are different from each other.
Each of the light receiving and emitting sections is constituted by the joining section 73. More specifically, as shown in FIG. 9C, the region where the junction depth is shallower than other portions and where the PN junction is formed is aligned with the direction in which the light emitting portions are arranged (in FIG. 9C, Two shallow junctions 73xa, 7
3xb, and these shallow junctions 73xa, 73x
Each light receiving / emitting portion is constituted by a PN junction portion 73 having a different junction depth b. In the example shown in FIG. 9C, of the shallow junctions 73xa and 73xb, the shallow junction 73xb on the light emitting end face 70a side is a shallow junction having a junction depth of J2, and the light emitting end face 70a The junction 73xa apart from the junction is a shallow junction having a junction depth of J1 (J1 <J2).

The LED array 70 according to the fifth embodiment
According to the embodiment, since the light emitting portion is formed by the PN junction portion 73 having an uneven bonding interface, the bonding area per unit flat area is larger than that of the related art as in the first to fourth embodiments. it can. Further, in the case of the fifth embodiment,
Looking at the PN junction 73 from the light emitting end face, the shallow junction 73xa
And the junction interface at the shallow junction 73xb does not overlap. It is possible to extract light from the non-overlapping joint to the light emitting end face side,
An effect unique to the fifth embodiment, which is not the first to fourth embodiments, can be obtained.

A characteristic step in manufacturing the LED array of the fifth embodiment is that one opening for forming a light emitting portion in the diffusion prevention mask 71 is constituted by three openings 71a, 71b and 71c. In addition, the distance between the openings is different. More specifically, as shown in FIG. 9A, an opening for forming one light emitting unit in the diffusion prevention mask 71 is arranged along the direction perpendicular to the direction in which the light emitting units are arranged from the light emitting end face side. 71a, 71
It is constituted by three openings indicated by b and 71c.
Of course, the distance between the opening 71a and the opening 71b (the width of the insulating film remaining between the two openings) is d2, and the opening 71b
The distance between the opening and the opening 71c (the width of the insulating film remaining between the openings) is d1 (d1> d2). of course,
These d1 and d2 are selected from values within twice the lateral diffusion distance of the P-type impurity introduced into the semiconductor base through each of the adjacent openings. When d1 and d2 are set as described above, the lateral diffusion regions formed by the impurities passing through the openings 71b and 71c and diffused in the horizontal direction are in immediate contact with each other because the distance d1 is relatively large. Instead, the contact is made at a point where the junction depth of each lateral diffusion region is reduced. Therefore, the junction depth of the shallow junction 73xa generated in the semiconductor base between the openings 71b and 71c is smaller than the shallow junction 73xb generated in the semiconductor base between the openings 71a and 71b. Therefore, using this diffusion prevention mask 71, the PN junction 73 having shallow junctions 73xa and 73xb having different diffusion depths can be easily formed.

In the fifth embodiment, an example is shown in which an opening for forming one light emitting portion is formed by three openings. However, the opening may be formed by four or more openings. .

In each of the embodiments described above, examples have been described in which each invention of this application is applied to an LED array. However, these inventions relate to a light receiving element, a light receiving element array, and a method for manufacturing the light receiving element which constitute a light receiving section with a PN junction. In this case, a light-receiving element (light-receiving element array) having a larger light-receiving area per unit flat area than conventional can be realized, and such an element can be easily manufactured.

[0055]

As is clear from the above description, according to the light emitting / receiving element of the present invention, the light emitting / receiving section is constituted by the PN junction having the uneven junction interface. Further, according to the light emitting / receiving element array of the present invention, each light emitting / receiving section is constituted by the PN junction having the uneven bonding interface. Therefore, since the bonding area per unit flat area can be made larger than before, the light emitting and receiving element and the light receiving and emitting element array exhibiting a desired light emitting amount or light receiving amount even when the plane area of the light emitting and receiving section is narrower than before. I can do it. Therefore, it is possible to arrange the light receiving and emitting at a high density and to reduce the chip size.

According to the manufacturing method of the present invention,
An impurity diffusion region of a second conductivity type is formed in a semiconductor base of a first conductivity type by using a diffusion prevention mask in which an opening for forming one light emitting / receiving section is constituted by two or more openings. For this reason, the semiconductor base portion below each opening is provided with a second predetermined depth.
A conductive impurity diffusion region can be formed, and a shallow junction caused by lateral diffusion can be formed in a semiconductor base portion between the openings. Therefore, a PN junction having an uneven junction interface can be easily formed, so that the light emitting and receiving element and the light emitting and receiving element array of this application can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment, and is a plan view and a cross-sectional view of a main part of an LED array according to the first embodiment.

FIG. 2 is a process chart for explaining a manufacturing method.

FIG. 3 is a process drawing following FIG. 2 for explaining a manufacturing method;

FIG. 4 is a process drawing following FIG. 3 for describing a manufacturing method;

FIG. 5 is an explanatory diagram of the second embodiment, and is a plan view and a cross-sectional view of main parts of an LED array according to the second embodiment.

FIG. 6 is an explanatory diagram of the third embodiment, and is a plan view and a cross-sectional view of a main part of an LED array according to the third embodiment.

FIG. 7 is an explanatory diagram of a manufacturing process added in the case of an edge emission type.

FIG. 8 is an explanatory diagram of the fourth embodiment, and is a plan view and a cross-sectional view of a main part of an LED array according to the fourth embodiment.

FIG. 9 is an explanatory diagram of the fifth embodiment, and is a plan view and a cross-sectional view of a main part of the LED array according to the fifth embodiment.

[Explanation of symbols]

10: Light receiving / emitting element array (LED array) according to the first embodiment 11: First conductive type semiconductor base 11a: N-type GaAs substrate 11b: N-type GaAsP layer 13: Second conductive type impurity diffusion region (P-type GaAsP) 13a: contour (outline of P-type GaAsP layer) 15: PN junction 15s: junction interface 15x: strip-shaped shallow junction 15ya, 15yb: region where junction depth is deep 17: P-side electrode 19: N Side electrode 21: Insulating film (also referred to as diffusion prevention mask) 21a, 21b: Opening 23: Diffusion control film 31: Planned dicing area 40: Light receiving / emitting element array (LED in the second embodiment)
Array) 41: PN junction 41s: junction interface 41x: cross-shaped shallow junction 41ya to 41yc: region with deep junction 43: insulating film (also referred to as diffusion prevention mask) 43a to 43d: opening 50 : Light receiving / emitting element array (LED according to third embodiment)
Array: 50a: Light-emitting end face 51: Planned dicing area 53: Etching mask 60: Light-receiving / light-emitting element array (LED in the fourth embodiment)
Array: 60a: Light-emitting end face 70: Light-receiving and light-emitting element array (LED in the fifth embodiment)
(Array) 70a: Light-emitting end face 71: Insulating film (also referred to as diffusion prevention mask) 73: PN having two or more shallow junctions having different junction depths
Junction 73xa, 73xb: Strip-shaped shallow junction d1, d2: Spacing between openings J1, J2: Junction depth

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yukio Nakamura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (12)

[Claims] 1. A light emitting / receiving element, wherein a light receiving / emitting unit is constituted by a PN junction having a concave / convex junction interface. 2. A PN having at least one band-shaped shallow junction having a junction depth shallower than other portions and crossing a region where a PN junction is formed along a first direction.
A light emitting / receiving element, wherein a light emitting / receiving section is constituted by the joining portion. 3. An intersection in which the junction depth is shallower than other portions and crosses the region where the PN junction is formed in a first direction and a second direction intersecting the first direction. A light emitting / receiving element comprising a PN junction having at least one shallow junction in a shape of a light. 4. A light-emitting / receiving section is formed by a PN junction having a junction interface that is uneven and includes two or more projections, and of which the diffusion depths of the projections are different from each other. A light emitting / receiving element of an end face light emitting / receiving type. 5. A semiconductor device comprising two or more strip-shaped shallow junctions having a junction depth shallower than other portions and traversing a region in which a PN junction is formed along a first direction. A light emitting / receiving element of an end face light emitting / receiving type, wherein a light receiving / emitting section is constituted by PN junctions having different junction depths of the junctions. 6. A light emitting / receiving element array having a large number of light receiving / emitting sections in an array, wherein each of the light receiving / emitting sections is constituted by the PN junction according to any one of claims 1 to 3. A light receiving / emitting element array characterized by the above-mentioned. 7. An end face light receiving / emitting type light emitting / receiving element array having a large number of light emitting / receiving sections in an array, wherein each of the light receiving / emitting sections is constituted by the PN junction according to claim 4 or 5. A light emitting / receiving element array of an end face light receiving / emitting type. 8. A step of forming an anti-diffusion mask having an opening exposing a region where a light emitting / receiving section is to be formed in the semiconductor base on the semiconductor base of the first conductivity type; Forming a second conductivity type impurity diffusion region in the semiconductor base by introducing a two conductivity type impurity to obtain a PN junction for forming a light emitting / receiving section. A method for manufacturing a light emitting / receiving element, wherein a diffusion prevention mask in which the opening for forming one light emitting / receiving section is formed of two or more openings is used as the prevention mask. 9. The method for manufacturing a light emitting / receiving element according to claim 8, wherein a diffusion prevention mask in which the two or more openings are arranged in a one-dimensional direction is used as the diffusion prevention mask. A method for manufacturing a light receiving / emitting element. 10. The method for manufacturing a light emitting / receiving element according to claim 8, wherein the two or more openings are three or more openings, and the three or more openings are two-dimensionally arranged as the diffusion prevention mask. A method for manufacturing a light emitting / receiving element, comprising using a diffusion prevention mask described above. 11. The method for manufacturing a light receiving / emitting element according to claim 8, wherein the two or more openings are three or more openings as the diffusion prevention mask, and the three or more openings are one-dimensionally arranged. A method for manufacturing a light emitting / receiving element, wherein a diffusion preventing mask arranged with a different interval between openings is used. 12. The method for manufacturing a light emitting and receiving element according to claim 8, wherein a distance between ends of the two or more openings that are close to each other is introduced into the semiconductor base through these openings. A method for manufacturing a light emitting / receiving element, characterized in that these openings are arranged so as to be within twice the lateral diffusion distance of a second conductivity type impurity.