CN105529303A - Method for removing bubble region in bonding process - Google Patents
Method for removing bubble region in bonding process Download PDFInfo
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- CN105529303A CN105529303A CN201510946206.8A CN201510946206A CN105529303A CN 105529303 A CN105529303 A CN 105529303A CN 201510946206 A CN201510946206 A CN 201510946206A CN 105529303 A CN105529303 A CN 105529303A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
The invention relates to a method for removing a bubble region in a bonding process. The method comprises the following steps of (a) bonding and fixing a surface wafer and a substrate wafer; (b) determining the position of the bubble region; (c) thinning the back surface of the surface wafer to a required thickness so as to obtain a thin wafer; (d) arranging cutting line mask layer on the above thin wafer, and obtaining a cutting line window passing through the cutting line mask layer, wherein the cutting line window is at least arranged above a cutting line corresponding to an outer ring of the bubble region; (e) etching the cutting line corresponding to the outer ring of the bubble region by using the above cutting line window to remove the cutting line corresponding to the outer ring of the bubble region; and (f) removing the above cutting line mask layer, and removing the thin wafer corresponding to the bubble region after positioning. The method is simple in process step, is compatible with the traditional process step, is wide in application range and is safe and reliable, the bubble region in the bonding process can be effectively removed, and the utilization rate and the finished rate of the wafer are improved.
Description
Technical field
The present invention relates to a kind of process, remove the method for bubble area in especially a kind of bonding technology, belong to the technical field of semiconductor.
Background technology
Along with the development of semiconductor technology, the characteristic size of integrated circuit constantly reduces, and device interconnection density improves constantly.So wafer-level packaging (WaferLevelPackage, WLP) replaces wire bond package gradually becomes a kind of comparatively conventional method for packing.Wafer-level packaging (WaferLevelPackaging, WLP) technology is that after carrying out packaging and testing to full wafer wafer, cutting obtains the technology of single finished product chip again, chip size after encapsulation and nude film completely the same, complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.
Wafer-level packaging adopts MEMS or CISBSI technique all will use bonding, comprises permanent bonding and interim bonding etc.Permanent bonding technology is generally divided into the techniques such as anode linkage, metal melting bonding, silica Direct Bonding, and interim bonding then has zone-bond(wafer central edge glue bonding) bonding, organic gel thermal bonding etc.Carry out thinning to wafer after bonding, then carry out conventional semiconductor technology, comprise photoetching, etching, thin film deposition etc.
But in the engineering of bonding, because technique is unstable or crystal column surface is unclean, easily cause wafer bonding face to there is bubble.Once there be bubble to be formed, then in follow-up wafer is thinning, this region will form projection, and is very easy to break, and even whole wafer cracked, pollutes board, also result in scrapping of wafer.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of method removing bubble area in bonding technology is provided, its processing step is simple, mutually compatible with existing processing step, effectively can remove the bubble area in bonding technology, improve utilance and the rate of finished products of wafer, wide accommodation, safe and reliable.
According to technical scheme provided by the invention, remove the method for bubble area in a kind of bonding technology, described bubble area minimizing technology comprises the steps:
A, provide required substrate wafer and surperficial wafer, and described surperficial wafer and substrate wafer are carried out bonding fix;
Surperficial wafer after b, para-linkage and substrate wafer detect, to determine the position of bubble area;
C, the thickness extremely required to the thinning back side of above-mentioned surperficial wafer, to obtain the thin wafer be positioned in substrate wafer, in described thin wafer, some chip wafers are separated by Cutting Road;
D, Cutting Road mask layer is set on above-mentioned thin wafer, and described Cutting Road mask layer is optionally sheltered and etched, to obtain the Cutting Road window of through Cutting Road mask layer, described Cutting Road window is at least distributed in above Cutting Road corresponding to bubble area outer ring;
E, the above-mentioned Cutting Road window Cutting Road corresponding to bubble area outer ring is utilized to etch, to remove Cutting Road corresponding to bubble area outer ring;
F, remove above-mentioned Cutting Road mask layer, and remove the thin wafer corresponding with bubble area after positioning.
The mode that described substrate wafer and surperficial wafer bonding are fixed comprises metal melting bonding, Si-Si bonding or silica bonding.
In described step b, infrared detection or C-SAM scanning is utilized to determine the position of bubble area.
Described Cutting Road mask layer comprises photoresist.
Advantage of the present invention: the surperficial wafer after para-linkage and substrate wafer detect determines bubble area, effects on surface wafer carries out thinning, obtain thin wafer, thin wafer arranges Cutting Road mask layer and required Cutting Road window, utilize Cutting Road window can remove Cutting Road corresponding to bubble area outer ring, thus effectively can remove bubble area, processing step is simple, mutually compatible with existing processing step, improves utilance and the rate of finished products of wafer, wide accommodation, safe and reliable.
Accompanying drawing explanation
Fig. 1 ~ Fig. 7 is the cutaway view of a kind of embodiment of the present invention, wherein,
Fig. 1 is the schematic diagram before substrate wafer of the present invention and surperficial wafer carry out bonding.
Fig. 2 is the schematic diagram after substrate wafer of the present invention and surperficial wafer bonding.
Fig. 3 is the distribution schematic diagram of bubble area of the present invention.
Fig. 4 is the schematic diagram after effects on surface wafer of the present invention carries out thinning back side.
Fig. 5 is that the present invention arranges the first mask layer and schematic diagram after obtaining the first Cutting Road window on thin wafer.
Fig. 6 is the schematic diagram after the present invention removes Cutting Road.
Fig. 7 is the schematic diagram after the present invention removes bubble area.
Fig. 8 ~ Figure 10 is the cutaway view of the another kind of embodiment of the present invention, wherein
Fig. 8 is that the present invention arranges the second Cutting Road mask layer and schematic diagram after obtaining the second Cutting Road window on thin wafer.
Fig. 9 is the schematic diagram after the present invention removes Cutting Road.
Figure 10 is the schematic diagram that the present invention removes bubble area.
Description of reference numerals: 1-substrate wafer, 2-surface wafer, 3-bubble area, 4-Cutting Road, the thin wafer of 5-, 6-first mask layer, 7-first Cutting Road window, 8-first cuts road junction, 9-first removes groove, 10-second mask layer, 11-second Cutting Road window, 12-second cuts road junction and 13-second removes groove.
Embodiment
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below.Apparently, the accompanying drawing in the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Below in conjunction with concrete drawings and Examples, the invention will be further described.
In order to effectively remove the bubble area in bonding technology, improve utilance and the rate of finished products of wafer, bubble area minimizing technology of the present invention comprises the steps:
A, provide required substrate wafer 1 and surperficial wafer 2, and described surperficial wafer 2 is carried out bonding with substrate wafer 1 fix;
As depicted in figs. 1 and 2, the mode that described substrate wafer 1 is fixing with surperficial wafer 2 bonding comprises metal melting bonding, Si-Si bonding or silica bonding.Surface wafer 2 can, for the product wafer prepared through semiconductor technology, also can be nude film, and the process that substrate wafer 1 and surperficial wafer 2 bonding are fixed, known by the art personnel, repeats no more herein.
Surperficial wafer 2 after b, para-linkage and substrate wafer 1 detect, to determine the position of bubble area 3;
As shown in Figure 3, infrared detection or C-SAM(ultrasound examination is utilized) scan the position determining bubble area 3.Usually, bubble area 3 is positioned between the interface of the Contact of surperficial wafer 2 and substrate wafer 1, utilizes infrared detection or C-SAM scanning to determine that the process of bubble area 3 is known by the art personnel, repeats no more herein.
C, the thickness extremely required to the thinning back side of above-mentioned surperficial wafer 2, to obtain the thin wafer 5 be positioned in substrate wafer 1, in described thin wafer 5, some chip wafers are separated by Cutting Road 4;
As shown in Figure 4, the back side of effects on surface wafer 2 can adopt directly grinding thinning, also can adopt wet method or dry etching thinning, or first grinding is thinned to setting thickness, use etching technics thinning again, concrete thinning mode can be selected as required, be specially known by the art personnel, repeat no more herein.Usually, after effects on surface wafer 2 is thinning, the thickness of thin wafer 5 is in 100nm ~ 300 μm.For the surperficial wafer 2 of product wafer, in thin wafer 5, there is Cutting Road 4, after being cut thin wafer 5 by Cutting Road 4, obtain required chip.After obtaining thin wafer 5 after surperficial wafer 2 is thinning, Cutting Road 4 can be made exposed.
D, Cutting Road mask layer is set on above-mentioned thin wafer 5, and described Cutting Road mask layer is optionally sheltered and etched, to obtain the Cutting Road window of through Cutting Road mask layer, described Cutting Road window is at least distributed in above Cutting Road 4 corresponding to bubble area 3 outer ring;
Usually, Cutting Road mask layer can adopt photoresist.As shown in Figure 5 and Figure 8, in the specific implementation, the position distribution of Cutting Road window can be selected as required, under regard to Cutting Road window particular location distribution be described in detail.
As shown in Figure 5, thin wafer 5 applies the first mask layer 6, described first mask layer 6 is photoresist layer, by optionally sheltering and etching the first mask layer 6, obtain the first Cutting Road window 7 of through first mask layer 6, wherein, described first Cutting Road window 7 is distributed in the top of all Cutting Roads 4, namely all Cutting Roads 4 of below can be made exposed by the first Cutting Road window 7.
As shown in Figure 8, thin wafer 5 applies the second mask layer 10, described second mask layer 10 is also photoresist layer.By sheltering the selectivity of the second mask layer 10 and etch, obtain the second Cutting Road window 11 of through second mask layer 10, wherein, described second Cutting Road window 11 is only positioned at above Cutting Road 4 corresponding to bubble area 3 outer ring, corresponding Cutting Road 4 can be made exposed by the second Cutting Road window 11.
E, the Cutting Road 4 utilizing above-mentioned Cutting Road window corresponding to bubble area 3 outer ring etch, to remove Cutting Road 4 corresponding to bubble area 3 outer ring;
In the embodiment of the present invention, laser beam or electron beam can be adopted to etch Cutting Road 4.When surperficial wafer 2 is nude film, the Cutting Road 4 of described bubble area 3 outer ring is the unit area of corresponding definition, is specially known by the art personnel.When the distributing position of Cutting Road window is different, different Cutting Roads 4 can be removed.Particularly, as shown in Figure 6, because the first Cutting Road window 8 is positioned at the top of all Cutting Roads 4, when utilizing the first Cutting Road window 7 to etch, all Cutting Roads 4 can be removed, after Cutting Road 4 is removed, the first cutting road junction 8, cutting road junction 8, first can be obtained corresponding chip in thin wafer 5 can be made to be separated from each other.
As shown in Figure 9, because the second Cutting Road window 11 is only positioned at above the Cutting Road 4 of bubble area 3 outer ring, when utilizing the second Cutting Road window 11 to etch, the second cutting road junction 12 can be obtained, the chip area corresponding with bubble area 3 can be made to be separated by the second cutting road junction 12.
F, remove above-mentioned Cutting Road mask layer, and remove the thin wafer 5 corresponding with bubble area 3 after positioning.
In the embodiment of the present invention, remove the first above-mentioned mask layer 6 or the second mask layer 10 by routine techniques means.After removal first mask layer 6 or the second mask layer 10, because the Cutting Road 4 of bubble area 3 outer ring is removed, due to the existence of bubble area 3, thin wafer 5 region corresponding with bubble area 3 is made to locate removal, location is removed and can be adopted dry etching or wet etching that thin wafer 5 region corresponding for bubble area 3 is removed, certainly, also mode can be adopted during concrete enforcement to position removal, process is removed known by the art personnel in concrete location, repeats no more herein.After location is removed, the first removal groove 9 or second can be obtained and remove groove 13, respectively as shown in Fig. 7 or Figure 10.
In addition, the thin wafer 5 eliminating bubble area 3 can continue to do reduction process, or directly does follow-up semiconductor technology, and removing first the material can filling out colloid class in groove 9 or the second removal groove 13 and make it smooth, also can be exposed.
Surperficial wafer 2 after para-linkage of the present invention and substrate wafer 1 detect determines bubble area 3, effects on surface wafer 2 carries out thinning, obtain thin wafer 5, thin wafer 5 arranges Cutting Road mask layer and required Cutting Road window, utilize Cutting Road window can remove Cutting Road 4 corresponding to bubble area 3 outer ring, thus can effectively remove bubble area 3, processing step is simple, mutually compatible with existing processing step, improves utilance and the rate of finished products of wafer, wide accommodation, safe and reliable.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (4)
1. remove a method for bubble area in bonding technology, it is characterized in that, described bubble area minimizing technology comprises the steps:
(a), required substrate wafer (1) and surperficial wafer (2) are provided, and described surperficial wafer (2) and substrate wafer (1) carried out bonding fix;
B the surperficial wafer (2) after (), para-linkage and substrate wafer (1) detect, to determine the position of bubble area (3);
(c), the thickness extremely required to the thinning back side of above-mentioned surperficial wafer (2), to obtain the thin wafer (5) be positioned in substrate wafer (1), in described thin wafer (5), some chip wafers are separated by Cutting Road (4);
(d), on above-mentioned thin wafer (5), Cutting Road mask layer is set, and described Cutting Road mask layer is optionally sheltered and etched, to obtain the Cutting Road window of through Cutting Road mask layer, described Cutting Road window is at least distributed in Cutting Road (4) top corresponding to bubble area (3) outer ring;
E (), the Cutting Road (4) utilizing above-mentioned Cutting Road window corresponding to bubble area (3) outer ring etch, to remove Cutting Road (4) corresponding to bubble area (3) outer ring;
(f), remove above-mentioned Cutting Road mask layer, and remove the thin wafer (5) corresponding with bubble area (3) after positioning.
2. remove the method for bubble area in bonding technology according to claim 1, it is characterized in that: the mode that described substrate wafer (1) is fixed with surperficial wafer (2) bonding comprises metal melting bonding, Si-Si bonding or silica bonding.
3. remove the method for bubble area in bonding technology according to claim 1, it is characterized in that: in described step (b), utilize infrared detection or C-SAM scanning to determine the position of bubble area (3).
4. remove the method for bubble area in bonding technology according to claim 1, it is characterized in that: described Cutting Road mask layer comprises photoresist.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510946206.8A CN105529303B (en) | 2015-12-16 | 2015-12-16 | The method that bubble area is removed in bonding technology |
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| CN201510946206.8A CN105529303B (en) | 2015-12-16 | 2015-12-16 | The method that bubble area is removed in bonding technology |
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| CN105529303A true CN105529303A (en) | 2016-04-27 |
| CN105529303B CN105529303B (en) | 2018-07-06 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712875A (en) * | 2018-12-29 | 2019-05-03 | 上海华力微电子有限公司 | Wafer direct bonding method |
| CN110289209A (en) * | 2019-07-05 | 2019-09-27 | 长春长光圆辰微电子技术有限公司 | A kind of processing method of SOI wafer |
| CN110349877A (en) * | 2019-07-12 | 2019-10-18 | 芯盟科技有限公司 | Detect the method and wafer bonding board of wafer bonding intensity |
| CN110571163A (en) * | 2019-09-18 | 2019-12-13 | 武汉新芯集成电路制造有限公司 | Bubble defect treatment method for wafer bonding process |
| CN112538610A (en) * | 2020-12-07 | 2021-03-23 | 珠海光库科技股份有限公司 | Lithium niobate single crystal thin film chip and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428403C (en) * | 2005-12-28 | 2008-10-22 | 中国科学院半导体研究所 | Optimization method of the experimental parameters in the direct key bonding process of the wafer |
| CN103466541B (en) * | 2013-09-12 | 2016-01-27 | 上海矽睿科技有限公司 | Wafer-level packaging method and wafer |
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2015
- 2015-12-16 CN CN201510946206.8A patent/CN105529303B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712875A (en) * | 2018-12-29 | 2019-05-03 | 上海华力微电子有限公司 | Wafer direct bonding method |
| CN109712875B (en) * | 2018-12-29 | 2020-11-20 | 上海华力微电子有限公司 | Wafer direct bonding method |
| CN110289209A (en) * | 2019-07-05 | 2019-09-27 | 长春长光圆辰微电子技术有限公司 | A kind of processing method of SOI wafer |
| CN110349877A (en) * | 2019-07-12 | 2019-10-18 | 芯盟科技有限公司 | Detect the method and wafer bonding board of wafer bonding intensity |
| CN110571163A (en) * | 2019-09-18 | 2019-12-13 | 武汉新芯集成电路制造有限公司 | Bubble defect treatment method for wafer bonding process |
| CN110571163B (en) * | 2019-09-18 | 2021-12-03 | 武汉新芯集成电路制造有限公司 | Bubble defect treatment method for wafer bonding process |
| CN112538610A (en) * | 2020-12-07 | 2021-03-23 | 珠海光库科技股份有限公司 | Lithium niobate single crystal thin film chip and manufacturing method thereof |
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| CN105529303B (en) | 2018-07-06 |
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