TW202238834A - 半導體裝置的形成方法 - Google Patents
半導體裝置的形成方法 Download PDFInfo
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- 238000012545 processing Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
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- HVEIXSLGUCQTMP-UHFFFAOYSA-N selenium(2-);zirconium(4+) Chemical compound [Se-2].[Se-2].[Zr+4] HVEIXSLGUCQTMP-UHFFFAOYSA-N 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
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- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- HQZPMWBCDLCGCL-UHFFFAOYSA-N tantalum telluride Chemical compound [Te]=[Ta]=[Te] HQZPMWBCDLCGCL-UHFFFAOYSA-N 0.000 description 1
- OEIMLTQPLAGXMX-UHFFFAOYSA-I tantalum(v) chloride Chemical compound Cl[Ta](Cl)(Cl)(Cl)Cl OEIMLTQPLAGXMX-UHFFFAOYSA-I 0.000 description 1
- CXXKWLMXEDWEJW-UHFFFAOYSA-N tellanylidenecobalt Chemical compound [Te]=[Co] CXXKWLMXEDWEJW-UHFFFAOYSA-N 0.000 description 1
- CFJRPNFOLVDFMJ-UHFFFAOYSA-N titanium disulfide Chemical compound S=[Ti]=S CFJRPNFOLVDFMJ-UHFFFAOYSA-N 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
- KPGXUAIFQMJJFB-UHFFFAOYSA-H tungsten hexachloride Chemical compound Cl[W](Cl)(Cl)(Cl)(Cl)Cl KPGXUAIFQMJJFB-UHFFFAOYSA-H 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Images
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Abstract
本揭露描述了一種半導體裝置和用於形成半導體裝置的方法。上述方法包括在基板上形成鰭式結構,在鰭式結構上形成閘極結構,以及在未被閘極結構覆蓋的鰭式結構上形成源極/汲極(S/D)區。上述方法還包括在S/D區上形成接觸結構。形成接觸結構的步驟包括在S/D區上形成過渡金屬硫族化合物(transition metal chalcogenide; TMC)層,以及在TMC層上形成接觸插塞。
Description
本揭露實施例是關於半導體裝置,特別是關於具有接觸結構的半導體裝置及其形成方法。
積體電路(integrated circuits ; IC)的性能可能取決於觸件、導孔和互連件的電阻。由於高肖特基能障高度(Schottky barrier height ; SBH),接觸電阻(Contact resistance)可能受到源極/汲極(source/drain ; S/D)區和S/D觸點之間接觸電阻率(contact resistivity)的影響。接觸電阻可進一步受襯層電阻率影響且可自不同層間的表面散射。金屬矽化物可以在S/D區和S/D觸點之間形成,然而以製造的角度而言,難以在n型S/D區上及在p型S/D區上找到熱穩定的n型矽化物及p型矽化物。
本發明實施例提供一種半導體裝置的形成方法,包括:在基板上形成鰭式結構;在鰭式結構上形成閘極結構;在未被閘極結構覆蓋的鰭式結構上形成源極/汲極(source/drain; S/D)區;在S/D區上形成接觸結構,其中形成接觸結構的步驟包括:在S/D區上形成過渡金屬硫族化合物(transition metal chalcogenide; TMC)層;以及在TMC層上形成接觸插塞。
本發明實施例提供一種半導體裝置的形成方法,包括:在基板上形成鰭式結構;在鰭式結構上形成閘極結構及源極/汲極(S/D)區;在S/D區上形成接觸結構,其中形成接觸結構的步驟包括:在S/D區上形成接觸開口; 在接觸開口內沉積金屬層;對金屬層使用硫族元素材料進行電漿製程;以及在接觸開口內形成接觸插塞。
本發明實施例提供一種半導體裝置,包括:基板;鰭式結構,設置於基板上;閘極結構,設置於鰭式結構上;源極/汲極(S/D)區,設置於鰭式結構未被閘極結構覆蓋的多個部分上;以及接觸結構,設置於S/D區上,其中接觸結構包括:過渡金屬硫族化合物(TMC)層,設置於S/D區上;以及接觸插塞,設置於TMC層上。
以下配合所附圖式詳述本揭露各實施例,以便本揭露所屬技術領域中具有通常知識者可製作及使用本揭露。在本揭露所屬技術領域中具有通常知識者應理解,他們能在閱讀本揭露後,在不脫離本揭露的範圍下將此處描述的示例進行各種改變或修改。因此,本揭露不限於在此描述和說明的示例性實施例和應用。另外,本文揭露的方法中,步驟的特定順序及/或層級僅為示例性方法。根據設計偏好,可以在本揭露的範圍內重新設置所揭露的方法或製程中步驟的特定順序或層級。因此,所屬技術領域中具有通常知識者將理解,本文揭露的方法和技術以示例順序呈現各種步驟或動作,除非另有明示,否則本揭露內容不限於所呈現的特定順序或層級。
再者,其中可能用到與空間相對用詞,例如「在…之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作程序中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
需要注意的是,說明書中提到的 「一個實施例」、「一實施例」、「一個示例性實施例」、「示例性」等表示所描述的實施例可以包括特定的部件、結構或特性,但每個實施例不一定包括特定的部件、結構或特性。此外,這樣的詞組不一定指的是同一個實施例。此外,當一個特定的部件、結構或特性被描述為與一個實施例相關時,在所屬技術領域具有通常知識者的知識範圍內,無論是否明確描述,都會在與其他實施例相關時利用這種部件、結構或特性。
應理解的是,此處的詞組或術語是為了描述而非限制性的,因此本說明書的術語或詞組應由所屬技術領域具有通常知識者根據此處的教示來進行解釋。
在一些實施例中,術語「大約」和 「大抵上」可以表示表示給定數量的值在該值的5% 範圍內變化(例如,該值的±1%、±2%、±3%、±4%、±5%)。這些數值僅為示例,並非限制性的。術語「大約」和 「大抵上」可以指相關技術的熟練人員根據本文的教示所解釋的數值百分比。
本文揭露的鰭式結構可以透過任何合適的方法進行圖案化。例如,可使用一種或多種光學微影製程對鰭式結構進行圖案化,包括雙重圖案化或多重圖案化製程。雙重圖案或多重圖案製程可以結合光學微影和自對準製程,允許創建的圖案具有如間距小於使用單一、直接的光學微影製程可獲得的間距。例如,在基板上方形成犧牲層,並使用微影製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。之後移除犧牲層,然後可以使用剩餘的間隔物作為遮罩以圖案化鰭片。
除非另有說明,否則具有相同註釋的圖在第1A-1C圖、第2A-2I圖、第4-5圖、第6A-6B圖、第7A-7C圖、第8A-8B圖、第9A-9C圖、第10A-10B圖和第11A-12D圖中彼此通用。
源/汲(S/D)極區和S/D接觸結構之間的高肖特基能障高度(SBH)導致了高接觸電阻。其他因素包括襯層電阻率和自不同層間的表面散射。金屬矽化物可以在S/D區和S/D接觸結構之間形成,以降低SBH。然而,以製造的角度而言,難以在n型S/D區上及在p型S/D區上找到熱穩定的n型矽化物及p型矽化物。
本揭露內容提供了具有S/D接觸結構的示例性半導體裝置(例如,finFETs(fin field-effect transistors)、全繞式閘極FETs (gate-all-around field-effect transistors) ; GAA及/或MOSFETs(metal-oxide-semiconductor field-effect transistors)),其具有SBH降低層以實現低接觸電阻,以及形成這種半導體裝置的方法。在一些實施例中,SBH降低層設置在S/D區和S/D接觸插塞之間,以降低接觸電阻,並消除金屬矽化物層的形成,以減少S/D區的材料消耗。在一些實施例中,SBH降低層包括過渡金屬硫族化合物(TMC)材料。
在一些實施例中,SBH降低層可以透過在S/D區上沉積硫族元素材料層(chalcogen material),例如硫(S)、 硒(Se)或碲(Te),然後沉積過渡金屬層,例如鈦(Ti)、鎢(W)或鉬(Mo)形成。這兩層可以一起擴散並形成SBH降低層的TMC材料。TMC層可以產生從S/D區到S/D接觸插塞的半導體-半金屬-金屬的梯度轉換,從而降低SBH,即SBH調諧(SBH tuning)。
在一些實施例中,SBH降低層可以透過在S/D區沉積過渡金屬層,例如Ti、W或 Mo,然後用硫族元素材料,例如硫或硒基氣體處理過渡金屬層來形成。在這兩種形成SBH降低層的方法中,在S/D區和SBH降低層間的介面上的S或Se終端鍵可以減少帶隙和降低電阻率。另一方面,在S/D接觸插塞和SBH降低層之間的過渡金屬終端鍵(terminated bonds)可以降低接觸電阻率。
在一些實施例中,可以在S/D接觸插塞的側壁上形成襯層。在一些實施例中,襯層可以在SBH降低層上形成。襯層可具有導電材料,例如,硫化鈦(TiS
2)。襯層可以減少彈性散射並改善導電性。透過使用SBH降低層、更薄和更高導電性的襯墊,以及在一些實施例中使用金屬矽化物,可以降低接觸電阻。SBH降低層的製造過程可以使用低溫催化劑輔助生長,這減少了製造過程中對於實現低接觸電阻的挑戰。
第1A圖是根據一些實施例,繪示出FET 100之等角視圖。在一些實施例中,FET 100可以代表finFET 100或GAA FET 100。在一些實施例中,FET 100可以代表n型FET 100(NFET 100)或p型FET 100(PFET 100),除非另有提及,否則關於FET 100的討論同時適用於NFET 100和PFET 100。第1B圖及第1C圖是根據一些實施例,繪示出鰭式結構上的S/D區之剖面圖。第2A、2C、2E、2G和2I圖是繪示出FET100沿A-A線之剖面圖,為簡單起見,第1A圖沒有示出額外的結構。第2B、2D、2F和2H圖繪示出FET100沿B-B線之剖面圖,為簡單起見,第1A圖沒有示出額外的結構。除非另有提及,否則對於第1A-1C圖及第2A-2I圖中的元件使用相同的標註所作的討論可彼此相互應用。
FET 100可以包括設置在鰭式結構106上閘極結構112A-112C陣列和設置在未被閘極結構112A-112C覆蓋的鰭式結構106部分上的S/D區陣列(在第1A圖中僅可見一個S/D區110A;在第2A、2C、2E、2G和2I圖中可見S/D區110B)。FET 100可以進一步包括閘極間隔物114和淺溝槽隔離(shallow trench isolation ; STI)區116。FET 100可以進一步包括蝕刻停止層(etch stop layer; ESL)117,和層間介電(interlayer dielectric; ILD)層118。ILD層118可以設置在ESLs 117上。在一些實施例中,閘極間隔物114、STI區116、ESLs 117A和ILD層118可以包括絕緣材料,例如氧化矽(SiO
x)、氮化矽(SiN)、氮化矽碳(SiCN)、氮化矽氧碳(SiOCN)和氧化矽鍺。在一些實施例中,閘極間隔物114的厚度可以是約2奈米至約9奈米,以便將閘極結構112A-112C與相鄰結構充分進行電性隔離。
FET 100可以在基板104上形成。可以有其他FET及/或結構(例如隔離結構)在基板104上形成。基板104可以是半導體材料,例如矽(Si)、鍺(Ge)、矽鍺(SiGe)、絕緣層上覆矽(silicon-on-insulator ; SOI)結構及/或其組合。此外,基板104可以摻入p型摻雜物,例如,硼(B)、銦(In)、鋁(Al)或鎵(Ga),或n型摻雜物,例如,磷(P)或砷(As)。在一些實施例中,鰭式結構106可以包括類似於基板104的材料,並沿X軸延伸。
根據一些實施例,第1B和1C圖是鰭式結構106上的S/D區之剖面圖。在如第1A圖所示的一些實施例中,兩個相鄰的磊晶生長區可以在鰭式結構106上形成合併的S/D區110A,所述鰭式結構106具有大抵上平坦的頂面。在如第1B圖所示的一些實施例中,兩個相鄰的磊晶生長區可以在具有非平坦頂面的鰭式結構106上形成合併的S/D區120。在如第1C圖所示的一些實施例中,一個磊晶生長區可以在具有非平坦頂面的鰭式結構106上形成S/D區122。S/D接觸結構可以在S/D區110A、120和122上形成。在S/D接觸結構和S/D區110A、120和122之間可以穿插SBH降低層,以減少接觸電阻。可以設置襯層,以減少表面散射並進一步降低接觸電阻。在一些實施例中,可以在S/D區110A、120和122中形成金屬矽化物,以進一步降低S/D區110A、120和122與S/D接觸結構之間的SBH。
參考第1A圖和第2A圖,在一些實施例中,閘極結構112A-112C可以是多層結構。為簡單起見,未示出閘極結構112A-112C的多層。每個閘極結構112A-112C可以包括介面氧化物(interfacial oxide; IO)層,設置在IO層上的高介電常數閘極介電層(high-k ; HK)閘極介電層,和設置在HK閘極介電層上的導電層。IO層可以包括SiO
x、矽鍺氧化物(SiGeO
x)或鍺氧化物(GeO
x)。HK閘極介電層可以包括高介電材料,如氧化鉿(HfO
2)、氧化鈦(TiO
2)、氧化鋯鉿(HfZrO)、氧化鉭(Ta
2O
3)、矽酸鉿(HfSiO
4)、氧化鋯(ZrO
2)、矽酸鋯(ZrSiO
2)。導電層可以是多層結構。每個導電層可以包括設置在HK介電層上的功函數金屬(work function metal ; WFM)層,以及WFM層上的閘極金屬填充層。在一些實施例中,WFM層可以包括鈦鋁(TiAl)、碳化鈦鋁(TiAlC)、鉭鋁(TaAl)、碳化鉭鋁(TaAlC)、鋁摻雜的鈦、鋁摻雜的氮化鈦(TiN)、鋁摻雜的鉭(Ta)、鋁摻雜的氮化鉭(TaN)、其他合適的鋁基材料,或其組合。在一些實施例中,WFM層可以包括大抵上不含鋁(例如不含鋁)的鈦基或鉭基氮化物或合金,例如TiN、鈦矽氮化物(TiSiN)、鈦金(Ti-Au)合金、鈦銅(Ti-Cu)合金、TaN、鉭矽氮化物(TaSiN)、鉭金(Ta-Au)合金、鉭銅(Ta-Cu),及其組合。閘極金屬填充層可以包括合適的導電材料,如鎢(W)、鈦(Ti)、銀(Ag)、釕(Ru)、鉬(Mo)、銅(Cu)、鈷(Co)、鋁(Al)、銥(Ir)、鎳(Ni)、金屬合金及其組合。
參考第1A圖和第2A-2B圖,對於NFET 100,每個S/D區110A-110B可以包括磊晶生長的半導體材料,例如Si,和n型摻雜物,例如P和其他合適的n型摻雜物。對於PFET 100,每個S/D區110A-110B可以包括磊晶生長的半導體材料,如Si和SiGe,以及p型摻雜物,如硼(B)和其他合適的p型摻雜物。
參照第1A圖和第2B圖,在一些實施例中,S/D區110A-110B可以具有多個子區(sub-regions)110x-110z,這些子區可以包括SiGe並且可以基於如摻雜濃度、磊晶生長製程條件及/或Ge相對於Si的相對濃度而彼此不同。每個子區110x-110z都可以有類似或不同的厚度,厚度可以從約0.5奈米至約5奈米。在一些實施例中,第一子區110x中的Ge原子百分比(atomic percent)可以小於第二子區110z中的Ge原子百分比。在一些實施例中,子區110x可以包括約15個原子百分比至約35個原子百分比的Ge,而子區110z可以包括約25個原子百分比至約50個原子百分比的Ge,任何剩餘的原子百分比是子區中的Si。根據一些實施例,多個子區110x-110z彼此之間可以有不同的p型摻雜物濃度。例如,子區110x可以是未摻雜的,或者可以具有比子區110z的摻雜濃度(例如,摻雜濃度小於約8x10
20原子/立方公分)更低的摻雜濃度(例如,摻雜濃度在約1x10
20至約3x10
22原子/立方公分之間)。
在一些實施例中,子區110x可以具有具有矽砷(SiAs)、SiC或磷化矽(SiCP)的材料,摻雜物濃度從約1x10
20原子/cm
3至約1x10
21原子/cm
3,厚度從約1奈米至約3奈米。設置在子區110x上的子區110y可以具有具有SiP和摻雜物濃度從約1x1020原子/公分至約1x10
22原子/公分的材料。設置在子區110y上的子區110z可以有材料成分和厚度與子區110x相似的材料。
作為示例而非限制,可以使用源氣體(source gase),例如矽烷(SiH
4)、四氯化矽(SiCl
4)、三氯矽烷(trichlorosilane ; TCS)和二氯矽烷(SiH
2Cl
2或DSC(dichlorosilane))來生成磊晶S/D區110A-110B。氫氣(H
2)可作為反應氣體,以減少上述源氣體。磊晶生長過程中的生長溫度可以從約700℃至約1250℃,取決於所使用的氣體。例如,與具有較多氯原子的源氣體(如SiCl
4或TCS)相比,具有較少氯原子的源氣體(如DSC)可能需要較低的形成溫度。根據一些實施例,磊晶S/D區110A-110B可以承襲與半導體基板104或鰭式結構106相同的結晶方向,因為半導體基板104有效地用作磊晶S/D區110A-110B的晶種層。這意味著磊晶S/D區110A-110B的頂面也可以與(100)晶面平行。在一些實施例中,兩個相鄰的磊晶區可以形成類似於第1A、2B、2D、2F和2H圖中所示的組合平坦頂面。在一些實施例中,兩個相鄰的磊晶區可以形成類似於第1B圖所示的組合非平坦頂面。
參照第2A-2B圖,FET 100可進一步包括設置在S/D區110B上的S/D接觸結構219。類似的S/D接觸結構219可以被設置在S/D區110A和110C上。在一些實施例中,S/D接觸結構219可以包括設置在S/D區110B上的SBH降低層220和設置在SBH降低層220上的接觸插塞222。
在一些實施例中,接觸插塞222可以包括具有低電阻率的導電材料(例如,電阻率約50 μΩ-cm、約40 μΩ-cm、約30 μΩ-cm、約20 μΩ-cm或約10 μΩ-cm),例如鈷(Co)、鎢(W)、釕(Ru)、銥(Ir)、鎳(Ni)、鋨(Os)、銠(Rh)、鋁(Al)、鉬(Mo)、鈦(Ti)、其他具有低電阻率的合適導電材料以及其組合。在S/D接觸開口405內形成接觸插塞222之前,可以先在ILD層118和ESL117內形成S/D接觸開口405(如第5圖所示)。在一些實施例中,寬度W1可以為從約10奈米至約30奈米的範圍,寬度W2可為從約10奈米至約200奈米的範圍,高度H1可為從約20奈米至約100奈米的範圍,而斜角(slant angle)A可為從約80度至約90度的範圍。在一些實施例中,W1:W2的比例可為從約1:1至約1:10的範圍。接觸插塞222的這些尺寸範圍和比例提供了S/D區110B和上方互連結構(未示出)之間的最佳接觸區,而不影響裝置尺寸和製造成本。
SBH降低層220在接觸插塞222和S/D區110B之間提供低電阻介面。如果沒有SBH降低層220,接觸插塞222和S/D區110B之間的直接接觸會導致高半導體-金屬SBH,並因此導致高接觸電阻。在一些實施例中,使用SBH降低層220可以消除接觸插塞222和S/D區110B之間的矽化物層的使用。
在一些實施例中,SBH降低層220可以包括金屬硫族化合物(TMC)材料,例如週期表的任何過渡金屬的硫化物(sulfide)、週期表的任何過渡金屬的硒化物(selenide)、週期表的任何過渡金屬的碲化物(telluride)、週期表的任何過渡金屬的氧化物或其組合。在一些實施例中,TMC材料可以包括硫化鎢(WS
2)、硒化鎢(Se
2)、碲化鎢(WTe
2)、硫化鉬(MoS2)、硒化鉬(MoSe
2)。碲化鉬(MoTe2),TiS
2,硒化鈦(TiSe
2),碲化鈦(TiTe
2),硫化鋯(ZrS
2),硒化鋯(ZrSe
2),碲化鋯(ZrTe
2),硫化鉭(TaS
2)。硒化鉭(TaSe
2),碲化鉭(TaTe
2),硫化鎳(NiS
2),硒化鎳(NiSe
2),碲化鎳(NiTe
2),硫化鈷(CoS
2),硒化鈷(CoSe
2),碲化鈷(CoTe
2)。硫化鈮(NbS
2)、硒化鈮(NbSe
2)、碲化鈮(NbTe
2)、硫化鉿(HfS
2)、硒化鉿(HfSe
2)、碲化鉿(HfTe
2),或其組合。在一些實施例中,對於n型S/D區110B,SBH降低層220的TMC材料可以包括MoS
2、WS
2、硒化鉿鋯(zirconium hafnium sulfide selenide; (Zr(Hf)S(Se)
2) ),、MoTe
2、WTe
2或TaTe
2。在一些實施例中,對於p型S/D區110B,SBH降低層220的TMC材料可以包括MoSe
2(如果在S/D區110B中Ge濃度小於約25%)、WSe
2、MoTe
2、WTe
2、TiTe
2、HfTe
2、NbSe
2、TaSe
2、TiS
2、或TaS
2。
TMC材料可以包括M
xS
y、M
xSe
y及/或M
xTe
y的成分,其中M是金屬,並且y值和x值的比例可以在約1.2:1至約2.1:1之間。在一些實施例中,TMC材料中的氧(O)、氯(Cl)及/或氟(F)的原子濃度可以是約0%至約30%。在一些實施例中,TMC材料中的S或Se的原子濃度可以是約40%至約66%。在一些實施例中,TMC材料中過渡金屬的原子濃度可以是約20 %至約33 %。TMC材料可以產生從S/D區110B到S/D接觸插塞222的半導體-半金屬-金屬功函數(work function; WF)轉換。所述過渡可以降低S/D區110B和S/D接觸插塞222之間的SBH,即SBH調諧,以造成低接觸電阻。SBH降低層220在SBH降低層220和S/D區110B間的介面上可具有S、Te及/或Se的終端鍵,在SBH降低層220和接觸插塞222間的介面上可具有過渡金屬的終端鍵。這些末端接鍵可以降低SBH並降低電阻率。為了充分降低S/D區110B和接觸插塞222之間的SBH,SBH降低層220的厚度T1可以是約0.5奈米至約3奈米。在一些實施例中,T1:W1的比例可以在約0.017:1和約0.3:1之間。
在一些實施例中,SBH降低層220的TMC材料可以由以下材料的擴散形成:(i)硫族元素材料層702(如第7A圖所示),例如S、Se及/或Te層,和(ii)過渡金屬層704(如第7B圖所示),例如W、Mo、Ti、Ta、Ni、Zr及/或Co層。硫族元素材料層702可用例如帶有脈衝驅淨(pulse purge)的原子層沉積(atomic layer deposition ; ALD)製程,或帶有連續氣體供應的化學氣相沉積(chemical vapor deposition ; CVD)製程來沉積。用於沉積硫族元素材料層702的前驅物可以包括S或Se粉末/氣體、硫化氫(H
2S)或硒化氫(H
2Se)、二硫化氫(H
2S
2)或二硒化氫(H
2Se
2)、二硫二矽環己二烯(dithienodisilacyclohexadiene ; DTDS)、二叔丁基硫化物(di-tert-butyl sulfide ; DTBS)、二乙基硫化物(diethyl sulfide ; DES)等。沉積可以是電漿增強,例如,電感耦合電漿(inductively coupled plasma ; ICP)、電容耦合電漿(capacitively coupled plasma ; CCP)、微波、電子迴旋共振(electron cyclotron resonance ; ECR)電漿等。電漿增強的功率可以為約50W至約5000W。沉積溫度可以為約300⁰C至約800⁰C(有電漿增強),或約500⁰C至約1100⁰C(無電漿增強)。前驅氣體(如硫或硒基氣體)的流速可以是約0.5 sccm至約10 sccm。氬氣(Ar)或氮氣(N
2)保護氣體的流速可以是約5 sccm至約1000 sccm。H
2電漿氣體的流速可以是約0 sccm至約100 sccm。沉積室的壓力可為約1托至約10托。基於硫族元素材料層702的生長速率和期望厚度,沉積可持續一段預定的時間。硫族元素材料層702可以是單層、雙層或多層。硫族元素材料層702的厚度可為約0.7奈米至約2.1奈米。
過渡金屬層704可以用例如ALD製程、CVD製程、金屬有機化學氣相沉積(metal-organic chemical vapor deposition ; MOCVD)製程、分子束磊晶(molecular beam epitaxy ; MBE)、化學氣相傳輸(chemical vapor transport ; CVT)等進行沉積。用於沉積過渡金屬層704的前驅體可以包括金屬基氣體,例如。三氧化鎢(WO
3)、三氧化鉬(MoO
3)、四氯化鈦(TiCl
4)、四氯化鉿(HfCl
4)、四(二甲胺基)鈦(tetrakis(dimethylamino)titanium ; TDMAT)、四(二甲胺基)鉿(tetrakis(dimethylamino)hafnium ; TDMAHf)。羰基鎢(W(CO)
6)、六氟化鎢(WF
6)、六氟化鉬(MoF
6)、六氯化鎢(WCl
6)、五氯化鉬(MoCl
5)、五氯化鈮(NbCl
5)、五氯化鉭(TaCl
5)等。沉積可以是電漿增強,例如,電感耦合電漿(ICP)、電容耦合電漿(CCP)、微波、電子迴旋共振(ECR)電漿等。電漿增強的功率可以是約50W至約5000W。沉積溫度可以是約300⁰C至約800⁰C(有電漿增強),或約500⁰C至約1100⁰C(無電漿增強)。金屬基氣體的流速可以是約0.5 sccm至約10 sccm。Ar或N
2保護氣體流量可以是約5 sccm至約1000 sccm。H
2電漿氣體的流速可以是約0 sccm至約100 sccm。沉積室的壓力可以是約1托至約10托。根據過渡金屬層704的生長速度和期望厚度,沉積可以持續預定的時間。過渡金屬層704可以是單層、雙層、或多層。過渡金屬層704的厚度可以是約0.7奈米至約2.1奈米。
參考第2C-2D圖,在一些實施例中,FET100可以包括S/D接觸結構229,而不是S/D接觸結構219。在一些實施例中,S/D接觸結構229可以包括設置在S/D區110B上的SBH降低層220,設置在SBH降低層220上的接觸插塞222,以及設置在接觸插塞222側壁上的襯層228(也被稱為阻障層或粘附層)。在一些實施例中,襯層228可以包括與SBH降低層220相似或相異的TMC材料,並且可以在大抵上相同的製程中形成。在襯層228可以與SBH降低層220大抵上相同的實施例中,硫族元素材料(例如S或Se)的濃度可以從襯層228頂部的約2.1變化到襯層228底部的約1.6。這種變化可以由非順應性電漿製程引起。非順應性電漿製程還可導致襯層228的形狀為三角形,在接觸插塞222的頂部附近較厚,而在接觸插塞222的底部附近較薄。順應性電漿製程也會使襯層228的厚度均勻。襯層228可以利用高導電性材料,這將進一步降低插塞的電阻。襯層228還可以減少接觸插塞222和ILD層118之間的彈性散射,提高導電性。在一些實施例中,襯層228可以具有約0.7奈米至約2.1奈米的厚度T2。在一些實施例中,T1:T2的比例可以是約1:1至約2:1。襯層228的這些尺寸範圍和比例可以充分降低接觸電阻,並使接觸插塞222與ILD層118充分黏合,而不影響裝置的尺寸和製造成本。
在一些實施例中,襯層228可以在SBH降低層220形成之前形成,因此襯墊228沒有在SBH降低層220上形成,如第2C-2D圖所示。在一些實施例中,襯層228可以在SBH降低層220形成之後形成,因此襯墊228在SBH降低層220上並沿著接觸插塞222的側壁形成,如第2E-2F圖所示。
參考第2G-2H圖,在一些實施例中,FET100可以包括S/D接觸結構239而不是S/D接觸結構219或229。在一些實施例中,S/D接觸結構239可以包括設置在S/D區110B內的金屬矽化物層236、設置在金屬矽化物層236上的SBH降低層220、設置在SBH降低層220上的襯墊228,以及設置在襯層228上的接觸插塞222。金屬矽化物層236可以包括Si、或SiGe、磊晶區208的頂面所用的摻雜物,以及與襯層228或SBH降低層220相同的金屬。金屬矽化物結構236可以進一步包括S或Se。在一些實施例中,金屬矽化物層236可以包括Ti。金屬矽化物結構236可以在襯層228或SBH降低層220的沉積過程中,在約400⁰C至約550⁰C的溫度下形成。在一些實施例中,金屬矽化物結構236可以有約0.5奈米至約2.5奈米的厚度T3。在一些實施例中,T1:T3的比例可以是約1:1至約1:2。金屬矽化物層236可以進一步降低S/D區110B和接觸插塞222之間的SBH,從而減少接觸電阻。即使在第2G-2H圖中,金屬矽化物層236是在襯層228形成於SBH降低層220之上時形成的,但金屬矽化物層236也可以在沒有襯層228或有襯層228的情況下在接觸插塞222的側壁上形成。
參考第2I圖,在一些實施例中,FET 100可以是GAA FET 100,而不是第2A-2H圖所示的finFET 100。對於GAA FET 100,閘極結構112A-112B可以具有如第2I圖中所示的剖面圖,而不是第2A、2C、2E和2G圖所示的剖面圖。雖然第2I圖中的GAA FET 100被示為具有S/D接觸結構219,但根據一些實施例,GAA FET 100可以具有S/D接觸結構229或239。GAA FET 100的閘極結構112A-112B可以被包繞在奈米結構的通道區221周圍。奈米結構的通道區221可以是奈米片(nanosheet)或奈米導線(nanowire)。如本文所用,術語 「奈米結構」將結構、層及/或區定義為具有水平尺寸(例如,沿X軸及/或Y軸)及/或垂直尺寸(例如,沿Z軸)小於約100奈米,例如約90奈米、約50奈米、約10奈米,或者,其他小於約100奈米的數值皆涵蓋於本揭露的範圍之中。
奈米結構通道區221可以包括與基板104相似或相異的半導體材料。在一些實施例中,奈米結構通道區221可以包括Si、SiAs、磷化矽(SiP)、SiC、SiCP、SiGe、矽鍺硼(SiGeB)、鍺硼(GeB)、矽鍺錫硼(SiGeSnB)、III-V半導體化合物或其他合適的半導體材料。雖然奈米結構通道區221的矩形剖面被顯示出來,但奈米結構通道區221可以有其他幾何形狀的剖面(例如,圓形、橢圓形、三角形或多邊形)。環繞奈米結構通道區221的閘極結構112A-112B的閘極部分可以透過內間隔物113與相鄰的S/D區110B進行電性隔離。內間隔物113可以包括絕緣材料,如SiOx、SiN、SiCN、SiOCN和其他合適的絕緣材料。
根據一些實施例,第3圖是根據一些實施例,繪示出用於製造FET 100的方法300之流程圖,如第1A和2A-2H圖所示。為了說明問題,將參照第4-5、6A-6B、7A-7C、8A-8B、9A-9C、10A-10B和11A-12D圖繪示的用於製造FET 100的示例製造過程來描述於第3圖繪示的操作。第4圖是根據一些實施例,FET100沿第1A圖的A-A線在製造階段的剖面圖。第5、6A-6B、7A-7C、8A-8B、9A-9C、10A-10B和11A-12D圖是根據一些實施例的FET 100,在製造過程的各個階段沿第1A圖的B-B線的剖面圖。第6A-6B、7A-7C、8A-8B、9A-9C、10A-10B和11A-12D圖是第5圖的區101的放大圖。在方法300的各個操作之間可以進行額外的製造操作,為了簡單起見可以省略。這些額外的製造操作是在本揭露的精神和範圍內。此外,並非所有的操作都需要執行本文提供的揭露內容。此外,一些操作可以同時進行,或以與第3圖所示不同的順序進行。應注意的是,方法300可能不會產生完整的FET 100。因此,可以理解的是,在方法300之前、期間和之後都可以提供額外的過程,而且其他一些過程在這此可能只是簡單描述。第4-5、6A-6B、7A-7C、8A-8B、9A-9C、10A-10B和11A-12D圖中的元件,其注釋與第1A和2A-2I圖中的元件相同。
參考第3圖,在操作302中,在基板上形成鰭式結構,並且在鰭式結構上形成多晶矽結構和S/D區。例如,如第4-5圖所示,鰭式結構106在基板104上形成,並且多晶矽結構412和S/D區110B在鰭式結構106上形成。ILD層118和ESL 117是在S/D區110B的形成之後形成的。
參照第3圖,在操作304中,在S/D區上形成S/D接觸開口。例如,如第4-5圖所示,在S/D區110B上形成S/D接觸開口405。S/D接觸開口405可以透過ILD層118和ESL 117形成。S/D接觸開口405可以透過圖案化的光阻劑(此處未示)形成。光阻層可以被圖案化,以便在ILD層118上形成圖案化的光阻結構。光阻層的圖案化可以藉由以網罩(例如,光罩)來將暴露光阻層於UV或EUV光下並隨後移除光阻層的未暴露(或暴露)的部分來完成。圖案化光阻結構的間距(例如,間隔)可以根據圖案設計而變化。因此,在ILD層118的不同區上可以形成高密度和低密度的圖案化光阻結構(例如,具有不同間距或間隔的圖案化光阻結構)。ILD層118可以受到蝕刻化學的保護,因為光阻層可以作為蝕刻遮罩。
乾式蝕刻製程可以在圖案化光阻結構之間移除ILD層118和ESL 117,以形成S/D接觸開口405。換句話說,圖案化光阻結構可用作蝕刻遮罩以定義S/D接觸開口405的幾何樣態。例如,圖案化光阻結構的寬度和間距可用於進一步定義所形成的S/D接觸開口405的寬度和間距。S/D接觸開口405的底部長度(沿Y軸)可以是約10奈米至約200奈米,S/D接觸開口405的頂部長度(沿Y軸)可以是約10奈米至約200奈米,且可以與底部長度相似或不同。S/D接觸開口405的寬度(沿X軸)可以是約10奈米至約30奈米。S/D接觸開口405的高度可以是約20至約100奈米。S/D接觸開口405的斜角可以是約80度至約90度。在一些實施例中,所產生的S/D接觸開口405的側壁可具有正斜度。然而,這不是限制性的,因為S/D接觸開口405可以被設計為具有大抵上垂直的側壁(例如,在約86度和約90度之間),或具有負斜率的側壁。側壁和S/D接觸開口405的底部之間的角被示為角形,但在一些實施例中,角可以是圓形。S/D接觸開口405的側壁斜度(或側壁角度)可以透過乾式蝕刻製程條件來調整。因此,乾式蝕刻製程條件可以被調整,以實現S/D接觸開口405側壁的期望斜度。在一些實施例中,乾式蝕刻製程可以包括多個蝕刻子步驟,每個子步驟的蝕刻化學不同。在S/D接觸開口405形成後,可以用濕式清潔製程(例如,濕式剝離(wet strip))移除圖案化的光阻結構。
乾式蝕刻製程(例如,反應性離子蝕刻製程(reactive ion etching process))可以使用具有碳氟化合物(C
xF
y)、氮和氬的氣體混合物。上述氣體混合物可以具有約10%至約70%的C
xF
y。C
xF
y的流速可以從約100 sccm至約400 sccm,氮氣和氬氣的流速可以從約50 sccm至約300 sccm。蝕刻過程可以在約10秒至約90秒的時間內進行,溫度範圍為約10℃至約90℃,壓力範圍為約15毫托至約100毫托。或者,S/D接觸開口405可以透過濕式蝕刻製程形成。濕式蝕刻過程可以包括氫氟酸(HF)與緩衝劑的稀釋溶液,如氟化銨(NH
4F)、稀釋的HF(HF/H
2O)、磷酸(H
3PO
4)、硫酸與去離子水(H
2SO
4/H
2O),或其任何組合。蝕刻過程可以是選擇性蝕刻(selective etch)或定時蝕刻(timed etch)。
參照第3圖,在操作306中,在S/D接觸開口的側壁上形成襯層。例如,如參照第6A-6B圖所述,襯層228在S/D接觸開口405的側壁上形成。在一些實施例中,襯層228可以在形成SBH降低層220之前在S/D接觸開口405的側壁上形成。在一些實施例中,在形成SBH降低層220之前不形成襯墊228且不執行操作306。在這種情況下,在操作304之後為操作308,而非操作306。
在S/D接觸開口405的側壁上形成襯層228可以包括以下順序操作:(i)在第4-5圖的結構上沉積金屬層(未示出),(ii)用硫族元素材料處理金屬層以形成襯層602,如第6A圖所示,以及(iii)在蝕刻襯層602位於S/D區110B上的部分以形成襯層228,如第6B圖所示。
金屬層可以包括過渡金屬(例如,W、Co、Cu、Hf、Zr、Ti等)、稀土金屬(例如,Y、Yb或Er)或其組合。金屬層可以透過濺射(sputtering)、物理氣相沉積(physical vapor deposition ; PVD)、CVD、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition ; PECVD)、MOCVD進行沉積。用於沉積金屬層的前驅物可以包括金屬基氣體,例如,WO
3、MoO
3、TiCl
4、HfCl
4、TDMAT、TDMAHf、W(CO)
6、WF
6、MoF
6、WCl
6、MoCl
5、NbCl
5、TaCl
5等。沉積過程可為電漿增強,例如,ICP、CCP、微波、ECR電漿等。電漿增強的功率可以是約50W至約5000W。沉積溫度可以是約300⁰C至約800⁰C(有電漿增強),或約500⁰C至約1100⁰C(沒有電漿增強)。金屬基氣體的流速可以是約0.5 sccm至約10 sccm。Ar或N
2保護氣體的流量可以是約5 sccm至約1000 sccm。H
2電漿氣體的流速可以是約0 sccm至約100 sccm。沉積室的壓力可以是約1托至約10托。
用硫族元素材料處理金屬層可以包括使用硫或硒基的氣體、H
2S或H
2Se、H
2S
2或H
2Se
2、DTDS、DTBS、DES等。處理過程可以是電漿增強的,例如ICP、CCP、微波、ECR電漿等。電漿增強的功率可以是約50W到5000W。處理溫度可以是約300⁰C至約800⁰C(有電漿增強),或約500⁰C至約1100⁰C(沒有電漿增強)。硫或硒基氣體的流速可以是約0.5 sccm至約10 sccm。Ar或N
2保護氣體的流量可以是約5 sccm至約1000 sccm。H
2電漿氣體的流速可以是約0 sccm至約100 sccm。沉積室的壓力可以是約1托至約10托。
在第6B圖中,襯層602在ILD層118頂部和S/D接觸開口405底部(即,S/D區110B的頂部)的部分被移除,以在S/D接觸開口405的側壁上形成襯層228。在ILD層118頂部和S/D接觸開口405底部的襯層602可以透過選擇性的乾式蝕刻來移除。選擇性乾式蝕刻可以是定向的,並且可以從水平面移除襯層602,但不能從垂直面移除。在一些實施例中,定向乾式蝕刻(directional dry etch)可以使襯層602在垂直方向上的蝕刻明顯多於水平方向上。乾式蝕刻過程可以是反應性離子蝕刻過程,可以使用具有碳氟化合物(C
xF
y)、氮氣和氬氣的氣體混合物。在一些實施例中,蝕刻過程可以是異向性的—例如,在垂直方向(如Z軸)的蝕刻率高於橫向方向(如X軸和Y軸)。在一些實施例中,蝕刻過程可以是化學和物理蝕刻的組合。在一些實施例中,蝕刻過程可以包括具有不同蝕刻化學成分的多種蝕刻操作。可以將蝕刻劑選擇為對ILD層118和S/D區110B具有低選擇性,對襯層602的材料具有高選擇性。襯層602與ILD層118和S/D區110B之間的選擇性比例可以在2到10之間。舉例來說,襯層602和ILD層118之間的蝕刻選擇性比例可以是約3:1,襯層602和S/D區110B之間的蝕刻選擇性比例可以是約10:1。
參照第3圖,在操作308中,在S/D接觸開口內形成SBH降低層。例如,SBH降低層220可以在操作304之後在S/D區110B上形成,如參照第7A-7C和8A-8B圖所述,或者可以在操作306之後在S/D區110B上形成,如參照第9A-9C圖所述。
第7A-7C圖繪示出一種形成SBH降低層220的方法。參照第7D圖,在一些實施例中,SBH降低層220的形成可以包括以下順序操作:(i)如第7A圖所示,在S/D區110B上而不是在ILD層118上選擇性地沉積硫族元素材料層702,(ii)以氬氣驅淨沉積室(例如。(iii)選擇性地將過渡金屬層704沉積在硫族元素材料層702上而不是ILD層118上,如第7B圖所示,以及(iv)以氬氣驅淨沉積室(例如,在過渡金屬層704的ALD之後)。在一些實施例中,SBH降低層220的形成可以包括(v)在過渡金屬層704的沉積之後用H
2氣體進行電漿處理。順序操作(i)-(v)可以重複,以形成多個TMC層。
諸如S、Se和Te層的硫族元素材料層702可以用例如ALD製程或CVD製程進行沉積。用於沉積硫族元素材料層702的前驅物可以包括硫或硒基氣體、硫或硒粉末/氣體、H
2S或H
2Se、H
2S
2或H
2Se
2、DTDS、DTBS、DES等。沉積可以是電漿增強的,例如,ICP、CCP、微波、ECR電漿等。電漿增強的功率可以是約50W至約5000W。沉積溫度可以是約300⁰C至約800⁰C(有電漿增強),或約500⁰C至約1100⁰C(無電漿增強)。硫或硒基氣體的流速可以是約0.5 sccm至約10 sccm。Ar或N
2保護氣體的流速可以是約5 sccm至約1000 sccm。H
2電漿氣體的流速可以是約0 sccm至約100 sccm。沉積室的壓力可以是約1托至約10托。硫族元素材料層702的沉積厚度T4可以是約0.7奈米至約2.1奈米。
過渡金屬層704可以用例如ALD、CVD、MOCVD、MBE、CVT等進行沉積。用於沉積過渡金屬層704的前驅物可以包括金屬基氣體,例如,WO
3、MoO
3、TiCl
4、HfCl
4、TDMAT、TDMAHf、W(CO)
6、WF
6、MoF
6、WCl
6、MoCl
5、NbCl
5、TaCl
5等。沉積可以是電漿增強的,例如,ICP、CCP、微波、ECR電漿等。電漿增強的功率可以是約50W至約5000W。沉積溫度可以是約300⁰C至約800⁰C(有電漿增強),或約500⁰C至約1100⁰C(沒有電漿增強)。金屬基氣體的流速可以是約0.5 sccm至約10 sccm。Ar或N
2保護氣體的流量可以是約5 sccm至約1000 sccm。H
2電漿氣體的流速可以是約0 sccm至約100 sccm。沉積室的壓力可以是約1至10托。過渡金屬層704可以以約0.7奈米至約2.1奈米的厚度T5進行沉積。T4:T5的比例可以從約1:1至約1:2。
在過渡金屬層704的沉積之後,硫族元素材料層702和過渡金屬層704可以擴散以形成SBH降低層220的TMC材料,如第7C圖所示。擴散層可以包括M
xS
y、M
xSe
y、M
xTe
y等組成,其中M是一種金屬,y值和x值的比例可以是約1.2:1至約2.1:1。如果金屬前驅物含有O、Cl或F,則TMC材料中O、Cl或F的原子濃度可以是約0%至約30%。S或Se在TMC材料中的原子濃度可以是約40 %至約66 %。過渡金屬在TMC材料中的原子濃度可以是約20 %至約33 %。
第8A和8B圖繪示出形成SBH降低層220的另一種方法。在一些實施例中,SBH降低層220的形成可以包括以下順序操作:(i)選擇性地將過渡金屬層704沉積在S/D區110B上而不是ILD層118上,如第8A圖所示,以及(ii)用硫族元素材料處理過渡金屬層704以形成SBH降低層220,如第8B圖所述。過渡金屬層704在S/D區110B上的選擇性沉積可以以類似於參照第7B圖描述的方式進行。
用致癌物質處理過渡金屬層704可以包括使用硫或硒基氣體、H
2S或H
2Se、H
2S
2或 H
2Se
2、DTDS、DTBS、DES等。處理過程可以是電漿增強的,例如ICP、CCP、微波、ECR電漿等。電漿增強的功率可以是約50W到5000W。處理溫度可以是約300⁰C至約800⁰C(有電漿增強),或約500⁰C至約1100⁰C(沒有電漿增強)。硫或硒基氣體的流速可以是約0.5 sccm至約10 sccm。Ar或N
2保護氣體的流量可以是約5 sccm至約1000 sccm。H
2電漿氣體的流速可以是約0 sccm至約100 sccm。處理室的壓力可以是約1托至約10托。
第9A-9C圖繪示出在操作306之後在第6B圖的結構上形成SBH降低層220,其中S/D接觸開口405的側壁被襯層228覆蓋。襯層228可以根據第6A和6B圖所示的方法設置在S/D接觸開口405的側壁上。在襯層228在S/D接觸開口405的側壁上形成後,可根據第7A-7C圖或第8A-8B圖所述的方法在S/D接觸開口405中形成SBH降低層220。
參考第3圖,在一些實施例中,可以執行操作310而不是操作304。在一些實施例中,可以不執行操作310,並且在操作308之後可以是操作312。在操作310中,在S/D接觸開口的側壁和SBH降低層上形成襯層。例如,如第10A圖所示,襯層228在S/D接觸開口405的側壁和SBH降低層220上形成。襯層228可以在第7B或8B圖的結構上形成。在操作308中形成SBH降低層220後,可以在SBH降低層228和S/D接觸開口405的側壁上形成襯層228。襯層228可以根據操作304中與第6A圖描述的方法形成。
如第10B圖所示,在一些實施例中,可以在SBH降低層220、和S/D區110B之間形成金屬矽化物層236。金屬矽化物層236的組成可以取決於SBH降低層220的組成及/或襯層228的組成,因為金屬矽化物層236可以透過S/D區110B的材料與SBH降低層220及/或襯層228的金屬之間的矽化反應形成。
在一些實施例中,金屬矽化物層236可以包括Ti。金屬矽化物層236可以在襯層228的形成過程中在約400⁰C的溫度下形成。金屬矽化物層236可以在更高的溫度下與其他金屬形成。用這種方法形成的金屬矽化物層236可以是熱穩定的。金屬矽化物層236可以是n型S/D區110B上熱穩定的n型矽化物,可以是p型S/D區110B上熱穩定的p型矽化物。
即使在第10B圖中,當襯層228在SBH降低層220的頂部形成時,金屬矽化物層236也可以在沒有襯層228或有襯層228的S/D接觸開口405的側壁上形成。SBH降低層220包括金屬,在適當的溫度下,可以與S/D區110B中的矽(Si)反應,形成金屬矽化物層236。
參考第3圖,在操作312中,在S/D接觸開口內形成接觸插塞。例如,如參照第11A-12D圖所述,在S/D接觸開口405內形成接觸插塞222。接觸插塞222的形成可以包括以下順序操作:(i)在第7C或8B圖的結構上沉積金屬層1122以形成第11A圖的結構,在第9C圖的結構上形成第11B圖的結構,在第10A圖的結構上形成第11B圖的結構。在第10A圖的結構上形成形成第11C圖的結構,或在第10B圖的結構上形成第11D圖的結構,以及(ii)對第11A-11D圖的結構進行化學機械拋光(CMP)處理,分別形成第12A-12D圖的結構。在一些實施例中,SBH降低層220和接觸插塞222的形成是原位(in-situ)製程。在一些實施例中,CMP可用於移除ILD層118上的金屬層1122的額外厚度,從而使金屬層1122和ILD層118的頂面可以彼此大抵上共面。
本揭露內容提供了具有S/D接觸結構(例如S/D接觸結構219、229和239)以實現低接觸電阻的SBH降低層(例如SBH降低層220)的示例半導體裝置(例如finFETs 100、GAA FET 100)以及用於形成此類半導體裝置的方法(例如方法300)。在一些實施例中,SBH降低層設置在S/D區(例如S/D區110B)和S/D接觸插塞(例如S/D接觸插塞222)之間,以降低接觸電阻並消除金屬矽化物層的形成,從而減少S/D區的材料消耗。在一些實施例中,第SBH降低層包括TMC材料。
在一些實施例中,SBH降低層可以透過在S/D區上沉積硫族元素材料(例如S、Se或Te)層(例如,層702),然後沉積過渡金屬(例如Ti、W或Mo)層(例如,層704)而形成。這兩層可以一起擴散並形成SBH降低層的TMC材料。TMC層可以產生從S/D區到S/D接觸插塞的半導體-半金屬-金屬的梯度轉換,從而降低SBH,即SBH調諧。
在一些實施例中,SBH降低層可以透過在S/D區沉積過渡金屬層,例如Ti、W或 Mo,然後用硫族元素材料,例如硫或硒基氣體處理過渡金屬層而形成。在這兩種形成SBH降低層的方法中,在S/D區和SBH降低層間的介面上的S或Se終端鍵可以減少帶隙和降低電阻率。另一方面,在S/D接觸插塞和SBH降低層之間的過渡金屬終端鍵可以降低接觸電阻率。
在一些實施例中,可以在S/D接觸插塞的側壁上形成襯層(例如,襯層228)。在一些實施例中,襯層可以在SBH降低層上形成。襯層可以有導電材料,例如,TiS
2。襯層可以減少彈性散射並提高導電性。透過使用SBH降低層、更薄和更高導電性的襯墊,以及在一些實施例中使用金屬矽化物,可以降低接觸電阻。SBH降低層的製造過程可以使用低溫催化劑輔助生長,這減少了製造過程中對於實現低接觸電阻的挑戰。
在一些實施例中,揭露了一種半導體裝置的形成方法,包括:在基板上形成鰭式結構;在鰭式結構上形成閘極結構;在未被閘極結構覆蓋的鰭式結構上形成源極/汲極(source/drain; S/D)區;在S/D區上形成接觸結構,其中形成接觸結構的步驟包括:在S/D區上形成過渡金屬硫族化合物(transition metal chalcogenide; TMC)層;以及在TMC層上形成接觸插塞。
在一實施例中,TMC層的厚度與TMC層沿鰭式結構的長度之比例介於約0.017:1至約0.3:1之間。在一實施例中,形成TMC層的步驟包括:在約300 ℃及約800 ℃之間的溫度下使用電漿製程或在約500 ℃及約1100 ℃之間的溫度下不使用電漿製程,以在S/D區上沉積硫族元素材料層;以及在約300 ℃及約800 ℃之間的溫度下使用電漿製程或在約500 ℃及約1100 ℃之間的溫度下不使用電漿製程,以在硫族元素材料層上沉積過渡金屬層。在一實施例中,形成TMC層的步驟包括:在S/D區上沉積硫族元素材料層;在硫族元素材料層上沉積過渡金屬層;以及在過渡金屬層上進行電漿製程。在一實施例中,形成TMC層的步驟包括:在S/D區上形成接觸開口;在S/D區上而不在接觸開口的多個側壁上,選擇性地沉積硫族元素材料層;以及在硫族元素材料層上而不在接觸開口的多個側壁上選擇性地沉積過渡金屬層。在一實施例中,形成TMC層的步驟包括在S/D區上選擇性地沉積層硫、硒或碲。在一實施例中,形成TMC層的步驟包括在S/D區上形成一層硫化物、硒化物或碲化物。在一實施例中,在接觸插塞的多個側壁上及在TMC層上沉積襯層,其中TMC層的厚度與襯層的厚度之間的比例介於約1:1至約2:1之間。在一實施例中,在接觸插塞的多個側壁上形成一襯層,其中形成襯層的步驟包括形成一過渡金屬硫族化合物材料層。在一實施例中,在接觸插塞的多個側壁上形成襯層,其中形成襯層的步驟包括形成一層硫化鎢、硒化鎢、硫化鉬、硒化鉬,或其組合。
在一些實施例中,揭露了一種半導體裝置的形成方法,包括:在基板上形成鰭式結構;在鰭式結構上形成閘極結構及源極/汲極(S/D)區;在S/D區上形成接觸結構,其中形成接觸結構的步驟包括:在S/D區上形成接觸開口; 在接觸開口內沉積金屬層;對金屬層使用硫族元素材料進行電漿製程;以及在接觸開口內形成接觸插塞。
在一實施例中,沉積金屬層的步驟包括在約300 ℃及約800 ℃之間的溫度下使用電漿製程或在約500 ℃及約1100 ℃之間的溫度下不使用電漿製程來沉積過渡金屬層。在一實施例中,沉積金屬層的步驟包括在S/D區上沉積金屬層。在一實施例中,進行電漿製程的步驟包括使用硫化物氣體、硒化物氣體或碲化物氣體在約300℃及約800℃的溫度下進行電漿製程。在一實施例中,在接觸開口的多個側壁上形成襯層,其中形成襯層的步驟包括形成過渡金屬硫族化合物層。在一實施例中,形成接觸結構的步驟更包括在S/D區中形成金屬矽化物層,其中金屬層的厚度與金屬矽化物層的厚度之間的比例介於約1:1至約1:2之間。
在一些實施例中,揭露了一種半導體裝置,包括:基板;鰭式結構,設置於基板上;閘極結構,設置於鰭式結構上;源極/汲極(S/D)區,設置於鰭式結構未被閘極結構覆蓋的多個部分上;以及接觸結構,設置於S/D區上,其中接觸結構包括:過渡金屬硫族化合物(TMC)層,設置於S/D區上;以及接觸插塞,設置於TMC層上。
在一實施例中,TMC層的厚度與TMC層的長度之間的比例介於約0.017:1至0.3:1之間。在一實施例中,半導體裝置,更包括:一襯層,沿接觸插塞的多個側壁設置,其中襯層包括硫化鎢、硒化鎢、硫化鉬、硒化鉬或其組合。在一實施例中,半導體裝置,更包括一金屬矽化物層,設置於S/D區及TMC層之間,其中金屬矽化物層包括過渡金屬,以及硫族元素材料。
應當理解的是,除了本揭露的摘要內容,本揭露的詳細描述內容旨在用於解釋請求項。本揭露的摘要內容可以闡述發明人所設想的本揭露的一或多個實施例,但並非所有可能的實施例,因此本揭露的摘要內容不意圖以任何形式限制所附的請求項。
以上概述數個實施例之特徵,以使本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解,可輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且可在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:場效應電晶體
101:區
104:基板
106:鰭式結構
110A-B:源極/汲極區
110x-z:子區
112A-C:閘極結構
114:閘極間隔物
116:淺溝槽隔離區
117:蝕刻停止層
118:層間介電層
120:源極/汲極區
122:源極/汲極區
219:源極/汲極接觸結構
220:高肖特基能障高度降低
221:通道區
222:接觸插塞
228:襯層
229:源極/汲極接觸結構
236:金屬矽化物層
239:源極/汲極接觸結構
302-312:操作
405:源極/汲極接觸開口
412:多晶矽結構
602:襯層
702:硫族元素材料層
704:過渡金屬層
1122:金屬層
A-A,B-B:線
H1:高度
W1-2:寬度
T1-5:厚度
由以下的詳細敘述配合所附圖式,可最好地理解本發明實施例。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製。事實上,可任意地放大或縮小各種元件的尺寸,以清楚地表現出本發明實施例之特徵。
第1A圖是根據本揭露的一實施例,繪示出半導體裝置之等角視圖。
第1B圖及第1C圖是根據本揭露的一實施例,繪示出半導體裝置之剖面圖。
第2A-2I圖是根據本揭露的一實施例,繪示出具有接觸結構的半導體裝置之剖面圖。
第3圖是根據本揭露的一實施例,繪示出用於製造具有接觸結構的半導體裝置的方法之流程圖。
第4 -5圖、第6A -6B圖以及第7A-7C圖、第8A-8B圖、第9A-9C圖、第10A-10B圖、第11A-11D圖、第12A-12D圖是根據本揭露的一實施例,繪示出在其製造過程的各個階段具有接觸結構的半導體裝置之剖面圖。
第7D圖是根據本揭露的一實施例,繪示出用於製造過渡金屬硫族化合物(transition metal chalcogenide ; TMC)層的方法之流程圖。
104:基板
110B:源極/汲極區
110x-z:子區
116:淺溝槽隔離區
117:蝕刻停止層
118:層間介電層
219:源極/汲極接觸結構
220:高肖特基能障高度降低層
222:接觸插塞
A-A:線
H1:高度
T1:厚度
W2:寬度
Claims (1)
- 一種半導體裝置的形成方法,包括: 在一基板上形成一鰭式結構; 在該鰭式結構上形成一閘極結構; 在未被該閘極結構覆蓋的該鰭式結構上形成一源極/汲極(source/drain; S/D)區; 在該S/D區上形成一接觸結構,其中形成該接觸結構的步驟包括: 在該S/D區上形成一過渡金屬硫族化合物(transition metal chalcogenide; TMC)層;以及 在該TMC層上形成一接觸插塞。
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US20220293736A1 (en) * | 2021-03-11 | 2022-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | 2D Channel Transistors with Low Contact Resistance |
US20230023186A1 (en) * | 2021-07-26 | 2023-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method for forming the same |
US20230197836A1 (en) * | 2021-12-21 | 2023-06-22 | Intel Corporation | Integrated circuits with max or mx conductive materials |
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2021
- 2021-11-23 US US17/533,575 patent/US20220310800A1/en active Pending
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2022
- 2022-03-14 TW TW111109207A patent/TW202238834A/zh unknown
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