TW202238588A - Arbitration control for pseudostatic random access memory device - Google Patents

Abstract

An arbitration control circuit in a pseudo–static random access memory (PSRAM) device includes a set–reset latch circuit receiving a normal access request signal and a refresh access request signal as first and second input signals and generating a first output signal having zero or more signal transitions in response to the order the first input signal and the second input signal is asserted. The arbitration control circuit further includes a unidirectional delay circuit applying a unidirectional delay to the first output signal and a D–flip–flop circuit latching the first output signal as data in response to the delayed signal as clock. The D–flip–flop generates a second output signal having a first logical state indicative of granting the normal access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.

Description

Arbitration Control of Pseudo-Static Random Access Memory Devices

The present invention relates to controlling operation of pseudo-static random access memory (PSRAM) devices, and in particular, to providing arbitration control in a PSRAM device to suppress and eliminate metastability during simultaneous external and internal access requests .

A pseudo-static random access memory (PSRAM) is a type of random access memory whose internal structure is that of a dynamic random access memory (DRAM) in which reordering control signals are internally generated so that it can simulate a static random access memory Take the function of memory (SRAM). Unlike so-called self-rearranging DRAM devices, PSRAM devices have unmultiplexed address lines and pinout lines similar to those of SRAM devices. A PSRAM device incorporates on-chip reordering and control circuitry (eg, reordering address counters and multiplexers, reordering interval timers, arbitrators). These circuits allow PSRAM operating characteristics to be very similar to those of SRAM. In this way, a PSRAM device combines the high density of DRAM with the ease of use of a true SRAM.

PSRAM can be distinguished from DRAM with a "self-refresh mode", which is mainly used in standby mode to allow a host system to suspend the operation of an external DRAM controller to save power without losing data stored in DRAM . Self-refresh mode refreshes DRAM data during standby mode when no control signal is received from the external DRAM controller. PSRAM devices operate without an external DRAM controller and include built-in reordering controls to allow PSRAM to behave like an SRAM.

In operation, a PSRAM device performs read and write operations in response to read/write requests received external to the PSRAM, and performs memory cell reorganization between read or write operations. PSRAM devices contain a counter to generate internal rearrangement requests. Therefore, read/write requests and reorder requests operate on different frequency domains. Therefore, when an external read/write request arrives at the same time that an internal refresh request is issued, there may be a conflict between the read/write request and the refresh request.

According to one embodiment of the present application, an arbitration control circuit in a pseudo static random access memory (PSRAM) device is provided, the arbitration control circuit includes: a set-reset (SR) latch circuit receiving a A first input signal and a second input signal, the first input signal being a normal access request signal indicating a read or write access request to a memory cell of the PSRAM device, the second input signal being a normal access request signal a reorder access request signal indicating a reorder access request to memory cells of the PSRAM device, the SR latch circuit responding to a logical operation of the first input signal and the second input signal to generate a A first output signal responsive to asserting the first input signal without a signal transition prior to asserting the second input signal, or in response to asserting the second input signal after or in conjunction with asserting the second input signal signals simultaneously asserting the first input signal with two or more signal transitions; a one-way delay circuit having an input terminal receiving the first output signal and introducing a first delay to the first output a leading signal transition of a signal to produce a delayed signal on an output terminal, the delayed signal responding to the first output signal having no signal transition or having a pulse width shorter than the first delay without having a signal transition; and a D-type flip-flop circuit having a data input terminal receiving the first output signal, a clock input terminal receiving the delayed signal, a reset input terminal receiving a reset signal and providing a second output signal An output terminal, the second output signal has a first logic state in response to the delayed signal having no signal transition and has a second logic state in response to a signal transition in the delayed signal, the second The output signal maintains the second logic state until the reset signal is asserted to reset the second output signal to the first logic state, wherein the second output signal has a value indicating one of granting the read or write access request A first logic state and a second logic state indicative of the reorder access request granted to the memory cells of the PSRAM device.

According to another embodiment of the present application, there is provided a method for providing arbitration control in a pseudo static random access memory (PSRAM) device, the method comprising: receiving a first input signal, the first input signal A normal access request signal indicating a read or write access request to a memory cell of the PSRAM device; receiving a second input signal indicating a request for a memory cell of the PSRAM device a reordering access request signal; a first output signal is generated in response to a logical operation of the first input signal and the second input signal, the first output signal is in response to confirming the first asserting the first input signal without a signal transition prior to the second input signal, or having two or more assertions of the first input signal in response to asserting the first input signal after or simultaneously with asserting the second input signal secondary signal transition; generating a delayed signal having a leading signal transition a first delay after a leading signal transition of the first output signal, the delayed signal responding to the first output signal having a ratio The first delay is short by a pulse width without a signal transition; a second output signal is generated having a first logic state in response to the delayed signal without a signal transition and in response to the delayed signal The first signal transition on the signal is received to have a second logic state, the second output signal maintains the second logic state until reset to the first logic state, wherein the second output signal has an indication that the read A first logic state of a fetch or write access request and a second logic state indicating the reorder access request granted to the memory cells of the PSRAM device.

In an embodiment of the present invention, an arbitration control circuit in a pseudo static random access memory (PSRAM) device incorporates a SR connected in series to receive normal (read/write) and rearrangement access request signals One of the outputs of the latch circuit metastable control filter. The arbitration control circuit generates access grant signals to grant normal (read/write) requests or rearrangement requests. When simultaneously asserting external read/write access requests and internal rearrangement access requests, the arbitration control circuit operates to suppress and eliminate the risk of metastability that can cause PSRAM operation to fail. In some embodiments, the metastable control filter of the arbitration control circuit includes a one-way delay circuit for eliminating unwanted short glitches in the output signal of the SR latch circuit and acts as an SR lock to act as the first arbiter One of the D-type flip-flop circuits of the second arbiter of the storage circuit. By using two arbiters connected in series, the probability of metastability of the PSRAM device is reduced by several orders of magnitude. In some embodiments, the delay introduced by the one-way delay circuit can be tuned to achieve the desired resolution time and target mean time between failures (MTBF) requirements of the PSRAM device.

In some embodiments, a reorder timer circuit is coupled to the D-type flip-flop circuit to reset the reorder access grant signal after a given duration. In this way, the arbitration control circuit ensures that the reorder access grant signal has a minimum duration to ensure a stable reorder operation.

FIG. 1 is a schematic diagram of a PSRAM device in an embodiment of the present invention. As described above, a pseudo static random access memory (PSRAM) is a type of random access memory that includes DRAM type memory cells and built-in reordering controls to simulate the function of a static random access memory (SRAM). Referring to FIG. 1, the PSRAM device 100 includes a memory array 120, one of the dynamic memory cells. Each dynamic memory cell includes a single access transistor T connected to a storage capacitor C. The memory array is organized as a two-dimensional array, and each dynamic memory cell is accessed by a word line WL and a bit line BL.

The PSRAM device 100 includes a command and address control circuit 102 for receiving input control signals including a clock signal, a chip select signal CE, a write enable signal WE, and a memory cell address ADDR. An input/output (I/O) circuit 124 receives and provides memory data. That is, the memory data written into the memory cell is provided to the I/O circuit 124, and the memory data read from the memory cell is provided on the I/O circuit 124 as an output signal.

The PSRAM device 100 receives the write enable signal WE to indicate that a write operation or a read operation will be performed at the input address ADDR. In this example, the write enable signal WE is an active low signal (denoted as /WE). The write enable signal /WE is asserted to a logic high to initiate a read operation and asserted to a logic low to initiate a write operation. The command and address control circuit 102 generates a control signal Control provided to a write and read control circuit 112 . The write and read control circuit 112 generates control signals to control the I/O circuit 124 to receive incoming memory write data or provide outgoing memory read data.

The command and address control circuit 102 decodes the input address ADDR and generates a column address RADDR for addressing the word lines WL and a row address CADDR for addressing the bit lines. The row address CADDR is provided to a row access control circuit 108 which is coupled to control a row select/sense amplifier/write driver circuit 122 . The row address CADDR is used to activate a selected row. For a read operation, the bit lines for the selected row are precharged and the sense amplifier reads memory data from the selected memory cell, and the read memory is provided to the I/O circuit 124 through the I/O bus 123 . For a write operation, the write driver drives the bit line of the selected row to the write data received from the I/O circuit 124 and passed on the I/O bus 123 to the write driver.

Meanwhile, the column address RADDR is provided to an external column access control circuit 106 . The external column access control circuit 106 generates a normal access request REQ_NOM in response to a column address RADDR received from the command and address control circuit 102 . In this description, a read or write operation to the PSRAM device 100 is referred to as an external request or an external access or an external access request when the read and write operations are initiated outside the PSRAM device. In this description, external access requests to the PSRAM device 100 are also referred to as normal access requests or normal requests to mean access requests made for normal PSRAM operations (ie, read and write operations).

PSRAM devices include built-in reordering circuitry to perform reordering operations on the dynamic memory cells in memory array 120 . In this description, when a reordering operation is initiated inside a PSRAM device, a built-in reordering operation refers to an internal request or an internal access or an internal access request. In this description, an internal access request in the PSRAM device 100 is also referred to as a reorder access request or a reorder request to mean an access request for a memory cell reorder operation. To this end, the PSRAM device 100 includes an internal reorder control circuit 104 to generate an internal reorder access request REQ_REF for initiating a reorder operation of the memory array 120 . For example, internal reorder control circuit 104 may include a counter or a timer circuit configured to generate a reorder access request REQ_REF in response to the counter reaching a certain value or a given duration of time having occurred.

The normal access request REQ_NOM and the rearrangement access request REQ_REF are signals operating on different frequency domains. That is, the normal access request REQ_NOM and the refresh access request REQ_REF do not operate at the same or related clock frequency. Therefore, when the normal access request REQ_NOM and the rearrangement access request REQ_REF want to access the word line at the same time, the two requests sometimes experience conflicts. In operation, only one request (normal or refresh) can access a word line. Accordingly, the normal access request signal REQ_NOM and the rearrangement access request signal REQ_REF are coupled to the arbiter circuit 110, which operates to determine which access request should be granted.

When the external access request is granted, the arbiter 110 asserts the normal access grant signal GRANT_NOM provided to the external column access control circuit 106 . In response, the external column access control circuit 106 generates a normal column address (“normal RADDR”) that is provided to a word line decoder 114 . When the GRANT access request is granted, the arbiter 110 asserts the GRANT_REF signal provided to the internal GRG control circuit 104 . In response, internal rearrangement control circuit 104 generates a rearrangement column address (“Rearrangement RADDR”) that is provided to wordline decoder 114 . The word line decoder 114 decodes the column address (rearranged column address or normal column address) and enables selected word line signals in the memory array 120 for respective read, write or reorder operations.

In digital circuit design, different clock frequencies are often used in the circuit and the different clock frequencies must be synchronized. However, any kind of synchronization will inevitably lead to metastable failures and metastable failures tend to increase with increasing pulse frequency, especially the high performance and low power design trend. In the PSRAM device 100 of FIG. 1 , the arbiter 110 is configured to arbitrate external access requests and internal access requests to ensure stable and reliable performance of the PSRAM device. In an embodiment of the present invention, the arbiter 110 (also referred to as an arbitration control circuit in the present invention) incorporates a metastable control circuit connected in series to the output of the SR latch circuit receiving normal and rearranged access request signals filter. When so configured, arbiter 110 suppresses and eliminates the risk of metastability of PSRAM device 100 . Additionally, the metastable control filter in the arbiter 110 can be tuned to enable the PSRAM device to achieve a target mean time between failures (MTBF) while providing clean access grant signals to respective column address control circuits. The arbiter 110 of the present invention minimizes speed loss by minimizing clock output time, while the additional arbiter circuit in the metastable control filter reduces the probability of metastable risk by several orders of magnitude. The details of the metastable control filter are described in more detail below.

2 is a circuit diagram illustrating a conventional arbiter circuit that may be used in a conventional PSRAM in some examples. Referring to FIG. 2, one conventional method for arbitrating incoming commands from external requests and internal requests simultaneously uses a set-reset latch circuit, such as a NAND latch circuit or a NOR latch circuit. FIG. 2 shows an arbiter circuit 1 implemented as a NAND latch circuit using a pair of cross-coupled NAND logic gates 2 and 3 . In order to arbitrate between the normal access request signal REQ_NOM and the rearrangement access request signal REQ_REF, the NAND logic gate 2 receives the normal access request signal REQ_NOM and the output signal of the NAND logic gate 3 (node 5), and the NAND logic gate 3 Receive the rearrangement access request signal REQ_REF and the output signal of NAND logic gate 2 (node 4). The normal access grant signal GRANT_NOM (node 8 ) is the inversion of the output signal (node 4 ) of NAND logic gate 2 , such as by inverter 6 . The rearrangement access grant signal GRANT_REF (node 9 ) is the inversion of the output signal (node 5 ) of the NAND logic gate 3 , eg by inverter 7 .

FIG. 3 is a timing diagram illustrating the operation of the conventional arbiter circuit of FIG. 2 in some examples. The normal access request signal REQ_NOM and the rearrangement access request signal REQ_REF are two command signals belonging to different frequency domains. When the signal REQ_NOM (curve 62 ) is earlier than the signal REQ_REF (curve 64 ), the arbiter circuit 1 grants the normal access request and asserts the signal GRANT_NOM (curve 66 ). Meanwhile, when the signal REQ_REF is earlier than the signal REQ_NOM, the arbiter circuit 1 grants the rearrangement access request and asserts the signal GRANT_REF (curve 68 ). However, when both the command signals REQ_NOM and REQ_REF arrive almost simultaneously within a metastable window, the arbiter circuit 1 may be delayed in generating the access grant signal or the resulting access grant signal may be distorted. For example, access grant signals can be corrupted by irregular waveforms or shortened pulse widths. The amount of delay or distortion depends on the probability of command signal collisions. The closer in time two commands arrive, the lower the probability of this happening, but this can translate into longer resolution times. That is, when two command signals arrive very close together, the arbiter circuit 1 takes longer to determine which command to grant.

， 其中 T _w ： 元窗 f _c ： 時脈頻率 f _r ： 重新整理頻率 t： 解析時間

： 解析之時間常數 Due to the nature of two independent command signals belonging to different frequency domains, the rare probability that a normal access request will transition within the metastable window is usually described by the equation of mean time between failures (MTBF). In this description, the metastable window refers to the time window in which two command signals arrive within each other. Generally speaking, from the perspective of failure detection, this probability is very rare, but from the perspective of users, if the MTBF is assumed to be about 1 year, this probability may be very common. Specifically, the mean time between failures can be given as:

, where T _w : meta window f _c : clock frequency f _r : rearrangement frequency t : resolution time

: time constant of analysis

If the MTBF of a synchronous system is not at an acceptable level, the system will fail. This is especially problematic for PSRAM devices due to the destructive read nature of dynamic memory cells. Figure 6 is a plot of output access time versus arrival time of a reorder request for a conventional arbiter circuit in some examples. Referring to FIG. 6, the arbitration operation basically compares normal access request signals and rearranged access request signals provided by external systems and internal circuit operations. In FIG. 6, it is assumed that the normal access request signal REQ_NOM has an arrival time indicated by the line 52, and the x-axis represents the arrival time of the rearrangement access request signal REQ_REF. The metastable window 54 is the period during which two signals arrive within a given time of each other. Curve 50 depicts the output access time of the arbiter circuit, also referred to as resolution time. After determining the metastable window, clock frequency, rearrangement frequency, and time constant, the analysis time is the logarithmic scale of the MTBF. In simple terms, choosing a lower resolution time threshold tR in the system will incur more system-level failures. As shown in FIG. 6 , in most cases, regardless of the request signal sequence, the conventional arbiter circuit 1 can generate the access grant signal within the normal clock output time tCO. However, as the reordering access request signal REQ_REF approaches the normal access request signal REQ_NOM, the output access time increases exponentially, albeit with a low probability of occurrence. Within the metastable window, the resolution time becomes very high, greater than the desired resolution time threshold tR for PSRAM devices.

FIG. 4 is a schematic diagram illustrating an arbiter circuit that may be incorporated into a PSRAM device in an embodiment of the present invention. In some embodiments, the arbiter circuit 20 of FIG. 4 may be used to implement the arbiter 110 in the PSRAM device 100 of FIG. 1 . Referring to FIG. 4 , the arbiter circuit 20 (also referred to as an arbitration control circuit) is configured to arbitrate normal access request signals and rearrangement access request signals in a PSRAM device (such as the PSRAM device 100 of FIG. 1 ). The arbiter circuit 20 receives the normal access request signal REQ_NOM as a first input signal indicating a command signal received from a host system external to the PSRAM device to initiate a read or a write operation to the PSRAM device. The arbiter circuit 20 also receives the reorder access request signal REQ_REF as a second input signal indicating a command signal received from the internal reorder control circuit of the PSRAM device for initiating a reorder operation in the PSRAM device.

The arbiter circuit 20 includes a first arbiter 25 formed as a set-reset latch circuit. In this embodiment, the set-reset latch circuit is implemented as a NAND latch circuit comprising a pair of cross-coupled NAND gates 2,3 and accompanying inverters 6,7. More specifically, NAND logic gate 2 receives the normal access request signal REQ_NOM and the output signal of NAND logic gate 3 (node 5), and NAND logic gate 3 receives the rearrangement access request signal REQ_REF and the output signal of NAND logic gate 2 (node 4). The first arbiter 25 provides an arbitration signal ARB (node 32 ) obtained from the output signal of the NAND logic gate 3 and inverted by the inverter 7 . In this embodiment, the output signal from NAND gate 2 is not used, and inverter 6 at the output terminal (node 4) of NAND gate 2 is included to provide a balance between NAND gates 2 and 3 One of the loads is a virtual gate. In other embodiments of the present invention, the inverter 6 may be omitted.

The first arbiter 25 arbitrates between the normal access request signal REQ_NOM and the rearrangement access request signal REQ_REF and generates the arbitrated signal ARB on the output node 32 as an output signal. The arbitrated signal ARB has no signal transitions in response to the normal access request signal arriving before the rearranged access request signal. The arbitrated signal ARB is a signal pulse in response to the normal access request signal arriving after the rearranged access request signal. However, when the normal access request signal arrives very close to the rearrangement access request signal before or after the rearrangement access request signal, the arbitrated signal ARB may have a distorted or corrupted waveform with two or more signal transitions .

The arbiter circuit 20 includes a metastable control filter 30 coupled in series to the first arbiter 25 . In particular, metastable control filter 30 is connected to output node 32 of the first arbiter to receive arbitrated signal ARB and to generate rearranged access grant signal GRANT_REF (node 38). The normal access grant signal GRANT_NOM (node 24) is the inverse of the rearrangement access grant signal GRANT_REF and may be generated using an inverter 22 coupled to signal GRANT_REF.

Metastable control filter 30 includes a one-way delay circuit 34 coupled to receive arbitrated signal ARB. The one-way delay circuit 34 has the function of eliminating short glitches of the arbitrated signal ARB. In particular, unidirectional delay circuit 34 applies a delay to leading signal transitions via arbitration signal ARB and no delay to trailing signal transitions to generate a delayed signal at output node 35 . In case the arbitrated signal ARB has no signal transitions, the delayed signal also has no signal transitions. When the arbitrated signal ARB has a pulse width shorter than the delay introduced by the one-way delay circuit, the delayed leading signal transition occurs after the trailing signal transition and the delayed signal has no signal transitions. In this way, one-way delay circuit 34 eliminates arbitrated signal ARB that is only a short glitch or has a short pulse width. Only when the arbitrated signal ARB has a pulse width greater than the delay, the signal ARB will pass through the one-way delay circuit 34 . In some embodiments, the delay provided by one-way delay circuit 34 is tunable or programmable. For example, the delay of unidirectional delay circuit 34 can be programmed to a value based on the MTBF requirements of the PSRAM device. In FIG. 4, an MTBF programming circuit 45 is shown coupled to the one-way delay circuit 34 for programming the delay value. The MTBF programming circuit 45 is for illustration only and other circuits and methods may be used to tune or program the delay value in the one-way delay circuit 34 .

The metastable control filter 30 further includes a second arbiter 36 configured as a D-type flip-flop. The D-type flip-flop 36 receives the undelayed arbitration signal ARB (node 32 ) as the data input signal D and the delayed signal (node 35 ) as the clock signal K, and provides a data output signal Q (node 38 ). The D-type flip-flop 36 passes the data input signal D (ie, the undelayed arbitration signal ARB) to the data output signal Q in response to the delayed signal as the clock signal. Therefore, an arbitrated signal ARB with a short pulse width will be rejected at the D-type flip-flop because there will be no clock signal K. An arbitrated signal ARB with a sufficiently long pulse width will travel through the D-flip-flop as clocked by the clock signal K.

So constructed, the metastable control filter 30 provides the fault removal function and a second arbiter in series with the first arbiter 25 . The probability of metastability of two serially connected arbiters with a delay is greatly reduced. Even though there is still a mathematical chance of metastability, the probability is orders of magnitude lower than conventional schemes using a single NAND latch as an arbiter.

Metastable control filter 30 generates an output signal (node 38) provided as rearrangement access grant signal GRANT_REF. The normal access grant signal GRANT_NOM is the inverse of the rearrangement access grant signal GRANT_REF. Inverter 22 may be used to invert rearrangement access grant signal GRANT_REF to generate normal access grant signal GRANT_NOM (node 24). In this embodiment, the rearrangement access grant signal GRANT_REF and the normal access grant signal GRANT_NOM are complementary signals. In operation, the normal access grant signal GRANT_NOM is normally asserted, and when the rearrangement access grant signal GRANT_REF is asserted, the normal access grant signal GRANT_NOM is deasserted.

In an embodiment of the present invention, the arbiter circuit 20 may further include a rearrangement timer circuit 40 . Refresh timer circuit 40 implements the self-resetting function of the refresh operation. Specifically, the reordering timer circuit 40 is triggered by the output signal of the metastable control filter 30 or the data output signal Q of the D-type flip-flop 36 . The reorder timer circuit 40 generates an end reorder signal END_REF (node 42 ) coupled to one of the reset terminals of the D-type flip-flop 36 . Thus, in response to asserting the reorganization access grant signal GRANT_REF, the reorganization timer circuit 40 is triggered and asserts the end reorganization signal END_REF after a given duration. D flip-flop 36 resets the reorder access grant signal GRANT_REF (or data output signal 38 ), and terminates the reorder operation. By using the reorder timer circuit 40, the arbiter circuit 20 ensures a stable reorder operation by ensuring that the reorder access grant signal GRANT_REF is asserted for a sufficient duration to complete the reorder operation.

FIG. 5 is a timing diagram illustrating the arbiter circuit of FIG. 4 operating in a PSRAM device in an embodiment of the present invention. Referring to FIG. 5 , the normal access request signal REQ_NOM (curve 72 ) and the rearrangement access request signal REQ_REF (curve 74 ) belong to different frequency domains and may arrive before or after other signals. When the signal REQ_NOM (curve 72 ) is earlier than the signal REQ_REF (curve 74 ), the first arbiter circuit 25 generates an arbitrated signal ARB (curve 76 ) with no signal transitions. The delayed signal (plot 78 ) also has no signal transitions, and metastable control filter 30 generates a reorder access grant signal GRANT_REF (plot 82 ) at a logic low state (deasserted). The normal access grant signal GRANT_NOM (curve 84 ) is at a logic high state (asserted), and the arbiter circuit 20 grants the normal access request.

On the other hand, when the rearrangement access request signal REQ_REF is earlier than the normal access request signal REQ_NOM, the first arbiter circuit 25 generates the arbitrated signal ARB with one pulse in response to the rearrangement access request signal REQ_REF. The one-way delay circuit 34 of the metastable control filter 30 applies a delay to the leading edge of the pulse and no delay to the trailing edge of the pulse. Therefore, the D-type flip-flop 36 clocks the arbitrated signal ARB as the data output signal Q at the leading edge of the delayed signal. Thus, the rearrangement access grant signal GRANT_REF is asserted (logic high) and the normal access grant signal GRANT_NOM is deasserted (logic low). At the leading edge of the reorder access grant signal GRANT_REF, the reorder duration at the reorder timer circuit 40 is triggered. At the end of the reorder duration, the end reorder signal END_REF is asserted (plot 80 ) and the reorder access grant signal GRANT_REF is deasserted, wherein the normal access grant signal GRANT_NOM is asserted.

In some cases, the command signals REQ_NOM and REQ_REF may arrive at approximately the same time or within a closed timing window of one of the other. In this case, the first arbiter circuit 25 may generate an arbitrated signal ARB that is destroyed or has a shortened pulse width. For example, the first arbiter circuit 25 may generate a short fault as the arbitrated signal ARB. The short fault ARB signal is not expected to be used as a reorder access grant signal because short faults do not provide enough time for the reorder operation and thus may cause the PSRAM device to fail because the dynamic memory cells are not reordered as needed. PSRAM devices include DRAM memory cell structures that require a constant amount of time to write, read, and rearrange correctly. Refresh operations are important due to the destructive nature of reading from DRAM memory cells. Therefore, it is undesirable to reorder a short glitch in the access grant signal as it may lead to insufficient reordering of PSRAM memory cells. Therefore, elimination of short glitch waveforms from PSRAM operation is critical to the reliability and performance of PSRAM devices.

Therefore, in an embodiment of the present invention, the metastable control filter 30 uses a one-way delay circuit 34 to eliminate short-fault ARB signals. In particular, the leading edge of the short fault ARB signal is delayed, and when the delayed edge passes the trailing edge, the one-way delay circuit 34 will cancel the signal and no signal transition occurs on the delayed signal. When there is no clock signal at the D-type flip-flop 36, the rearrangement access grant signal GRANT_REF remains at a logic low (deasserted), and the normal access grant signal GRANT_NOM remains at a logic high (asserted). No PSRAM defragmentation operation started.

In another example, when the command signals REQ_NOM and REQ_REF can arrive almost simultaneously, the first arbiter circuit 25 can generate an arbitrated signal ARB with distortion delay. Distorted delayed signals can be a problem for high speed applications, although they are acceptable for non-speed critical applications. In either case, one-way delay circuit 34 of metastable control filter 30 applies a delay to the leading edge of arbitrated signal ARB and no delay to the trailing edge of arbitrated signal ARB. The one-way delay circuit 34 also restores the amplitude of the arbitrated signal ARB to generate a delayed signal having a delayed leading edge and restored waveform. The delayed signal is used as a clock signal to clock the arbitrated signal ARB. Therefore, the D-type flip-flop 36 clocks the arbitrated signal ARB as the data output signal Q at the leading edge of the delayed signal. Thus, the rearrangement access grant signal GRANT_REF is asserted (logic high) and the normal access grant signal GRANT_NOM is deasserted (logic low). At the leading edge of the reorder access grant signal GRANT_REF, the reorder duration at the reorder timer circuit 40 is triggered. At the end of the reorder duration, the end reorder signal END_REF is asserted and the reorder access grant signal GRANT_REF is deasserted, wherein the normal access grant signal GRANT_NOM is asserted.

FIG. 6 and FIG. 7 respectively show the resolution time comparison between the conventional arbiter circuit and the arbiter circuit of the present invention, the metastability window and the rearrangement access request time. As discussed above, FIG. 6 is, in some examples, a plot of the output access time versus the arrival time of a reorder request for a conventional arbiter circuit. FIG. 7 is a plot of output access time versus reorder request arrival time for the arbiter circuit of FIG. 4 in an embodiment of the present invention.

Referring to FIG. 6, conventional arbitrators have a resolution time tR determined by system performance and associated metastable windows. In the conventional case, the metastable window 54 is large. Referring to FIG. 7, it is assumed that the normal access request signal REQ_NOM has an arrival time indicated by line 56, and the x-axis represents the arrival time of the rearrangement access request signal REQ_REF. The metastable window 58 is the period of time that two signals arrive within a given time of each other. Curve 55 depicts the output access time of the arbiter circuit, also referred to as resolution time. The arbiter circuit of the present invention is able to reduce the metastable window 58 to be very narrow. Although fault cancellation using one-way delays increases the normal clock output time tCO by an amount of delay, the increase in normal clock output time tCO is tolerated because the metastable window 58 is several orders of magnitude smaller. Specifically, the use of the first arbiter and the second arbiter in the arbiter circuit of the present invention tightens the metastable window, making the chance of arbitration failure less and MTBF increased by several orders of magnitude.

The present invention can be implemented in many forms, including a composition as a program, device, system and/or element. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of steps of disclosed processes may be altered within the scope of the invention.

A detailed description of one or more embodiments of the invention has been presented above along with accompanying figures that illustrate the principles of the invention. The invention is described in conjunction with these embodiments, but the invention is not limited to any embodiment. The scope of the present invention is only limited by the patent scope of the invention, and the present invention covers many alternatives, modifications and equivalents. The description sets forth numerous specific details in order to provide a thorough understanding of the present invention. These details are illustrative only and the invention may be practiced as claimed in the invention without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.

The foregoing detailed description has been provided to illustrate particular embodiments of the invention and is not intended to be limiting. Many modifications and variations can be made within the scope of the invention. The present invention is defined by the claims of the accompanying invention claims.

1: Arbiter circuit 2: NAND logic gate 3: NAND logic gate 4: node 5: node 6: Inverter 7: Inverter 8: node 9: node 20: Arbiter circuit 22: Inverter 24: node 25: The first arbiter 30: Metastable control filter 32: node 34: One-way delay circuit 35: Output node 36: D type flip-flop 38: Node/data output signal 40: Rearranging the Timer Circuit 42: node 45: Mean time between failure (MTBF) program circuit 50: curve 52: line 54:Metastable window 55: curve 56: line 58:Metastable window 62: curve 64: curve 66: curve 68: curve 72: curve 74: curve 76: curve 78: curve 80: curve 82: curve 84: curve 100: Pseudo-static random access memory (PSRAM) device 102: Command and address control circuit 104: Internal rearrangement control circuit 106: External column access control circuit 108: row access control circuit 110: Arbiter circuit 112: Write and read control circuit 114: word line decoder 120: memory array 122: Row Select/Sense Amplifier/Write Driver Circuit 123: Input/Output (I/O) Bus 124: I/O circuit

Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings.

FIG. 1 is a schematic diagram of a PSRAM device in an embodiment of the present invention.

2 is a circuit diagram illustrating a conventional arbiter circuit that may be used in a conventional PSRAM in some examples.

FIG. 3 is a timing diagram illustrating the operation of the conventional arbiter circuit of FIG. 2 in some examples.

FIG. 4 is a schematic diagram illustrating an arbiter circuit that may be incorporated into a PSRAM device in an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating the arbiter circuit of FIG. 4 operating in a PSRAM device in an embodiment of the present invention.

Figure 6 is a plot of output access time versus arrival time of a reorder request for a conventional arbiter circuit in some examples.

FIG. 7 is a plot of output access time versus reorder request arrival time for the arbiter circuit of FIG. 4 in an embodiment of the present invention.

100: Pseudo-static random access memory (PSRAM) device

102: Command and address control circuit

104: Internal rearrangement control circuit

106: External column access control circuit

108: row access control circuit

110: Arbiter circuit

112: Write and read control circuit

114: word line decoder

120: memory array

122: Row Select/Sense Amplifier/Write Driver Circuit

123: Input/Output (I/O) Bus

124: I/O circuit

Claims (20)

An arbitration control circuit in a pseudo-static random access memory (PSRAM) device, the arbitration control circuit includes: A set-reset (SR) latch circuit receiving a first input signal and a second input signal, the first input signal indicating a read or write access to a memory cell of the PSRAM device requesting a normal access request signal, the second input signal indicating a reordering access request signal of a reordering access request to memory cells of the PSRAM device, the SR latch circuit responding to the first A logical operation of the input signal and the second input signal produces a first output signal responsive to asserting the first input signal prior to asserting the second input signal without a signal transition or in response to asserting the first input signal with two or more signal transitions after or concurrently with asserting the second input signal; a unidirectional delay circuit having an input terminal receiving the first output signal and introducing a first delay to a leading signal transition of the first output signal to produce a delayed signal at an output terminal, the delayed a signal responsive to the first output signal having no signal transition or having a pulse width shorter than the first delay without having a signal transition; and A D-type flip-flop circuit, which has a data input terminal for receiving the first output signal, a clock input terminal for receiving the delayed signal, a reset input terminal for receiving a reset signal, and a terminal for providing a second output signal an output terminal, the second output signal has a first logic state in response to the delayed signal having no signal transition and has a second logic state in response to a signal transition of the delayed signal, the second output signal maintaining the second logic state until asserting the reset signal to reset the second output signal to the first logic state, wherein the second output signal has a first logic state indicative of granting the read or write access request and a second logic state indicative of the reorder access request granted to the memory cells of the PSRAM device . The arbitration control circuit of claim 1, wherein the one-way delay circuit generates the delayed signal having a leading signal transition and a trailing signal transition, the leading signal transition being the first output signal delayed by the first delay The leading signal transition and the trailing signal transition are trailing signal transitions of the first output signal without delay. The arbitration control circuit of claim 2, wherein the delayed signal responds to the leading signal transition of the delayed signal occurring after the trailing signal transition of the delayed signal without a signal transition. The arbitration control circuit of claim 2, wherein the leading signal transition of the delayed signal includes a rising edge, and the trailing signal transition of the delayed signal includes a falling edge. The arbitration control circuit of claim 1, wherein the first delay is programmable to achieve a predetermined resolution time of the PSRAM device. As the arbitration control circuit of claim 1, it further includes: A reorder timer circuit having an input terminal receiving the second output signal and an output terminal providing the reset signal to the D-type flip-flop circuit, wherein the reorder timer circuit is on the second asserting the reset signal for a first duration after a preamble transition is detected on the output signal, wherein the reset signal is coupled to the reset terminal of the D-type flip-flop for the second output signal reset to the first logic state. The arbitration control circuit of claim 5, wherein the first duration includes a duration for completing a rearrangement operation of the memory cells in the PSRAM device. The arbitration control circuit of claim 1, wherein the second output signal is provided coupled to a rearrangement control circuit to grant the rearrangement control circuit access to the memory cells of the PSRAM device for a rearrangement operation a rearrangement access grant signal, and an inversion of the second output signal is provided coupled to a normal control circuit to grant the normal control circuit access to the memory cells of the PSRAM device for reading One of the normal access grant signals for a fetch or write operation. The arbitration control circuit of claim 1, wherein the SR latch circuit includes a NAND latch circuit, and the NAND latch circuit includes: A first NAND logic gate connected in series with a first inverter, the first NAND logic gate having a first input terminal receiving the first input signal, a second input terminal and coupled to the first inverter an output terminal of a phase device, the first input signal being the normal access request signal; and A second NAND logic gate connected in series with a second inverter, the second NAND logic gate having a first input terminal receiving the second input signal, a second input terminal and coupled to the second inverter One output terminal of the phase device, the second input signal is the rearrangement access request signal, wherein the second input terminal of the first NAND logic gate is coupled to the output terminal of the second NAND logic gate; and the second input terminal of the second NAND logic gate is coupled to the output of the first NAND logic gate terminals; and Wherein the second inverter provides the first output signal. The arbitration control circuit of claim 1, wherein the normal access request signal indicating the read or write access request to the memory cell of the PSRAM device is derived from a signal outside the PSRAM device, and indicates the The reorder access request signal of the reorder access request for memory cells of a PSRAM device is a signal generated within the PSRAM device. A method for providing arbitration control in a pseudo-static random access memory (PSRAM) device, the method comprising: receiving a first input signal indicating a normal access request signal for a read or write access request to a memory cell of the PSRAM device; receiving a second input signal, the second input signal being a reorder access request signal indicative of a reorder access request to a memory cell of the PSRAM device; generating a first output signal in response to a logical operation of the first input signal and the second input signal, the first output signal responsive to asserting the first input signal without asserting the second input signal prior to asserting the second input signal transitioning or having two or more signal transitions in response to asserting the first input signal after or concurrently with asserting the second input signal; generating a delayed signal having a leading signal transition a first delay after a leading signal transition of the first output signal, the delayed signal responding to the first output signal having a delay greater than the first delay short pulse width without signal transitions; generating a second output signal having a first logic state in response to the delayed signal having no signal transition and having a second logic state in response to receipt of the first signal transition on the delayed signal state, the second output signal maintains the second logic state until reset to the first logic state, wherein the second output signal has a first logic state indicative of granting the read or write access request and a second logic state indicative of the reorder access request granted to the memory cells of the PSRAM device . The method of claim 11, wherein generating the delayed signal comprises: generating the delayed signal having the leading signal transition of the first output signal delayed by the first delay and a trailing signal transition that is not delayed A trailing signal transition of the first output signal. The method of claim 12, wherein generating the delayed signal comprises: The delayed signal is generated without signal transitions in response to the leading signal transition occurring after the trailing signal transition in response to the delayed signal. The method of claim 12, wherein the leading signal transition of the delayed signal includes a rising edge, and the trailing signal transition of the delayed signal includes a falling edge. The method of claim 11, wherein the first delay is programmable to achieve a given resolution time of the PSRAM device. The method as claimed in item 11, further comprising: The second output signal is reset to the first logic state after a first duration in response to the second output signal being in the second logic state. The method of claim 16, wherein the first duration includes a duration for completing a rearrangement operation of the memory cells in the PSRAM device. The method as claimed in item 11, further comprising: providing the second output signal having the first logic state as a normal access grant signal to grant access to the memory cells of the PSRAM device for read or write operations; and The second output signal having the second logic state is provided as a reorder access grant signal to grant reorder operation access to the memory cells of the PSRAM device. The method of claim 11, wherein generating the first output signal comprises: The first output signal is generated using a NAND latch circuit comprising a pair of cross-coupled NAND logic gates, each NAND logic gate receiving a respective first input signal and a second input signal, the first output signal receiving the second input signal inverts one of the output signals of the NAND logic gate. The method of claim 11, wherein the normal access request signal indicating the read or write access request to the memory cell of the PSRAM device is derived from a signal external to the PSRAM device, and indicates the PSRAM device The reorder access request signal of the reorder access request for the memory cell is a signal generated within the PSRAM device.

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