TWI754569B - Arbitration control for pseudostatic random access memory device - Google Patents
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本發明係關於偽靜態隨機存取記憶體(PSRAM)裝置之控制操作,且特定言之,係關於在一PSRAM裝置中提供仲裁控制以在同時外部及內部存取請求期間抑制及消除亞穩態。The present invention relates to the control operation of pseudo-static random access memory (PSRAM) devices, and in particular, to providing arbitration control in a PSRAM device to suppress and eliminate metastability during simultaneous external and internal access requests .
一偽靜態隨機存取記憶體(PSRAM)係其內部結構為一動態隨機存取記憶體(DRAM)之一隨機存取記憶體,其中重新整理控制信號經內部產生使得其可模擬一靜態隨機存取記憶體(SRAM)之功能。與所謂之自重新整理DRAM裝置不同,PSRAM裝置具有類似於SRAM裝置之非多工位址線及引出線之非多工地址線及引出線。一PSRAM裝置併入晶片上重新整理及控制電路(例如重新整理位址計數器及多工器、重新整理間隔計時器、仲裁器)。此等電路容許PSRAM操作特性與SRAM之操作特性非常相似。以此方式,一PSRAM裝置組合DRAM之高密度與一真SRAM之易用性。A pseudo static random access memory (PSRAM) is a random access memory whose internal structure is a dynamic random access memory (DRAM), in which the rearrangement control signals are internally generated so that it can simulate a static random access memory Take the function of memory (SRAM). Unlike so-called self-rearranged DRAM devices, PSRAM devices have non-multiplexed address lines and pinouts similar to those of SRAM devices. A PSRAM device incorporates on-chip refresh and control circuitry (eg, refresh address counters and multiplexers, refresh interval timers, arbiters). These circuits allow PSRAM operating characteristics to be very similar to those of SRAMs. In this way, a PSRAM device combines the high density of DRAM with the ease of use of a true SRAM.
PSRAM可與具有「自重新整理模式」之DRAM區別,其中自重新整理模式主要用於待機模式中以容許一主機系統暫停一外部DRAM控制器之操作以節省電力而不丟失儲存於DRAM中之資料。當沒有控制信號自外部DRAM控制器接收時,自重新整理模式在待機模式期間重新整理DRAM資料。PSRAM裝置在操作中無需一外部DRAM控制器且包含內置重新整理控制以容許PSRAM表現得像一SRAM。PSRAM can be distinguished from DRAM with a "self-refresh mode" that is primarily used in standby mode to allow a host system to suspend the operation of an external DRAM controller to save power without losing data stored in DRAM . The self-refresh mode refreshes DRAM data during standby mode when no control signals are received from the external DRAM controller. PSRAM devices operate without an external DRAM controller and include built-in rearrangement controls to allow PSRAM to behave like a SRAM.
在操作中,PSRAM裝置回應於在PSRAM外部接收之讀取/寫入請求而執行讀取及寫入操作,且在讀取或寫入操作之間執行記憶體單元重新整理。PSRAM裝置包含一計數器以產生內部重新整理請求。因此,讀取/寫入請求及重新整理請求在不同頻域上操作。因此,當外部讀取/寫入請求在發出內部重新整理請求之相同時間到達時,讀取/寫入請求與重新整理請求之間可能存在衝突。In operation, the PSRAM device performs read and write operations in response to read/write requests received outside the PSRAM, and performs memory cell rearrangements between read or write operations. The PSRAM device includes a counter to generate internal refresh requests. Therefore, read/write requests and refresh requests operate on different frequency domains. Therefore, when the external read/write request arrives at the same time as the internal refresh request, there may be a conflict between the read/write request and the refresh request.
根據本申請案之一個實施例,提供一種一偽靜態隨機存取記憶體(PSRAM)裝置中之仲裁控制電路,該仲裁控制電路包括:一設定-重設(SR)鎖存電路,其接收一第一輸入信號及一第二輸入信號,該第一輸入信號係指示對該PSRAM裝置之記憶體單元之一讀取或寫入存取請求之一正常存取請求信號,該第二輸入信號係指示對該PSRAM裝置之記憶體單元之一重新整理存取請求之一重新整理存取請求信號,該SR鎖存電路回應於該第一輸入信號與該第二輸入信號之一邏輯運算而產生一第一輸出信號,該第一輸出信號回應於在確證該第二輸入信號之前確證該第一輸入信號而不具有信號轉變,或回應於在確證該第二輸入信號之後或與確證該第二輸入信號同時地確證該第一輸入信號而具有兩次或更多次信號轉變;一單向延遲電路,其具有接收該第一輸出信號之一輸入端子且將一第一延遲引入至該第一輸出信號之一前導信號轉變以在一輸出端子上產生一經延遲信號,該經延遲信號回應於該第一輸出信號不具有信號轉變或具有比該第一延遲短之一脈寬而不具有信號轉變;及一D型正反器電路,其具有接收該第一輸出信號之一資料輸入端子、接收該經延遲信號之一時脈輸入端子、接收一重設信號之一重設輸入端子及提供一第二輸出信號之一輸出端子,該第二輸出信號回應於該經延遲信號不具有信號轉變而具有一第一邏輯狀態及回應於該經延遲信號中之一信號轉變而具有一第二邏輯狀態,該第二輸出信號保持該第二邏輯狀態直至確證該重設信號以將該第二輸出信號重設至該第一邏輯狀態,其中該第二輸出信號具有指示授予該讀取或寫入存取請求之一第一邏輯狀態及指示授予對該PSRAM裝置之該等記憶體單元之該重新整理存取請求之一第二邏輯狀態。According to an embodiment of the present application, there is provided an arbitration control circuit in a pseudo static random access memory (PSRAM) device, the arbitration control circuit comprising: a set-reset (SR) latch circuit that receives a a first input signal, a normal access request signal indicating a read or write access request to a memory cell of the PSRAM device, and a second input signal, the second input signal A rearrangement access request signal indicating a rearrangement access request of a memory cell of the PSRAM device, the SR latch circuit generates a rearrangement access request signal in response to a logical operation of the first input signal and the second input signal a first output signal responsive to asserting the first input signal without a signal transition prior to asserting the second input signal, or in response to asserting the second input signal after or with asserting the second input a signal simultaneously asserting the first input signal with two or more signal transitions; a one-way delay circuit having an input terminal that receives the first output signal and introduces a first delay to the first output a leading signal transition of the signal to generate a delayed signal on an output terminal, the delayed signal having no signal transition or having a pulse width shorter than the first delay without a signal transition in response to the first output signal; and a D-type flip-flop circuit, which has a data input terminal for receiving the first output signal, a clock input terminal for receiving the delayed signal, a reset input terminal for receiving a reset signal, and a second output signal an output terminal, the second output signal has a first logic state in response to the delayed signal having no signal transition and a second logic state in response to a signal transition in the delayed signal, the second logic state The output signal maintains the second logic state until the reset signal is asserted to reset the second output signal to the first logic state, wherein the second output signal has one of indicating that the read or write access request is granted The first logic state and a second logic state indicating the refresh access request granted to the memory cells of the PSRAM device.
根據本申請案之另一實施例,提供一種在一偽靜態隨機存取記憶體(PSRAM)裝置中用於提供仲裁控制之方法,該方法包括:接收一第一輸入信號,該第一輸入信號係指示對該PSRAM裝置之記憶體單元之讀取或寫入存取請求之一正常存取請求信號;接收一第二輸入信號,該第二輸入信號係指示對該PSRAM裝置之記憶體單元之重新整理存取請求之一重新整理存取請求信號;回應於該第一輸入信號與該第二輸入信號之一邏輯運算而產生一第一輸出信號,該第一輸出信號回應於在確證該第二輸入信號之前確證該第一輸入信號而不具有信號轉變,或回應於在確證該第二輸入信號之後或與確證該第二輸入信號同時地確證該第一輸入信號而具有兩次或更多次信號轉變;產生具有一前導信號轉變之一經延遲信號,該前導信號轉變係該第一輸出信號之一前導信號轉變之後的一第一延遲,該經延遲信號回應於該第一輸出信號具有比該第一延遲短之一脈寬而不具有信號轉變;產生一第二輸出信號,該第二輸出信號回應於該經延遲信號不具有信號轉變而具有一第一邏輯狀態及回應於該經延遲信號上之該第一信號轉變接收而具有一第二邏輯狀態,該第二輸出信號保持該第二邏輯狀直至被重設至該第一邏輯狀態,其中該第二輸出信號具有指示授予該讀取或寫入存取請求之一第一邏輯狀態及指示授予對該PSRAM裝置之該等記憶體單元之該重新整理存取請求之一第二邏輯狀態。According to another embodiment of the present application, there is provided a method for providing arbitration control in a pseudo static random access memory (PSRAM) device, the method comprising: receiving a first input signal, the first input signal is a normal access request signal indicating a read or write access request to the memory cell of the PSRAM device; receives a second input signal indicating the memory cell of the PSRAM device A rearrangement access request signal is one of the rearrangement access requests; a first output signal is generated in response to a logical operation of the first input signal and the second input signal, the first output signal is responsive to confirming the first output signal The first input signal is asserted before two input signals without a signal transition, or in response to asserting the first input signal after or concurrently with asserting the second input signal with two or more times secondary signal transition; generating a delayed signal having a leading signal transition that is a first delay after a leading signal transition of the first output signal, the delayed signal responsive to the first output signal having a ratio of The first delay is one pulse width short without signal transitions; generating a second output signal having a first logic state in response to the delayed signal having no signal transitions and in response to the delayed signal The first signal on the signal transitions received to have a second logic state, the second output signal maintains the second logic state until reset to the first logic state, wherein the second output signal has an indication that the read is granted A first logic state for a fetch or write access request and a second logic state indicating the refresh access request granted to the memory cells of the PSRAM device.
在本發明之實施例中,一偽靜態隨機存取記憶體(PSRAM)裝置中之一仲裁控制電路併入串聯連接至接收正常(讀取/寫入)及重新整理存取請求信號之一SR鎖存電路之輸出之一亞穩態控制濾波器。仲裁控制電路產生存取授予信號以授予正常(讀取/寫入)請求或重新整理請求。當同時確證外部讀取/寫入存取請求及內部重新整理存取請求時,仲裁控制電路操作以抑制及消除可導致PSRAM操作失效之亞穩態風險。在一些實施例中,仲裁控制電路之亞穩態控制濾波器包含用於消除SR鎖存電路輸出信號中之非想要短故障之一單向延遲電路及充當至充當第一仲裁器之SR鎖存電路之第二仲裁器之一D型正反器電路。藉由使用兩個串聯連接之仲裁器,PSRAM裝置之亞穩態之概率降低幾個數量級。在一些實施例中,由單向延遲電路引入之延遲可調諧以達成PSRAM裝置之期望解析時間及目標平均失效間隔時間(MTBF)要求。In an embodiment of the present invention, an arbitration control circuit in a pseudo static random access memory (PSRAM) device is incorporated in series connected to an SR that receives normal (read/write) and refresh access request signals The output of the latch circuit is a metastable control filter. The arbitration control circuit generates an access grant signal to grant a normal (read/write) request or a refresh request. When both external read/write access requests and internal rearrangement access requests are validated simultaneously, the arbitration control circuit operates to suppress and eliminate the risk of metastability that can cause PSRAM operation to fail. In some embodiments, the metastable control filter of the arbitration control circuit includes a one-way delay circuit for eliminating undesired short faults in the output signal of the SR latch circuit and the SR latch that acts as the first arbiter One of the second arbiters of the storage circuit is a D-type flip-flop circuit. By using two arbiters connected in series, the probability of metastability of PSRAM devices is reduced by orders of magnitude. In some embodiments, the delay introduced by the one-way delay circuit is tunable to achieve the desired resolution time and target mean time between failures (MTBF) requirements of the PSRAM device.
在一些實施例中,一重新整理計時器電路耦合至D型正反器電路以在一給定持續時間之後重設重新整理存取授予信號。以此方式,仲裁控制電路確保重新整理存取授予信號具有一最小持續時間以保證穩定重新整理操作。In some embodiments, a refresh timer circuit is coupled to the D-type flip-flop circuit to reset the refresh access grant signal after a given duration. In this way, the arbitration control circuit ensures that the refresh access grant signal has a minimum duration to ensure stable refresh operation.
圖1係繪示本發明之實施例中之一PSRAM裝置之一示意圖。如上文描述,一偽靜態隨機存取記憶體(PSRAM)係包含DRAM型記憶體單元及內置重新整理控制以模擬一靜態隨機存取記憶體(SRAM)之功能之一隨機存取記憶體。參考圖1,PSRAM裝置100包含動態記憶體單元之一記憶體陣列120。各動態記憶體單元包含連接至一儲存電容器C之一單個存取電晶體T。記憶體陣列經組織為二維陣列,且各動態記憶體單元由一字線WL及一位元線BL存取。FIG. 1 is a schematic diagram illustrating a PSRAM device in an embodiment of the present invention. As described above, a pseudo static random access memory (PSRAM) is a random access memory that includes DRAM-type memory cells and built-in rearrangement controls to simulate the functions of a static random access memory (SRAM). Referring to FIG. 1, a
PSRAM裝置100包含一命令及位址控制電路102以接收包含時脈信號、晶片選擇信號CE、寫入啟用信號WE及記憶體單元位址ADDR之輸入控制信號。一輸入/輸出(I/O)電路124接收及提供記憶體資料。即,將寫入至記憶體單元之記憶體資料提供至I/O電路124,且將自記憶體單元讀出之記憶體資料作為輸出信號提供於I/O電路124上。The
PSRAM裝置100接收寫入啟用信號WE以指示將在輸入位址ADDR處執行一寫入操作或一讀取操作。在本實例中,寫入啟用信號WE係一有源低信號(表示為/WE)。寫入啟用信號/WE經確證為一邏輯高以啟動一讀取操作及經確證為一邏輯低以啟動一寫入操作。命令及位址控制電路102產生提供至一寫入及讀取控制電路112之一控制信號Control。寫入及讀取控制電路112產生控制信號以控制I/O電路124接收傳入記憶體寫入資料或提供傳出記憶體讀出資料。The
命令及位址控制電路102對輸入位址ADDR解碼且產生用於定址字線WL之一列位址RADDR及用於定址位元線之行位址CADDR。行位址CADDR經提供至一行存取控制電路108,行存取控制電路108經耦合以控制行選擇/感測放大器/寫入驅動器電路122。行位址CADDR用於啟動一選定行。針對讀取操作,用於選定行之位元線經預充電且感測放大器自選定記憶體單元讀出記憶體資料,且讀出儲存透過I/O匯流排123提供至I/O電路124。針對寫入操作,寫入驅動器將選定行之位元線驅動至自I/O電路124接收且在I/O匯流排123上傳遞至寫入驅動器之寫入資料。Command and
同時,列位址RADDR經提供至一外部列存取控制電路106。外部列存取控制電路106回應於自命令及位址控制電路102接收之一列位址RADDR而產生一正常存取請求REQ_NOM。在本描述中,當讀取及寫入操作在PSRAM裝置外部啟動時,對PSRAM裝置100之讀取或寫入操作指稱外部請求或外部存取或外部存取請求。在本描述中,對PSRAM裝置100之外部存取請求亦指稱正常存取請求或正常請求以意指針對正常PSRAM操作(即,讀取及寫入操作)作出之存取請求。At the same time, the column address RADDR is provided to an external column
PSRAM裝置包含內置重新整理電路以執行記憶體陣列120中之動態記憶體單元之重新整理操作。在本描述中,當重新整理操作在PSRAM裝置內部啟動時,內置重新整理操作指稱內部請求或內部存取或內部存取請求。在本描述中,PSRAM裝置100中之內部存取請求亦指稱重新整理存取請求或重新整理請求以意指針對記憶體單元重新整理操作作出之存取請求。為此,PSRAM裝置100包含一內部重新整理控制電路104以產生用於啟動記憶體陣列120之一重新整理操作之一內部重新整理存取請求REQ_REF。舉例而言,內部重新整理控制電路104可包含經組態以回應於計數器達到一某個值或一給定持續時間已發生而產生一重新整理存取請求REQ_REF之一計數器或一計時器電路。PSRAM devices include built-in rearrangement circuitry to perform rearrangement operations for dynamic memory cells in
正常存取請求REQ_NOM及重新整理存取請求REQ_REF係在不同頻域上操作之信號。即,正常存取請求REQ_NOM及重新整理存取請求REQ_REF不在相同時脈頻率或相關時脈頻率上操作。因此,當正常存取請求REQ_NOM及重新整理存取請求REQ_REF想要同時存取字線時,兩個請求有時經歷衝突。在操作中,僅一個請求(正常或重新整理)可存取字線。因此,正常存取請求信號REQ_NOM及重新整理存取請求信號REQ_REF耦合至仲裁器電路110,仲裁器電路110操作以確定應授予哪個存取請求。The normal access request REQ_NOM and the rearrangement access request REQ_REF are signals operating in different frequency domains. That is, the normal access request REQ_NOM and the refresh access request REQ_REF do not operate at the same clock frequency or related clock frequencies. Therefore, when the normal access request REQ_NOM and the rearrangement access request REQ_REF want to access a word line at the same time, the two requests sometimes experience conflict. In operation, only one request (normal or refresh) can access a word line. Therefore, the normal access request signal REQ_NOM and the rearrangement access request signal REQ_REF are coupled to the
當授予外部存取請求時,仲裁器110確證提供至外部列存取控制電路106之正常存取授予信號GRANT_NOM。作為回應,外部列存取控制電路106產生提供至一字線解碼器114之一正常列地址(「正常RADDR」)。當授予重新整理存取請求時,仲裁器110確證提供至內部重新整理控制電路104之重新整理存取授予信號GRANT_REF。作為回應,內部重新整理控制電路104產生提供至字線解碼器114之一重新整理列地址(「重新整理RADDR」)。字線解碼器114對列位址(重新整理列位址或正常列位址)解碼且啟動記憶體陣列120中之選定字線信號用於各自讀取、寫入或重新整理操作。When an external access request is granted, the
在數位電路設計中,不同時脈頻率常用於電路內且不同時脈頻率必須同步。然而,任何種類之同步將不可避免地導致亞穩態失效且亞穩態失效趨向於隨時脈頻率增大而增加,特別係高性能及低電力設計趨勢。在圖1之PSRAM裝置100中,仲裁器110經組態以仲裁外部存取請求與內部存取請求以確保PSRAM裝置之穩定及可靠性能。在本發明之實施例中,仲裁器110 (在本發明中亦指稱一仲裁控制電路)併入串聯連接至接收正常及重新整理存取請求信號之SR鎖存電路之輸出之一亞穩態控制濾波器。當經如此組態時,仲裁器110抑制及消除PSRAM裝置100之亞穩態風險。此外,仲裁器110中之亞穩態控制濾波器可調諧以使PSRAM裝置能夠達成目標平均失效間隔時間(MTBF),同時將乾淨存取授予信號提供至各自列位址控制電路。本發明之仲裁器110藉由最小化時脈輸出時間來最小化速度損失,同時亞穩態控制濾波器中之額外仲裁器電路將亞穩態風險之概率降低幾個數量級。下文將更詳細描述亞穩態控制濾波器之細節。In digital circuit design, different clock frequencies are often used in the circuit and the different clock frequencies must be synchronized. However, synchronization of any kind will inevitably lead to metastable failures and metastable failures tend to increase with increasing pulse frequency, especially for high performance and low power designs. In the PSRAM
圖2係繪示在一些實例中可用於一習知PSRAM中之一習知仲裁器電路之一電路圖。參考圖2,用於同時仲裁來自外部請求及內部請求之傳入命令之一習知方法係使用一設定-重設鎖存電路,諸如一NAND鎖存電路或一NOR鎖存電路。圖2繪示使用一對交叉耦合之NAND邏輯閘2及3實施為一NAND鎖存電路之一仲裁器電路1。為在正常存取請求信號REQ_NOM與重新整理存取請求信號REQ_REF之間進行仲裁,NAND邏輯閘2接收正常存取請求信號REQ_NOM及NAND邏輯閘3之輸出信號(節點5),且NAND邏輯閘3接收重新整理存取請求信號REQ_REF及NAND邏輯閘2之輸出信號(節點4)。正常存取授予信號GRANT_NOM (節點8)係NAND邏輯閘2之輸出信號(節點4)之反相,諸如由反相器6反相。重新整理存取授予信號GRANT_REF (節點9)係NAND邏輯閘3之輸出信號(節點5)之反相,例如由反相器7反相。FIG. 2 shows a circuit diagram of a conventional arbiter circuit that may be used in a conventional PSRAM in some examples. Referring to FIG. 2, one conventional method for arbitrating incoming commands from external and internal requests simultaneously uses a set-reset latch circuit, such as a NAND latch circuit or a NOR latch circuit. Figure 2 illustrates an arbiter circuit 1 implemented as a NAND latch circuit using a pair of
圖3係繪示在一些實例中操作圖2之習知仲裁器電路之一時序圖。正常存取請求信號REQ_NOM及重新整理存取請求信號REQ_REF係屬於不同頻域之兩個命令信號。當信號REQ_NOM (曲線62)早於信號REQ_REF (曲線64)時,仲裁器電路1授予正常存取請求且確證信號GRANT_NOM (曲線66)。同時,當信號REQ_REF早於信號REQ_NOM時,仲裁器電路1授予重新整理存取請求且確證信號GRANT_REF (曲線68)。然而,當命令信號REQ_NOM及REQ_REF兩者在一亞穩態窗內幾乎同時到達時,仲裁器電路1可能在產生存取授予信號時延遲或所得存取授予信號可能失真。例如,存取授予信號可因不規則波形或縮短脈寬而毀壞。延遲或失真量取決於命令信號衝突之概率。兩個命令到達之時間越接近,發生之概率越低,但其可轉化為更長解析時間。即,當兩個命令信號一起非常接近地到達時,仲裁器電路1要花更長時間來確定授予哪個命令。FIG. 3 is a timing diagram illustrating operation of the conventional arbiter circuit of FIG. 2 in some examples. The normal access request signal REQ_NOM and the rearrangement access request signal REQ_REF are two command signals belonging to different frequency domains. When signal REQ_NOM (curve 62 ) is earlier than signal REQ_REF (curve 64 ), arbiter circuit 1 grants a normal access request and asserts signal GRANT_NOM (curve 66 ). At the same time, when the signal REQ_REF is earlier than the signal REQ_NOM, the arbiter circuit 1 grants the refresh access request and asserts the signal GRANT_REF (curve 68). However, when both the command signals REQ_NOM and REQ_REF arrive at approximately the same time within a metastability window, the arbiter circuit 1 may be delayed in generating the access grant signal or the resulting access grant signal may be distorted. For example, access grant signals can be corrupted by irregular waveforms or shortened pulse widths. The amount of delay or distortion depends on the probability of command signal collision. The closer the arrival of two commands, the lower the probability of occurrence, but this translates into longer resolution times. That is, when the two command signals arrive very close together, it takes the arbiter circuit 1 longer to determine which command to grant.
由於兩個獨立命令信號屬於不同頻域之性質,正常存取請求將在亞穩態窗內轉變之罕見概率通常由平均失效間隔時間(MTBF)之方程式描述。在本描述中,亞穩態窗指代兩個命令信號在彼此內到達之時間窗。一般而言,自失效偵測之角度看,此概率係非常罕見的,但自用戶之角度看,若假設MTBF為1年左右,則此概率可能非常常見。特定言之,平均失效間隔時間可給定為: , 其中 T w : 元窗 f c : 時脈頻率 f r : 重新整理頻率 t: 解析時間 : 解析之時間常數 Due to the nature of the two independent command signals belonging to different frequency domains, the rare probability that a normal access request will transition within the metastability window is usually described by the equation for mean time between failures (MTBF). In this description, a metastability window refers to the time window during which two command signals arrive within each other. In general, from a failure detection perspective, this probability is very rare, but from a user perspective, if the MTBF is assumed to be around 1 year, this probability may be very common. Specifically, the mean time between failures can be given as: , where Tw : meta window f c : clock frequency fr : rearrangement frequency t : resolution time : Analytical time constant
若一同步系統之MTBF不在可接受位準,則系統將失效。此對PSRAM裝置而言尤其成問題,由於動態記憶體單元之破壞性讀取性質。圖6係在一些實例中用於習知仲裁器電路之輸出存取時間與重新整理請求到達時間之一作圖。參考圖6,仲裁操作基本上比較由外部系統及內部電路操作提供之正常存取請求信號與重新整理存取請求信號。在圖6中,假設正常存取請求信號REQ_NOM具有由線52表示之一到達時間,且x軸表示重新整理存取請求信號REQ_REF之到達時間。亞穩態窗54係兩個信號在彼此之給定時間內到達之時段。曲線50描繪仲裁器電路之輸出存取時間,亦指稱解析時間。在確定亞穩態窗、時脈頻率、重新整理頻率及時間常數之後,解析時間係MTBF之對數尺度。簡單而言,在系統中選擇較低解析時間閾值tR將招致更多系統級失效。如圖6中展示,在大多數情況下,無論請求信號序列如何,習知仲裁器電路1可在正常時脈輸出時間tCO內產生存取授予信號。然而,隨著重新整理存取請求信號REQ_REF接近正常存取請求信號REQ_NOM,輸出存取時間呈指數增長,儘管發生之概率較低。在亞穩態窗內,解析時間變得非常高,大於PSRAM裝置之期望解析時間閾值tR。If the MTBF of a synchronous system is not at an acceptable level, the system will fail. This is especially problematic for PSRAM devices due to the destructive read nature of dynamic memory cells. 6 is a graph of one of output access times and refresh request arrival times for a conventional arbiter circuit in some examples. Referring to FIG. 6, the arbitration operation basically compares the normal access request signal and the rearrangement access request signal provided by the external system and internal circuit operations. In FIG. 6, it is assumed that the normal access request signal REQ_NOM has an arrival time represented by
圖4係繪示在本發明之實施例中可併入一PSRAM裝置中之一仲裁器電路之一示意圖。在一些實施例中,圖4之仲裁器電路20可用於實施圖1之PSRAM裝置100中之仲裁器110。參考圖4,仲裁器電路20 (亦指稱一仲裁控制電路)經組態以仲裁一PSRAM裝置(諸如圖1之PSRAM裝置100)中之正常存取請求信號與重新整理存取請求信號。仲裁器電路20接收正常存取請求信號REQ_NOM作為指示自PSRAM裝置外部之一主機系統接收之一命令信號之一第一輸入信號以動對PSRAM裝置之一讀取或一寫入操作。仲裁器電路20亦接收重新整理存取請求信號REQ_REF作為指示自PSRAM裝置之內部重新整理控制電路接收之一命令信號之一第二輸入信號用於啟動PSRAM裝置中之一重新整理操作。4 is a schematic diagram illustrating an arbiter circuit that may be incorporated into a PSRAM device in an embodiment of the present invention. In some embodiments, the
仲裁器電路20包含形成為一設定-重設鎖存電路之一第一仲裁器25。在本實施例中,設定-重設鎖存電路經實施為包含一對交叉耦合之NAND閘2、3及伴隨反相器6、7之一NAND鎖存電路。更具體而言,NAND邏輯閘2接收正常存取請求信號REQ_NOM及NAND邏輯閘3之輸出信號(節點5),且NAND邏輯閘3接收重新整理存取請求信號REQ_REF及NAND邏輯閘2之輸出信號(節點4)。第一仲裁器25提供自NAND邏輯閘3之輸出信號取得且由反相器7反相之一仲裁信號ARB (節點32)。在本實施例中,不使用來自NAND邏輯閘2之輸出信號,且NAND邏輯閘2之輸出端子(節點4)處之反相器6係經包含以提供NAND閘2與3之間的一平衡負載之一虛擬閘。在本發明之其他實施例中,可省略反相器6。The
第一仲裁器25在正常存取請求信號REQ_NOM與重新整理存取請求信號REQ_REF之間進行仲裁且在輸出節點32上產生經仲裁信號ARB作為一輸出信號。經仲裁信號ARB回應於正常存取請求信號在重新整理存取請求信號之前到達而不具有信號轉變。經仲裁信號ARB係回應於正常存取請求信號在重新整理存取請求信號之後到達之一信號脈衝。然而,當正常存取請求信號在重新整理存取請求信號之前或之後非常接近重新整理存取請求信號到達時,經仲裁信號ARB可具有含兩次或更多次信號轉變之一失真或毀壞波形。The
仲裁器電路20包含串聯耦合至第一仲裁器25之一亞穩態控制濾波器30。特定言之,亞穩態控制濾波器30連接至第一仲裁器之輸出節點32以接收經仲裁信號ARB且產生重新整理存取授予信號GRANT_REF (節點38)。正常存取授予信號GRANT_NOM (節點24)係重新整理存取授予信號GRANT_REF之反相,且可使用耦合至信號GRANT_REF之一反相器22產生。The
亞穩態控制濾波器30包含經耦合以接收經仲裁信號ARB之一單向延遲電路34。單向延遲電路34具有消除經仲裁信號ARB之短故障之功能。特定言之,單向延遲電路34將一延遲應用於經仲裁信號ARB之前導信號轉變且不講延遲應用於尾接信號轉變以在輸出節點35上產生一延遲信號。在經仲裁信號ARB不具有信號轉變之情況下,經延遲信號亦不具有信號轉變。當經仲裁信號ARB具有比由單向延遲電路引入之延遲短之一脈寬時,經延遲前導信號轉變發生於尾接信號轉變之後且經延遲信號不具有信號轉變。以此方式,單向延遲電路34消除只是一短故障或具有一短脈寬之經仲裁信號ARB。只有當經仲裁信號ARB具有大於延遲之一脈寬時,才會使信號ARB藉由單向延遲電路34。在一些實施例中,由單向延遲電路34提供之延遲可調諧或可程式化。例如,單向延遲電路34之延遲可經程式化為基於PSRAM裝置之MTBF之要求之一值。在圖4中,一MTBF程式電路45經展示為耦合至單向延遲電路34以程式化延遲值。MTBF程式電路45僅供繪示,且可使用其他電路及方法來調諧或程式化單向延遲電路34中之延遲值。The
亞穩態控制濾波器30進一步包含構造為一D型正反器之一第二仲裁器36。D型正反器36接收未經延遲仲裁信號ARB (節點32)作為資料輸入信號D及接收經延遲信號(節點35)作為時脈信號K,且提供一資料輸出信號Q (節點38)。D型正反器36回應於作為時脈信號之經延遲信號而將資料輸入信號D (即,未經延遲仲裁信號ARB)傳遞至資料輸出信號Q。因此,具有一短脈寬之一經仲裁信號ARB將在D型正反器處被拒絕,因為不會存在一時脈信號K。具有一足夠長脈寬之一經仲裁信號ARB將行進通過D型正反器,如由時脈信號K時控。The
在經如此構造之後,亞穩態控制濾波器30提供故障消除功能及與第一仲裁器25串聯之一第二仲裁器。具有延遲之兩個串聯連接之仲裁器之亞穩態概率大大降低。即使在數學上仍有機會出現亞穩態,但概率比使用一單個NAND鎖存器作為仲裁器之習知方案降低幾個數量級。After being so constructed, the
亞穩態控制濾波器30產生作為重新整理存取授予信號GRANT_REF提供之一輸出信號(節點38)。正常存取授予信號GRANT_NOM係重新整理存取授予信號GRANT_REF之反相。反相器22可用於使重新整理存取授予信號GRANT_REF反相以產生正常存取授予信號GRANT_NOM (節點24)。在本實施例中,重新整理存取授予信號GRANT_REF及正常存取授予信號GRANT_NOM係互補信號。在操作中,正常確證正常存取授予信號GRANT_NOM,且當確證重新整理存取授予信號GRANT_REF時,解除確證正常存取授予信號GRANT_NOM。The
在本發明之實施例中,仲裁器電路20可進一步包含一重新整理計時器電路40。重新整理計時器電路40實施重新整理操作之自重設功能。特定言之,重新整理計時器電路40由亞穩態控制濾波器30之輸出信號或D型正反器36之資料輸出信號Q觸發。重新整理計時器電路40產生耦合至D型正反器36之重設端子之一結束重新整理信號END_REF (節點42)。因此,回應於確證重新整理存取授予信號GRANT_REF,重新整理計時器電路40被觸發且在一給定持續時間之後確證結束重新整理信號END_REF。D型正反器36使重新整理存取授予信號GRANT_REF (或資料輸出信號38)重設,且終止重新整理操作。藉由使用重新整理計時器電路40,仲裁器電路20藉由確保在足夠持續時間內確證重新整理存取授予信號GRANT_REF以完成重新整理操作來確保穩定重新整理操作。In an embodiment of the present invention, the
圖5係繪示在本發明之實施例中操作一PSRAM裝置中之圖4之仲裁器電路之一時序圖。參考圖5,正常存取請求信號REQ_NOM (曲線72)及重新整理存取請求信號REQ_REF (曲線74)屬於不同頻域且可在其他信號之前或之後到達。當信號REQ_NOM (曲線72)早於信號REQ_REF (曲線74)時,第一仲裁器電路25產生不具有信號轉變之經仲裁信號ARB (曲線76)。延遲信號(曲線78)亦不具有信號轉變,且亞穩態控制濾波器30在一邏輯低狀態(解除確證)處產生一重新整理存取授予信號GRANT_REF (曲線82)。正常存取授予信號GRANT_NOM (曲線84)處於一邏輯高狀態(確證),且仲裁器電路20授予正常存取請求。5 is a timing diagram illustrating the arbiter circuit of FIG. 4 operating in a PSRAM device in an embodiment of the present invention. Referring to FIG. 5, the normal access request signal REQ_NOM (curve 72) and the refresh access request signal REQ_REF (curve 74) belong to different frequency domains and may arrive before or after other signals. When signal REQ_NOM (curve 72 ) precedes signal REQ_REF (curve 74 ),
另一方面,當重新整理存取請求信號REQ_REF早於正常存取請求信號REQ_NOM時,第一仲裁器電路25回應於重新整理存取請求信號REQ_REF而產生具有一脈衝之經仲裁信號ARB。亞穩態控制濾波器30之單向延遲電路34將一延遲應用於脈衝之前導邊緣且不將延遲應用於脈衝之尾接邊緣。因此,在經延遲信號之前導邊緣處,D型正反器36將經仲裁信號ARB時控為資料輸出信號Q。因此,確證重新整理存取授予信號GRANT_REF (邏輯高)且解除確證正常存取授予信號GRANT_NOM (邏輯低)。在重新整理存取授予信號GRANT_REF之前導邊緣處,觸發重新整理計時器電路40處之重新整理持續時間。在重新整理持續時間結束時,確證結束重新整理信號END_REF (曲線80)且解除確證重新整理存取授予信號GRANT_REF,其中確證正常存取授予信號GRANT_NOM。On the other hand, when the refresh access request signal REQ_REF is earlier than the normal access request signal REQ_NOM, the
在一些情況下,命令信號REQ_NOM及REQ_REF可幾乎同時或在彼此之一關閉計時窗內到達。在此情況下,第一仲裁器電路25可產生被毀壞或具有縮短脈寬之一經仲裁信號ARB。舉例而言,第一仲裁器電路25可產生一短故障作為經仲裁信號ARB。不期望短故障ARB信號用作重新整理存取授予信號,因為短故障無法為重新整理操作提供足夠時間且因此可能導致PSRAM裝置失效,因為動態記憶體單元沒有根據需要重新整理。PSRAM裝置包含需要固定時間量來正確寫入、讀取及重新整理之DRAM記憶體單元結構。重新整理操作很重要,由於自DRAM記憶體單元讀取之破壞性質。因此,不期望重新整理存取授予信號中之一短故障,因為其可能導致PSRAM記憶體單元之重新整理不足。因此,自PSRAM操作消除短故障波形對PSRAM裝置之可靠性及性能而言至關重要。In some cases, the command signals REQ_NOM and REQ_REF may arrive at approximately the same time or within one of each other's off timing windows. In this case, the
因此,在本發明之實施例中,亞穩態控制濾波器30使用單向延遲電路34消除短故障ARB信號。特定言之,使短故障ARB信號之前導邊緣延遲,且當經延遲邊緣藉由尾接邊緣時,單向延遲電路34將消除信號且經延遲信號上不出現信號轉變。在D型正反器36處沒有時脈信號時,重新整理存取授予信號GRANT_REF保持為一邏輯低(解除確證),而正常存取授予信號GRANT_NOM保持為一邏輯高(確證)。無PSRAM重新整理操作啟動。Therefore, in an embodiment of the present invention, the
在另一實例中,當命令信號REQ_NOM及REQ_REF可幾乎同時到達時,第一仲裁器電路25可產生具有失真延遲之一經仲裁信號ARB。失真延遲信號可能成為高速應用之一問題,儘管其對非速度臨界應用而言係可接受之。無論何種情況,亞穩態控制濾波器30之單向延遲電路34將一延遲應用於經仲裁信號ARB之前導邊緣且不將延遲應用於經仲裁信號ARB之尾接邊緣。單向延遲電路34亦恢復經仲裁信號ARB之幅度以產生具有一經延遲前導邊緣及恢復波形之延遲信號。經延遲信號用作時脈信號以時控經仲裁信號ARB。因此,在經延遲信號之前導邊緣處,D型正反器36將經仲裁信號ARB時控為資料輸出信號Q。因此,確證重新整理存取授予信號GRANT_REF (邏輯高)且解除確證正常存取授予信號GRANT_NOM (邏輯低)。在重新整理存取授予信號GRANT_REF之前導邊緣處,觸發重新整理計時器電路40處之重新整理持續時間。在重新整理持續時間結束時,確證結束重新整理信號END_REF且解除確證重新整理存取授予信號GRANT_REF,其中確證正常存取授予信號GRANT_NOM。In another example, when the command signals REQ_NOM and REQ_REF may arrive at approximately the same time, the
圖6及圖7中分別展示習知仲裁器與本發明之仲裁器電路之間的解析時間及亞穩態窗與重新整理存取請求時間比較。如上文論述,圖6係在一些實例中用於習知仲裁器電路之輸出存取時間與重新整理請求到達時間之一作圖。圖7係在本發明之實施例中用於圖4之仲裁器電路之輸出存取時間與重新整理請求到達時間之一作圖。The resolution time and the metastability window and the refresh access request time comparison between the conventional arbiter and the arbiter circuit of the present invention are shown in FIGS. 6 and 7, respectively. As discussed above, FIG. 6 is a graph of one of output access time and refresh request arrival time for a conventional arbiter circuit in some examples. 7 is a graph of one of output access time and refresh request arrival time for the arbiter circuit of FIG. 4 in an embodiment of the present invention.
參考圖6,習知仲裁器具有由系統性能及相關聯亞穩態窗確定之解析時間tR。在習知情況下,亞穩態窗54較大。參考圖7,假設正常存取請求信號REQ_NOM具有由線56表示之一到達時間,且x軸表示重新整理存取請求信號REQ_REF之到達時間。亞穩態窗58係兩個信號在彼此之給定時間內到達之一時段。曲線55描繪仲裁器電路之輸出存取時間,亦指稱解析時間。本發明之仲裁器電路能夠將亞穩態窗58減小至非常窄。儘管使用單向延遲之故障消除使正常時脈輸出時間tCO增加延遲量,但由於亞穩態窗58減小幾個數量級,因此可容忍正常時脈輸出時間tCO之增加。特定言之,在本發明之仲裁器電路中使用第一仲裁器及第二仲裁器收緊亞穩態窗,使得仲裁失效之機會很少且MTBF增加幾個數量級。Referring to FIG. 6, a conventional arbiter has a resolution time tR determined by system performance and an associated metastability window. Under conventional circumstances, the metastability window 54 is large. 7, it is assumed that the normal access request signal REQ_NOM has an arrival time represented by
本發明可以諸多方式實施,其包含作為程序、設備、系統及/或要素之組合物。在本說明書中,此等實施方案或本發明可採取之任何其他形式可指稱技術。一般而言,可在本發明之範疇內更改所揭示程序之步驟之順序。The present invention can be implemented in numerous ways, including compositions as programs, devices, systems, and/or elements. In this specification, these implementations, or any other form the invention may take, may be referred to as techniques. In general, the order of steps of the disclosed processes can be modified within the scope of the present invention.
上文結合繪示本發明之原理之附圖來提供本發明之一或多個實施例之一詳細描述。本發明結合此等實施例來描述,但本發明不受限於任何實施例。本發明之範疇僅受限於發明申請專利範圍,且本發明涵蓋諸多替代、修改及等效物。描述中闡述諸多特定細節以便提供本發明之透徹理解。此等細節僅供例示,且本發明可如發明申請專利範圍實踐,而無需此等特定細節中之一些或全部。為清楚起見,未詳細描述與本發明相關之技術領域中已知之技術材料以免不必要地使本發明不清楚。A detailed description of one or more embodiments of the invention is provided above in conjunction with the accompanying drawings that illustrate the principles of the invention. The present invention is described in conjunction with these embodiments, but the present invention is not limited to any embodiment. The scope of the present invention is limited only by the scope of the patent application for the invention, and the present invention covers many alternatives, modifications and equivalents. Numerous specific details are set forth in the description in order to provide a thorough understanding of the present invention. These details are by way of example only, and the invention may be practiced as claimed without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so as not to unnecessarily obscure the invention.
以上詳細描述經提供用於繪示本發明之特定實施例,且不意欲具限制性。可在本發明之範疇內進行諸多修改及變動。本發明由隨附發明申請專利範圍界定。The foregoing detailed description is provided to illustrate specific embodiments of the invention and is not intended to be limiting. Numerous modifications and variations are possible within the scope of the present invention. The invention is defined by the scope of the appended invention application.
1:仲裁器電路 2:NAND邏輯閘 3:NAND邏輯閘 4:節點 5:節點 6:反相器 7:反相器 8:節點 9:節點 20:仲裁器電路 22:反相器 24:節點 25:第一仲裁器 30:亞穩態控制濾波器 32:節點 34:單向延遲電路 35:輸出節點 36:D型正反器 38:節點/資料輸出信號 40:重新整理計時器電路 42:節點 45:平均失效間隔時間(MTBF)程式電路 50:曲線 52:線 54:亞穩態窗 55:曲線 56:線 58:亞穩態窗 62:曲線 64:曲線 66:曲線 68:曲線 72:曲線 74:曲線 76:曲線 78:曲線 80:曲線 82:曲線 84:曲線 100:偽靜態隨機存取記憶體(PSRAM)裝置 102:命令及位址控制電路 104:內部重新整理控制電路 106:外部列存取控制電路 108:行存取控制電路 110:仲裁器電路 112:寫入及讀取控制電路 114:字線解碼器 120:記憶體陣列 122:行選擇/感測放大器/寫入驅動器電路 123:輸入/輸出(I/O)匯流排 124:I/O電路1: Arbiter circuit 2: NAND logic gate 3: NAND logic gate 4: Node 5: Node 6: Inverter 7: Inverter 8: Node 9: Node 20: Arbiter circuit 22: Inverter 24: Node 25: First Arbiter 30: Metastable Control Filter 32: Node 34: One-way delay circuit 35: output node 36: D-type flip-flop 38: Node/Data output signal 40: Reorganize the timer circuit 42: Node 45: Mean Time Between Failure (MTBF) Program Circuit 50: Curves 52: Line 54: Metastable Window 55: Curves 56: Line 58: Metastable Window 62: Curves 64: Curves 66: Curves 68: Curves 72: Curves 74: Curves 76: Curves 78: Curves 80: Curves 82: Curves 84: Curves 100: Pseudo Static Random Access Memory (PSRAM) Device 102: Command and address control circuit 104: Internal rearrangement control circuit 106: External column access control circuit 108: Row access control circuit 110: Arbiter circuit 112: Write and read control circuit 114: word line decoder 120: Memory array 122: Row Select/Sense Amplifier/Write Driver Circuit 123: Input/Output (I/O) busbar 124: I/O circuit
下文詳細描述及附圖中揭示本發明之各種實施例。Various embodiments of the invention are disclosed in the following detailed description and in the accompanying drawings.
圖1係繪示本發明之實施例中之一PSRAM裝置之一示意圖。FIG. 1 is a schematic diagram illustrating a PSRAM device in an embodiment of the present invention.
圖2係繪示在一些實例中可用於一習知PSRAM中之一習知仲裁器電路之一電路圖。FIG. 2 shows a circuit diagram of a conventional arbiter circuit that may be used in a conventional PSRAM in some examples.
圖3係繪示在一些實例中操作圖2之習知仲裁器電路之一時序圖。FIG. 3 is a timing diagram illustrating operation of the conventional arbiter circuit of FIG. 2 in some examples.
圖4係繪示在本發明之實施例中可併入一PSRAM裝置中之一仲裁器電路之一示意圖。4 is a schematic diagram illustrating an arbiter circuit that may be incorporated into a PSRAM device in an embodiment of the present invention.
圖5係繪示在本發明之實施例中操作一PSRAM裝置中之圖4之仲裁器電路之一時序圖。5 is a timing diagram illustrating the arbiter circuit of FIG. 4 operating in a PSRAM device in an embodiment of the present invention.
圖6係在一些實例中用於習知仲裁器電路之輸出存取時間與重新整理請求到達時間之一作圖。6 is a graph of one of output access times and refresh request arrival times for a conventional arbiter circuit in some examples.
圖7係在本發明之實施例中用於圖4之仲裁器電路之輸出存取時間與重新整理請求到達時間之一作圖。7 is a graph of one of output access time and refresh request arrival time for the arbiter circuit of FIG. 4 in an embodiment of the present invention.
100:偽靜態隨機存取記憶體(PSRAM)裝置 100: Pseudo Static Random Access Memory (PSRAM) Device
102:命令及位址控制電路 102: Command and address control circuit
104:內部重新整理控制電路 104: Internal rearrangement control circuit
106:外部列存取控制電路 106: External column access control circuit
108:行存取控制電路 108: Row access control circuit
110:仲裁器電路 110: Arbiter circuit
112:寫入及讀取控制電路 112: Write and read control circuit
114:字線解碼器 114: word line decoder
120:記憶體陣列 120: Memory array
122:行選擇/感測放大器/寫入驅動器電路 122: Row Select/Sense Amplifier/Write Driver Circuit
123:輸入/輸出(I/O)匯流排 123: Input/Output (I/O) busbar
124:I/O電路 124: I/O circuit
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US5206830A (en) * | 1988-07-06 | 1993-04-27 | Kabushiki Kaisha Toshiba | Refresh control circuit of pseudo static random access memory and pseudo static random access memory apparatus |
US7203116B2 (en) * | 2001-08-08 | 2007-04-10 | Renesas Technology Corp. | Semiconductor memory device |
TWI282983B (en) * | 2004-05-20 | 2007-06-21 | Fujitsu Ltd | Semiconductor memory |
US10762945B2 (en) * | 2018-09-04 | 2020-09-01 | Winbond Electronics Corp. | Memory device and refresh method for PSRAM |
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US5206830A (en) * | 1988-07-06 | 1993-04-27 | Kabushiki Kaisha Toshiba | Refresh control circuit of pseudo static random access memory and pseudo static random access memory apparatus |
US7203116B2 (en) * | 2001-08-08 | 2007-04-10 | Renesas Technology Corp. | Semiconductor memory device |
TWI282983B (en) * | 2004-05-20 | 2007-06-21 | Fujitsu Ltd | Semiconductor memory |
US10762945B2 (en) * | 2018-09-04 | 2020-09-01 | Winbond Electronics Corp. | Memory device and refresh method for PSRAM |
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