TW202236680A - Recycleing and clamping the reflected voltage in cascode gan hemt devices - Google Patents

Abstract

A power switch circuit includes an internal node; a first field-effect transistor including a first drain, a first gate and a first source; a second field-effect transistor including a second drain, a second gate and a second source, wherein the first drain is coupled to a voltage supply terminal, the first gate is coupled to the second source, the first source and the second drain are coupled to the internal node, and the second source is coupled to a ground; and a regulating circuit is coupled to the internal node, wherein the regulating circuit is configured to regulate a voltage value of the internal node after the power switch circuit is activated.

Description

Recovery and Clamping of Reflected Voltage in High Electron Mobility Transistor Devices

The invention relates to a power switch circuit, in particular to a power switch circuit with a superimposed structure composed of a D-type gallium nitride high electron moving speed transistor and an N-type metal oxide half field effect transistor.

III-V compounds can be applied to form many kinds of integrated circuit devices due to their semiconductor properties, such as high-power transistors, high-voltage transistors, high-frequency transistors or high electron mobility transistors (high electron mobility transistors, HEMT). In recent years, gallium nitride (GaN) series materials are suitable for high power and high frequency products due to their wide energy gap and high saturation rate.

However, for D-type (Depletion-mode; D-mode) Gallium Nitride High Electron Mobility Transistor (GaN-HEMT), due to its normally on (normally on) characteristics, It is difficult to be directly used as a power switch. Therefore, how to make good use of the characteristics of D-type GaN transistors with high electron movement speed while avoiding the problems caused by its normally-on characteristics has become one of the topics that the industry pays attention to.

Therefore, the main objective of the present invention is to provide a power switch circuit that can adjust the voltage of internal nodes to avoid damage to the power switch circuit.

The present invention provides a power switch circuit, including an internal node; a first field effect transistor, including a first drain, a first gate, and a first source; a second field effect transistor, including There is a second drain, a second gate, and a second source, wherein the first drain is coupled to a voltage supply end, the first gate is coupled to the second source, and the first source coupling, the second drain is coupled to the internal node, and the second source is coupled to a ground voltage; and a regulating circuit is coupled to the internal node, and the regulating circuit is configured to be used in the power switch After the circuit is started, a voltage value of the internal node is adjusted.

Certain terms are used in the specification and subsequent claims to refer to particular elements. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This description and subsequent patent applications do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The "comprising" mentioned in the entire specification and the subsequent claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

Please refer to FIG. 1 , which is a schematic diagram of a power switch circuit 1 with a stacked structure. The power switch circuit 1 includes a first field effect transistor 100 and a second field effect transistor 102, which are respectively a D-type gallium nitride high electron moving speed transistor and an N-type metal oxide half field effect transistor, packaged In a first packaging module 10 . The source of the D-type GaN high electron velocity transistor 100 and the drain of the N-type MOSFET 102 form an internal node 104, and the gate of the D-type GaN high electron velocity transistor 100 It is coupled to the source of the N-type MOSFET 102 . The first packaging module 10 includes a high-voltage terminal 106, a low-voltage terminal 108, and a control terminal 110, which are respectively coupled to the drain of the D-type gallium nitride high-speed electron-moving transistor 100 and the N-type metal-oxide-semiconductor field-effect transistor 102. The gate and the source of the N-type metal oxide semiconductor field effect transistor 102. In one embodiment, the high-voltage terminal 106 is coupled to a high-voltage power supply and the low-voltage terminal 108 is coupled to a ground voltage GND or a current sensing element, wherein the other end of the current sensing element is coupled to the ground voltage GND, and the control terminal 110 receives a The control signal is used to control the operation of the power switch circuit 1 . When the D-type GaN high electron velocity transistor 100 and the N-type MOS field effect transistor 102 are both turned off and the high-voltage power supply voltage received by the high-voltage terminal 106 rises, an abnormally high voltage may appear on the internal node 104, thereby causing internal Node 104 overvoltage problem. For example, the drain-to-source voltage V _DS of the N-type MOSFET 102 is too large to cause a hard breakdown; or, the gate-to-source voltage of the D-type gallium nitride high electron moving speed transistor 100 V _GS exceeds the absolute rated voltage and causes the gate structure to collapse. Therefore, due to the overvoltage of the internal node 104 , the power switch circuit 1 cannot work normally under the rated voltage and load power.

In order to improve the shortcoming of the power switch circuit 1 , the present invention uses shaping and rectification to reduce the voltage of the internal node 104 .

For details, please refer to FIG. 2 , which is a schematic diagram of a power switch circuit 2 according to an embodiment of the present invention. The power switch circuit 2 is derived from the power switch circuit 1, so the same components are denoted by the same symbols. The difference from the power switch circuit 1 is that the D-type gallium nitride high electron moving speed transistor 100 and the N-type metal oxide semi-field effect transistor 102 of the power switch circuit 2 are packaged in a second packaging module 20, and Compared with the first packaging module 10 , the second packaging module 20 is coupled to the internal node 104 and a regulating circuit 30 through a regulating terminal 200 . Through the adjustment terminal 200 , the adjustment circuit 30 can adjust the voltage of the internal node 104 to ensure the normal operation of the power switch circuit 2 .

Specifically, in the power switch circuit 2, when the D-type GaN high electron velocity transistor 100 and the N-type metal-oxide-semiconductor field-effect transistor 102 are both turned off and the high-voltage power supply voltage received by the high-voltage terminal 106 rises, the regulating circuit 30 can adjust the voltage of internal node 104 . For example, the regulating circuit 30 utilizes shaping and rectification to reduce the voltage of the internal node 104 . In this way, the regulating circuit 30 can prevent the internal node 104 from possibly being damaged when the D-type GaN high electron velocity transistor 100 and the N-type MOS field effect transistor 102 are all turned off and the high-voltage power supply voltage received by the high-voltage terminal 106 rises. An abnormally high voltage has occurred. In one embodiment, the D-type gallium nitride high electron moving speed transistor 100 and the N-type metal oxide semi-field effect transistor 102 can also be an independent packaging module and form a power switch circuit 2, and the operation of the power switch circuit 2 I won't repeat them here. In another embodiment, the power switch circuit 2 can also be composed of a D-type gallium nitride high electron velocity transistor and an E-type gallium nitride high electron velocity transistor or an N-type metal oxide semiconductor field-effect transistor and an N-type gold The operation of the power switch circuit 2 will not be repeated here.

It should be noted that any circuit that can timely adjust the voltage of the internal node 104 can be used to realize the adjustment circuit 30 . For example, please refer to FIG. 3 , which is a schematic diagram of an embodiment of the regulating circuit 30 in FIG. 2 . In this embodiment, the regulating circuit 30 includes a diode D1, resistors R1, R2, and capacitors C1, C2, C3. The capacitors C1, C2, the cathode of the diode D1 and the resistor R2 are coupled to an adjustment node N, the capacitor C1 is coupled to the resistor R1, the resistor R2 and the capacitor C3 are coupled to a common voltage Vcc, and the capacitors C2 and C3 are coupled to the ground The voltage, the anode of the resistor R1 and the diode D1 are coupled to the adjustment terminal 200 . With the regulating circuit 30 in FIG. 3, when the D-type gallium nitride high electron moving speed transistor 100 and the N-type metal oxide semi-field effect transistor 102 are all turned off and the high-voltage power supply voltage received by the high-voltage terminal 106 rises, the regulating circuit 30 The voltage of the internal node 104 is adjusted through the adjustment terminal 200, avoiding the hard breakdown caused by the excessive drain-to-source voltage V _DS of the N-type MOSFET 102, or the D-type gallium nitride high-speed electron movement transistor The gate-to-source voltage V _GS of 100 Ω exceeds the absolute rated voltage and causes the gate structure to collapse. In one embodiment, when the high-voltage power supply voltage received by the high-voltage terminal 106 rises, so that when a DC component or an AC component of the voltage of the internal node 104 is higher than the voltage of the common voltage Vcc, the regulating circuit 30 rectifies or shapes Regulating the voltage of the internal node 104 means that the regulating circuit 30 clamps the voltage of the internal node 104 . At the same time, the regulator circuit 30 can also charge the common voltage Vcc when clamping the voltage of the internal node 104, so that the energy consumed by the power switch circuit 1 when the voltage of the internal node 104 is not adjusted can be recovered, thereby improving the efficiency of the power switch circuit 2 .

Specifically, please refer to FIG. 4 and FIG. 5 . FIG. 4 is a schematic diagram of the voltages of the internal node 104 and the high voltage terminal 106 when the power switch circuit 1 does not regulate the internal node 104 through the regulating terminal 200 . When the high-voltage supply voltage received by the high-voltage terminal 106 rises, an abnormally high voltage appears on the internal node 104 . This will cause the problem of overvoltage on the internal node 104 . For example, the drain-to-source voltage V _DS of the N-type MOSFET 102 is too large to cause a hard breakdown; or, the gate-to-source voltage of the D-type gallium nitride high electron moving speed transistor 100 V _GS exceeds the absolute rated voltage and causes the gate structure to collapse. FIG. 5 is a schematic diagram of the voltage of the internal node 104 and the high voltage terminal 106 when the power switch circuit 2 regulates the voltage of the internal node 104 through the regulating terminal 200 . When the high-voltage power supply voltage received by the high-voltage terminal 106 rises, the voltage of the internal node 104 will not follow the high-voltage power supply voltage as shown in FIG. Excessive source voltage V _DS causes hard breakdown, or the gate-to-source voltage V _GS of the D-type GaN high electron moving speed transistor 100 exceeds the absolute rated voltage, causing the gate structure to collapse.

To sum up, the embodiment of the present invention adjusts the voltage of the internal node of the power switch circuit through the regulating circuit, so that when the power switch circuit operates, the voltage of the internal node is within an appropriate range, so the power switch circuit operates under rated voltage and load power. It can work normally, and reduce the loss of the power switch circuit and improve the efficiency of the power switch circuit. In a power switch circuit with a superimposed structure composed of D-type gallium nitride high electron moving speed transistors and N-type metal oxide semi-field effect transistors, the present invention adjusts the internal nodes of the power switch circuit through the regulating circuit, and also reduces the D-type gallium nitride Difficulties in matching gallium high electron movement speed transistors and N-type metal oxide half field effect transistors. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

1, 2: Power switch circuit 10, 20: Encapsulation module 30: Regulating circuit 100: D-type Gallium Nitride High Electron Movement Speed Transistor 102: N-type metal oxide half field effect transistor 104: internal node R1, R2: resistance C1, C2, C3: capacitance D1: Diode

FIG. 1 is a schematic diagram of a power switch circuit with a conventional superposition structure. FIG. 2 is a schematic diagram of a power switch circuit according to an embodiment of the present invention. Fig. 3 is a schematic diagram of a regulating circuit according to an embodiment of the present invention. FIG. 4 is a schematic diagram of voltages of internal nodes and high voltage terminals of a power switch circuit according to an embodiment of the present invention. FIG. 5 is a schematic diagram of voltages of internal nodes and high voltage terminals of a power switch circuit according to another embodiment of the present invention.

2: Power switch circuit

20: Encapsulation module

30: Regulating circuit

100: D-type Gallium Nitride High Electron Movement Speed Transistor

102: N-type metal oxide half field effect transistor

104: internal node

106: High voltage end

108: Low voltage end

110: control terminal

Claims (7)

A power switch circuit comprising: an internal node; A first field effect transistor, including a first drain, a first gate, and a first source; A second field effect transistor includes a second drain, a second gate, and a second source, wherein the first drain is coupled to a voltage supply terminal, and the first gate is coupled to the first two sources, the first source is coupled, the second drain is coupled to the internal node, and the second source is coupled to a ground voltage; and A regulating circuit is coupled to the internal node, and the regulating circuit is configured to regulate a voltage value of the internal node after the power switch circuit is activated. The power switch circuit as claimed in claim 1, wherein the first field effect transistor and the second field effect transistor are packaged in a module. The power switch circuit as claimed in claim 1, wherein the regulation circuit is coupled to a common power supply, and through shaping and rectification, reduces the voltage value of the internal node while charging the common power supply. As the power switch circuit described in claim item 3, the regulating circuit includes: an adjustment terminal coupled to the internal node; a power terminal coupled to the common power supply; a ground terminal coupled between the second source and the ground voltage; a regulating node; A first resistor, one end of which is coupled to the adjustment end; a diode, an anode of which is coupled to the adjustment terminal, and a cathode which is coupled to the node; a first capacitor, coupled between the other end of the first resistor and the node; a second capacitor coupled between the node and the ground; a second resistor coupled between the node and the ground; and A third capacitor is coupled between the power terminal and the ground terminal. The power switch circuit according to claim 1, wherein the first field effect transistor is a D-type (Depletion-mode) GaN-HEMT (Gallium Nitride High Electron Mobility Transistor, GaN-HEMT). The power switch circuit as claimed in item 1, wherein the second field effect transistor is a low voltage N-type metal oxide half field effect transistor (Low Voltage N-MOSFET). The power switch circuit as claimed in claim 1, wherein the voltage supply terminal provides a high voltage.

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