TW202230993A - A method to test dac linearity with low cost - Google Patents

Abstract

A method to test DAC linearity with low cost is provided. (S1) A high precision parameter measuring unit operation parameter is set. (S2) A digital test channel is set to be in an input retrieving mode. (S3) A digital test channel pattern program is executed and an under-test ADC converts a trigger signal and is retrieved by the digital test channel. (S4) Whether the retrieved data is successful or failed is determined by the digital test channel such that a failed data report is recorded when the retrieved data is failed. (S5) Steps (S3) and (S4) are repeated until the voltage of the high precision parameter measuring unit rises to a terminal value. (S6) The failed data report is inquired to determine whether the test is under a condition of go or no-go and is analyzed. Comparing to a current technology, the present invention shortens a test time while maintaining high precision and increasing test efficiency.

Description

A low-cost method for testing the linearity of analog-to-digital converters

The present invention relates to the technical field of analog-to-digital converters, in particular to a low-cost method for testing the linearity of analog-to-digital converters.

At present, many digital chips integrate a small amount of analog and digital mixed-signal processing functions, with analog to digital converter (ADC) being the most typical. In order to judge the quality of an analog-to-digital converter, it is usually necessary to test the linearity of the analog-to-digital converter.

The traditional methods and technical requirements for testing the linearity of an analog-to-digital converter on an automatic test machine are: 1) Use the voltage ramp signal generated by an arbitrary waveform generator (AWG) to connect to the analog-to-digital converter The analog signal input terminal. The voltage range covers the entire analog-to-digital converter operating voltage input range. A high-quality voltage ramp signal with sufficient smoothness is required. In order to avoid step ripple, the low-pass filtering function of the arbitrary waveform generator should be used to smooth the ramp waveform, and the ramp should not be too slow to ensure the smoothing effect of the low-pass filter. 2) Use the capture function of the digital channel to capture the digital code output result converted from the analog to digital converter. It is necessary to convert enough times and capture enough data to ensure that each numerical code of the analog-to-digital converter has an average of 16 corresponding voltage inputs, and the analog-to-digital converter has all "0" codes and all "1" codes. The code has enough saturation voltage input; for example, a 10-bit analog-to-digital converter has 1024 numerical codes, and usually requires 1024*16+2000 points of sampling data. In addition, high-quality clock synchronization control is required, and the phase of each ramp generated by the arbitrary waveform generator must have a precise offset to ensure that the corresponding voltages of all digital codes will be sampled with equal probability. 3) Read back the collected data, analyze the histogram distribution in the background software, calculate the indicators of integral nonlinearity (INL) and differential nonlinearity (DNL), and judge whether to pass or fail (Pass/Fail).

The test usually requires the test machine to be equipped with a mixed-signal test module, including an arbitrary waveform generator. The mixed-signal test module is expensive and occupies the internal space of the test machine, which is equivalent to reducing the number of digital signal test channels of the machine.

Traditional testing methods require a large amount of data sampling, which takes up testing time. In addition, the sampling data must be read back to the computer, and software analysis can be done to judge the results. This read back process also takes up the test time. Also, there is no room for simplification in traditional test methods. For low-cost analog-to-digital converters, methods to accurately measure INL/DNL are typically only enabled during the chip design verification phase. The test requirements in the wafer mass production stage only need to meet the judgment of pass or fail (Go-NoGo). Specifically, it is to verify whether the INL/DNL exceeds the minimum encoding width. However, the traditional testing method cannot reduce the amount of sampling data in order to make the test judgment result correct, so the testing time cannot be reduced. Moreover, the judgment of pass or fail (Go-NoGo) should still be based on the calculation of INL/DNL, or all the data should be read back and analyzed by software.

Therefore, the traditional test method using mixed-signal test modules is uneconomical and unaffordable for low-cost analog-to-digital converter chip testing.

In order to overcome the deficiencies of the prior art, the present invention provides a low-cost method for testing the linearity of an analog-to-digital converter.

In order to achieve the above object, a low-cost method for testing the linearity of an analog-to-digital converter is designed, which is characterized by comprising the following steps:

(S1) Set the working parameters of the high-precision parameter measurement unit;

(S2) Set the digital test channel to input capture mode;

(S3) Execute the digital test channel pattern program, the analog-to-digital converter under test converts the trigger signal, and the signal is captured by the digital test channel;

(S4) The digital test channel makes a judgment on the success or error of the captured data, and if there is an error, records the error data report;

(S5) Repeat steps (S3)-(S4) until the voltage of the high-precision parameter measurement unit rises to the end value;

(S6) Query the error data report, judge whether it is passed or not, and obtain all the error data reports for analysis;

The step (S3) specifically includes the following steps:

(S31) Execute the digital test channel pattern program;

(S32) The high-precision parameter measuring unit sequentially outputs the voltage according to the ideal value of the central voltage corresponding to each numerical code from the analog to the digital converter under test;

(S33) After the voltage output by the high-precision parameter measurement unit is in place, the analog-to-digital converter under test performs an analog-to-digital conversion;

(S34) After waiting for a fixed time t, the digital test channel performs a data capture.

In the step (S1), the initial value of the step voltage output by the high-precision parameter measurement unit is set as the voltage corresponding to the digital code 0 of the analog-to-digital converter under test, and the single-step value is the voltage of the analog-to-digital converter under test. The minimum code width voltage, the end value is the voltage corresponding to the maximum digital code value of the analog-to-digital converter under test.

The fixed time t=1/f in the step (S34), f is the sampling rate of the analog-to-digital converter under test.

In the step (S4), the data captured by the digital test channel is compared with the expected value in the digital test channel pattern program. If the two values are completely equal, it is a success, and if there is a 1-bit difference, it is an error.

The criterion for passing or failing in the step (S6) is whether the error data report is completely empty, and the error data report is completely empty is passed, and if the error data report is not empty, it is failed.

A test circuit is provided between the digital test channel, the high-precision parameter measurement unit and the analog-to-digital converter under test, and the test circuit includes a digital test channel, a parameter-setting digital-to-analog converter, a forced amplifier, and an error comparison. The digital test channel's pattern trigger signal port is connected to one end of the parameter setting digital to analog converter, and the other end of the parameter setting digital to analog converter is respectively connected to the No. 1 of the error comparator. port and the No. 1 port of the forced amplifier, the No. 2 port of the error comparator is respectively connected to the No. 2 port of the forced amplifier, the high-precision parameter measurement unit and the No. 3 port of the voltage amplifier, and the No. 3 port of the error comparator is connected to the digital test channel. The parameter is in place to the signal port, and the No. 3 port of the amplifier is forced to connect the analog under test to the No. 1 port of the digital converter and one end of the first voltage follower. The other end of the first voltage follower is connected to the No. 1 port of the voltage amplifier. The second port of the analog-to-digital converter is respectively connected to one end of the second voltage follower and one end of the second system common ground, the other end of the second voltage follower is connected to the second port of the voltage amplifier, and the second system common ground The other end is connected to one end of the first system common ground, the other end of the first system common ground is connected to the fourth port of the forced amplifier, and the third port of the analog to digital converter under test is connected to the digital channel capture port of the digital test channel.

Compared with the prior art, the present invention has the following beneficial effects:

1. Through the two-way communication mechanism between the digital test channel and the high-precision parameter measurement unit, the waiting time for voltage stabilization is optimized and the test time is shortened;

2. Utilize the four-wire mode of the high-precision parameter measurement unit to ensure that the voltage loaded into the input terminal of the analog-to-digital converter under test is accurate, which is better than the accuracy of more than 10 times the minimum code width of the analog-to-digital converter under test.

3. The digital test channel directly judges the captured data, without the need to read back the data for analysis, the test results can be obtained intuitively, and the test efficiency can be improved;

4. When there is an error in the test process, only the error data report is recorded, and the error data report is read back when there is an error, and it is not necessary to read back the data every time the test is performed; and the read back data includes all errors, which is convenient for direct analysis of the results, without the need for a large number of test data. Searching for error data.

Regarding the features, implementation and effects of this case, a preferred embodiment is described in detail as follows in conjunction with the drawings.

The present invention will be further described below according to the accompanying drawings.

The analog-to-digital converter ADC converts the input voltage signal into an output digital code. As shown in Figure 4 to Figure 5. The digital code is represented by binary bits. In the quantization range, each voltage will be converted into a unique digital code value. Each digital code value corresponds to a voltage range, and the voltages in this range will be converted into the same digital code value. The width of this range is called the digital code width. The midpoint of this voltage range is called the transition point. The total quantization range divided by the total number of digitally encoded values, called the minimum code width, marks the resolution of the analog-to-digital converter ADC.

Ideally, all digit codes have the same digit code width, which is equal to the minimum code width, and each transition point is located on the ideal ADC characteristic line.

The deviation between the actual transfer function and the ideal transfer function is shown in Figure 6. In the entire quantification range, the maximum deviation between the actual transition point and the ideal transition point is called integral nonlinearity.

If the tested input voltages are all ideal transition points, when the deviation between the actual transition point and the ideal transition point is greater than one digit code width, the conversion result does not meet expectations. We verify the analog-to-digital converter ADC conversion by looping through the voltages of all ideal transition points in turn, and the conversion results show multiple values that are not as expected.

Therefore, if the pass or fail criterion of integral nonlinearity is that the error is less than a minimum code width, the pass or fail of integral nonlinearity can be detected only by the verification of the ideal transition point.

In the actual transfer function, there is an error for each digit code width, as shown in Figure 7. That is, the deviation between the actual width and the standard width (minimum encoded width). The largest value among the deviations of all digit-encoded values is called differential nonlinearity.

If the tested input voltages are all ideal transition points, each digital code value corresponds to only one measurement point, and the actual digital code width cannot be calibrated, so the differential nonlinearity cannot be obtained. However, when the deviation between the actual transition point and the ideal transition point is greater than one digit code width, not only the conversion result is not as expected, but also the phenomenon of missing codes or duplicate codes will inevitably appear when checking adjacent results. We verify the analog-to-digital converter conversion by going through the voltages of all ideal transition points in turn, resulting in missing codes and duplicate codes. And the phenomenon of missing codes and duplicate codes should appear in pairs, and the data between the two are not as expected.

If the missing code and the repeated code are closely spaced or even adjacent, the differential nonlinearity is exhibited here. If there is a large series of non-conforming data between the missing code and the repeated code, the integral nonlinearity is manifested here. According to this feature, it can be judged whether the differential nonlinearity exceeds a minimum code width.

Therefore, if the pass or fail criterion of the differential nonlinearity is that the error is less than a minimum code width, only the verification of the ideal transition point can also detect the pass or fail of the differential nonlinearity.

Please refer to Figure 1 to Figure 3. FIG. 1 is a flowchart of a low-cost method 100 for testing the linearity of an analog-to-digital converter according to an embodiment of the present invention. FIG. 2 is a flowchart of steps (S3)-(S4) of the present invention in an embodiment of the present invention. FIG. 3 is a circuit diagram for implementing the method 100 according to an embodiment of the present invention.

As shown in Figures 1 to 3, a low-cost method for testing the linearity of an analog-to-digital converter includes the following steps:

(S1) Set the working parameters of the high-precision parameter measurement unit PMU;

(S2) Set the digital test channel PE to the input capture mode;

(S3) Execute the digital test channel PE style program, the analog to digital converter ADC converts the trigger signal, and is captured by the digital test channel PE;

(S4) The digital test channel PE judges the success or error of the captured data, and if there is an error, records the error data report of the error;

(S5) Repeat steps (S3)-(S4) until the voltage of the high-precision parameter measurement unit PMU rises to the end value;

(S6) Query the error data report, judge whether it is passed or not, and obtain all the error data reports for analysis;

The step (S3) specifically includes the following steps:

(S31) Execute the digital test channel PE style program;

(S32) The high-precision parameter measurement unit PMU sequentially encodes the corresponding ideal value of the central voltage according to each value of the analog to the digital converter ADC under test and outputs the voltage;

(S33) After the voltage output by the high-precision parameter measurement unit PMU is in place, the analog-to-digital converter ADC under test performs an analog-to-digital conversion;

(S34) After waiting for a fixed time t, the digital test channel PE performs a data capture.

In step (S1), the initial value of the step voltage output by the high-precision parameter measurement unit PMU is set as the voltage corresponding to the digital code 0 of the analog-to-digital converter ADC under test, and the single-step value is the voltage of the analog-to-digital converter ADC under test. The minimum code width voltage, the end value is the voltage corresponding to the maximum digital code value of the analog-to-digital converter ADC under test.

The fixed time t=1/f in step (S34), f is the sampling rate of the analog-to-digital converter ADC under test.

In step (S4), the data captured by the digital test channel PE is compared with the expected value in the digital test channel style program. If the two values are completely equal, it is a success, and if there is a 1-bit difference, it is an error.

The criterion for passing or failing in step (S6) is whether the error data report is completely empty, and the error data report is completely empty is passed, and the error data report is not empty is the failure. The error data report is completely empty, which means that the voltage error of all digital code values is less than a minimum code width, which meets the passed standard. If the error data report is not empty, it means that the voltage error of at least one digital code value is greater than a minimum code width, which meets the standard of rejection.

A test circuit is provided between the digital test channel PE, the high-precision parameter measurement unit PMU and the analog-to-digital converter ADC under test. The test circuit includes a digital test channel PE, a parameter setting digital-to-analog converter DAC, a forced amplifier FA, an error comparator EC, a voltage amplifier VA, an analog-to-digital converter ADC under test, and the pattern trigger signal port T1 connection of the digital test channel PE The parameters set the digital to one end of the analog converter DAC, and the other end of the parameter set digital to the analog converter DAC are respectively connected to the first port of the error comparator EC and the first port of the forced amplifier FA, and the second port of the error comparator EC respectively Connect the No. 2 port of the forced amplifier FA, the high-precision parameter measurement unit PMU and the No. 3 port of the voltage amplifier VA, the No. 3 port of the error comparator EC is connected to the parameter in-position signal port T2 of the digital test channel PE, and the No. 3 port of the forced amplifier FA The ports are respectively connected to the first port of the analog under test to the digital converter ADC and one end of the first voltage follower VF1, the other end of the first voltage follower VF1 is connected to the first port of the voltage amplifier VA, and the analog under test is connected to the digital converter. The second port of the ADC is respectively connected to one end of the second voltage follower VF2 and one end of the second system common ground GND2, the other end of the second voltage follower VF2 is connected to the second port of the voltage amplifier VA, and the second system common ground The other end of GND2 is connected to one end of the first system common ground terminal GND1, the other end of the first system common ground terminal GND1 is connected to the fourth port of the forced amplifier FA, and the third port of the analog to digital converter ADC is connected to the digital test channel. PE's digital channel capture port T3.

In specific use, the model of digital test channel PE is ADATE318BCPZ. Parameter setting The model of the digital-to-analog converter DAC is the built-in 16-BIT FIN DAC of the AD5522JSVUZ. The model number of the forced amplifier FA is OPA547. The model of the error comparator EC is the built-in two voltage comparators CPL and CPH of the AD5522JSVUZ, and its threshold voltages are respectively set to the target voltage plus/minus a minimum code width voltage. When the actual voltage reaches the middle interval between the two threshold voltages, the output logic of the two comparators can be used as an indication that the voltage is in place. The model of the voltage amplifier is the VA built into the AD5522JSVUZ. The models of the first voltage follower VF1 and the second voltage follower VF2 are both built-in voltage followers in the AD5522JSVUZ chip.

As shown in Figure 3, the linearity test of the analog-to-digital converter ADC can be achieved only by using the high-precision parameter measurement unit PMU. The density of the channels reduces the test cost and improves the test efficiency.

The high-precision parameter measurement unit PMU works in the step voltage output mode. The output voltage is set by the parameter setting digital-to-analog converter DAC, and the step value is pre-set, starting from 0 voltage, each time a trigger signal is received, the output voltage will increase by one step, and there is no need to set it every time. When the accuracy of the parameter setting the digital-to-analog converter DAC is much higher than the minimum code width of the analog-to-digital converter ADC under test, the high-precision parameter measurement unit PMU can be used to test the nonlinearity of the analog-to-digital converter ADC.

The output voltage of the forced amplifier FA is sent to the input end of the analog to digital converter ADC through the multi-segment line, and then returned to the high-precision parameter measurement unit PMU circuit through the chip ground pin and the system common ground. This is a pair of signals drive line. Currents on the drive lines introduce voltage errors. However, through the four-wire connection method, the input end of the tested chip and the grounding of the chip are introduced into the measurement circuit of the high-precision parameter measurement unit PMU with a pair of dedicated signal transmission lines. The current on the transmission line is extremely small, so almost no voltage error is introduced. The actual value of the wafer under test can be measured very accurately. Through the closed loop control of the negative loop, the actual value of the loaded voltage of the wafer under test can be precisely controlled.

Forcing the amplifier FA to have a compensation capacitor will slow down the actual voltage arrival speed to ensure the stability of the closed loop circuit. The error comparator can judge whether the actual voltage is in place, and send a parameter in-place signal to the digital test channel after the voltage is in place.

Although the specific embodiments of the present invention are described above, those skilled in the art should understand that these are only examples, and various changes or modifications can be made to these embodiments without departing from the principle and essence of the present invention .

100: Method S1~S6: Steps S31~S34: Steps ADC: Analog to Digital Converter DAC: Parameterized Digital-to-Analog Converter EC: Error Comparator FA: Force Amplifier GND1: Common ground terminal of the first system GND2: Common ground terminal of the second system PE: digital test channel PMU: High Precision Parametric Measurement Unit T1: Pattern trigger signal port T2: parameter in place signal port T3: Digital channel capture port VA: Voltage Amplifier VF1: first voltage follower VF2: Second Voltage Follower

[FIG. 1] is a flowchart of a low-cost method for testing the linearity of an analog-to-digital converter in an embodiment of the present invention; [Fig. 2] is a flowchart of steps (S3)-(S4) of the present invention in an embodiment of the present invention; [FIG. 3] is a circuit diagram for implementing the method in an embodiment of the present invention; [FIG. 4] is a schematic diagram of the principle of an analog-to-digital converter in an embodiment of the present invention; [Fig. 5] is a partial enlarged view of A in Fig. 4 in an embodiment of the present invention; [ Fig. 6 ] is a schematic diagram of the deviation between the actual transfer function and the ideal transfer function in an embodiment of the present invention; and [ FIG. 7 ] is a schematic diagram of the error of each digit code width of the actual conversion function in an embodiment of the present invention.

S31~S34: Steps

Claims (6)

A low-cost method for testing the linearity of an analog-to-digital converter, comprising the following steps: (S1) setting a working parameter of a high-precision parameter measuring unit; (S2) Set a digital test channel to input capture mode; (S3) Execute a digital test channel pattern program, so that a tested analog-to-digital converter converts a trigger signal and is captured by the digital test channel; (S4) The digital test channel judges whether the captured data is successful or erroneous, and if there is an error, a report of the erroneous data is recorded; (S5) repeating steps (S3)-(S4) until a voltage of the high-precision parameter measuring unit rises to an end value; and (S6) Query the error data report, judge whether it passes or fail, and obtain all the error data reports for analysis; Wherein, the step (S3) specifically includes the following steps: (S31) Execute the digital test channel pattern program; (S32) causing the high-precision parameter measuring unit to sequentially output the voltage according to an ideal value of a central voltage corresponding to each numerical code from the analog to digital converter to be measured; (S33) After the voltage output by the high-precision parameter measurement unit is in place, make the analog-to-digital converter under test perform an analog-to-digital conversion; and (S34) After waiting for a fixed time t, the digital test channel performs a data capture. A low-cost method for testing the linearity of an analog-to-digital converter as claimed in claim 1, further comprising: in step (S1), setting an initial value of the high-precision parameter measurement unit to output a step voltage for the analog to be tested The voltage corresponding to the digital code 0 to the digital converter, a single step value is a minimum code width voltage of the analog-to-digital converter under test, and an end value is a maximum digital code value of the analog-to-digital converter under test corresponding voltage. A low-cost method for testing the linearity of an analog-to-digital converter as described in claim 1, further comprising: the fixed time t=1/f in step (S34), where f is the measured analog-to-digital converter a sampling rate. A low-cost method for testing the linearity of an analog-to-digital converter as described in claim 1, further comprising: in step (S4), comparing the data captured by the digital test channel with an expected value in the digital test channel pattern program If the two values are completely equal, the comparison is successful, and there is a 1-bit difference, which is an error. A low-cost method for testing the linearity of an analog-to-digital converter as described in claim 1, further comprising: the criterion for passing or failing in step (S6) is whether the error data report is completely empty, and the error data report is full Empty means pass, if the error data report is not empty means fail. A low-cost method for testing the linearity of an analog-to-digital converter as claimed in claim 1, wherein a test circuit is provided between the digital test channel, the high-precision parameter measurement unit and the analog-to-digital converter under test, and the The test circuit includes the digital test channel, a parameter-setting digital-to-analog converter, a forcing amplifier, an error comparator, a voltage amplifier, and the analog-to-digital converter under test. A pattern trigger signal port of the digital test channel is connected to This parameter sets one end of the digital-to-analog converter, and the other end of the digital-to-analog converter is respectively connected to port 11 of the error comparator and port 11 of the forced amplifier. The No. 1 and No. 2 ports are respectively connected to the No. 1 and No. 2 ports of the forced amplifier, the high-precision parameter measurement unit and the No. 1 and 3 ports of the voltage amplifier. The No. 1 and 3 ports of the error comparator are connected to a parameter-in-place signal port of the digital test channel. Ports 1 and 3 of the forced amplifier are respectively connected to the analog-to-digital converter port 11 and one end of the first voltage follower, and the other end of the first voltage follower is connected to the voltage amplifier's port 11 Ports 1 and 2 of the analog-to-digital converter under test are respectively connected to one end of a second voltage follower and one end of a second system common ground, and the other end of the second voltage follower is connected to one end of the voltage amplifier Port No. 2, the other end of the second system common ground terminal is connected to one end of a first system common ground terminal, the other end of the first system common ground terminal is connected to the No. 14 port of the forced amplifier, the analog to digital converter under test is Port 1 and 3 are connected to a digital channel capture port of the digital test channel.

Images