CN101895294B - Self-testing device and self-testing method for cut-and-trial digital-to-analog converter - Google Patents

Abstract

The invention relates to a self-testing device and a self-testing method for a cut-and-trial digital-to-analog converter. The self-testing device comprises a primary digital-to-analog converter, a secondary digital-to-analog converter, a self-calibration digital-to-analog converter and a comparator which are connected through a circuit, and a cut-and-trial controller, a self-testing controller and a self-calibration controller which are connected through a circuit. The self-testing method comprises the steps of self-calibration, single capacitance test and interval capacitance test. The device and the method can effectively detect the reasonableness of a capacitance value and determine the position of a defective capacitor by introducing new 1/2 reference voltage in the measuring process.

Description

A kind of for progressively near self-measuring device and the self-testing method of pattern number converter

Technical field

The present invention relates to a kind of for progressively near self-measuring device and the self-testing method of pattern number converter.

Background technology

As shown in Figure 1, progressively generally comprise following components near the structure of analog to digital converter: high-performance comparator 101, digital analog converter 103, the control circuit 102 that progressively approaches.Progressively the operation principle near digital to analog converter is: begun by most significant bit, progressively establishing most significant bit near control circuit 102 is 1, the output of digital analog converter 103 and input voltage are by high-performance comparator 101 relatively, if input voltage is bigger, then most significant bit is 1, otherwise is 0; And then to establish next most significant bit be 1, compares again, if input voltage is bigger, then this bit is 1, otherwise is 0.Arrive last bit by that analogy.

As shown in Figure 2, an analog to digital converter commonly used is to adopt electric capacity to arrange, and maximum electric capacity is the twice of second largest electric capacity, and second largest capacitance is again the twice of the third-largest capacitance, by that analogy.This expression and binary bit are closely similar.When ideal situation, the capacitance among Fig. 2 is except C _1B=C _1AIn addition, following relationship is arranged

C _i+1＝2C _i (1)

In actual track, equation (1) has certain error, so the deviation of voltage can be expressed as

$V_{\mathrm{error}}=\underset{i=1B}{\overset{N}{\mathrm{\Σ}}}{V}_{\mathrm{ei}}{S}_i---\left(2\right)$

When switch S is received reference voltage VREF, S _i=1; When switch S ground connection GND, S _i=0.V _EiRepresentative is because capacitor C _iThe voltage deviation that causes of deviation.

If analog to digital converter is wanted operate as normal, capacitance C and minimum capacity C _1AOr C _1BCompare, error amount must be littler, so just can effectively measure.Compare C _1AOr C _1BBig deviation can cause digital discontinuity, and therefore initiating failure, needs a kind of method of measurement and measuring sequence to find out analog to digital converter because the improper fault that causes of capacitance.

Summary of the invention

The invention provides a kind of for progressively near self-measuring device and the self-testing method of pattern number converter, can detect the reasonability of capacitance effectively, and can determine the position of defective electric capacity.

In order to achieve the above object, the invention provides a kind of for progressively near the self-measuring device of pattern number converter, this self-measuring device comprises main digital to analog converter, inferior digital to analog converter, self-calibrating digital to analog converter and the comparator that circuit connects;

This self-measuring device also comprise circuit connect described main digital to analog converter and time digital to analog converter progressively near controller, circuit be connected described main digital to analog converter the selftest controller and, circuit connects the self-calibrating controller of described self-calibrating digital to analog converter;

This self-measuring device also comprise circuit connect described self-calibrating controller calibration data memory and, circuit connects the accumulator of described calibration data memory and self-calibrating digital to analog converter;

Described main digital to analog converter comprises some electric capacity row, the upper end parallel connection of each electric capacity, connect master switch, master switch can disconnect or ground connection, the lower end correspondence of each electric capacity is provided with some electric capacity control switchs, be provided with reference voltage end, 1/2 reference voltage end and earth terminal in this main digital to analog converter, described some electric capacity control switchs can select to connect reference voltage end, 1/2 reference voltage end or earth terminal;

Described main digital to analog converter is used for the output of the seniority top digit (MSB) of analog-digital converter, and control to carry out selftest by switch, and inferior digital to analog converter is used for obtaining simulating the result of the lower-order digit (LSB) of digital to analog converter, and measure the residual voltage value on some electric capacity in the main digital to analog converter, comparator output is regulated the input self-calibrating digital to analog converter of time digital to analog converter under the control of self-calibrating controller, after residual voltage value on the electric capacity added up and store, be used for revising the voltage error of main digital to analog converter, the selftest controller is used for finding because the electric capacity that manufacturing process causes is unreasonable;

The relation of residual voltage value and error voltage value is by following equation (3) and (4) expression, so can the calculating voltage deviate by the measurement of residual voltage value.

$V_{\mathrm{eN}}=\frac{V_{\mathrm{xN}}}{2}---\left(3\right)$

$V_{\mathrm{ei}}=\frac{1}{2}(V_{\mathrm{xi}}-\underset{k=i+1}{\overset{N}{\mathrm{\Σ}}}{V}_{\mathrm{ek}})---\left(4\right)$

Residual voltage value and error voltage value are stored in calibration data memory, and during operate as normal, these values will be removed, and be used as the correction of capacitance error.

The present invention also provide a kind of for progressively near the self-testing method of pattern number converter, this self-testing method comprises following steps:

Step 1, self-calibrating;

The process of self-calibrating is from the electric capacity of maximum;

Step 1.1, with the master switch G1 ground connection in the main digital to analog converter, make i=N, if i--j＞=i, then makes S _j=0, that is, and with corresponding electric capacity control switch ground connection, if j＜i then makes S _j=1, that is, corresponding electric capacity control switch is met reference voltage end VREF1;

Step 1.2, disconnection master switch G1 make i=N, and i--is if j=i then makes S _j=1, that is, corresponding electric capacity control switch is met reference voltage end VREF1, if j!=i then makes S _j=0, that is, and with corresponding electric capacity control switch ground connection;

Step 1.3, utilization time digital to analog converter are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th1If,, then jump to step 1.4, if not, then jump to step 1.5;

There are manufacturing defect in step 1.4, prompting, jump to step 1.5;

Step 1.5, judge whether i=1 sets up, if, then jump to step 2, if not, then jump to step 1.1;

Step 2, single capacity measurement;

The process of single capacity measurement is from the electric capacity of maximum;

Step 2.1, with master switch G1 ground connection, make i=N, i--makes S _i=1/2, that is, corresponding electric capacity control switch is met 1/2 reference voltage end VREF2;

Step 2.2, disconnection master switch G1 make S _I-1=1, that is, corresponding electric capacity control switch is met reference voltage end VREF1;

Step 2.3, utilization time digital to analog converter are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th2If,, then jump to step 2.4, if not, then jump to step 2.5;

There are manufacturing defect in step 2.4, prompting, jump to step 2.5;

Step 2.5, judge whether i=1 sets up, if, then jump to step 3, if not, then jump to step 2.1;

Step 3, interval capacity measurement;

Step 3.1, with master switch G1 ground connection, make S _N=S _N-2=S _N-4=...=1/2, that is, the electric capacity control switch of even number electric capacity is met 1/2 reference voltage end VREF2, make S _N-1=S _N-3=S _N-5=...=0, that is, and with the electric capacity control switch ground connection of odd number electric capacity;

Step 3.2, disconnection master switch G1 make S _N-1=S _N-3=S _N-5=...=1, that is, the electric capacity control switch of odd number electric capacity is met reference voltage end VREF1, make S _N=S _N-2=S _N-4=...=0, that is, and with the electric capacity control switch ground connection of even number electric capacity;

Step 3.3, utilization time digital to analog converter are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th3If,, then jump to step 3.4, if not, then jump to step 3.5;

There are manufacturing defect in step 3.4, prompting, jump to step 3.5;

Step 3.5, judge whether not exist mistake, if, then by test, if not, then not by test, if the test of step 1, step 2 and step 3 does not all have mistake, that total test is passed through, if there is mistake in one of them of step 1, step 2 and step 3, then chip has manufacturing defect.

In above-mentioned steps 1.3, step 2.3 and the step 3.3, inferior digital to analog converter adopts cut-and-trial to measure residual voltage;

In step 1, threshold value V _Th1Be made as the value littler than the least significant bit of main digital to analog converter, this value is used for comparison residual voltage value, if residual voltage is too big, illustrates that there is manufacturing defect in measured capacitance;

In step 2, threshold value V _Th2Can be made as and threshold value V _Th1The same, but also can do certain adjustment according to system requirements, this value is used for comparison residual voltage value, can determine the reasonability of capacitance like this, because be that single electric capacity is tested one by one, this process can also be used to determining the position of bad electric capacity;

In step 3, threshold value V _Th3Can be made as and threshold value V _Th1The same, but also can do certain adjustment according to system requirements.

The present invention has introduced 1/2 new reference voltage in measuring process, can detect the reasonability of capacitance effectively, and can determine the position of defective electric capacity.

Description of drawings

Fig. 1 is progressively near the structural representation of digital to analog converter in the background technology;

Fig. 2 is the structural representation of the digital to analog converter arranged of electric capacity commonly used in the background technology;

Fig. 3 is provided by the invention a kind of for progressively near the structural representation of the self-measuring device of pattern number converter;

Fig. 4 is provided by the invention a kind of for progressively near the flow chart of the self-testing method of pattern number converter.

Embodiment

Following according to Fig. 3 and Fig. 4, specify preferred embodiments of the present invention:

As shown in Figure 3, be a kind of for progressively near the structural representation of the self-measuring device of pattern number converter, this self-measuring device comprises main digital to analog converter 201, inferior digital to analog converter 203, self-calibrating digital to analog converter 204 and the comparator 202 that circuit connects;

This self-measuring device also comprise circuit connect described main digital to analog converter 201 and time digital to analog converter 203 progressively near controller 205, circuit be connected described main digital to analog converter 201 selftest controller 210 and, circuit connects the self-calibrating controller 208 of described self-calibrating digital to analog converter 204;

This self-measuring device also comprises calibration data memory 207 and that circuit connects described self-calibrating controller 208, and circuit connects the accumulator 206 of described calibration data memory 207 and self-calibrating digital to analog converter 204;

Described main digital to analog converter 201 comprises some electric capacity row C _1A, C _1BC _N, the upper end parallel connection of each electric capacity meets master switch G1, and master switch G1 can disconnect or ground connection, and the lower end correspondence of each electric capacity is provided with some electric capacity control switch S _i, here the value of i be N, N-1 ..., 1B, 1A, be provided with reference voltage end VREF1,1/2 reference voltage end VREF2 and earth terminal GND in this main digital to analog converter 201, described some electric capacity control switch S _iCan select to connect reference voltage end VREF1,1/2 reference voltage end VREF2 or earth terminal GND;

Described main digital to analog converter 201 is used for the output of seniority top digit, and control to carry out selftest by switch, and inferior digital to analog converter 203 is used for obtaining the result of lower-order digit, and measure the residual voltage value on some electric capacity in the main digital to analog converter, comparator 202 outputs are regulated the input self-calibrating digital to analog converter 204 of time digital to analog converter 203 under the control of self-calibrating controller 208, after residual voltage value on the electric capacity added up and store, be used for revising the voltage error of main digital to analog converter 201, selftest controller 210 is used for finding because the electric capacity that manufacturing process causes is unreasonable;

The relation of residual voltage value and error voltage value is by following equation (3) and (4) expression, so can the calculating voltage deviate by the measurement of residual voltage value.

$V_{\mathrm{eN}}=\frac{V_{\mathrm{xN}}}{2}---\left(3\right)$

$V_{\mathrm{ei}}=\frac{1}{2}(V_{\mathrm{xi}}-\underset{k=i+1}{\overset{N}{\mathrm{\Σ}}}{V}_{\mathrm{ek}})---\left(4\right)$

Residual voltage value and error voltage value are stored in calibration data memory 207, and during operate as normal, these values will be removed, and be used as the correction of capacitance error.

As shown in Figure 4, be that the self-measuring device of a kind of Fig. 3 of utilization comes the flow chart to the method for progressively testing oneself near the pattern number converter, this self-testing method comprises following steps:

Step 1, self-calibrating;

The process of self-calibrating is from the electric capacity of maximum;

Step 1.1, with the master switch G1 ground connection in the main digital to analog converter 201, make i=N, if i--j＞=i, then makes S _j=0, that is, and with corresponding electric capacity control switch ground connection, if j＜i then makes S _j=1, that is, corresponding electric capacity control switch is met reference voltage end VREF1;

Step 1.2, disconnection master switch G1 make i=N, and i--is if j=i then makes S _j=1, that is, corresponding electric capacity control switch is met reference voltage end VREF1, if j!=i then makes S _j=0, that is, and with corresponding electric capacity control switch ground connection;

Step 1.3, utilization time digital to analog converter 203 are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th1If,, then jump to step 1.4, if not, then jump to step 1.5;

There are manufacturing defect in step 1.4, prompting, jump to step 1.5;

Step 1.5, judge whether i=1 sets up, if, then jump to step 2, if not, then jump to step 1.1;

Step 2, single capacity measurement;

The process of single capacity measurement is from the electric capacity of maximum;

Step 2.1, with master switch G1 ground connection, make i=N, i--makes S _i=1/2, that is, corresponding electric capacity control switch is met 1/2 reference voltage end VREF2;

Step 2.2, disconnection master switch G1 make S _I-1=1, that is, corresponding electric capacity control switch is met reference voltage end VREF1;

Step 2.3, utilization time digital to analog converter 203 are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th2If,, then jump to step 2.4, if not, then jump to step 2.5;

There are manufacturing defect in step 2.4, prompting, jump to step 2.5;

Step 2.5, judge whether i=1 sets up, if, then jump to step 3, if not, then jump to step 2.1;

Step 3, interval capacity measurement;

Step 3.1, with master switch G1 ground connection, make S _N=S _N-2=S _N-4=...=1/2, that is, the electric capacity control switch of even number electric capacity is met 1/2 reference voltage end VREF2, make S _N-1=S _N-3=S _N-5=...=0, that is, and with the electric capacity control switch ground connection of odd number electric capacity;

Step 3.2, disconnection master switch G1 make S _N-1=S _N-3=S _N-5=...=1, that is, the electric capacity control switch of odd number electric capacity is met reference voltage end VREF1, make S _N=S _N-2=S _N-4=...=0, that is, and with the electric capacity control switch ground connection of even number electric capacity;

Step 3.3, utilization time digital to analog converter 203 are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th3If,, then jump to step 3.4, if not, then jump to step 3.5;

There are manufacturing defect in step 3.4, prompting, jump to step 3.5;

Step 3.5, judge whether not exist mistake, if, then by test, if not, then not by test, if the test of step 1, step 2 and step 3 does not all have mistake, that total test is passed through, if there is mistake in one of them of step 1, step 2 and step 3, then chip has manufacturing defect.

In above-mentioned steps 1.3, step 2.3 and the step 3.3, inferior digital to analog converter adopts cut-and-trial to measure residual voltage;

In step 1, threshold value V _Th1Be made as the value littler than the least significant bit of main digital to analog converter, this value is used for comparison residual voltage value, if residual voltage is too big, illustrates that there is manufacturing defect in measured capacitance;

In step 2, threshold value V _Th2Can be made as and threshold value V _Th1The same, but also can do certain adjustment according to system requirements, this value is used for comparison residual voltage value, can determine the reasonability of capacitance like this, because be that single electric capacity is tested one by one, this process can also be used to determining the position of bad electric capacity;

In step 3, threshold value V _Th3Can be made as and threshold value V _Th1The same, but also can do certain adjustment according to system requirements.

Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims (6)

1. one kind is used for progressively near the self-measuring device of pattern number converter, it is characterized in that, this self-measuring device comprises main digital to analog converter (201), inferior digital to analog converter (203), self-calibrating digital to analog converter (204) and the comparator (202) that circuit connects;

This self-measuring device also comprise circuit connect described main digital to analog converter (201) and time digital to analog converter (203) progressively near controller (205), circuit be connected described main digital to analog converter (201) selftest controller (210) and, circuit connects the self-calibrating controller (208) of described self-calibrating digital to analog converter (204);

Be provided with reference voltage end (VREF1), 1/2 reference voltage end (VREF2) and earth terminal (GND) in the described main digital to analog converter (201).

2. as claimed in claim 1 for progressively near the self-measuring device of pattern number converter, it is characterized in that, described self-measuring device also comprises calibration data memory (207) and accumulator (206), this calibration data memory (207) circuit connects described self-calibrating controller (208) and accumulator (206), and this accumulator (206) circuit connects described calibration data memory (207) and self-calibrating digital to analog converter (204).

As claimed in claim 2 for progressively near the self-measuring device of pattern number converter, it is characterized in that described main digital to analog converter (201) comprises some electric capacity row (C _1A, C _1BC _N), the upper end parallel connection of each electric capacity connects master switch (G1), and master switch (G1) can disconnect or ground connection, and the lower end correspondence of each electric capacity is provided with some electric capacity control switch (S _i), here the value of i be N, N-1 ..., 1B, 1A, described some electric capacity control switch (S _i) connect reference voltage end (VREF1) or 1/2 reference voltage end (VREF2), perhaps earth terminal (GND);

In the electric capacity row, maximum capacitor C _NIt is second largest capacitor C _N-1Twice, second largest capacitor C _N-1It is again the third-largest capacitor C _N-2Twice, by that analogy, this expression and binary bit are closely similar, when ideal situation, except C _1B=C _1AIn addition, following relationship C is arranged _I+1=2C _i(1).

4. one kind is utilized the described self-measuring device of claim 1 to come the method for testing oneself near the pattern number converter to progressively, it is characterized in that this self-testing method comprises following steps:

Step 1, self-calibrating;

The process of self-calibrating is from the electric capacity of maximum;

Step 2, single capacity measurement;

The process of single capacity measurement is from the electric capacity of maximum;

Step 3, interval capacity measurement;

Described step 1 comprises following steps:

Step 1.1, with master switch (G1) ground connection in the main digital to analog converter (201), make i=N, if i--j＞=i, then makes S _j=0, that is, and with corresponding electric capacity control switch ground connection, if j＜i then makes S _j=1, that is, corresponding electric capacity control switch is connect reference voltage end (VREF1);

Step 1.2, disconnection master switch (G1) make i=N, and i--is if j=i then makes S _j=1, that is, corresponding electric capacity control switch is connect reference voltage end (VREF1), if j!=i then makes S _j=0, that is, and with corresponding electric capacity control switch ground connection;

Step 1.3, utilization time digital to analog converter (203) are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th1If,, then jump to step 1.4, if not, then jump to step 1.5;

There are manufacturing defect in step 1.4, prompting, jump to step 1.5;

Step 1.5, judge whether i=1 sets up, if, then jump to step 2, if not, then jump to step 1.1;

Described step 2 comprises following steps:

Step 2.1, with master switch (G1) ground connection, make i=N, i--makes S _i=1/2, that is, corresponding electric capacity control switch is connect 1/2 reference voltage end (VREF2);

Step 2.2, disconnection master switch (G1) make S _I-1=1, that is, corresponding electric capacity control switch is connect reference voltage end (VREF1);

Step 2.3, utilization time digital to analog converter (203) are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th2If,, then jump to step 2.4, if not, then jump to step 2.5;

There are manufacturing defect in step 2.4, prompting, jump to step 2.5;

Step 2.5, judge whether i=1 sets up, if, then jump to step 3, if not, then jump to step 2.1;

Described step 3 comprises following steps:

Step 3.1, with master switch (G1) ground connection, make S _N=S _N-2=S _N-4=...=1/2, that is, the electric capacity control switch of even number electric capacity is connect 1/2 reference voltage end (VREF2), make S _N-1=S _N-3=S _N-5=...=0, that is, and with the electric capacity control switch ground connection of odd number electric capacity;

Step 3.2, disconnection master switch (G1) make S _N-1=S _N-3=S _N-5=...=1, that is, the electric capacity control switch of odd number electric capacity is connect reference voltage end (VREF1), make S _N=S _N-2=S _N-4=...=0, that is, and with the electric capacity control switch ground connection of even number electric capacity;

Step 3.3, utilization time digital to analog converter (203) are measured residual voltage V _Xi, and judge residual voltage V _XiWhether greater than preset threshold V _Th3If,, then jump to step 3.4, if not, then jump to step 3.5;

There are manufacturing defect in step 3.4, prompting, jump to step 3.5;

Step 3.5, judge whether not exist mistake, if, then by test, if not, then not by test, if the test of step 1, step 2 and step 3 does not all have mistake, that total test is passed through, if there is mistake in one of them of step 1, step 2 and step 3, then chip has manufacturing defect.

5. as any one described method to progressively testing oneself near the pattern number converter in the claim 4, it is characterized in that inferior digital to analog converter adopts cut-and-trial to measure residual voltage.

6. the method to progressively testing oneself near the pattern number converter as claimed in claim 4 is characterized in that, in step 1, and threshold value V _Th1Be made as the value littler than the least significant bit of main digital to analog converter, threshold value V _Th2With threshold value V _Th3Numerical value and threshold value V _Th1Identical.

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