TW202230719A - 利用具有＜１１１＞晶體取向之主體半導體基板的裝置整合方案 - Google Patents

利用具有＜１１１＞晶體取向之主體半導體基板的裝置整合方案 Download PDF

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TW202230719A
TW202230719A TW110134592A TW110134592A TW202230719A TW 202230719 A TW202230719 A TW 202230719A TW 110134592 A TW110134592 A TW 110134592A TW 110134592 A TW110134592 A TW 110134592A TW 202230719 A TW202230719 A TW 202230719A
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semiconductor substrate
transistor
device region
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馬克 利維
正鉉 黃
西瓦Ｐ 阿度蘇米利
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明揭示了整合在主體半導體基板上的包括諸如電晶體之類的裝置的結構和形成包括整合在主體半導體基板上的諸如電晶體之類的裝置的結構的方法。主體半導體基板含有具有金剛石晶格結構和<111>晶體取向的單晶半導體材料。第一電晶體形成在主體半導體基板的第一裝置區中，以及第二電晶體形成在主體半導體基板的第二裝置區中。第二電晶體包括在主體半導體基板上的層堆疊，以及層堆疊包括由III-V化合物半導體材料組成的層。

Description

利用具有<111>晶體取向之主體半導體基板的裝置整合方案
本發明係關於半導體裝置製造和積體電路，更具體地，係關於包括整合在主體(bulk)半導體基板上的裝置(例如電晶體)的結構以及形成包括整合在主體半導體基板上的裝置(例如電晶體)的結構的方法。
高壓電力電子裝置，例如高電子遷移率電晶體，可使用III-V族化合物半導體來製造，以利用其材料特性，例如大於矽的載流子遷移率的載流子遷移率。III-V族化合物半導體包括III族元素(鋁、鎵、銦)和V族元素(氮、磷、砷、銻)。高電子遷移率電晶體可以包括具有不同帶隙的晶體III-V族化合物半導體材料之間的異質接面，例如二元氮化鎵和三元氮化鋁鎵之間的異質接面。在操作期間，在異質接面處的界面附近形成二維電子氣並定義高電子遷移率電晶體的通道。
高電子遷移率電晶體與由互補金屬氧化物半導體(CMOS)處理在同一晶片上形成的場效電晶體或異質接面雙極電晶體的整合已被證明是一個 複雜的製程。整合可以藉由晶圓接合或藉由使用工程或混合基板來實現，這些基板的性質使得將高電子遷移率電晶體與這些其他類型的電晶體整合的製程非常複雜。
需要包括整合在主體半導體基板上的裝置(例如電晶體)的結構和形成包括整合在主體半導體基板上的裝置(例如電晶體)的結構的方法。
在本發明的一個實施例中，一種結構包括由具有金剛石(diamond)晶體晶格結構和<111>晶體取向的單晶半導體材料組成的主體半導體基板。所述主體半導體基板具有第一裝置區和第二裝置區。所述結構包括位於所述主體半導體基板的所述第一裝置區中的第一電晶體和位於所述主體半導體基板的所述第二裝置區中的第二電晶體。所述第二電晶體包括在所述主體半導體基板上的層堆疊，並且所述層堆疊包括由III-V化合物半導體材料組成的層。
在本發明的一個實施例中，一種方法包括提供由具有金剛石晶體晶格結構和<111>晶體取向的單晶半導體材料組成的主體半導體基板。所述方法還包括在所述主體半導體基板的第一裝置區中形成第一電晶體，在所述主體半導體基板的第二裝置區中形成包括由III-V化合物半導體材料組成的層的層堆棧，以及使用所述層堆棧形成第二電晶體。
10:半導體基板
12:頂面
14:淺溝槽隔離區
16:裝置區
18:裝置區
20:裝置區
22:閘極導體層、層
24:閘極介電層、層
26:硬遮罩
29:側壁、溝槽側壁
30:溝槽
31:側壁、溝槽側壁
32:表面
34:側壁間隔件
35:頂面
36:層堆疊
37:側壁
38:介電層
40:源極/汲極區
42:場效電晶體、電晶體
44:雙極接面電晶體、電晶體
46:集極電極
48:射極電極
50:基極層
52:閘極電極
54:電晶體
56:源極區
58:汲極區
60:互連結構
62:介電層
64:觸點
66:金屬線
68:開口
76:緩衝層、層
78:通道層、層
80:間隔層、層
82:阻擋層、層
合併在本說明書中並構成本說明書一部分的附圖說明了本發明的各種實施例，並與上面給出的本發明的一般描述和下面給出的實施例的詳細 描述一起，用於解釋本發明的各實施例。在附圖中，相同的元件符號表示各種視圖中的相同特徵。
圖1至圖6為根據本發明實施例的處理方法的連續製造階段的結構的橫截面圖。
圖3A為根據本發明實施例的圖3的一部分的放大截面圖。
圖7為根據本發明的替代實施例的結構的橫截面圖。
圖8和圖9是根據本發明的替代實施例的處理方法的連續製造階段的結構的橫截面圖。
圖10是根據本發明的替代實施例的結構的橫截面圖。
參考圖1，根據本發明的實施例，提供包含單晶半導體材料(例如單晶矽)的半導體基板10。半導體基板10具有頂面12，其可以是平面的。半導體基板10是包含單晶半導體材料(例如，單晶矽)的主體基板。在一實施例中，半導體基板10的單晶半導體材料可以具有如Miller指數所規定的<111>晶體取向的金剛石晶體晶格結構。在一實施例中，半導體基板10可包含具有<111>晶體取向的金剛石晶格結構的單晶矽。對於具有<111>晶體取向的半導體基板10，(111)晶體學平面(crystallographic plane)平行於半導體基板10的頂面12，並且[111]晶體學方向(crystallographic direction)垂直於(111)平面。(100)晶體學軸(crystallographic axe)未位於頂面12的平面內。半導體基板10可以被表徵為非絕緣體上矽基板(即，非SOI基板)，其缺少絕緣體上矽(SOI)基板的埋置氧化物層特性。在一實施例中，半導體基板10可完全由具有<111>晶體取向 的半導體材料組成。
形成從半導體基板10的頂面12延伸到半導體基板10的淺溝槽隔離區14。淺溝槽隔離區14可包含藉由化學氣相沉積而沉積到蝕刻在半導體基板10中的溝槽中的介電材料，並進行拋光和去釉(deglazed)。包含在淺溝槽隔離區14中的介電材料可包括二氧化矽、氮化矽、碳化矽、富矽二氧化矽或這些材料中的兩種或多種的組合。淺溝槽隔離區14可延伸至相對於頂面12進入半導體基板10的深度d1。淺溝槽隔離區14包圍並定義多個裝置區16、18、20。在一實施例中，裝置區18中的頂面12可以與裝置區16中的頂面12共面，也可以與裝置區20中的頂面12共面。
在半導體基板10上形成由摻雜多晶矽(即，摻雜多晶矽)組成的閘極導體層22和由電性絕緣體(例如二氧化矽)組成的閘極介電層24。這些層22、24形成在所有裝置區16、18、20的頂面12上。
硬遮罩26可以形成在半導體基板10上的層22、24的上方，並且被圖案化為包括通常位於裝置區18上方的開口。硬遮罩26可以由介電材料(例如氮化矽)組成，並可藉由微影和蝕刻製程形成圖案。由硬遮罩26中的開口暴露的閘極導體層22和閘極介電層24的區段可以藉由蝕刻製程(例如反應離子蝕刻製程)進行蝕刻來移除，所述蝕刻製程可將半導體基板10的頂面12暴露在裝置區18中。
隨後，藉由使用另一蝕刻製程(例如反應離子蝕刻製程)進行蝕刻，在硬遮罩26中的開口位置處形成半導體基板10中的溝槽30。溝槽30可延伸至位於半導體基板10的表面32的溝槽底部，並且可具有側面或側壁29、31。溝槽30可被定義裝置區18的淺溝槽隔離區14包圍。表面32可位於半導體基板 10中相對於頂面12的深度d2處，深度d2大於淺溝槽隔離區14的深度d1。硬遮罩26在蝕刻製程期間保護裝置區16和裝置區20中的閘極導體層22和閘極介電層24的區段。在一實施例中，表面32可以是平面的並且沒有形貌。在一實施例中，頂面12可以是平面的，表面32可以是平面的，並且頂面12和表面32的平面可以是平行的。
參考圖2，其中，類似的元件符號表示圖1中的類似特徵，在處理方法的後續製造階段，在與溝槽30的側壁29、31相鄰處形成側壁間隔件34。側壁間隔件34可從半導體基板10的頂面12延伸至溝槽30底部的表面32。側壁間隔件34可藉由沉積由介電材料(例如，氮化矽)組成的襯層，並使用非等向性蝕刻製程(例如反應離子蝕刻製程)蝕刻沉積的襯層來形成。
參考圖3、圖3A，其中，類似的元件符號表示圖2中的類似特徵，在處理方法的後續製造階段，在位於溝槽30內的半導體基板10的表面32上形成包含一個或多個化合物半導體層的層堆疊36。在一實施例中，層堆疊36可包括至少一個由III-V化合物半導體材料組成的晶體層。在一實施例中，層堆疊36可包括至少一個由二元III-V化合物半導體材料組成的晶體層。在一實施例中，層堆疊36可包括至少一個由三元III-V化合物半導體材料組成的晶體層。在一實施例中，層堆疊36可包括由不同III-V化合物半導體材料組成的多晶體層。在一實施例中，層堆疊36可包括由二元III-V化合物半導體材料組成的至少一個晶體層和由三元III-V化合物半導體材料組成的至少一個晶體層。在一實施例中，層堆疊36可包括一個或多個包含氮化鎵或基於氮化鎵(例如，氮化鋁鎵)的三元III-V化合物半導體材料的晶體層。在一實施例中，層堆疊36可包括一個或多個含有鎵和氮的晶體層。
層堆疊36可藉由磊晶生長製程形成。層堆疊36的每一層可以具有單晶的晶體結構，或者，可選地，具有存在不同程度的晶體缺陷率的基本上單晶的晶體結構。半導體基板10的半導體材料(例如，單晶矽)的<111>晶體取向可通過比具有<100>晶體取向的基板更接近的晶格匹配來促進具有低晶體缺陷率的層堆疊36的III-V化合物半導體材料(例如氮化鎵)的磊晶生長。具體地，半導體基板10的表面平面上具有<111>晶體取向的原子以六邊形排列，其可以與層堆疊36中的一種或多種化合物半導體材料的晶體結構合理地晶格匹配(例如，氮化鎵的纖鋅礦晶體結構(基於二元六角形密排晶體系統)。
在一實施例中，層堆疊36可藉由選擇性磊晶生長製程形成，其中，半導體材料不在介電表面上形成，例如硬遮罩26和側壁間隔件34。在一實施例中，層堆疊36可由非選擇性磊晶生長製程形成，其中，半導體材料藉由微影和蝕刻製程沉積和圖案化。在一實施例中，層堆疊36的側壁37可位於與溝槽側壁29、31鄰接處並與之隔開，在這種情況下，溝槽30可基本上由層堆疊36填充。在代表性實施例中，層堆疊36具有向內傾斜以遠離溝槽側壁29、31的側壁37，以定義例如梯形形狀，並將側壁37與溝槽側壁29、31隔開。在一實施例中，側壁37可在層堆疊36的頂面35處會聚，頂面35可與半導體基板10的頂面12共面或基本上共面。隔離區(未示出)可藉由例如氮或氬的遮罩植入，在層堆疊36的頂面35處形成。
在一實施例中，如圖3A所示，層堆疊36可包括緩衝層76、通道層78、間隔層80和阻擋層82。層76、78、80、82可使用磊晶生長製程(例如金屬有機化學氣相沉積)連續形成。層76、78、80、82各自可以具有單晶的晶體結構，或者，可選地，具有不同程度的晶體缺陷率的基本上單晶的晶體結構。 層76、78、80、82中的一個或多個可包括具有不同組成或摻雜的多個子層。緩衝層76可包含III-V化合物半導體材料，例如氮化鎵，其根據材料組成、摻雜和/或層厚定制以適應半導體基板10的材料和通道層78的材料之間的晶格失配。配置在緩衝層76上方的通道層78可以包含III-V化合物半導體材料，例如氮化鎵。間隔層80和阻擋層82設置在通道層78上方，間隔層80位於通道層78和阻擋層82之間。間隔層80可以是薄的，並且可以包含III-V化合物半導體，例如氮化鋁。阻擋層82可包含III-V化合物半導體，例如氮化鋁鎵、氮化鋁或氮化銦鋁，其具有與不同組成的通道層78的異質界面。間隔層80和阻擋層82以及通道層78的材料特性有助於在裝置操作期間在充滿高度可移動和豐富電子的異質界面處產生二維電子氣。
參考圖4，其中，類似的元件符號表示圖3中的類似特徵，在處理方法的後續製造階段，介電層38可以藉由微影和蝕刻製程沉積和圖案化，從而覆蓋裝置區18中的層堆疊36。在介電層38沉積和圖案化之後，藉由蝕刻製程從裝置區16和裝置區20移除硬遮罩26，以暴露閘極導體層22和閘極介電層24。
閘極導體層22和閘極介電層24可隨後藉由微影和蝕刻製程來圖案化，以定義裝置區16中的場效電晶體42的閘極結構。在圖案化期間，閘極導體層22和閘極介電層24從裝置區20移除。場效電晶體42的附加元件可以藉由互補金屬氧化物(CMOS)處理來製造，以在半導體基板10的裝置區16中形成裝置結構。場效電晶體42還可以包括源極/汲極區40和閘極結構下方的通道區。場效電晶體42的通道區和源極/汲極區40包含半導體基板10的單晶半導體材料的相應部分。源極/汲極區40至少部分位於頂面12下方，並且通道區通常位於 源極/汲極區40之間的頂面12下方。包含在場效電晶體42的閘極結構中的圖案化後的閘極導體層22和閘極介電層24可以作為裝置層定位在半導體基板10的頂面12上和之上。在一個實施例中，包含在場效電晶體42的閘極結構中的圖案化後的閘極介電層24可以作為裝置層直接定位在半導體基板10的頂面12上。
雙極接面電晶體44可在半導體基板10的裝置區20中製造作為裝置結構。雙極接面電晶體44可包括多個端子，其形式為半導體基板10中定義的集極電極46、射極電極48、以及設置在集極電極46和射極電極48之間的基極層50。在替代實施例中，可以形成集極電極上(collector-up)雙極接面電晶體，其中，射極電極被設置為半導體基板10中的端子。射極電極48和基極層50可以被定位為半導體基板10的頂面12上和之上的裝置層。在一個實施例中，基極層50可以作為裝置層直接定位在半導體基板10的頂面12上。集極電極46包含半導體基板10的半導體材料的一部分，其可至少部分地且較佳地完全地位於頂面12下方的半導體基板10中。基極層50可包含在半導體基板10的頂面12上磊晶生長的單晶半導體材料(例如，矽鍺)。在一個實施例中，集極電極46和射極電極48可包含n型半導體材料，基極層50可包含p型半導體材料以定義NPN電晶體。雙極接面電晶體44可以由雙極互補金屬氧化物(BiCMOS)處理形成，其為CMOS處理的變體。
場效電晶體42和雙極接面電晶體44構成不同類型或分類的電晶體結構。場效電晶體42和雙極接面電晶體44之間的區別在於，只有大多數電荷載流子在場效電晶體42中流動，然而，大多數和少數的電荷載流子均可在雙極接面電晶體44中流動。場效電晶體42和雙極接面電晶體44在其各自的結構中不包括任何碳化矽層，因此不含碳化矽。場效電晶體42和雙極接面電晶體44都 形成在具有與用於形成層堆疊36的半導體材料相同的<111>晶體取向的半導體材料上。
參考圖5，其中類似的元件符號表示圖4中的類似特徵，在處理方法的後續製造階段，使用層堆疊36將電晶體54形成為裝置結構。為此，介電層38在裝置區18中藉由微影和蝕刻製程被圖案化，以定義形成電晶體54的閘極電極52的開口。閘極電極52可由金屬(例如金屬氮化物)組成，金屬藉由微影和蝕刻製程沉積和圖案化以定義給定形狀。電晶體54的源極區56和汲極區58可以藉由利用微影和蝕刻製程在介電層38中圖案化開口，然後在圖案化開口中形成金屬(例如金屬氮化物)來形成。來自源極區56和汲極區58的金屬原子可以擴散到層堆疊36中。
電晶體54不是由CMOS製程形成的，因此可以認為是非CMOS電晶體。在一個實施例中，電晶體54可以是高電子遷移率電晶體(HEMT)。在一個實施例中，電晶體54可以是金屬絕緣體半導體高電子遷移率電晶體(MISHEMT)。在一個實施例中，電晶體54可以是金屬氧化物半導體高電子遷移率電晶體(MOSHEMT)。
儘管半導體基板10的半導體材料(例如，單晶矽)的<111>晶體取向使得具有低晶體缺陷率的層堆疊36的III-V化合物半導體材料能夠磊晶生長，但是場效電晶體42和/或雙極接面電晶體44與在其它晶體取向的半導體基板上形成的可比較的電晶體相比，由於<111>晶體取向，可表現出非優化的電性能。單晶半導體基板的許多結構和電子性質是高度非等向性的，並且依賴於晶體的取向。儘管如此，具有<111>晶體取向的半導體基板10的實施允許電晶體54與場效電晶體42和/或雙極接面電晶體44整合在同一半導體基板10上，而無需 複雜的製造製程，例如晶圓接合，或使用工程或混合基板(例如，對於裝置層具有一個或多個晶體取向的SOI基板)，這對較差電性能而言可被認為是可接受權衡的方案。
參考圖6，其中類似的元件符號表示圖5中的類似特徵，在處理方法的後續製造階段，中段製程以及其後的後段製程，包括形成用於位於半導體基板10上方和電晶體42、44、54之上的互連結構60的觸點、通孔、以及佈線。可以形成互連結構60的各種金屬化層級，例如第一金屬化(M1)層級，這些金屬化層級藉由接觸層級與場效電晶體42、雙極接面電晶體44和電晶體54耦合。就此而言，互連結構60可包括一個或多個介電層62、具有金屬線66的金屬化層級和具有將金屬線66耦合到場效電晶體42、雙極接面電晶體44和電晶體54的觸點64的接觸層級。
參考圖7並根據替代實施例，層堆疊36的側壁37可與溝槽側壁29、31共同延伸，在這種情況下，溝槽30可由層堆疊36完全填充。可選擇生長條件以賦予層堆疊36給定形狀。處理可如結合圖4至圖6所述繼續。
參考圖8並根據替代實施例，在完成場效電晶體42和雙極接面電晶體44的形成之後，可以完全形成通道30、層堆疊36和電晶體54。在這方面，一個或多個介電層62可被形成和圖案化以提供定義通往裝置區18中的半導體基板10的頂面12的路徑的開口68。在代表性實施例中，在形成觸點64和金屬線66之前形成開口68。在一個實施例中，可以在形成耦合到場效電晶體42和雙極接面電晶體44的接觸層級的觸點64之後形成開口68。在一個實施例中，可以在形成第一金屬化層級的金屬線66和將金屬線66耦合到場效電晶體42和雙極接面電晶體44的接觸層級的觸點64之後形成開口68。
參考圖9，其中類似的元件符號表示圖8中的類似特徵，在處理方法的後續製造階段，溝槽30隨後形成在半導體基板10中的一個或多個介電層62中的開口68的位置處。隨後使用半導體基板10中的通道30形成側壁間隔件34、層堆疊36和電晶體54。在形成電晶體54之後，可以用介電材料重新填充開口68，並且可以藉由形成耦合到電晶體54的觸點64和金屬線66來完成互連結構60。
參考圖10並根據替代實施例，層堆疊36可形成在半導體基板10的頂面12上，而無需預先形成溝槽30。藉由放棄溝槽形成，層堆疊36和使用層堆疊36形成的電晶體54可以位於與場效電晶體42和雙極接面電晶體44相同的平面中。更具體地，層堆疊36、場效電晶體42的閘極結構以及雙極接面電晶體44的射極電極48和基極層50可位於頂面12上，其可被認為為電晶體42、44、54提供公共平面。
上述方法用於製造積體電路晶片。由此產生的積體電路晶片可由製造商以原始晶圓形式(例如，作為具有多個未封裝晶片的單個晶圓)、作為裸晶片或以封裝形式分發。在後一種情況下，晶片安裝在單個晶片封裝中(例如，塑料載體，帶有固定在主板或其他更高級別載體上的引線)或多晶片封裝中(例如，具有表面互連或埋置互連中的一個或兩個的陶瓷載體)。在任何情況下，晶片可以與其他晶片、分立電路元件和/或其他信號處理裝置整合，作為中間產品或最終產品的一部分。
本文中引用的由近似語言修改的術語，例如“關於”、“大約”和“實質上”，不限於指定的精確值。近似語言可能對應於用於測量值的儀器的精度，除非另有取決於儀器的精度，否則可能表示規定值的+/-10%。
本文中對諸如“垂直”、“水平”等術語的引用是作為示例而不是作為限制來建立參考框架的。本文中使用的術語“水平”被定義為與半導體基板的常規平面平行的平面，而不管其實際三維空間取向如何。術語“垂直”和“法線”指的是與水平面垂直的方向，正如剛才定義的那樣。術語“橫向”是指水平面內的方向。
與另一個特徵“連接”或“耦合”的一個特徵可以直接連接或耦合到另一個特徵或與另一個特徵耦合，或者可以存在一個或多個中間特徵。如果不存在中間特徵，則一個特徵可以“直接連接”或“直接耦合”到另一特徵或與另一特徵一起。如果存在至少一個中間特徵，則一個特徵可以與另一特徵“間接連接”或“間接耦合”。一個特徵在另一特徵上或接觸另一特徵可以直接在另一特徵上或與另一特徵直接接觸，或者相反，可以存在一個或多個中間特徵。如果不存在中間特徵，則一個特徵可以直接在另一特徵上或與另一特徵直接接觸。如果存在至少一個中間特徵，則一個特徵可間接在另一特徵上或與另一特徵間接接觸。
本發明的各種實施例的描述是為了說明的目的而提供的，但並不打算詳盡或限於所公開的實施例。在不脫離所描述的實施例的範圍和精神的情況下，許多修改和變化對於本領域的普通技術人員將是顯而易見的。選擇本文中使用的術語是為了最好地解釋實施例的原理、相對於市場中發現的技術的實際應用或技術改進，或者使本領域的普通技術人員能夠理解本文中公開的實施例。
10:半導體基板
12:頂面
14:淺溝槽隔離區
16:裝置區
18:裝置區
20:裝置區
29:側壁、溝槽側壁
31:側壁、溝槽側壁
32:表面
34:側壁間隔件
36:層堆疊
38:介電層
40:源極/汲極區
42:場效電晶體、電晶體
44:雙極接面電晶體、電晶體
54:電晶體
60:互連結構
62:介電層
64:觸點
66:金屬線

Claims (20)

  1. 一種結構，包括：
    主體半導體基板，包括具有金剛石晶體晶格結構和<111>晶體取向的單晶半導體材料，且該主體半導體基板具有第一裝置區和第二裝置區；
    第一電晶體，位於該主體半導體基板的該第一裝置區中；以及
    第二電晶體，位於該主體半導體基板的該第二裝置區中，該第二電晶體包括位於該主體半導體基板上的層堆疊，以及該層堆疊包括由III-V化合物半導體材料組成的層。
  2. 如請求項1所述的結構，其中，該單晶半導體材料為單晶矽。
  3. 如請求項1所述的結構，其中，該III-V化合物半導體材料為氮化鎵。
  4. 如請求項1所述的結構，其中，該層堆疊的該III-V化合物半導體材料具有基本上為單晶的晶體結構。
  5. 如請求項1所述的結構，其中，該主體半導體基板具有頂面，以及該第一電晶體為場效電晶體，該場效電晶體包括位於該主體半導體基板中且至少部分位於該頂面下方的源極/汲極區。
  6. 如請求項5所述的結構，其中，該主體半導體基板具有第三裝置區，且進一步包括：
    雙極接面電晶體，位於該主體半導體基板的該第三裝置區中，該雙極接面電晶體包括位於該主體半導體基板中且至少部分位於該頂面下方的端子。
  7. 如請求項1所述的結構，其中，該主體半導體基板具有頂面，以及該第一電晶體為包括位於該主體半導體基板中且至少部分位於該頂面下方 的端子的雙極接面電晶體。
  8. 如請求項1所述的結構，其中，該主體半導體基板具有第三裝置區，且進一步包括：
    第三電晶體，位於該主體半導體基板的該第三裝置區中；
    其中，該第一電晶體和該第三電晶體為不同電晶體類型。
  9. 如請求項1所述的結構，其中，該主體半導體基板具有頂面，以及該層堆疊位於該主體半導體基板的該頂面上。
  10. 如請求項9所述的結構，其中，該主體半導體基板的該頂面在該第一裝置區中和該第二裝置區中是平面的，以及該第一電晶體包括位於該主體半導體基板的該頂面上的裝置層。
  11. 如請求項1所述的結構，其中，該主體半導體基板具有第一表面和從該第一表面延伸至該主體半導體基板中的溝槽，以及該層堆疊位於該溝槽內的該主體半導體基板上。
  12. 如請求項11所述的結構，其中，該主體半導體基板具有位於該溝槽的底部的第二表面，以及該層堆疊位於該第二表面上。
  13. 如請求項11所述的結構，進一步包括：
    淺溝槽隔離區，位於該主體半導體基板中，該淺溝槽隔離區橫向位於該第一裝置區和該第二裝置區之間；
    其中，與該淺溝槽隔離區相比，該溝槽相對於該第一表面延伸到該主體半導體基板中更深的深度。
  14. 如請求項11所述的結構，其中，該溝槽包括複數個側壁，且進一步包括：
    間隔件，位於該複數個側壁的每一個上，該間隔件由介電材料組成。
  15. 如請求項1所述的結構，進一步包括：
    互連結構，位於該主體半導體基板上方，該互連結構包括耦合到該第一電晶體的複數個第一觸點和耦合到該第二電晶體的複數個第二觸點。
  16. 如請求項1所述的結構，進一步包括：
    淺溝槽隔離區，位於該主體半導體基板中，該淺溝槽隔離區橫向位於該第一裝置區和該第二裝置區之間。
  17. 一種方法，包括：
    提供由具有金剛石晶體晶格結構和<111>晶體取向的單晶半導體材料組成的主體半導體基板；
    在該主體半導體基板的第一裝置區中形成第一電晶體；
    在該主體半導體基板的第二裝置區中形成包括由III-V化合物半導體材料組成的層的層堆疊；以及
    使用該層堆疊形成第二電晶體。
  18. 如請求項17所述的方法，其中，該單晶半導體材料為單晶矽，且該III-V化合物半導體材料為氮化鎵。
  19. 如請求項17所述的方法，進一步包括：
    形成溝槽，從第一表面延伸到該主體半導體基板中到該溝槽底部的第二表面；
    其中，該層堆疊位於該溝槽內的該主體半導體基板的該第二表面上。
  20. 如請求項17所述的方法，進一步包括：
    在該主體半導體基板中形成淺溝槽隔離區；
    其中，該淺溝槽隔離區橫向位於該第一裝置區和該第二裝置區之間。
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