TW202230696A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TW202230696A
TW202230696A TW110133144A TW110133144A TW202230696A TW 202230696 A TW202230696 A TW 202230696A TW 110133144 A TW110133144 A TW 110133144A TW 110133144 A TW110133144 A TW 110133144A TW 202230696 A TW202230696 A TW 202230696A
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Taiwan
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layer
copper
ruthenium
sidewalls
damascene structure
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TW110133144A
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Chinese (zh)
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金書正
紀志堅
林其鋒
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台灣積體電路製造股份有限公司
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Publication of TW202230696A publication Critical patent/TW202230696A/en

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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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Abstract

Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiO x) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance/capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

Description

半導體裝置semiconductor device

本發明實施例是關於一種半導體裝置，特別是關於一種具有具有低電阻銅內連線的半導體裝置。Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having low-resistance copper interconnects.

生產線後端（back end of line, BEOL） 區為電子裝置（例如，處理器、記憶體）的區域，其中各個半導體裝置（例如，電晶體、電容器、電阻器）藉由金屬化層（也稱作導線）及連接金屬化層的導孔而互連。可在同一製造製程期間形成金屬化層及一個或多個導孔，上述製造製程被稱作雙鑲嵌製程。在雙鑲嵌製程中，使用導孔先製方法（via-first procedure）或溝槽先製方法（trench-first procedure）蝕刻用於金屬化層的導孔及溝槽。然後，在相同的鍍膜操作（例如，電鍍）中用導電材料填充溝槽及導孔。The back end of line (BEOL) area is the area of electronic devices (eg, processors, memories) in which individual semiconductor devices (eg, transistors, capacitors, resistors) are protected by metallization layers (also called as wires) and vias connected to the metallization layer for interconnection. The metallization layer and one or more vias may be formed during the same manufacturing process, referred to as a dual damascene process. In a dual damascene process, via-first procedure or trench-first procedure is used to etch vias and trenches for metallization layers. The trenches and vias are then filled with conductive material in the same coating operation (eg, electroplating).

本發明實施例提供一種半導體裝置，包括：內連線，被包括於半導體裝置的介電層中，包括接觸插塞；氧化釕膜，直接位於接觸插塞的側壁上；釕襯層，位於接觸插塞的側壁上的氧化釕膜上方及接觸插塞的底表面上方；及銅層，位於接觸插塞中的釕襯層上方。An embodiment of the present invention provides a semiconductor device, comprising: an interconnection included in a dielectric layer of the semiconductor device, including a contact plug; a ruthenium oxide film directly on the sidewall of the contact plug; a ruthenium liner layer, located on the contact plug over the ruthenium oxide film on the sidewalls of the plug and over the bottom surface of the contact plug; and a copper layer over the ruthenium liner in the contact plug.

本發明實施例提供一種半導體裝置的形成方法，包括：形成內連線於半導體裝置的一或多個介電層中，其中內連線包括導孔及位於導孔上方的溝槽；形成氧化鋅矽 (zinc silicon oxide)阻障於導孔的側壁上及溝槽的側壁上；及用銅層填充導孔及溝槽。An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming interconnects in one or more dielectric layers of the semiconductor device, wherein the interconnects include via holes and trenches above the via holes; forming zinc oxide Zinc silicon oxide is blocked on the sidewalls of the via and the sidewalls of the trench; and the via and trench are filled with a copper layer.

本發明實施例提供一種半導體裝置的形成方法，包括：形成內連線於半導體裝置的一或多個介電層中，其中內連線包括導孔及位於導孔上方的溝槽；進行預處理操作於導孔的底表面上，使導孔的底表面變非金屬性；在預處理操作之後，形成氮化鉭(tantalum nitride, TaN)膜於導孔的側壁上及溝槽的側壁上；在形成氮化鉭膜後，進行電漿處理操作於導孔的底表面上，使導孔的底表面變金屬性；形成釕(ruthenium, Ru)襯層於氮化鉭膜上及導孔的底表面上；及形成銅 (copper, Cu) 層於溝槽中的釕襯層上。An embodiment of the present invention provides a method for forming a semiconductor device, including: forming interconnects in one or more dielectric layers of the semiconductor device, wherein the interconnects include via holes and trenches above the via holes; and performing preprocessing operating on the bottom surface of the via hole to make the bottom surface of the via hole non-metallic; after the pretreatment operation, a tantalum nitride (TaN) film is formed on the sidewall of the via hole and the sidewall of the trench; After the tantalum nitride film is formed, plasma treatment is performed on the bottom surface of the via hole to make the bottom surface of the via hole metallic; a ruthenium (Ru) lining is formed on the tantalum nitride film and the bottom surface of the via hole. on the bottom surface; and forming a copper (Cu) layer on the ruthenium liner in the trench.

以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件及其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一及第二元件直接接觸的實施例，也可能包含額外的元件形成在第一及第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值以及∕或字母。如此重複是為了簡明及清楚之目的，而非用以表示所討論的不同實施例及∕或配置之間的關係。The following disclosure provides numerous embodiments, or examples, for implementing various elements of the provided subject matter. Specific examples of components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples, and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. Furthermore, embodiments of the present invention may repeat reference numerals and/or letters in various examples. This repetition is for the purpose of brevity and clarity and is not intended to represent the relationship between the different embodiments and/or configurations discussed.

再者，其中可能用到與空間相對用詞，例如「在…之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個（些）部件或特徵與另一個（些）部件或特徵之間的關係。空間相對用詞用以包括使用中或製程中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。Furthermore, words relative to space may be used, such as "below", "below", "lower", "above", "higher" and the like, for the convenience of describing the diagram. The relationship between one component(s) or feature(s) and another component(s) or feature(s) in the formula. Spatially relative terms are used to include different orientations of the device in use or in the process, as well as the orientation depicted in the drawings. When the device is turned in a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

由於相對於例如鋁的其他導電材料，銅具有較低的接觸電阻及片電阻（sheet resistance），銅已成為 BEOL 金屬化層及導孔的首選材料。銅的較低電阻率（resistivity）提供了較低的電阻/電容 （resistance/capacitance, RC） 時間常數及電子裝置之間更快的信號傳播（propagation）。然而，銅表現出例如高擴散（或電遷移）率等缺點，這會導致銅離子擴散到周圍的介電材料中。這會導致BEOL金屬化層及導孔的電阻率增加，這可降低電子裝置的電氣性能（electrical performance）。再者，擴散可能導致銅離子遷移到較低的裝置層（例如，生產線中端（middle end of line, MEOL）層及/或生產線前端（front end of line, FEOL）層），這會導致半導體裝置故障並降低製造產率（manufacturing yield）。Copper has become the material of choice for BEOL metallization and vias due to its lower contact and sheet resistance relative to other conductive materials such as aluminum. The lower resistivity of copper provides a lower resistance/capacitance (RC) time constant and faster signal propagation between electronic devices. However, copper exhibits disadvantages such as high diffusion (or electromobility) rates, which can cause copper ions to diffuse into the surrounding dielectric material. This results in an increase in the resistivity of the BEOL metallization and vias, which can degrade the electrical performance of the electronic device. Furthermore, diffusion can cause copper ions to migrate to lower device layers (eg, middle end of line (MEOL) layers and/or front end of line (FEOL) layers), which can lead to semiconductor devices failure and reduced manufacturing yield.

本文所述的一些實施方式提供包括低電阻銅內連線的半導體結構及用於形成低電阻銅內連線的製造技術。本文所述的低電阻銅內連線可被包括於電子裝置的各個區中，並且可包括雙鑲嵌結構、單鑲嵌結構、或接觸插塞，上述區域例如BEOL區或MEOL區。本文所述的各種技術及材料的組合可用於實現銅內連線的低接觸電阻及低片電阻，特別是例如減少氮化鉭 （antalum nitride,TaN） 襯層/膜厚度（或排除使用氮化鉭作為銅擴散阻障）以及使用釕 （ruthenium， Ru） 及/或氧化鋅矽 （zinc silicon oxide, ZnSiO x） 作為銅擴散阻障層。本文所述的銅內連線件的低接觸電阻及低片電阻特別是可藉由降低電子裝置的RC時間常數及增加電子裝置之間的信號傳播速度等來提高包括此類銅內連線件的電子裝置的電氣性能。 Some embodiments described herein provide semiconductor structures including low resistance copper interconnects and fabrication techniques for forming low resistance copper interconnects. The low resistance copper interconnects described herein can be included in various regions of an electronic device, such as BEOL regions or MEOL regions, and can include dual damascene structures, single damascene structures, or contact plugs. The various techniques and combinations of materials described herein can be used to achieve low contact resistance and low sheet resistance for copper interconnects, particularly, for example, to reduce tantalum nitride (TaN) liner/film thickness (or to exclude the use of nitrides) tantalum as a copper diffusion barrier) and ruthenium (Ru) and/or zinc silicon oxide ( ZnSiOx ) as a copper diffusion barrier. The low contact resistance and low sheet resistance of the copper interconnects described herein can improve the inclusion of such copper interconnects, among other things, by reducing the RC time constant of the electronic device and increasing the speed of signal propagation between the electronic devices. electrical performance of electronic devices.

第1圖係在其中可實現本文描述的系統及/或方法的例示性環境100的圖。如第1圖所示，環境100可包括複數個半導體製程（processing）設備102-116及晶圓/晶粒運輸設備118。複數個半導體製程設備102-116可包括沉積設備102、曝光設備104、顯影設備106、蝕刻設備108、平坦化設備110、鍍膜（plating）設備112、預處理設備114、電漿設備116、及/或另一種類型的半導體製程設備。被包括於例示性環境100中的設備可被包括於半導體無塵室（clean room）、半導體代工廠（foundry）、半導體處理及/或製造設施等中。FIG. 1 is a diagram of an exemplary environment 100 in which the systems and/or methods described herein may be implemented. As shown in FIG. 1 , the environment 100 may include a plurality of semiconductor processing equipment 102 - 116 and wafer/die transport equipment 118 . The plurality of semiconductor processing equipment 102-116 may include deposition equipment 102, exposure equipment 104, development equipment 106, etching equipment 108, planarization equipment 110, plating equipment 112, pretreatment equipment 114, plasma equipment 116, and/or or another type of semiconductor process equipment. The equipment included in the exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing and/or manufacturing facility, and the like.

沉積設備102是包括半導體處理腔室及能夠將各種類型的材料沉積到基板上的一個或多個裝置的半導體製程設備。在一些實施方式中，沉積設備102包括能夠在例如晶圓的基板上沉積光阻層的旋轉塗佈設備。在一些實施方式中，沉積設備102包括化學氣相沉積（chemical vapor deposition, CVD）設備、原子層沉積 （atomic layer deposition, ALD） 設備、電漿增強原子層沉積 （plasma-enhanced atomic layer deposition, PEALD） 設備、或其他類型的 CVD 設備，上述化學氣相沉積設備例如電漿增強CVD（plasma-enhance, PECVD）設備、高密度電漿CVD（high-density plasma CVD, HDP-CVD）設備、次氣壓CVD（sub-atmospheric CVD, SACVD）設備。在一些實施方式中，沉積設備102包括物理氣相沉積（physical vapor deposition, PVD）設備，例如濺鍍設備或另一種類型的PVD設備。在一些實施方式中，例示性環境100包括多種類型的沉積設備102。Deposition equipment 102 is a semiconductor processing equipment that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition apparatus 102 includes a spin coating apparatus capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, the deposition apparatus 102 includes a chemical vapor deposition (CVD) apparatus, an atomic layer deposition (ALD) apparatus, a plasma-enhanced atomic layer deposition (PEALD) apparatus ) equipment, or other types of CVD equipment, the above-mentioned chemical vapor deposition equipment such as plasma-enhanced CVD (plasma-enhance, PECVD) equipment, high-density plasma CVD (high-density plasma CVD, HDP-CVD) equipment, sub-pressure CVD (sub-atmospheric CVD, SACVD) equipment. In some embodiments, deposition apparatus 102 includes a physical vapor deposition (PVD) apparatus, such as a sputtering apparatus or another type of PVD apparatus. In some embodiments, the exemplary environment 100 includes multiple types of deposition apparatus 102 .

曝光設備104是能夠將光阻層暴露於例如下列輻射源的半導體製程設備：紫外光（ultraviolet light, UV）源（例如，深紫外光源、極紫外光（extreme UV light, EUV）源等）、x射線源、電子束（electron beam, e-beam）源等。曝光設備104可將光阻層暴露於輻射源，以將圖案從光罩轉移至光阻層。圖案可包括用於形成一個或多個半導體裝置的一個或多個半導體裝置層圖案、可包括用於形成半導體裝置的一個或多個結構的圖案、可包括用於蝕刻半導體裝置的各個部分的圖案、及/或類似圖案。在一些實施方式中，曝光設備104包括掃描曝光器（scanner）、步進機（stepper）、或類似類型的曝光設備。Exposure equipment 104 is semiconductor processing equipment capable of exposing the photoresist layer to radiation sources such as: an ultraviolet light (UV) source (eg, a deep UV light source, an extreme UV light (EUV) source, etc.), X-ray source, electron beam (electron beam, e-beam) source, etc. Exposure apparatus 104 may expose the photoresist layer to a radiation source to transfer the pattern from the reticle to the photoresist layer. Patterns may include one or more layer patterns of semiconductor devices for forming one or more semiconductor devices, may include patterns for forming one or more structures of semiconductor devices, may include patterns for etching portions of semiconductor devices , and/or similar patterns. In some embodiments, exposure apparatus 104 includes a scanner, stepper, or similar type of exposure apparatus.

顯影設備（developer tool）106為能夠將已經暴露於輻射源的光阻層顯影的半導體製程設備，以將從曝光設備104轉移至光阻層的圖案顯影。在一些實施方式中，顯影設備106藉由移除光阻層的未曝光部分來顯影圖案。在一些實施方式中，顯影設備106藉由移除光阻層的曝光部分來顯影圖案。在一些實施方式中，顯影設備106藉由使用化學顯影劑溶解光阻層的曝光或未曝光部分來顯影圖案。A developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop patterns transferred from the exposure tool 104 to the photoresist layer. In some embodiments, developing device 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, developing device 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, developing device 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

蝕刻設備108為能夠蝕刻基板、晶圓、或半導體裝置的各種類型的材料的半導體製程設備。舉例而言，蝕刻設備108可包括濕式蝕刻設備、乾式蝕刻設備等。在一些實施方式中，蝕刻設備108包括填充蝕刻劑的腔室，並且將基板放置在腔室中歷時特定時間長度以移除特定量之基板的一個或多個部分。在一些實施方式中，蝕刻設備108可使用電漿蝕刻（plasma etch）或電漿輔助蝕刻（plasma-assisted etch）來蝕刻基板的一個或多個部分，這可涉及使用離子化（ionized）氣體來等向地或定向（directionally）地蝕刻一個或多個部分。Etch equipment 108 is a semiconductor process equipment capable of etching various types of materials of substrates, wafers, or semiconductor devices. For example, the etching apparatus 108 may include a wet etching apparatus, a dry etching apparatus, and the like. In some embodiments, the etching apparatus 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specified length of time to remove a specified amount of one or more portions of the substrate. In some embodiments, the etching apparatus 108 may use plasma etch or plasma-assisted etch to etch one or more portions of the substrate, which may involve the use of an ionized gas to One or more portions are etched isotropically or directionally.

平坦化設備110為能夠拋光或平坦化晶圓或半導體裝置之各層的半導體製程設備。舉例而言，平坦化設備110可包括化學機械平坦化（chemical mechanical planarization, CMP）設備及/或另一類型的平坦化設備，上述另一類型的平坦化設備將沉積的材料或鍍膜的材料的層或表面拋光或平坦化。平坦化設備110可利用化學力（chemical forces）及機械力（mechanical forces）的組合（例如，化學蝕刻及自由研磨拋光（free abrasive polishing））來拋光或平坦化半導體裝置的表面。平坦化設備110可結合拋光墊（polishing pad）及固定環（retaining ring）（例如，通常具有比半導體裝置更大的直徑）使用研磨性（abrasive）及腐蝕性化學漿料（chemical slurry）。拋光墊及半導體裝置可由動態拋光頭（dynamic polishing head）壓在一起並由固定環固定就位。動態拋光頭可以不同的旋轉軸旋轉，以移除材料甚至移出半導體裝置的任何不規則形貌，使得半導體裝置為平坦或平面的。The planarization equipment 110 is a semiconductor processing equipment capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the planarization apparatus 110 may include a chemical mechanical planarization (CMP) apparatus and/or another type of planarization apparatus that will deposit or coat the material of the film. Layer or surface polishing or planarization. The planarization apparatus 110 may utilize a combination of chemical and mechanical forces (eg, chemical etching and free abrasive polishing) to polish or planarize the surface of the semiconductor device. The planarization apparatus 110 may use abrasive and corrosive chemical slurries in conjunction with polishing pads and retaining rings (eg, typically having a larger diameter than semiconductor devices). The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head can be rotated on different rotational axes to remove material and even out of any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

鍍膜設備112是能夠用一或多個金屬來電鍍基板（例如，晶圓、半導體裝置等）或其一部分的半導體製程設備。舉例而言，鍍膜設備112可包括銅電鍍裝置、鋁電鍍裝置、鎳電鍍裝置、錫電鍍裝置、化合物材料或合金（例如錫-銀、錫-鉛等）電鍍裝置、及/或用於導電材料、金屬及/或類似類型材料的一種或多種其他類型的電鍍裝置。Coating equipment 112 is semiconductor processing equipment capable of electroplating a substrate (eg, wafer, semiconductor device, etc.) or a portion thereof with one or more metals. For example, the coating apparatus 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (eg, tin-silver, tin-lead, etc.) electroplating device, and/or for conductive materials , metal and/or one or more other types of electroplating devices of similar types of materials.

預處理設備114是能夠使用各種類型的濕化學品（wet chemicals）及/或氣體來處理（treat）裝置的一或多層的表面，以為一個或多個後續半導體處理操作做準備。舉例而言，預處理設備114可包括可放置裝置的腔室。腔室可填充濕化學品及/或氣體，用於修飾（modify）裝置的一或多層的物理及/或化學特性。Pretreatment equipment 114 is capable of treating the surface of one or more layers of the device with various types of wet chemicals and/or gases in preparation for one or more subsequent semiconductor processing operations. For example, the pretreatment apparatus 114 may include a chamber in which the device may be placed. The chamber may be filled with wet chemicals and/or gases for modifying the physical and/or chemical properties of one or more layers of the device.

電漿設備116是夠使用電漿處理裝置的一或多層的表面的半導體製程設備，例如去耦合電漿源（decoupled plasma source, DPS）設備、感應耦合電漿（inductively coupled plasma, ICP）設備、變壓耦合電漿（transformer coupled plasma, TCP）設備、或另一種類型的電漿基（plasma-based）半導體製程設備。舉例而言，電漿設備116可使用電漿離子從裝置層的表面濺擊蝕刻（sputter etch）或以其他方式移除材料。Plasma equipment 116 is semiconductor processing equipment capable of processing the surface of one or more layers of a device using plasma, such as decoupled plasma source (DPS) equipment, inductively coupled plasma (ICP) equipment, Transformer coupled plasma (TCP) equipment, or another type of plasma-based semiconductor process equipment. For example, the plasma apparatus 116 may use plasma ions to sputter etch or otherwise remove material from the surface of the device layers.

晶圓/晶粒運輸設備118包括移動式機器人（mobile robot）、機械手臂（robot arm）、有軌電車（tram car）或軌道車（rail car）、及/或另一種類型的裝置，用於在半導體處理裝置102-116及/或其他位置之間往返運輸晶圓及/或晶粒，上述其他位置例如晶圓架（wafer rack）、儲藏室（storage room）、及/或類似位置。在一些實施方式中，晶圓/晶粒運輸設備118可為以特定路徑行進及/或可半自主或自主地操作的編程裝置。Wafer/die transport equipment 118 includes a mobile robot, robot arm, tram or rail car, and/or another type of device for Wafers and/or dies are transported to and from semiconductor processing apparatuses 102-116 and/or other locations, such as wafer racks, storage rooms, and/or the like. In some embodiments, wafer/die transport apparatus 118 may be a programmed device that travels in a specific path and/or may operate semi-autonomously or autonomously.

提供第1圖中所示的裝置的數量及設置作為一或多個示例。實作上，相較於第1圖所示的裝置，可能存在額外裝置、更少的裝置、不同的裝置、或設置不同的裝置。再者，可在單個裝置內實施第1圖所示的兩個或多個裝置，或可將第1圖所示的單個裝置實施為複數個分佈式裝置（distributed devices）。額外地或可替代地，環境100的一組裝置（例如，一或多個裝置）可進行由環境100的另一組裝置進行之所述的一或多個功能。The number and arrangement of devices shown in Figure 1 are provided as one or more examples. In practice, compared to the device shown in FIG. 1, there may be additional devices, fewer devices, different devices, or different devices. Furthermore, two or more of the devices shown in FIG. 1 may be implemented within a single device, or the single device shown in FIG. 1 may be implemented as a plurality of distributed devices. Additionally or alternatively, one set of devices (eg, one or more devices) of environment 100 may perform one or more functions described by another set of devices of environment 100 .

第2圖係本文所述的例示性裝置200的一部分的圖。裝置200可包括例如處理器、記憶體裝置、或另一種類型的電子裝置。如第2圖所示，裝置200可包括各種裝置區，例如基板210、FEOL區220、生產線中端（middle-end-of-line,  MEOL）區230及BEOL區240。基板210可包括裝置200的區域，在其中及/或上可形成裝置200的半導體裝置。基板210可包括半導體晶粒基板、半導體晶圓、或可在其中及/或在其上形成半導體裝置的另一種類型的基板。在一些實施方式中，基板210是由矽（silicon, Si）、包括矽的材料、III-V族化合物半導體材料、絕緣體上覆矽（silicon-on-insulator, SOI）基板、或另一類型的半導體材料所形成，上述III-V族化合物半導體材料例如砷化鎵（gallium arsenide, GaAs）。Figure 2 is a diagram of a portion of an exemplary device 200 described herein. Device 200 may include, for example, a processor, a memory device, or another type of electronic device. As shown in FIG. 2 , the device 200 may include various device areas, such as a substrate 210 , a FEOL area 220 , a middle-end-of-line (MEOL) area 230 and a BEOL area 240 . Substrate 210 may include regions of device 200 in and/or on which semiconductor devices of device 200 may be formed. Substrate 210 may include a semiconductor die substrate, a semiconductor wafer, or another type of substrate in which and/or on which semiconductor devices may be formed. In some embodiments, the substrate 210 is made of silicon (Si), a material including silicon, a III-V compound semiconductor material, a silicon-on-insulator (SOI) substrate, or another type of The semiconductor material is formed of the above-mentioned III-V compound semiconductor material such as gallium arsenide (gallium arsenide, GaAs).

FEOL區220可形成在基板210中及/或上。FEOL區220可包括由例如下列低介電常數（low dielectric constant, low-k）材料所形成的介電層222：氧化矽（silicon oxide, SiO x）（例如，二氧化矽（silicon dioxide, SiO 2））、氮化矽 （silicon nitride, SiN x）、碳化矽（silicon carbide, SiC x）、氮化鈦（titanium nitride, TiN x）、氮化鉭 （tantalum nitride, TaN x）、氧化鉿（hafnium oxide, HfO x）、氧化鉭（tantalum oxide, TaO x）、或氧化鋁（aluminum oxide, AlO x）。FEOL區220可更包括裝置200的半導體裝置。半導體裝置可形成在介電層222中，並且可包括電晶體、電容器、電阻器、雷射（lasers）、發光二極體（light emitting diodes, LEDs）、及/或其他類型的半導體基（semiconductor-based）電子裝置。包括於FEOL區220中的電晶體可包括例如平面電晶體、鰭式場效應電晶體（fin field-effect transistors, FinFETs）、及/或其他類型的電晶體。FinFETs可包括傳統的FinFETs、奈米片（nano-sheet）FinFETs、奈米線（nano-wire）FinFETs、及/或其他類型的FinFETs。電晶體可包括形成在基板210中及/或上的一個或多個源極或汲極區224及高k金屬閘極（high-k metal gate, HKMG）226。 The FEOL region 220 may be formed in and/or on the substrate 210 . The FEOL region 220 may include a dielectric layer 222 formed of, eg, a low dielectric constant (low-k) material: silicon oxide (SiO x ) (eg, silicon dioxide (SiO x ) 2 )), silicon nitride (SiN x ), silicon carbide (SiC x ), titanium nitride (TiN x ), tantalum nitride (TaN x ), hafnium oxide ( hafnium oxide, HfO x ), tantalum oxide (TaO x ), or aluminum oxide (aluminum oxide, AlO x ). The FEOL region 220 may further include the semiconductor devices of the device 200 . Semiconductor devices may be formed in the dielectric layer 222 and may include transistors, capacitors, resistors, lasers, light emitting diodes (LEDs), and/or other types of semiconductor-based (semiconductor) -based) electronic device. The transistors included in the FEOL region 220 may include, for example, planar transistors, fin field-effect transistors (FinFETs), and/or other types of transistors. FinFETs may include conventional FinFETs, nano-sheet FinFETs, nano-wire FinFETs, and/or other types of FinFETs. The transistor may include one or more source or drain regions 224 and a high-k metal gate (HKMG) 226 formed in and/or on the substrate 210 .

MEOL區230可形成在FEOL區220上，並且可將FEOL區220電性連接至BEOL區240。MEOL區230可包括介電層232及形成在介電層232中的接觸插塞（也稱作接觸導孔）234。接觸插塞234可電性連接至FEOL區220的半導體裝置的源極或汲極區224及金屬閘極226。接觸插塞234可包括一種或多種例如下列金屬：鎢（tungsten）、鈷（cobalt）、釕（ruthenium）、或銅（copper）。The MEOL region 230 may be formed on the FEOL region 220 and may electrically connect the FEOL region 220 to the BEOL region 240 . The MEOL region 230 may include a dielectric layer 232 and contact plugs (also referred to as contact vias) 234 formed in the dielectric layer 232 . The contact plug 234 may be electrically connected to the source or drain region 224 and the metal gate 226 of the semiconductor device of the FEOL region 220 . The contact plug 234 may include one or more of the following metals, for example: tungsten, cobalt, ruthenium, or copper.

BEOL區240可形成在MEOL區230上。BEOL區240可將FEOL區220的半導體裝置電性互連（electrically interconnect），並且可將FEOL區220的半導體裝置與裝置200的外部封裝（external packaging）電性連接。BEOL區240可包括一個或多個介電層（例如，介電層242、介電層244、及/或一個或多個其他介電層）。BEOL區240可更包括形成在一個或多個介電層中的金屬化層及導孔。金屬化層可提供導孔之間的電性連接。電路導孔（circuitry via）可提供半導體裝置之間的互連。密封環導孔（seal ring via）可保護及/或隔離裝置200的內部電路免受裂縫（cracks）及濕氣（moisture）的影響，並且可電性連接裝置200的複數個半導體晶粒。The BEOL region 240 may be formed on the MEOL region 230 . The BEOL region 240 can electrically interconnect the semiconductor devices in the FEOL region 220 and can electrically connect the semiconductor devices in the FEOL region 220 with the external packaging of the device 200 . BEOL region 240 may include one or more dielectric layers (eg, dielectric layer 242, dielectric layer 244, and/or one or more other dielectric layers). The BEOL region 240 may further include metallization layers and vias formed in one or more dielectric layers. The metallization layer can provide electrical connection between the vias. Circuitry vias may provide interconnections between semiconductor devices. The seal ring via can protect and/or isolate the internal circuit of the device 200 from cracks and moisture, and can electrically connect a plurality of semiconductor dies of the device 200 .

被包括於一個或多個介電層中的單鑲嵌（single damascene）結構246可用作BEOL區240中的金屬化層之間的導孔。雙鑲嵌結構（dual damascene）248可用作BEOL區240中的金屬化層及導孔。單鑲嵌結構246及雙鑲嵌結構248可包括各種類型的導電材料，例如銅、釕、或鈷。可在 BEOL區240中的介電層之間提供蝕刻停止層（未繪示），以促進在BEOL區240中形成單鑲嵌結構246及雙鑲嵌結構248。A single damascene structure 246 included in one or more dielectric layers may be used as vias between metallization layers in the BEOL region 240 . A dual damascene 248 may be used as a metallization layer and vias in the BEOL region 240 . Single damascene structure 246 and dual damascene structure 248 may include various types of conductive materials, such as copper, ruthenium, or cobalt. An etch stop layer (not shown) may be provided between the dielectric layers in the BEOL region 240 to facilitate the formation of the single damascene structure 246 and the dual damascene structure 248 in the BEOL region 240 .

如前文所述，提供第2圖作為示例。其他示例可能與關於第2圖所述的不同。As previously mentioned, Figure 2 is provided as an example. Other examples may differ from those described with respect to Figure 2.

第3圖係本文所述的例示性內連線300的圖。內連線300可為可被包括於裝置200中的接觸插塞234的示例。內連線300可包括接觸插塞302。接觸插塞302可連接至下金屬化層（lower metallization layer）304，上述下金屬化層30可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層304可包括連接至半導體裝置的金屬源極或汲極區224的金屬閘極（metal gate, MG）226或MEOL內連線，上述半導體裝置的金屬源極或汲極區224被包括於裝置200的FEOL區220中。可在下金屬化層304及位於下金屬化層304上方的介電層308之間提供蝕刻停止層306，以促進內連線300的形成。FIG. 3 is a diagram of an exemplary interconnect 300 described herein. Interconnect 300 may be an example of contact plug 234 that may be included in device 200 . The interconnect 300 may include contact plugs 302 . The contact plugs 302 may be connected to a lower metallization layer 304, which may be formed of copper, cobalt, or other types of metal materials. The lower metallization layer 304 may include a metal gate (MG) 226 or MEOL interconnection connected to the metal source or drain region 224 of the semiconductor device that is connected to the metal source or drain region 224 of the semiconductor device. Included in the FEOL region 220 of the device 200 . An etch stop layer 306 may be provided between the lower metallization layer 304 and the dielectric layer 308 overlying the lower metallization layer 304 to facilitate formation of the interconnect 300 .

可穿過介電層308並穿過蝕刻停止層306形成接觸插塞302。介電層308可包括位於裝置200的MEOL區中230的介電層232。接觸插塞 302 可包括側壁310及底表面312。側壁310可包括介電層308圍繞接觸插塞302的部分。底表面312可包括位於接觸插塞302下方的下金屬化層304的一部分。在一些實施方式中，接觸插塞302的底表面312的寬度在約6奈米（nanometers, nm）至約15nm的範圍。在一些實施方式中，接觸插塞302的底表面312的寬度等於或小於約10nm。Contact plugs 302 may be formed through dielectric layer 308 and through etch stop layer 306 . Dielectric layer 308 may include dielectric layer 232 located in MEOL region 230 of device 200 . The contact plug 302 may include sidewalls 310 and a bottom surface 312. Sidewalls 310 may include portions of dielectric layer 308 surrounding contact plugs 302 . Bottom surface 312 may include a portion of lower metallization layer 304 underlying contact plug 302 . In some embodiments, the width of the bottom surface 312 of the contact plug 302 is in the range of about 6 nanometers (nm) to about 15 nm. In some embodiments, the width of the bottom surface 312 of the contact plug 302 is equal to or less than about 10 nm.

氧化釕 （ruthenium oxide, RuO x） 膜 314 可被包括於接觸插塞 302 的側壁 310 上。氧化釕膜 314 可促進周圍介電層 308 及釕襯層 316 之間的黏著性，上述釕襯層 316被包括於側壁 310上方及氧化釕膜314上。因此，氧化釕膜314減少了及/或防止了在釕襯層316的沉積期間在釕襯層316中不連續性（discontinuities）的形成。側壁310上的氧化釕膜314的厚度可在約3埃（以最小化或防止氧化釕膜314中的不連續性）至約10埃（以實現接觸插塞302的低片電阻並在接觸插塞302中提供大的銅填充寬裕度（filling window））的範圍。 A ruthenium oxide (RuO x ) film 314 may be included on the sidewalls 310 of the contact plug 302 . The ruthenium oxide film 314 promotes adhesion between the surrounding dielectric layer 308 and the ruthenium liner layer 316 , which is included over the sidewalls 310 and on the ruthenium oxide film 314 . Thus, the ruthenium oxide film 314 reduces and/or prevents the formation of discontinuities in the ruthenium liner 316 during the deposition of the ruthenium liner 316 . The thickness of the ruthenium oxide film 314 on the sidewalls 310 may range from about 3 angstroms (to minimize or prevent discontinuities in the ruthenium oxide film 314) to about 10 angstroms (to achieve low sheet resistance of the contact plug 302 and A large copper filling window is provided in plug 302.

釕襯層316可用作銅（copper, Cu）層318的擴散阻障層，上述銅層318填充在釕襯層316上方的接觸插塞302中。因此，釕襯層316減少了或防止了銅離子擴散進入介電層308及介電層308之下的層。再者，釕襯層316可降低接觸插塞302的整體電阻率，因為薄膜釕的片電阻低於其他銅擴散阻障層的片電阻，例如氮化鉭 （tantalum nitride, TaN）。位於側壁310上的釕襯層316的厚度可在約10埃（以提供足夠的銅擴散阻障）至約30埃（以實現接觸插塞302的低片電阻並提供接觸插塞302中大的銅的填充寬裕度）。The ruthenium liner 316 may serve as a diffusion barrier for the copper (Cu) layer 318 that fills the contact plugs 302 above the ruthenium liner 316 . Thus, the ruthenium liner 316 reduces or prevents the diffusion of copper ions into the dielectric layer 308 and the layers below the dielectric layer 308 . Furthermore, the ruthenium liner layer 316 can reduce the overall resistivity of the contact plug 302 because the sheet resistance of thin film ruthenium is lower than that of other copper diffusion barrier layers, such as tantalum nitride (TaN). The thickness of the ruthenium liner 316 on the sidewalls 310 may range from about 10 angstroms (to provide a sufficient copper diffusion barrier) to about 30 angstroms (to achieve low sheet resistance for the contact plugs 302 and to provide large copper fill margin).

氧化釕膜314及釕襯層316的組合可比其他銅擴散阻障層更薄，同時仍然提供足夠的銅擴散阻障功能，這增加了可填充銅的接觸插塞302中的體積（稱作銅填充寬裕度）。由氧化釕膜314及釕襯層316所提供增加的銅填充寬裕度可提高在銅電鍍製程之後在接觸插塞中進行銅回焊（copper reflow）的能力並減少及/或消除接觸插塞 302中的空隙（voids）、銅島狀物（copper islands）、及其他不連續性。The combination of ruthenium oxide film 314 and ruthenium liner 316 can be thinner than other copper diffusion barrier layers, while still providing sufficient copper diffusion barrier function, which increases the volume in the copper-fillable contact plug 302 (referred to as copper). padding allowance). The increased copper fill margin provided by the ruthenium oxide film 314 and the ruthenium liner 316 may improve copper reflow in the contact plugs after the copper electroplating process and reduce and/or eliminate the contact plugs 302 voids, copper islands, and other discontinuities in

釕襯層 316 可進一步被包括在底表面 312 上方，以減少、最小化、及/或防止銅層 318穿過底表面312至下部FEOL區220的銅擴散。在一些實施方式中，如第3圖中的示例所示，接觸插塞302的底表面312省略了氧化釕膜314。在這些情況下，釕襯層316被包括直接在底表面312上，並且銅層318被包括在底表面312上的釕襯層 316 上方。在一些實施方式中，在將氧化釕膜 314 沉積在側壁 310 上的期間，氧化釕膜314的殘留量形成在底表面312上。在這些情況下，位於底表面312上的殘留氧化釕膜314的厚度可大於0埃並且小於約8埃，以實現接觸插塞302的低接觸電阻。在這些實施方式中，在位於接觸插塞302的底表面312上之氧化釕膜314的殘留量上方形成釕襯層316。A ruthenium liner 316 may be further included over bottom surface 312 to reduce, minimize, and/or prevent copper diffusion of copper layer 318 through bottom surface 312 to lower FEOL region 220. In some embodiments, as shown in the example of FIG. 3, the bottom surface 312 of the contact plug 302 omits the ruthenium oxide film 314. In these cases, a ruthenium liner layer 316 is included directly on the bottom surface 312, and a copper layer 318 is included over the ruthenium liner layer 316 on the bottom surface 312. In some embodiments, a residual amount of the ruthenium oxide film 314 is formed on the bottom surface 312 during the deposition of the ruthenium oxide film 314 on the sidewalls 310 . In these cases, the thickness of the residual ruthenium oxide film 314 on the bottom surface 312 may be greater than 0 angstroms and less than about 8 angstroms to achieve low contact resistance of the contact plugs 302 . In these embodiments, a ruthenium liner 316 is formed over the remainder of the ruthenium oxide film 314 on the bottom surface 312 of the contact plug 302 .

如前文所述，提供第3圖作為示例。其他示例可能與關於第3圖所描述的不同。As previously mentioned, Figure 3 is provided as an example. Other examples may differ from those described with respect to Figure 3.

第4A圖至第4N圖係本文所述的例示性實施方式400的圖。例示性實施方式400可為形成第3圖的內連線300的接觸插塞302的示例。在一些實施方式中，半導體製程設備102-116中的一個或多個進行結合第4A圖至第4N圖所述的製程（processes）、及/或操作（operations）。如第4A圖所示，接觸插塞302可形成在位於下金屬化層304之上的介電層308中。蝕刻停止層306可被包括在介電層308及下金屬化層304之間，以促進形成介電層308中的內連線300。4A-4N are diagrams of an exemplary embodiment 400 described herein. The exemplary embodiment 400 may be an example of the contact plug 302 forming the interconnect 300 of FIG. 3 . In some embodiments, one or more of the semiconductor process equipment 102-116 performs the processes, and/or operations, described in connection with Figures 4A-4N. As shown in FIG. 4A , contact plugs 302 may be formed in dielectric layer 308 overlying lower metallization layer 304 . An etch stop layer 306 may be included between the dielectric layer 308 and the lower metallization layer 304 to facilitate formation of the interconnects 300 in the dielectric layer 308 .

如第4B圖所示，可從介電層308的頂表面穿過介電層308形成接觸插塞302。可進一步穿過蝕刻停止層306並且到下金屬化層304形成接觸插塞302。沉積設備102可在介電層308上形成光阻層，曝光設備104可將光阻層暴露於輻射源以圖案化光阻層，顯影設備106可顯影並移除部分光阻層以暴露圖案，並且蝕刻設備108可蝕刻介電層308及蝕刻停止層306，以穿過介電層308及蝕刻停止層306形成接觸插塞302的側壁310。可蝕刻接觸插塞302至下金屬化層304，使得下金屬化層304的頂表面為接觸插塞302的底表面312。在一些實施方式中，光阻移除設備（例如，使用化學剝離劑（chemical stripper）、及/或其他技術）將光阻層的剩餘部分移除。As shown in FIG. 4B , contact plugs 302 may be formed through the dielectric layer 308 from the top surface of the dielectric layer 308 . Contact plugs 302 may be formed further through the etch stop layer 306 and to the lower metallization layer 304 . Deposition apparatus 102 may form a photoresist layer on dielectric layer 308, exposure apparatus 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, developing apparatus 106 may develop and remove portions of the photoresist layer to expose the pattern, And the etching apparatus 108 can etch the dielectric layer 308 and the etch stop layer 306 to form the sidewalls 310 of the contact plug 302 through the dielectric layer 308 and the etch stop layer 306 . The contact plugs 302 can be etched to the lower metallization layer 304 such that the top surface of the lower metallization layer 304 is the bottom surface 312 of the contact plugs 302 . In some embodiments, photoresist removal equipment (eg, using a chemical stripper, and/or other techniques) removes the remaining portion of the photoresist layer.

如第4C圖所示，可修飾（modified）接觸插塞302的底表面312，以抵抗或防止在底表面312上形成氧化釕膜314。具體而言，預處理設備114可進行預處理操作，使接觸插塞302的底表面312變非金屬性（non-metallic）。預處理操作可包括將接觸插塞302的底表面312浸入（immersing）苯並三唑（benzotriazole, BTA）中約1分鐘至約10分鐘的持續時間，以使非金屬鈍化層（passive layer）402形成在底表面312上。可將底表面312浸入（soaked in）BTA中，這導致下金屬化層304的金屬材料（例如，銅或鈷）與BTA之間的錯合物（complex）形成鈍化層402。鈍化層402中的銅-BTA錯合物防止了或阻止了釕前驅物被吸收到接觸插塞302的底表面312（其為下金屬化層304的頂表面）中，以選擇性地沉積釕及氧化釕。As shown in FIG. 4C , the bottom surface 312 of the contact plug 302 may be modified to resist or prevent the formation of the ruthenium oxide film 314 on the bottom surface 312 . Specifically, the preconditioning apparatus 114 may perform a preconditioning operation to render the bottom surface 312 of the contact plug 302 non-metallic. The pretreatment operation may include immersing the bottom surface 312 of the contact plug 302 in benzotriazole (BTA) for a duration of about 1 minute to about 10 minutes to cause the non-metallic passive layer 402 formed on the bottom surface 312 . Bottom surface 312 may be soaked in BTA, which results in a complex between the metallic material (eg, copper or cobalt) of lower metallization layer 304 and the BTA to form passivation layer 402 . The copper-BTA complex in passivation layer 402 prevents or prevents ruthenium precursor from being absorbed into bottom surface 312 of contact plug 302 (which is the top surface of lower metallization layer 304 ) to selectively deposit ruthenium and ruthenium oxide.

如第4D圖所示，氧化釕膜314可形成在接觸插塞302的側壁310上。沉積設備102可藉由進行ALD操作或CVD 操作將氧化釕膜314直接沉積到側壁310上。沉積設備102可在接觸插塞302的側壁310上形成氧化釕膜314約3埃至約10埃的範圍的厚度。可在側壁310上沉積氧化釕膜314，以對氧化釕膜314的形成具有精確的控制並且最小化氧化釕膜314的厚度變化（例如，與自生長（self-growing）氧化釕膜314相反）。As shown in FIG. 4D , a ruthenium oxide film 314 may be formed on the sidewalls 310 of the contact plugs 302 . The deposition apparatus 102 may directly deposit the ruthenium oxide film 314 on the sidewalls 310 by performing an ALD operation or a CVD operation. The deposition apparatus 102 may form the ruthenium oxide film 314 on the sidewalls 310 of the contact plug 302 to a thickness in the range of about 3 angstroms to about 10 angstroms. Ruthenium oxide film 314 may be deposited on sidewall 310 to have precise control over the formation of ruthenium oxide film 314 and to minimize thickness variation of ruthenium oxide film 314 (eg, as opposed to self-growing ruthenium oxide film 314 ) .

如前文所述，非金屬鈍化層402阻擋了或防止了釕前驅物被吸收至下金屬化層304中。因此，非金屬鈍化層402可阻擋或防止氧化釕膜314 中的釕前驅物被吸收到接觸插塞302的底表面312中。在一些實施方式中，在接觸插塞302的底表面312上方形成氧化釕膜 314的殘留量（例如，小於約 8 埃）。As previously described, the non-metallic passivation layer 402 blocks or prevents the ruthenium precursor from being absorbed into the lower metallization layer 304 . Therefore, the non-metal passivation layer 402 can block or prevent the ruthenium precursor in the ruthenium oxide film 314 from being absorbed into the bottom surface 312 of the contact plug 302 . In some embodiments, a residual amount of ruthenium oxide film 314 is formed over bottom surface 312 of contact plug 302 (eg, less than about 8 Angstroms).

如第4E圖所示，在形成氧化釕膜314之後，可從接觸插塞302的底表面312移除鈍化層402。電漿設備116可使用氨基（ammonia-based）電漿、氧基（oxygen-based）電漿、或包括另一類型離子的電漿進行電漿處理操作，以從底表面312移除鈍化層402。舉例而言，電漿設備116可用氨離子、氧離子、或其他類型的離子轟擊（bombard）鈍化層402，以從底表面312濺擊蝕刻鈍化層402，這導致底表面312再次變為金屬性（metallic）。可進行退火（anneal）以蒸發鈍化層 402 的移除材料，並且可從電漿設備 116 的處理腔室將蒸發材料抽真空。將接觸插塞302的底表面312返回金屬性特性促進了底表面312的銅或鈷與將在底表面312上形成的釕襯層316中的釕（過渡金屬）之間的金屬對金屬（metal-to-metal）黏著性，這最小化或防止了釕襯層 316中空隙及其他缺陷的形成。As shown in FIG. 4E , after the ruthenium oxide film 314 is formed, the passivation layer 402 may be removed from the bottom surface 312 of the contact plug 302 . Plasma device 116 may perform plasma processing operations using ammonia-based plasma, oxygen-based plasma, or plasma including another type of ion to remove passivation layer 402 from bottom surface 312 . For example, the plasma device 116 may bombard the passivation layer 402 with ammonia ions, oxygen ions, or other types of ions to sputter etch the passivation layer 402 from the bottom surface 312, which causes the bottom surface 312 to become metallic again (metallic). An anneal may be performed to evaporate the removed material of the passivation layer 402, and the evaporated material may be evacuated from the processing chamber of the plasma apparatus 116. Returning the bottom surface 312 of the contact plug 302 to metallic properties promotes metal-to-metal between the copper or cobalt of the bottom surface 312 and the ruthenium (transition metal) in the ruthenium liner 316 to be formed on the bottom surface 312. -to-metal) adhesion, which minimizes or prevents the formation of voids and other defects in the ruthenium liner 316.

如第4F圖所示，可在底表面312的電漿處理操作之後形成釕襯層316。可在位於接觸插塞302的側壁310上方的氧化釕膜314上形成釕襯層316。釕襯層316也可直接形成在接觸插塞302的底表面312上（或者在可保留在底表面312上的任何氧化釕膜314的殘留量上方）。沉積設備102可藉由進行ALD操作或CVD操作來沉積釕襯層316。沉積設備102可在位於接觸插塞302的側壁310及底表面312上方的氧化釕膜314上形成釕襯層316至約10埃至約30埃的範圍的厚度。As shown in Figure 4F, a ruthenium liner 316 may be formed after the plasma treatment operation of the bottom surface 312. A ruthenium liner 316 may be formed on the ruthenium oxide film 314 over the sidewalls 310 of the contact plug 302 . Ruthenium liner 316 may also be formed directly on bottom surface 312 of contact plug 302 (or over any residue of ruthenium oxide film 314 that may remain on bottom surface 312). The deposition apparatus 102 may deposit the ruthenium liner 316 by performing an ALD operation or a CVD operation. Deposition apparatus 102 may form ruthenium liner 316 to a thickness in the range of about 10 angstroms to about 30 angstroms on ruthenium oxide film 314 over sidewalls 310 and bottom surface 312 of contact plug 302 .

如第4G圖所示，銅層318可形成在釕襯層316上方的接觸插塞302的剩餘體積中，使得接觸插塞302填充有銅。鍍膜設備112可進行鍍膜操作（例如，電鍍（electroplating）操作或無電鍍（electroless plating）操作），以使銅離子在位於接觸插塞302中的釕襯層316上方生長銅層318。在一些實施方式中，銅層318的形成可包括PVD操作，以在接觸插塞302中的釕襯層316上沉積銅晶種層，然後可在鍍膜操作中將剩餘的銅沉積到銅晶種層上。在一些實施方式中，在鍍膜操作之後進行回焊操作。回焊操作可包括加熱銅層318（例如，到400

Figure 02_image001
或更高）以允許銅層318流動。這允許銅層318填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在鍍膜操作之後及回焊操作之後，平坦化設備110可進行CMP操作以將銅層318平坦化。 As shown in Figure 4G, a copper layer 318 may be formed in the remaining volume of the contact plug 302 over the ruthenium liner layer 316 such that the contact plug 302 is filled with copper. The coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to grow copper ions over the ruthenium liner 316 in the contact plug 302 to grow the copper layer 318 . In some embodiments, the formation of the copper layer 318 may include a PVD operation to deposit a copper seed layer on the ruthenium liner 316 in the contact plug 302, and then the remaining copper may be deposited to the copper seed in a plating operation layer. In some embodiments, the reflow operation is performed after the coating operation. The reflow operation may include heating the copper layer 318 (eg, to 400
Figure 02_image001
or higher) to allow the copper layer 318 to flow. This allows the copper layer 318 to fill any voids or eliminate any islands of material that may have formed during the coating operation. After the plating operation and after the reflow operation, the planarization apparatus 110 may perform a CMP operation to planarize the copper layer 318 .

第4H圖至第4N圖繪示在接觸插塞302上方形成溝槽（例如，第零階金屬化（metallization zero）（M0）層溝槽）的示例。溝槽可形成在裝置200的BEOL區240中。如第4H圖所示，溝槽可形成在蝕刻停止層404及介電層406（例如，BEOL區240的介電層242）中。FIGS. 4H-4N illustrate an example of forming a trench (eg, a metallization zero (M0) layer trench) over the contact plug 302 . The trenches may be formed in the BEOL region 240 of the device 200 . As shown in FIG. 4H, trenches may be formed in etch stop layer 404 and dielectric layer 406 (eg, dielectric layer 242 of BEOL region 240).

如第4I圖所示，溝槽可包括單鑲嵌結構408。單鑲嵌結構408可穿過介電層406。具體而言，可形成單鑲嵌結構408從介電層的頂表面穿過介電層406並到達介電層406的底表面。單鑲嵌結構408可進一步形成穿過蝕刻停止層404並到達接觸插塞302的銅層318。沉積設備102可在介電層406上形成光阻層，曝光設備104可將光阻層暴露於輻射源以圖案化光阻層，顯影設備106可顯影及移除光阻層的部分以暴露圖案，並且蝕刻設備108可蝕刻介電層406及蝕刻停止層404，以穿過介電層406及蝕刻停止層404形成單鑲嵌結構408的側壁410。單鑲嵌結構408可蝕刻到接觸插塞302的銅層318，使得銅層318的頂表面為單鑲嵌結構408的底表面412。在一些實施方式中，光阻移除設備（例如，使用化學剝離劑及/或其他技術）將光阻層的剩餘部分移除。As shown in FIG. 4I , the trenches may include a single damascene structure 408 . The single damascene structure 408 may pass through the dielectric layer 406 . Specifically, a single damascene structure 408 may be formed from the top surface of the dielectric layer through the dielectric layer 406 and to the bottom surface of the dielectric layer 406 . The single damascene structure 408 may further form the copper layer 318 through the etch stop layer 404 and to the contact plug 302 . Deposition apparatus 102 may form a photoresist layer on dielectric layer 406, exposure apparatus 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, and developing apparatus 106 may develop and remove portions of the photoresist layer to expose the pattern , and the etching apparatus 108 may etch the dielectric layer 406 and the etch stop layer 404 to form the sidewalls 410 of the single damascene structure 408 through the dielectric layer 406 and the etch stop layer 404 . The single damascene structure 408 may be etched into the copper layer 318 of the contact plug 302 such that the top surface of the copper layer 318 is the bottom surface 412 of the single damascene structure 408 . In some embodiments, photoresist removal equipment (eg, using chemical strippers and/or other techniques) removes the remaining portion of the photoresist layer.

如第4J圖所示，可修飾（modified）單鑲嵌結構408的底表面412，以阻止或防止在底表面412上形成氮化鉭膜。具體地，預處理設備114可進行預處理操作，使單鑲嵌結構408的底表面412變為非金屬性（non-metallic）。預處理操作可包括將單鑲嵌結構408的底表面412浸入苯並三唑（benzotriazole, BTA）一段時間，以在底表面412上形成非金屬鈍化層414。可將底表面412浸泡在BTA中，這導致銅層318的銅及BTA之間的錯合物形成鈍化層414。鈍化層414中的銅-BTA錯合物防止了或阻止了氮化鉭前驅物被吸收至單鑲嵌結構408的底表面412（其為銅層318的頂表面）中。As shown in FIG. 4J , the bottom surface 412 of the single damascene structure 408 may be modified to prevent or prevent the formation of a tantalum nitride film on the bottom surface 412 . Specifically, the preprocessing apparatus 114 may perform a preprocessing operation to make the bottom surface 412 of the single damascene structure 408 non-metallic. The pretreatment operation may include dipping the bottom surface 412 of the single damascene structure 408 in benzotriazole (BTA) for a period of time to form a non-metallic passivation layer 414 on the bottom surface 412 . Bottom surface 412 may be soaked in BTA, which results in complexes between copper and BTA of copper layer 318 forming passivation layer 414 . The copper-BTA complex in the passivation layer 414 prevents or prevents the tantalum nitride precursor from being absorbed into the bottom surface 412 of the single damascene structure 408 , which is the top surface of the copper layer 318 .

如第4K圖所示，可在單鑲嵌結構408的側壁410上形成氮化鉭膜416。沉積設備102可藉由進行ALD操作或 CVD 操作將氮化鉭膜416直接沉積到側壁410上。沉積設備102可在側壁410上形成氮化鉭膜416至約3埃（以最小化或防止氮化鉭膜416中的不連續性）至約8埃（以實現側壁410的低片電阻及底表面412的低接觸電阻）的範圍的厚度。As shown in FIG. 4K, a tantalum nitride film 416 may be formed on the sidewalls 410 of the single damascene structure 408. The deposition apparatus 102 may deposit the tantalum nitride film 416 directly onto the sidewalls 410 by performing an ALD operation or a CVD operation. Deposition apparatus 102 may form tantalum nitride film 416 on sidewalls 410 to about 3 Angstroms (to minimize or prevent discontinuities in tantalum nitride film 416 ) to about 8 Angstroms (to achieve low sheet resistance and bottom of sidewalls 410 ) low contact resistance of surface 412).

如前文所述，非金屬鈍化層414阻擋了或防止了氮化鉭前驅物被吸收至銅層318中。因此，非金屬鈍化層414可阻擋或防止氮化鉭膜416中的氮化鉭前驅物被吸收至單鑲嵌結構408的底表面412中。在一些實施方式中，在單鑲嵌結構408的底表面412上方形成氮化鉭膜416的殘留量（例如，大於0埃且小於約5埃，以將氮化鉭膜416對於單鑲嵌結構408的接觸電阻的影響最小化）。As previously discussed, the non-metallic passivation layer 414 blocks or prevents the tantalum nitride precursor from being absorbed into the copper layer 318 . Accordingly, the non-metallic passivation layer 414 may block or prevent the tantalum nitride precursor in the tantalum nitride film 416 from being absorbed into the bottom surface 412 of the single damascene structure 408 . In some implementations, a residual amount of tantalum nitride film 416 (eg, greater than 0 angstroms and less than about 5 angstroms) is formed over the bottom surface 412 of the single damascene structure 408 , so that the the effect of contact resistance is minimized).

如第4L圖所示，在形成氮化鉭膜416之後，可從單鑲嵌結構408的底表面412移除鈍化層414。電漿設備116可使用氨基電漿、氧基電漿、氫基電漿、或包括另一類型離子的電漿進行電漿處理操作，以從底表面412移除鈍化層414。舉例而言，電漿設備116可用氨離子、氧離子、或其他類型的離子轟擊鈍化層414，以從底表面412濺擊蝕刻鈍化層414，這導致底表面412再次變為金屬性。可進行退火以蒸發鈍化層414的移除材料，並且可從電漿設備116的處理腔室將蒸發的材料抽真空。將單鑲嵌結構408的底表面412返回金屬性特性促進了金屬底表面412的銅與將要形成在底表面412上的釕襯層中的釕之間的金屬對金屬（metal-to-metal）黏著性，這最小化或防止了在釕襯層中形成空隙及其他缺陷。As shown in FIG. 4L, after the formation of the tantalum nitride film 416, the passivation layer 414 may be removed from the bottom surface 412 of the single damascene structure 408. Plasma device 116 may perform a plasma processing operation to remove passivation layer 414 from bottom surface 412 using amino plasma, oxygen-based plasma, hydrogen-based plasma, or plasma including another type of ion. For example, plasma device 116 may bombard passivation layer 414 with ammonia ions, oxygen ions, or other types of ions to sputter etch passivation layer 414 from bottom surface 412, which causes bottom surface 412 to become metallic again. An anneal may be performed to evaporate the removed material of passivation layer 414 , and the evaporated material may be evacuated from the processing chamber of plasma apparatus 116 . Returning the bottom surface 412 of the single damascene structure 408 to metallic properties promotes metal-to-metal adhesion between the copper of the metal bottom surface 412 and the ruthenium in the ruthenium liner to be formed on the bottom surface 412 , which minimizes or prevents the formation of voids and other defects in the ruthenium liner.

如第4M圖所示，在底表面412的電漿處理操作之後可形成釕襯層418。可在位於單鑲嵌結構408的側壁410上方的氮化鉭膜416上形成釕襯層418。釕襯層418也可直接形成在單鑲嵌結構408的底表面412上（或者在可保留在底表面412上的任何氮化鉭膜416的殘留量上方）。沉積設備102可藉由進行ALD操作或CVD操作來沉積釕襯層418。As shown in FIG. 4M, a ruthenium liner 418 may be formed after the plasma treatment operation of the bottom surface 412. A ruthenium liner 418 may be formed on the tantalum nitride film 416 over the sidewalls 410 of the single damascene structure 408 . Ruthenium liner 418 may also be formed directly on bottom surface 412 of single damascene structure 408 (or over any residual amount of tantalum nitride film 416 that may remain on bottom surface 412). The deposition apparatus 102 may deposit the ruthenium liner 418 by performing an ALD operation or a CVD operation.

氮化鉭膜416可改善側壁410上的釕襯層418與周圍介電層406之間的連續性及黏著性。釕襯層418可為單鑲嵌結構408提供銅擴散阻障，並且允許薄化（thinning）氮化鉭膜416（例如，允許減小氮化鉭膜416的厚度）。氮化鉭膜416的縮減厚度降低了單鑲嵌結構408的片電阻，並且薄氮化鉭膜416及釕襯層418的組合為單鑲嵌結構408提供了足夠的銅擴散阻障功能。The tantalum nitride film 416 can improve the continuity and adhesion between the ruthenium liner 418 on the sidewalls 410 and the surrounding dielectric layer 406 . The ruthenium liner 418 may provide a copper diffusion barrier for the single damascene structure 408 and allow thinning of the tantalum nitride film 416 (eg, allowing the thickness of the tantalum nitride film 416 to be reduced). The reduced thickness of the tantalum nitride film 416 reduces the sheet resistance of the single damascene structure 408 , and the combination of the thin tantalum nitride film 416 and the ruthenium liner 418 provides sufficient copper diffusion barrier function for the single damascene structure 408 .

沉積設備102可在位於側壁410上方的氮化鉭膜416上將釕襯層418形成為約10埃（以最小化及/或防止銅從單鑲嵌結構408擴散至接觸插塞302及/或位於單鑲嵌結構408下方的層的其他區域中）至約35埃（以實現單鑲嵌結構408的低片電阻）的範圍的厚度。沉積設備102也可在單鑲嵌結構408的底表面412上形成釕襯層418至約8埃至約25埃的範圍的厚度，以實現單鑲嵌結構408的低接觸電阻並且最小化及/或防止銅從單鑲嵌結構408擴散至接觸插塞302及/或位於單鑲嵌結構408下方的層的其他區域中。Deposition apparatus 102 may form ruthenium liner 418 to about 10 Angstroms on tantalum nitride film 416 over sidewall 410 (to minimize and/or prevent copper diffusion from single damascene structure 408 to contact plug 302 and/or to thicknesses in the range of about 35 angstroms (to achieve low sheet resistance for the single damascene structure 408) in other regions of the layer below the single damascene structure 408. The deposition apparatus 102 may also form a ruthenium liner 418 on the bottom surface 412 of the single damascene structure 408 to a thickness ranging from about 8 angstroms to about 25 angstroms to achieve low contact resistance for the single damascene structure 408 and to minimize and/or prevent Copper diffuses from the single damascene structure 408 into the contact plugs 302 and/or other regions of the layer below the single damascene structure 408 .

如第4N圖所示，可在位於釕襯層418上方的單鑲嵌結構408的剩餘體積中形成銅層420，使得單鑲嵌結構408填充有銅。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以使銅離子在單鑲嵌結構408中的釕襯層418上方生長銅層420。在一些實施方式中，形成銅層420可包括PVD操作，以在雙鑲嵌結構408中的釕襯層418上沉積銅晶種層，然後可在鍍膜操作中將剩餘的銅沉積到銅晶種層上。在一些實施方式中，在鍍膜操作之後進行回焊操作。回焊操作可包括加熱銅層420以允許銅層420流動。這允許銅層420填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在鍍膜操作之後及回焊操作之後，平坦化設備110可進行CMP操作，以將銅層420平坦化。As shown in Figure 4N, a copper layer 420 may be formed in the remaining volume of the single damascene structure 408 over the ruthenium liner 418, such that the single damascene structure 408 is filled with copper. Coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause copper ions to grow copper layer 420 over ruthenium liner 418 in single damascene structure 408 . In some embodiments, forming the copper layer 420 may include a PVD operation to deposit a copper seed layer on the ruthenium liner layer 418 in the dual damascene structure 408, and then the remaining copper may be deposited to the copper seed layer in a plating operation superior. In some embodiments, the reflow operation is performed after the coating operation. The reflow operation may include heating the copper layer 420 to allow the copper layer 420 to flow. This allows the copper layer 420 to fill any voids or eliminate any islands of material that may have formed during the coating operation. After the coating operation and after the reflow operation, the planarization apparatus 110 may perform a CMP operation to planarize the copper layer 420 .

如前文所述，提供第4A圖至第4N圖作為示例。其他示例可能與關於第4A圖至第4N圖所描述的不同。舉例而言，雖然第4H圖至第4N圖繪示出單鑲嵌結構408電性連接至包括氧化釕膜、釕襯層、及銅層的接觸插塞的示例，單鑲嵌結構408可電性連接至其他類型的接觸插塞。作為示例，單鑲嵌結構408可電性連接至僅含釕的接觸插塞（具有包括超過95原子%釕的一個材料的插塞）、包括釕襯層及鈷層的接觸插塞、或另一種類型的接觸插塞。As previously mentioned, Figures 4A to 4N are provided as examples. Other examples may differ from those described with respect to Figures 4A-4N. For example, although FIGS. 4H to 4N illustrate an example in which the single damascene structure 408 is electrically connected to a contact plug including a ruthenium oxide film, a ruthenium liner, and a copper layer, the single damascene structure 408 may be electrically connected to other types of contact plugs. As an example, the single damascene structure 408 may be electrically connected to a ruthenium-only contact plug (plug having a material that includes more than 95 atomic % ruthenium), a contact plug that includes a ruthenium liner and a cobalt layer, or another type of contact plug.

第5圖係本文所述的例示性內連線500的圖。內連線500可為可被包括在裝置200中的接觸插塞234的示例。內連線500可包括接觸插塞502。接觸插塞502可連接至下金屬化層504，上述下金屬化層504可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層504可包括連接至半導體裝置之金屬源極或汲極區224的金屬閘極226或MEOL內連線，上述半導體裝置被包括在裝置200的FEOL區220中。可在下金屬化層504及位於下金屬化層504上方的介電層508之間提供蝕刻停止層506，以促進內連線500的形成。FIG. 5 is a diagram of an exemplary interconnect 500 described herein. Interconnect 500 may be an example of contact plug 234 that may be included in device 200 . The interconnect 500 may include contact plugs 502 . Contact plugs 502 may be connected to lower metallization layers 504, which may be formed of copper, cobalt, or other types of metal materials. Lower metallization layer 504 may include metal gate 226 or MEOL interconnects connected to metal source or drain regions 224 of the semiconductor device included in FEOL region 220 of device 200 . An etch stop layer 506 may be provided between the lower metallization layer 504 and the dielectric layer 508 overlying the lower metallization layer 504 to facilitate formation of the interconnect 500 .

接觸插塞502可形成在介電層 508 中並穿過蝕刻停止層506。介電層508可包括位於裝置200的MEOL區230中的介電層 232。接觸插塞502可包括側壁510及底表面512。側壁510可包括介電層508圍繞接觸插塞502的部分。底表面512可包括位於接觸插塞502之下的下金屬化層504的一部分。Contact plugs 502 may be formed in dielectric layer 508 and through etch stop layer 506. Dielectric layer 508 may include dielectric layer 232 in MEOL region 230 of device 200. Contact plug 502 may include sidewalls 510 and a bottom surface 512 . Sidewall 510 may include portions of dielectric layer 508 surrounding contact plug 502 . Bottom surface 512 may include a portion of lower metallization layer 504 underlying contact plug 502 .

釕襯層514可被包括直接位於側壁510上並且直接位於接觸插塞502的底表面512上。釕襯層514可用作銅 （copper, Cu） 層516的擴散阻障層，上述銅層516填充在位於釕襯層514上方的接觸插塞502中。因此，釕襯層514減少了或防止了銅離子擴散至介電層508及介電層508下方的層中。接觸插塞502可省略氧化釕膜，這進一步增加了接觸插塞502的銅填充寬裕度，代價是由於釕襯層514及介電層508之間的黏著性挑戰而在釕襯層514中增加形成不連續性的風險。Ruthenium liner 514 may be included directly on sidewall 510 and directly on bottom surface 512 of contact plug 502 . The ruthenium liner 514 may serve as a diffusion barrier for the copper (Cu) layer 516 that fills the contact plugs 502 over the ruthenium liner 514 . Thus, the ruthenium liner 514 reduces or prevents the diffusion of copper ions into the dielectric layer 508 and the layers below the dielectric layer 508 . The contact plug 502 can omit the ruthenium oxide film, which further increases the copper fill margin for the contact plug 502 at the expense of increased in the ruthenium liner 514 due to adhesion challenges between the ruthenium liner 514 and the dielectric layer 508 Risk of forming discontinuities.

如前文所述，提供第5圖作為示例。其他示例可能與關於第5圖所描述的不同。As previously mentioned, Figure 5 is provided as an example. Other examples may differ from those described with respect to Figure 5.

第6A圖至第6D圖係本文所述的例示性實施方式600的圖。例示性實施方式600可為形成第5圖的內連線500的接觸插塞502的示例。在一些實施方式中，半導體製程設備102-116中的一個或多個進行結合第6A圖至第6D圖所述的製程、及/或操作的一個或多個。如第6A圖所示，接觸插塞502可形成在位於下金屬化層504上方的介電層508中。蝕刻停止層506可被包括在介電層508及下金屬化層504之間，以促進形成介電層508中的接觸插塞502。6A-6D are diagrams of an exemplary embodiment 600 described herein. The exemplary embodiment 600 may be an example of the contact plug 502 forming the interconnect 500 of FIG. 5 . In some embodiments, one or more of the semiconductor process equipment 102-116 performs one or more of the processes, and/or operations described in connection with Figures 6A-6D. As shown in FIG. 6A , contact plugs 502 may be formed in dielectric layer 508 overlying lower metallization layer 504 . An etch stop layer 506 may be included between the dielectric layer 508 and the lower metallization layer 504 to facilitate formation of the contact plugs 502 in the dielectric layer 508 .

如第6B圖所示，可從介電層508的頂表面穿過介電層508形成接觸插塞502。可進一步形成接觸插塞502穿過蝕刻停止層506並且至下金屬化層504。沉積設備102可在介電層508上形成光阻層，曝光設備104可將光阻層暴露於輻射源以圖案化光阻層，顯影設備106可顯影並移除部分光阻層以暴露圖案，且蝕刻設備108可蝕刻介電層508及蝕刻停止層506，以穿過介電層508及蝕刻停止層506形成接觸插塞502的側壁510。可蝕刻接觸插塞502至下金屬化層 504，使得下金屬化層504的頂表面為接觸插塞502的底表面512。在一些實施方式中，光阻移除設備（例如，使用化學剝離劑及/或其他技術）移除光阻層的剩餘部分。As shown in FIG. 6B , contact plugs 502 may be formed through the dielectric layer 508 from the top surface of the dielectric layer 508 . Contact plugs 502 may be further formed through the etch stop layer 506 and to the lower metallization layer 504 . Deposition apparatus 102 may form a photoresist layer on dielectric layer 508, exposure apparatus 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, developing apparatus 106 may develop and remove portions of the photoresist layer to expose the pattern, And the etching apparatus 108 may etch the dielectric layer 508 and the etch stop layer 506 to form sidewalls 510 of the contact plug 502 through the dielectric layer 508 and the etch stop layer 506 . The contact plugs 502 may be etched to the lower metallization layer 504 such that the top surface of the lower metallization layer 504 is the bottom surface 512 of the contact plugs 502. In some embodiments, photoresist removal equipment (eg, using chemical strippers and/or other techniques) removes the remaining portions of the photoresist layer.

如第6C圖所示，釕襯層514可直接形成在側壁510上並且直接形成在接觸插塞502的底表面512上。沉積設備102可藉由進行ALD操作或 CVD 操作來沉積釕襯層514。沉積設備102可將釕襯層514形成為約10埃至約30埃的範圍的厚度。As shown in FIG. 6C , the ruthenium liner 514 may be formed directly on the sidewalls 510 and directly on the bottom surface 512 of the contact plug 502 . The deposition apparatus 102 may deposit the ruthenium liner 514 by performing an ALD operation or a CVD operation. The deposition apparatus 102 may form the ruthenium liner 514 to a thickness in the range of about 10 angstroms to about 30 angstroms.

如第6D圖所示，可在位於釕襯層514上方的接觸插塞502的剩餘體積中形成銅層516，使得接觸插塞502填充有銅。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以使銅離子在接觸插塞502中的釕襯層514上方生長銅層516。在一些實施方式中，銅層516的形成可包括PVD操作，以在釕襯層514上沉積銅晶種層，然後可在鍍膜操作中將剩餘的銅沉積到銅晶種層上。在一些實施方式中，在鍍膜操作之後進行回焊操作。回焊操作可包括加熱銅層516（例如，到400

Figure 02_image001
或更高）以允許銅層516流動。這允許銅層516填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在鍍膜操作之後及回焊操作之後，平坦化設備110可進行CMP操作以將銅層516平坦化。 As shown in Figure 6D, a copper layer 516 may be formed in the remaining volume of the contact plug 502 over the ruthenium liner 514, such that the contact plug 502 is filled with copper. Coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause copper ions to grow copper layer 516 over ruthenium liner 514 in contact plug 502 . In some embodiments, the formation of the copper layer 516 may include a PVD operation to deposit a copper seed layer on the ruthenium liner layer 514, and then the remaining copper may be deposited onto the copper seed layer in a plating operation. In some embodiments, the reflow operation is performed after the coating operation. The reflow operation may include heating the copper layer 516 (eg, to 400
Figure 02_image001
or higher) to allow the copper layer 516 to flow. This allows the copper layer 516 to fill any voids or eliminate any islands of material that may have formed during the plating operation. After the plating operation and after the reflow operation, the planarization apparatus 110 may perform a CMP operation to planarize the copper layer 516 .

如前文所述，提供第6A圖至第6D圖作為示例。其他示例可能與關於第6A圖至第6D圖所描述的不同。As previously mentioned, Figures 6A to 6D are provided as examples. Other examples may differ from those described with respect to Figures 6A-6D.

第7圖係本文所述的例示性雙鑲嵌結構700的圖。雙鑲嵌結構700可為可被包括在裝置200中的雙鑲嵌結構248的示例。雙鑲嵌結構700可包括溝槽702及導孔704。導孔704可連接至下金屬化層706，上述下金屬化層706可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層706可包括裝置200的BEOL區240中的另一雙鑲嵌結構的溝槽、BEOL區240中的單鑲嵌結構的導孔、裝置200的MEOL區230中的接觸插塞、或其他類型的內連線。可在下金屬化層706及位於下金屬化層706上方的介電層710之間提供蝕刻停止層708，以促進雙鑲嵌結構700的形成。FIG. 7 is a diagram of an exemplary dual damascene structure 700 described herein. Dual damascene structure 700 may be an example of dual damascene structure 248 that may be included in device 200 . The dual damascene structure 700 may include trenches 702 and vias 704 . Vias 704 may be connected to lower metallization layer 706, which may be formed of copper, cobalt, or other types of metal materials. The lower metallization layer 706 may include trenches of another dual damascene structure in the BEOL region 240 of the device 200 , vias of a single damascene structure in the BEOL region 240 , contact plugs in the MEOL region 230 of the device 200 , or other type of interconnect. An etch stop layer 708 may be provided between the lower metallization layer 706 and the dielectric layer 710 overlying the lower metallization layer 706 to facilitate formation of the dual damascene structure 700 .

雙鑲嵌結構700可形成在介電層710中並且穿過蝕刻停止層708。溝槽702可包括側壁712及底表面714。導孔704也可包括側壁716及底表面718。側壁712、底表面714、及側壁716可包括介電層710圍繞雙鑲嵌結構700的部分。The dual damascene structure 700 may be formed in the dielectric layer 710 and through the etch stop layer 708 . The trench 702 may include sidewalls 712 and a bottom surface 714 . The via 704 may also include sidewalls 716 and a bottom surface 718 . Sidewall 712 , bottom surface 714 , and sidewall 716 may include portions of dielectric layer 710 surrounding dual damascene structure 700 .

導孔704的底表面718可包括位於導孔704之下的下金屬化層706的一部分。在一些實施方式中，導孔704為電路導孔（circuit via）。在這些實施方式中，導孔704的底表面718的寬度可在約10nm至約22nm的範圍。在一些實施方式中，導孔704為密封環導孔。在這些實施方式中，導孔704的底表面718的寬度可在約100nm至約180nm的範圍。Bottom surface 718 of via 704 may include a portion of lower metallization layer 706 underlying via 704 . In some embodiments, the vias 704 are circuit vias. In these embodiments, the width of the bottom surface 718 of the via 704 may range from about 10 nm to about 22 nm. In some embodiments, the pilot hole 704 is a seal ring pilot hole. In these embodiments, the width of the bottom surface 718 of the via 704 may range from about 100 nm to about 180 nm.

氧化鋅矽（zinc silicon oxide, ZnSiO x）阻障720可被包括在雙鑲嵌結構700的側壁712、底表面714、及側壁716上。氧化鋅矽阻障720可包括薄膜氧化鋅矽層，其用作銅（copper, Cu）層722的擴散阻障，上述銅層722填充在位於氧化鋅矽阻障720上方的雙鑲嵌結構700中（例如，在溝槽702中及導孔704中）。因此，氧化鋅矽阻障720減少了或防止了銅離子擴散到介電層710及位於介電層710下方的層中。 A zinc silicon oxide (ZnSiO x ) barrier 720 may be included on the sidewalls 712 , the bottom surface 714 , and the sidewalls 716 of the dual damascene structure 700 . The zinc oxide silicon barrier 720 may include a thin film zinc oxide silicon layer that acts as a diffusion barrier for a copper (Cu) layer 722 that fills the dual damascene structure 700 over the zinc oxide silicon barrier 720 (eg, in trench 702 and in via 704). Thus, the zinc oxide silicon barrier 720 reduces or prevents the diffusion of copper ions into the dielectric layer 710 and the layers below the dielectric layer 710 .

再者，氧化鋅矽阻障720可形成為相較於其他銅擴散阻障的厚度而言更小的厚度，同時仍然提供足夠的銅擴散功能，這增加了雙鑲嵌結構700的銅填充寬裕度（例如，或在製程節點尺寸縮小到小於 10 nm 時保持銅填充寬裕度），上述其他銅擴散阻障例如氮化鉭及釕。舉例而言，氧化鋅矽阻障720的厚度可在約5埃至約15埃的範圍。Furthermore, the zinc oxide silicon barrier 720 can be formed to a smaller thickness compared to the thickness of other copper diffusion barriers, while still providing sufficient copper diffusion function, which increases the copper fill margin of the dual damascene structure 700 (eg, or to maintain copper fill margins as process node sizes shrink to less than 10 nm), other copper diffusion barriers such as tantalum nitride and ruthenium above. For example, the thickness of the zinc oxide silicon barrier 720 may range from about 5 angstroms to about 15 angstroms.

如第7圖中的示例所示，氧化鋅矽阻障720的形成方式，使得導孔704的底表面718省略氧化鋅矽阻障720。在這些實施方式中，銅層722被包括直接在導孔 704 的底表面718上，這為雙鑲嵌結構700提供了低接觸電阻。在一些實施方式中，蓋層（例如，鈷蓋層或另一金屬蓋層）可被包括在位於溝槽702之頂部的銅層722上。As shown in the example in FIG. 7 , the zinc oxide silicon barrier 720 is formed in such a way that the bottom surface 718 of the via hole 704 omits the zinc oxide silicon barrier 720 . In these embodiments, copper layer 722 is included directly on bottom surface 718 of via 704, which provides low contact resistance for dual damascene structure 700. In some embodiments, a capping layer (eg, a cobalt capping layer or another metal capping layer) may be included on the copper layer 722 on top of the trenches 702 .

如前文所述，提供第7圖作為示例。其他示例可能與關於第7圖所描述的不同。As previously mentioned, Figure 7 is provided as an example. Other examples may differ from those described with respect to Figure 7.

第8A圖至第8E圖係本文所述的例示性實施方式800的圖。例示性實施方式800可為形成第7圖的雙鑲嵌結構700的示例。在一些實施方式中，半導體製程設備102-116中的一個或多個進行結合第8A圖至第8E圖所述的製程、及/或操作中的一個或多個。如第8A圖所示，雙鑲嵌結構700可形成在位於下金屬化層706上方的介電層710中。蝕刻停止層708可被包括在介電層710及下金屬化層706之間，以促進形成位於介電層710中的雙鑲嵌結構700。Figures 8A-8E are diagrams of an exemplary embodiment 800 described herein. The exemplary embodiment 800 may be an example of forming the dual damascene structure 700 of FIG. 7 . In some embodiments, one or more of the semiconductor process equipment 102-116 performs one or more of the processes, and/or operations described in connection with Figures 8A-8E. As shown in FIG. 8A , a dual damascene structure 700 may be formed in a dielectric layer 710 overlying the lower metallization layer 706 . Etch stop layer 708 may be included between dielectric layer 710 and lower metallization layer 706 to facilitate formation of dual damascene structure 700 in dielectric layer 710 .

如第8B圖所示，可將溝槽702形成在介電層710中。具體而言，溝槽702可從介電層710的頂表面形成並進入介電層710的一部分。沉積設備102可在介電層710上形成光阻層，曝光設備104可將光阻層暴露於輻射源以圖案化光阻層，顯影設備106可顯影並移除光阻層的部分以暴露圖案，並且蝕刻設備108可蝕刻介電層710，以在介電層710中形成溝槽702的側壁712及底表面714。在一些實施方式中，光阻移除設備（例如，使用化學剝離劑及/或其他技術）將光阻層的剩餘部分移除。As shown in FIG. 8B , trenches 702 may be formed in dielectric layer 710 . Specifically, trench 702 may be formed from the top surface of dielectric layer 710 and into a portion of dielectric layer 710 . Deposition apparatus 102 may form a photoresist layer on dielectric layer 710, exposure apparatus 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, and developing apparatus 106 may develop and remove portions of the photoresist layer to expose the pattern , and etching apparatus 108 may etch dielectric layer 710 to form sidewalls 712 and bottom surface 714 of trench 702 in dielectric layer 710 . In some embodiments, photoresist removal equipment (eg, using chemical strippers and/or other techniques) removes the remaining portion of the photoresist layer.

如第8C圖所示，可在位於溝槽702之底表面714的一部分中的介電層710中形成導孔704。具體而言，導孔704可從位於介電層710中的溝槽702的底表面714形成，並穿過介電層710。可進一步形成穿過蝕刻停止層708並到達下金屬化層706的導孔704。沉積設備102可在介電層710上形成光阻層，曝光設備104可將光阻層暴露於輻射源以圖案化光阻層，顯影設備106可顯影並移除光阻層的部分以暴露圖案，並且蝕刻設備108可蝕刻介電層710及蝕刻停止層708，以穿過介電層710及蝕刻停止層708形成導孔704的側壁716。可蝕刻導孔704到下金屬化層706，使得下金屬化層706的頂表面為導孔704的底表面718。在一些實施方式中，光阻移除設備（例如，使用化學剝離劑及/或其他技術）移除光阻層的剩餘部分。As shown in FIG. 8C , vias 704 may be formed in dielectric layer 710 in a portion of bottom surface 714 of trench 702 . Specifically, vias 704 may be formed from bottom surfaces 714 of trenches 702 in dielectric layer 710 and through dielectric layer 710 . Vias 704 may be further formed through the etch stop layer 708 and to the lower metallization layer 706 . Deposition apparatus 102 may form a photoresist layer on dielectric layer 710, exposure apparatus 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, and developing apparatus 106 may develop and remove portions of the photoresist layer to expose the pattern , and the etching apparatus 108 may etch the dielectric layer 710 and the etch stop layer 708 to form sidewalls 716 of the via 704 through the dielectric layer 710 and the etch stop layer 708 . Via 704 may be etched into lower metallization layer 706 such that the top surface of lower metallization layer 706 is the bottom surface 718 of via 704 . In some embodiments, photoresist removal equipment (eg, using chemical strippers and/or other techniques) removes the remaining portions of the photoresist layer.

第8B圖及8C繪示出例示性溝槽先製（trench-first）雙鑲嵌製程（procedure），其中藉由在形成導孔704之前形成溝槽702來形成雙鑲嵌結構700。在一些實施方式中，進行溝槽先製雙鑲嵌製程以形成雙鑲嵌結構700，其中藉由在形成溝槽702（或另一種類型的雙鑲嵌製程）之前，在上述溝槽先製雙鑲嵌製程中形成雙鑲嵌結構700。FIGS. 8B and 8C illustrate an exemplary trench-first dual damascene process in which dual damascene structures 700 are formed by forming trenches 702 before vias 704 are formed. In some embodiments, a trench-first dual-damascene process is performed to form the dual-damascene structure 700 by performing a trench-first dual-damascene process before forming the trenches 702 (or another type of dual-damascene process). A dual damascene structure 700 is formed.

如第8D圖所示，銅晶種層802可直接形成在側壁712上及直接形成在溝槽702的底表面714上，並且可直接形成在側壁716上並直接形成在導孔704的底表面上718。銅晶種層802可包括藉由ALD（例如，藉由沉積設備102）沉積的銅，並且可在用於沉積銅層722的電鍍操作期間用作用於銅生長的銅的初始層（initial layer）。沉積設備102可形成銅晶種層802至約5埃至約15埃的範圍的厚度，以提供足夠量的銅，藉由電鍍在其上生長銅層722。As shown in FIG. 8D , copper seed layer 802 may be formed directly on sidewalls 712 and directly on bottom surface 714 of trench 702 , and may be formed directly on sidewall 716 and directly on the bottom surface of via 704 Go to 718. Copper seed layer 802 may include copper deposited by ALD (eg, by deposition apparatus 102 ) and may be used as an initial layer of copper for copper growth during electroplating operations for depositing copper layer 722 . The deposition apparatus 102 may form the copper seed layer 802 to a thickness in the range of about 5 angstroms to about 15 angstroms to provide a sufficient amount of copper on which to grow the copper layer 722 by electroplating.

如第8E圖所示，銅層722可形成在雙鑲嵌結構700的剩餘體積中（例如，在導孔704及溝槽702中），使得雙鑲嵌結構700填充有銅。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以使銅離子在位於導孔704及溝槽702中的銅晶種層802上方生長銅層722。銅晶種層802可促進銅層722的生長以及銅層722對側壁712、底表面714、側壁716、及底表面718的黏著性。可進行回焊操作，以將銅層722加熱，以允許銅層722流動。這允許銅層722填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在鍍膜操作之後及回焊操作之後，平坦化設備110可進行CMP操作以將銅層722平坦化。As shown in Figure 8E, a copper layer 722 may be formed in the remaining volume of the dual damascene structure 700 (eg, in the vias 704 and trenches 702) such that the dual damascene structure 700 is filled with copper. Coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause copper ions to grow copper layer 722 over copper seed layer 802 in via 704 and trench 702 . The copper seed layer 802 may promote the growth of the copper layer 722 and the adhesion of the copper layer 722 to the sidewalls 712 , the bottom surface 714 , the sidewalls 716 , and the bottom surface 718 . A reflow operation may be performed to heat the copper layer 722 to allow the copper layer 722 to flow. This allows the copper layer 722 to fill any voids or eliminate any islands of material that may have formed during the plating operation. After the plating operation and after the reflow operation, the planarization apparatus 110 may perform a CMP operation to planarize the copper layer 722 .

鍍膜操作可包括在雙鑲嵌結構700中沉積摻雜鋅的銅以形成銅層722。銅中的鋅可在鍍膜操作期間及/或在回焊操作期間朝向側壁712、底表面714、及側壁716的介電材料被向外驅出。鋅可與介電材料鍵結，以在側壁712、底表面714及側壁716上自形成（self-form）氧化鋅矽阻障720。The plating operation may include depositing zinc-doped copper in dual damascene structure 700 to form copper layer 722 . The zinc in the copper may be driven out toward the dielectric material of the sidewalls 712 , the bottom surface 714 , and the sidewalls 716 during the plating operation and/or during the reflow operation. Zinc can bond with the dielectric material to self-form a zinc oxide silicon barrier 720 on sidewalls 712 , bottom surface 714 , and sidewalls 716 .

如前文所述，提供第8A圖至第8E圖作為示例。其他示例可能與關於第8A圖至第8E圖描述的不同。As previously mentioned, Figures 8A to 8E are provided as examples. Other examples may differ from those described with respect to Figures 8A-8E.

第9圖係本文所述的例示性雙鑲嵌結構900的圖。雙鑲嵌結構900可為可被包括在裝置200中的雙鑲嵌結構248的示例。雙鑲嵌結構900可包括溝槽902及導孔904。導孔904可連接到下金屬化層906，上述下金屬化層906可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層906可包括位於裝置200的BEOL區240中的另一雙鑲嵌結構的溝槽、位於BEOL區240中的單鑲嵌結構的導孔、位於裝置200的MEOL區230中的接觸插塞、或其他類型的內連線。可在下金屬化層906及位於下金屬化層906上方的介電層910之間提供蝕刻停止層908，以促進雙鑲嵌結構900的形成。FIG. 9 is a diagram of an exemplary dual damascene structure 900 described herein. Dual damascene structure 900 may be an example of dual damascene structure 248 that may be included in device 200 . The dual damascene structure 900 may include trenches 902 and vias 904 . Vias 904 may be connected to lower metallization layer 906, which may be formed of copper, cobalt, or other types of metal materials. The lower metallization layer 906 may include trenches of another dual damascene structure in the BEOL region 240 of the device 200 , vias of a single damascene structure in the BEOL region 240 , contact plugs in the MEOL region 230 of the device 200 , or other types of interconnects. An etch stop layer 908 may be provided between the lower metallization layer 906 and the dielectric layer 910 overlying the lower metallization layer 906 to facilitate formation of the dual damascene structure 900 .

雙鑲嵌結構900可形成在介電層910中並且穿過蝕刻停止層908。溝槽902可包括側壁912及底表面914。導孔904也可包括側壁916及底表面918側壁。912、底表面914、及側壁916可包括介電層910圍繞雙鑲嵌結構900的部分。Dual damascene structure 900 may be formed in dielectric layer 910 and through etch stop layer 908 . The trench 902 may include sidewalls 912 and a bottom surface 914 . The vias 904 may also include sidewalls 916 and bottom surface 918 sidewalls. 912 , bottom surface 914 , and sidewalls 916 may include portions of dielectric layer 910 surrounding dual damascene structure 900 .

導孔904的底表面918可包括位於導孔904之下的下金屬化層906的一部分。在一些實施方式中，導孔904為電路導孔。在這些實施方式中，導孔904的底表面918的寬度可在約10nm至約22nm的範圍。在一些實施方式中，導孔904為密封環導孔。在這些實施方式中，導孔904的底表面918的寬度可在約100nm至約180nm的範圍。Bottom surface 918 of via 904 may include a portion of lower metallization layer 906 underlying via 904 . In some embodiments, vias 904 are circuit vias. In these embodiments, the width of the bottom surface 918 of the via hole 904 may range from about 10 nm to about 22 nm. In some embodiments, the pilot hole 904 is a seal ring pilot hole. In these embodiments, the width of the bottom surface 918 of the via hole 904 may range from about 100 nm to about 180 nm.

氧化鋅矽（zinc silicon oxide, ZnSiO x）阻障920可被包括在雙鑲嵌結構900的側壁912、底表面914、及側壁916上。氧化鋅矽阻障920可包括薄膜氧化鋅矽層，其用作銅（copper, Cu）層922的擴散阻障，上述銅層922填充在位於氧化鋅矽阻障920上方的雙鑲嵌結構900中（例如，在溝槽902中及導孔904中）中。因此，氧化鋅矽阻障920減少了或防止了銅離子擴散到介電層910及位於介電層910下方的層中。 A zinc silicon oxide (ZnSiO x ) barrier 920 may be included on the sidewalls 912 , the bottom surface 914 , and the sidewalls 916 of the dual damascene structure 900 . Zinc oxide silicon barrier 920 may include a thin film zinc oxide silicon layer that acts as a diffusion barrier for copper (Cu) layer 922 filled in dual damascene structure 900 over zinc oxide silicon barrier 920 (eg, in trenches 902 and in vias 904). Thus, the zinc oxide silicon barrier 920 reduces or prevents the diffusion of copper ions into the dielectric layer 910 and the layers below the dielectric layer 910 .

再者，氧化鋅矽阻障920可形成為相較於其他銅擴散阻障的厚度而言更小的厚度，同時仍然提供足夠的銅擴散功能，這增加了雙鑲嵌結構900的銅填充寬裕度（例如，或在製程節點尺寸縮小到小於 10 nm 時保持銅填充寬裕度），上述其他銅擴散阻障例如氮化鉭及釕。舉例而言，氧化鋅矽阻障920的厚度可在約5埃至約15埃的範圍。Furthermore, the zinc oxide silicon barrier 920 can be formed to a smaller thickness compared to the thickness of other copper diffusion barriers, while still providing sufficient copper diffusion function, which increases the copper fill margin of the dual damascene structure 900 (eg, or to maintain copper fill margins as process node sizes shrink to less than 10 nm), other copper diffusion barriers such as tantalum nitride and ruthenium above. For example, the thickness of the zinc oxide silicon barrier 920 may range from about 5 angstroms to about 15 angstroms.

如第9圖中的示例所示，形成氧化鋅矽阻障920，使得鋅層924被包括在導孔904的底表面918上。鋅層924可包括少量鋅材料（例如，在約3埃至約10埃的範圍的厚度，以促進氧化鋅矽阻障920的形成），其被形成為形成氧化鋅矽阻障920的一部分。具體而言，因為鋅層924形成在另一金屬（例如，下金屬化層906）上而不是形成在介電材料上（在這種情況下，鋅層924將與介電材料鍵結以形成氧化鋅，例如氧化鋅矽），所以鋅層924保持為鋅材料。鋅層924為金屬材料，因此為雙鑲嵌結構900的底表面918上提供低接觸電阻。As shown in the example in FIG. 9 , a zinc oxide silicon barrier 920 is formed such that a zinc layer 924 is included on the bottom surface 918 of the via 904 . Zinc layer 924 may include a small amount of zinc material (eg, in a thickness in the range of about 3 angstroms to about 10 angstroms to facilitate formation of zinc oxide silicon barrier 920 ) that is formed to form part of zinc oxide silicon barrier 920 . Specifically, because zinc layer 924 is formed on another metal (eg, lower metallization layer 906 ) rather than a dielectric material (in which case, zinc layer 924 would bond with the dielectric material to form zinc oxide, such as zinc oxide silicon), so the zinc layer 924 remains a zinc material. The zinc layer 924 is a metallic material and thus provides low contact resistance on the bottom surface 918 of the dual damascene structure 900 .

如前文所述，提供第9圖作為示例。其他示例可能與關於第9圖所描述的不同。As previously mentioned, Figure 9 is provided as an example. Other examples may differ from those described with respect to FIG. 9 .

第10A圖至第10F圖係在本文所述的例示性實施方式1000的圖。例示性實施方式1000可為形成第9圖的雙鑲嵌結構900的示例。在一些實施方式中，半導體製程設備102-116中的一個或多個進行結合第10A圖至第10F圖所述的製程及/或操作中的一個或多個。如第10A圖所示，雙鑲嵌結構900可形成在位於下金屬化層906上方的介電層910中。蝕刻停止層908可被包括在介電層910及下金屬化層906之間，以促進介電層910中的雙鑲嵌結構900的形成。Figures 10A-10F are diagrams of an exemplary embodiment 1000 described herein. The exemplary embodiment 1000 may be an example of forming the dual damascene structure 900 of FIG. 9 . In some embodiments, one or more of the semiconductor process equipment 102-116 performs one or more of the processes and/or operations described in connection with Figures 10A-10F. As shown in FIG. 10A , a dual damascene structure 900 may be formed in a dielectric layer 910 overlying a lower metallization layer 906 . Etch stop layer 908 may be included between dielectric layer 910 and lower metallization layer 906 to facilitate formation of dual damascene structure 900 in dielectric layer 910 .

如第10B圖所示，導孔904可形成在介電層910中。具體而言，導孔904可從介電層910的頂表面穿過介電層910形成。導孔904可進一步形成穿過蝕刻停止層908並到達下金屬化層906。沉積設備102可在介電層910上形成光阻層，曝光設備104可將光阻層暴露於輻射源以圖案化光阻層，顯影設備106可顯影並移除部分光阻層以暴露圖案，並且蝕刻設備108可蝕刻介電層910及蝕刻停止層908，以穿過介電層910及蝕刻停止層908形成導孔904的側壁916。可蝕刻導孔904到下金屬化層906，使得下金屬化層906的頂表面為導孔904的底表面918。在一些實施方式中，光阻移除設備（例如，使用化學剝離劑及/或其他技術）移除光阻層的剩餘部分。As shown in FIG. 10B , vias 904 may be formed in the dielectric layer 910 . Specifically, vias 904 may be formed through the dielectric layer 910 from the top surface of the dielectric layer 910 . Vias 904 may be further formed through etch stop layer 908 and to lower metallization layer 906 . Deposition apparatus 102 may form a photoresist layer on dielectric layer 910, exposure apparatus 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, developing apparatus 106 may develop and remove portions of the photoresist layer to expose the pattern, And the etching apparatus 108 can etch the dielectric layer 910 and the etch stop layer 908 to form sidewalls 916 of the via hole 904 through the dielectric layer 910 and the etch stop layer 908 . Via 904 can be etched into lower metallization layer 906 such that the top surface of lower metallization layer 906 is the bottom surface 918 of via 904 . In some embodiments, photoresist removal equipment (eg, using chemical strippers and/or other techniques) removes the remaining portions of the photoresist layer.

如第10C圖所示，可在導孔904上方的介電層910中形成溝槽902。具體而言，可形成溝槽902從介電層910的頂表面進入到介電層910的一部分中。沉積設備102可在介電層910上形成光阻層，曝光設備104可將光阻層暴露於輻射源以圖案化光阻層，顯影設備106可顯影並移除部分光阻層以暴露圖案，並且蝕刻設備108可蝕刻介電層910，以在介電層910中形成溝槽902的側壁912及底表面914。在一些實施方式中，光阻移除設備（例如，使用化學剝離劑及/或其他技術）移除光阻層的剩餘部分。As shown in FIG. 10C , trenches 902 may be formed in dielectric layer 910 over vias 904 . Specifically, trenches 902 may be formed into a portion of dielectric layer 910 from the top surface of dielectric layer 910 . Deposition apparatus 102 may form a photoresist layer on dielectric layer 910, exposure apparatus 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, developing apparatus 106 may develop and remove portions of the photoresist layer to expose the pattern, And etching apparatus 108 may etch dielectric layer 910 to form sidewalls 912 and bottom surface 914 of trench 902 in dielectric layer 910 . In some embodiments, photoresist removal equipment (eg, using chemical strippers and/or other techniques) removes the remaining portions of the photoresist layer.

第10B圖及10C圖繪示了例示性導孔先製（via-first）雙鑲嵌製程，其中藉由在形成溝槽902之前形成導孔904來形成雙鑲嵌結構900。在一些實施方式中，進行導孔先製雙鑲嵌製程以形成雙鑲嵌結構900，其中藉由在形成導孔904（或另一種類型的雙鑲嵌製程）之前，在上述導孔先製雙鑲嵌製程中形成雙鑲嵌結構900。FIGS. 10B and 10C illustrate an exemplary via-first dual damascene process in which dual damascene structure 900 is formed by forming vias 904 before trenches 902 are formed. In some embodiments, a via-first dual damascene process is performed to form dual damascene structure 900 by performing a via-first dual damascene process prior to forming vias 904 (or another type of dual damascene process). A dual damascene structure 900 is formed.

如第10D圖所示，鋅層924可直接形成在側壁912上及直接形成在溝槽902的底表面914上，也可直接形成在側壁916上及直接形成在導孔904的底表面918上。鋅層924可用於在側壁912上、底表面914上、及側壁916上形成氧化鋅矽阻障。沉積設備102可藉由進行ALD操作在側壁912上、底表面914上、及側壁916上沉積鋅層924。沉積設備102可形成鋅層924至約3埃至約10埃的範圍的厚度，以在側壁912上、底表面914上、及側壁916上提供足夠的銅擴散阻障，同時保持雙鑲嵌結構900的低片電阻。As shown in FIG. 10D , the zinc layer 924 can be formed directly on the sidewalls 912 and directly on the bottom surface 914 of the trench 902 , and can also be formed directly on the sidewalls 916 and directly on the bottom surface 918 of the via hole 904 . The zinc layer 924 may be used to form a zinc oxide silicon barrier on the sidewalls 912 , the bottom surface 914 , and the sidewalls 916 . The deposition apparatus 102 may deposit a zinc layer 924 on the sidewalls 912, on the bottom surface 914, and on the sidewalls 916 by performing an ALD operation. The deposition apparatus 102 may form the zinc layer 924 to a thickness in the range of about 3 angstroms to about 10 angstroms to provide sufficient copper diffusion barriers on the sidewalls 912 , on the bottom surface 914 , and on the sidewalls 916 while maintaining the dual damascene structure 900 low sheet resistance.

如第10E圖所示，銅晶種層1002可形成在位於側壁912上方的鋅層924上及在溝槽902的底表面914上方，並且可形成在位於側壁916上方的鋅層924上及在導孔904的底表面918上方。銅晶種層1002可包括藉由ALD（例如，藉由沉積設備102）沉積的銅，並且在用於沉積銅層922的電鍍操作期間，銅晶種層1002可用作用於銅生長的銅的初始層。沉積設備102可形成銅晶種層1002至約5埃至約15埃的範圍的厚度，以提供足夠量的銅，藉由電鍍在其上生長銅層922。As shown in FIG. 10E, a copper seed layer 1002 may be formed on the zinc layer 924 over the sidewalls 912 and over the bottom surface 914 of the trench 902, and may be formed over the zinc layer 924 over the sidewalls 916 and over the bottom surface 914 of the trench 902 Above the bottom surface 918 of the guide hole 904 . The copper seed layer 1002 can include copper deposited by ALD (eg, by the deposition apparatus 102 ), and during the electroplating operation used to deposit the copper layer 922 , the copper seed layer 1002 can be used as an initial source of copper for copper growth Floor. The deposition apparatus 102 may form the copper seed layer 1002 to a thickness in the range of about 5 angstroms to about 15 angstroms to provide a sufficient amount of copper on which to grow the copper layer 922 by electroplating.

如第10F圖所示，銅層922可形成在雙鑲嵌結構900的剩餘體積中（例如，在導孔904及溝槽902中），使得雙鑲嵌結構900填充有銅。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以使銅離子在位於導孔904及溝槽902中的銅晶種層1002上方生長銅層922。銅晶種層1002可促進銅層922的生長以及銅層922對側壁912、底表面914、側壁916、及底表面918的黏著性。可進行回焊操作，以將銅層922加熱到允許銅層922流動。這允許銅層922填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在鍍膜操作之後及回焊操作之後，平坦化設備110可進行CMP操作以將銅層922平坦化。As shown in FIG. 10F, a copper layer 922 may be formed in the remaining volume of the dual damascene structure 900 (eg, in the vias 904 and trenches 902) such that the dual damascene structure 900 is filled with copper. Coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause copper ions to grow copper layer 922 over copper seed layer 1002 in via 904 and trench 902 . The copper seed layer 1002 may promote the growth of the copper layer 922 and the adhesion of the copper layer 922 to the sidewalls 912 , the bottom surface 914 , the sidewalls 916 , and the bottom surface 918 . A reflow operation may be performed to heat the copper layer 922 to allow the copper layer 922 to flow. This allows the copper layer 922 to fill any voids or eliminate any islands of material that may have formed during the coating operation. After the plating operation and after the reflow operation, the planarization apparatus 110 may perform a CMP operation to planarize the copper layer 922 .

如第10F圖進一步所示，位於側壁912上、底表面914上、及側壁916上之鋅層924中的鋅可向外朝向側壁912、底表面914、及側壁916的介電材料被驅出。鋅可與介電材料鍵結，以在側壁912上、底表面914上、及側壁916上自形成氧化鋅矽阻障920。鋅層924及介電材料之間的鍵結可導致氧化鋅矽阻障920（例如，從最初在側壁912上、底表面914上、及側壁916上形成約3埃至約10埃的範圍的鋅層924）生長至約5埃至約15埃的範圍的厚度。形成在導孔904的底表面918處的下金屬化層906上的鋅層924可保持為鋅（例如，鋅層924的這部分不形成氧化鋅矽），因為鋅層924的這部分不直接與介電層910接觸。As further shown in FIG. 10F , the zinc in the zinc layer 924 on the sidewalls 912 , the bottom surface 914 , and the sidewalls 916 may be driven out toward the dielectric material of the sidewalls 912 , the bottom surface 914 , and the sidewalls 916 . . Zinc may bond with the dielectric material to self form zinc oxide silicon barriers 920 on sidewalls 912 , bottom surface 914 , and sidewalls 916 . Bonding between the zinc layer 924 and the dielectric material can result in a zinc oxide silicon barrier 920 (eg, initially forming a range of about 3 angstroms to about 10 angstroms on the sidewalls 912, on the bottom surface 914, and on the sidewalls 916). A zinc layer 924) is grown to a thickness in the range of about 5 angstroms to about 15 angstroms. The zinc layer 924 formed on the lower metallization layer 906 at the bottom surface 918 of the via 904 may remain zinc (eg, this portion of the zinc layer 924 does not form zinc oxide silicon) because this portion of the zinc layer 924 is not directly In contact with the dielectric layer 910 .

如前文所述，提供第10A圖至第10F圖作為示例。其他示例可能與關於第10A圖至第10F圖所描述的不同。As previously mentioned, Figures 10A to 10F are provided as examples. Other examples may differ from those described with respect to Figures 10A-10F.

第11圖係在本文所述的例示性雙鑲嵌結構1100的圖。雙鑲嵌結構1100可為可被包括在裝置200中的雙鑲嵌結構248的示例。雙鑲嵌結構1100可包括溝槽1102及導孔1104。導孔1104可連接到下金屬化層1106，上述下金屬化層1106可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層1106可包括位於裝置200的BEOL區240中的另一種雙鑲嵌結構的溝槽、位於BEOL區240中的單鑲嵌結構的導孔、位於裝置200的MEOL區230中的接觸插塞、或其他類型的內連線。可在下金屬化層1106及位於下金屬化層1106上方的介電層1110之間提供蝕刻停止層1108，以促進雙鑲嵌結構1100的形成。FIG. 11 is a diagram of an exemplary dual damascene structure 1100 described herein. Dual damascene structure 1100 may be an example of dual damascene structure 248 that may be included in device 200 . The dual damascene structure 1100 may include trenches 1102 and vias 1104 . Vias 1104 may be connected to lower metallization layer 1106, which may be formed of copper, cobalt, or other types of metal materials. The lower metallization layer 1106 may include trenches of another dual damascene structure in the BEOL region 240 of the device 200 , vias of a single damascene structure in the BEOL region 240 , contact plugs in the MEOL region 230 of the device 200 , or other types of interconnects. An etch stop layer 1108 may be provided between the lower metallization layer 1106 and the dielectric layer 1110 overlying the lower metallization layer 1106 to facilitate formation of the dual damascene structure 1100 .

雙鑲嵌結構1100可形成在介電層1110中並穿過蝕刻停止層1108。溝槽1102可包括側壁1112及底表面1114。導孔1104也可包括側壁1116及底表面1118。側壁1112、底表面1114、及側壁1116可包括介電層1110圍繞雙鑲嵌結構1100的部分。The dual damascene structure 1100 may be formed in the dielectric layer 1110 and through the etch stop layer 1108 . The trench 1102 may include sidewalls 1112 and a bottom surface 1114 . The via 1104 may also include sidewalls 1116 and a bottom surface 1118 . Sidewalls 1112 , bottom surface 1114 , and sidewalls 1116 may include portions of dielectric layer 1110 surrounding dual damascene structure 1100 .

導孔1104的底表面1118可包括位於導孔1104下方的下金屬化層1106的一部分。在一些實施方式中，導孔1104為電路導孔。在這些實施方式中，導孔1104的底表面1118的寬度可在約10nm至約22nm的範圍。在一些實施方式中，導孔1104為密封環導孔。在這些實施方式中，導孔1104的底表面1118的寬度可在約100nm至約180nm的範圍。The bottom surface 1118 of the via 1104 may include a portion of the lower metallization layer 1106 below the via 1104 . In some embodiments, the vias 1104 are circuit vias. In these embodiments, the width of the bottom surface 1118 of the via hole 1104 may range from about 10 nm to about 22 nm. In some embodiments, the pilot hole 1104 is a seal ring pilot hole. In these embodiments, the width of the bottom surface 1118 of the via hole 1104 may range from about 100 nm to about 180 nm.

氧化鋅矽（zinc silicon oxide, ZnSiO x）阻障1120可被包括在雙鑲嵌結構1100的側壁1112、底表面1114及側壁1116上。可在氧化鋅矽阻障1120上方及鋅層1124上形成釕（ruthenium, Ru）晶種層1122，上述鋅層1124被包括直接位於導孔1104的底表面1118上。氧化鋅矽阻障1120可包括薄膜氧化鋅矽層，其用作銅（copper, Cu）層1126的擴散阻障，上述銅層1126填充在位於氧化鋅矽阻障1120上方及釕晶種層1122上方的雙鑲嵌結構1100中（例如，在溝槽1102中及導孔1104中）。因此，氧化鋅矽阻障1120減少了或防止了銅離子擴散到介電層1110及位於介電層1110下方的層中。 Zinc silicon oxide (ZnSiO x ) barriers 1120 may be included on the sidewalls 1112 , the bottom surface 1114 and the sidewalls 1116 of the dual damascene structure 1100 . A ruthenium (Ru) seed layer 1122 can be formed over the zinc oxide silicon barrier 1120 and on the zinc layer 1124 , which is included directly on the bottom surface 1118 of the via 1104 . The zinc oxide silicon barrier 1120 may include a thin film zinc oxide silicon layer, which acts as a diffusion barrier for a copper (Cu) layer 1126 filled over the zinc oxide silicon barrier 1120 and the ruthenium seed layer 1122 In the dual damascene structure 1100 above (eg, in the trenches 1102 and in the vias 1104). Thus, the zinc oxide silicon barrier 1120 reduces or prevents the diffusion of copper ions into the dielectric layer 1110 and the layers below the dielectric layer 1110 .

再者，氧化鋅矽阻障1120可形成為相較於其他銅擴散阻障更薄的厚度，同時仍然提供足夠的銅擴散功能，這增加了雙鑲嵌結構1100的銅填充寬裕度（例如，或在製程節點尺寸縮小到小於 10 nm 時保持銅填充寬裕度），上述其他銅擴散阻障層例如氮化鉭及釕。舉例而言，氧化鋅矽阻障1120的厚度可在約5埃至約15埃的範圍。Furthermore, the zinc oxide silicon barrier 1120 can be formed to a thinner thickness compared to other copper diffusion barriers, while still providing sufficient copper diffusion function, which increases the copper fill margin of the dual damascene structure 1100 (eg, or Maintaining copper fill margins as process node sizes shrink to less than 10 nm), other copper diffusion barriers such as tantalum nitride and ruthenium above. For example, the thickness of the zinc oxide silicon barrier 1120 may range from about 5 angstroms to about 15 angstroms.

如第11圖中的示例所示，形成氧化鋅矽阻障1120，使得鋅層1124被包括在導孔1104的底表面1118上。替代地，如上文結合第8A圖至第8E所述，可省略鋅層1124，並且氧化鋅矽阻障1120可由摻雜鋅的銅電鍍自形成。鋅層1124可包括少量鋅材料（例如，在約3埃至約10埃的範圍的厚度），其被形成為形成鋅矽氧化物阻障1120的一部分而。具體而言，因為鋅層1124形成在另一金屬（例如，下金屬化層1106）上而不是形成在介電材料上（在這種情況下，鋅層1124將與介電材料鍵結以形成氧化鋅，例如氧化鋅矽），所以鋅層1124保持為鋅材料。鋅層1124為金屬材料，因此為雙鑲嵌結構1100的底表面1118上提供低接觸電阻。替代地，底表面118可省略鋅層1124。As shown in the example of FIG. 11 , a zinc oxide silicon barrier 1120 is formed such that a zinc layer 1124 is included on the bottom surface 1118 of the via 1104 . Alternatively, as described above in connection with FIGS. 8A-8E, the zinc layer 1124 may be omitted, and the zinc oxide silicon barrier 1120 may be electroplated from zinc doped copper. The zinc layer 1124 may include a small amount of zinc material (eg, in a thickness in the range of about 3 angstroms to about 10 angstroms) that is formed to form part of the zinc silicon oxide barrier 1120 . Specifically, because the zinc layer 1124 is formed on another metal (eg, the lower metallization layer 1106 ) rather than a dielectric material (in which case, the zinc layer 1124 would bond with the dielectric material to form zinc oxide, such as zinc oxide silicon), so the zinc layer 1124 remains a zinc material. The zinc layer 1124 is a metallic material and thus provides low contact resistance on the bottom surface 1118 of the dual damascene structure 1100 . Alternatively, the bottom surface 118 may omit the zinc layer 1124 .

釕晶種層1122可包括釕層，上述釕層用作電鍍操作的晶種層，以用銅層1126填充雙鑲嵌結構1100。位於側壁1112上、位於底表面1114上、及位於側壁1116上的釕晶種層1122的厚度可在約5埃（以最小化及/或防止釕晶種層1122中的不連續性）至約15埃（以實現雙鑲嵌結構 1100的低片電阻）。位於底表面1118上的釕晶種層1122的厚度可在約3埃至約10埃的範圍，以實現雙鑲嵌結構1100的低接觸電阻。雙鑲嵌結構1100可藉由類似於前文結合第10A圖至第10E圖所描述的製程來形成，但是差別在於使用釕晶種層1122代替銅晶種層1002。The ruthenium seed layer 1122 may include a ruthenium layer used as a seed layer for the electroplating operation to fill the dual damascene structure 1100 with the copper layer 1126 . The thickness of the ruthenium seed layer 1122 on the sidewalls 1112, on the bottom surface 1114, and on the sidewalls 1116 may be between about 5 angstroms (to minimize and/or prevent discontinuities in the ruthenium seed layer 1122) to about 15 Angstroms (to achieve low sheet resistance for dual damascene structure 1100). The thickness of the ruthenium seed layer 1122 on the bottom surface 1118 may range from about 3 angstroms to about 10 angstroms to achieve low contact resistance of the dual damascene structure 1100 . The dual damascene structure 1100 may be formed by a process similar to that described above in connection with Figures 10A-10E, but with the difference that a ruthenium seed layer 1122 is used instead of the copper seed layer 1002.

如前文所述，提供第11圖作為示例。其他示例可能與關於第11圖所描述的不同。As previously mentioned, Figure 11 is provided as an example. Other examples may differ from those described with respect to Figure 11.

第12圖係本文所述的例示性雙鑲嵌結構1200的圖。雙鑲嵌結構1200可為可被包括在裝置200中的雙鑲嵌結構248的示例。雙鑲嵌結構1200可包括溝槽1202及導孔1204。導孔1204可連接到下金屬化層1206，上述下金屬化層1206可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層1206可包括位於裝置200的BEOL區240中的另一雙鑲嵌結構的溝槽、位於BEOL區240中的單鑲嵌結構的導孔、位於裝置200的MEOL區230中的接觸插塞、或其他類型的內連線。可在下金屬化層1206及位於下金屬化層1206上方的介電層1210之間提供蝕刻停止層1208，以促進雙鑲嵌結構1200的形成。FIG. 12 is a diagram of an exemplary dual damascene structure 1200 described herein. Dual damascene structure 1200 may be an example of dual damascene structure 248 that may be included in device 200 . The dual damascene structure 1200 may include trenches 1202 and vias 1204 . Vias 1204 may be connected to lower metallization layer 1206, which may be formed of copper, cobalt, or other types of metal materials. The lower metallization layer 1206 may include trenches of another dual damascene structure in the BEOL region 240 of the device 200 , vias of a single damascene structure in the BEOL region 240 , contact plugs in the MEOL region 230 of the device 200 , or other types of interconnects. An etch stop layer 1208 may be provided between the lower metallization layer 1206 and the dielectric layer 1210 overlying the lower metallization layer 1206 to facilitate formation of the dual damascene structure 1200 .

雙鑲嵌結構1200可形成在介電層1210中並且穿過蝕刻停止層1208。溝槽1202可包括側壁1212及底表面1214。導孔1204也可包括側壁1216及底表面1218。側壁1212、底表面1214、及側壁1216可包括介電層1210圍繞雙鑲嵌結構1200的部分。The dual damascene structure 1200 may be formed in the dielectric layer 1210 and through the etch stop layer 1208 . The trench 1202 may include sidewalls 1212 and a bottom surface 1214 . The via 1204 may also include sidewalls 1216 and a bottom surface 1218 . Sidewalls 1212 , bottom surface 1214 , and sidewalls 1216 may include portions of dielectric layer 1210 surrounding dual damascene structure 1200 .

導孔1204的底表面1218可包括位於導孔1204下方的下金屬化層1206的一部分。在一些實施方式中，導孔1204為電路導孔。在這些實施方式中，導孔1204之底表面1218的寬度對於M1層導孔（例如，M0金屬化層上方的金屬化層）而言可在約8nm至約15nm的範圍、對於M2層導孔（例如，M1金屬化層上方的金屬化層）而言約14nm至約22nm、或對於M3層導孔（例如，M2金屬化層上方的金屬化層）而言約12nm至約16nm。在一些實施方式中，導孔1204為密封環導孔。在這些實施方式中，導孔1204的底表面1218的寬度可在約100nm至約180nm的範圍。The bottom surface 1218 of the via 1204 may include a portion of the lower metallization layer 1206 below the via 1204 . In some embodiments, vias 1204 are circuit vias. In these embodiments, the width of the bottom surface 1218 of the via 1204 may be in the range of about 8 nm to about 15 nm for the M1 layer via (eg, the metallization layer over the M0 metallization layer) and about 15 nm for the M2 layer via For example, about 14 nm to about 22 nm for the metallization layer over the M1 metallization layer, or about 12 nm to about 16 nm for the M3 layer vias (eg, the metallization layer over the M2 metallization layer). In some embodiments, the pilot hole 1204 is a seal ring pilot hole. In these embodiments, the width of the bottom surface 1218 of the via hole 1204 may range from about 100 nm to about 180 nm.

釕襯層1220可被包括在溝槽1202的側壁1212及底表面1214上、以及在導孔1204的側壁1216及底表面1218上。釕襯層1220可用作銅（copper, Cu）層1222的擴散阻障，上述銅層1222填充在位於釕襯層1220上方的雙鑲嵌結構1200中（例如，在溝槽1202中及導孔1204中）。因此，釕襯層1220減少了或防止了銅離子擴散到介電層1210及介電層1210下方的層中。再者，因為薄膜釕的片電阻低於其他銅擴散阻障層的片電阻，所以釕襯層1220可降低雙鑲嵌結構1200的整體電阻率，上述其他銅擴散阻障層例如氮化鉭（tantalum nitride, TaN）。位於側壁1212上、底表面1214上、及側壁1216上的釕襯層1220的厚度在裝置200的BEOL區240中的M2層或M3層中可在約10埃（以提供足夠的銅擴散阻障）至約35埃（以實現雙鑲嵌結構1200的低片電阻）的範圍、並且在BEOL區240中的M1層中可在約10埃至約35埃的範圍。Ruthenium liner 1220 may be included on sidewalls 1212 and bottom surface 1214 of trench 1202 , and on sidewalls 1216 and bottom surface 1218 of via 1204 . The ruthenium liner 1220 may serve as a diffusion barrier for the copper (Cu) layer 1222 that fills the dual damascene structure 1200 over the ruthenium liner 1220 (eg, in the trenches 1202 and vias 1204 ). middle). Thus, the ruthenium liner 1220 reduces or prevents copper ions from diffusing into the dielectric layer 1210 and the layers below the dielectric layer 1210. Furthermore, since the sheet resistance of thin film ruthenium is lower than that of other copper diffusion barrier layers, such as tantalum nitride, the ruthenium liner 1220 can reduce the overall resistivity of the dual damascene structure 1200. nitride, TaN). The thickness of the ruthenium liner 1220 on the sidewalls 1212, on the bottom surface 1214, and on the sidewalls 1216 may be about 10 angstroms in the M2 or M3 layer in the BEOL region 240 of the device 200 (to provide a sufficient copper diffusion barrier ) to about 35 angstroms (to achieve low sheet resistance for the dual damascene structure 1200 ), and may be in the range of about 10 angstroms to about 35 angstroms in the M1 layer in the BEOL region 240 .

釕襯層1220可進一步被包括在導孔1204的底表面1218上，並且可填充導孔1204中的體積的一部分。在導孔1204中沉積銅層1222可能因為鍍膜製程而導致銅層1222中的空隙、島狀物、及其他不連續性，上述鍍膜製程是用於將銅層1222沉積在導孔1204中。可在保形（或超保形（super conformal））沉積製程中將釕襯層1220形成在導孔1204中，這相對於銅層1222電鍍製程而言可導致更少的空隙及其他不連續性。A ruthenium liner 1220 may further be included on the bottom surface 1218 of the via 1204 and may fill a portion of the volume in the via 1204 . Depositing the copper layer 1222 in the via 1204 may cause voids, islands, and other discontinuities in the copper layer 1222 due to the coating process used to deposit the copper layer 1222 in the via 1204 . The ruthenium liner 1220 may be formed in the vias 1204 in a conformal (or super conformal) deposition process, which may result in fewer voids and other discontinuities relative to the copper layer 1222 electroplating process .

位於導孔1204的底表面1218上的釕襯層1220的厚度可大於位於側壁1212上、底表面1214上、及側壁1216上的釕襯層1220的厚度，以最小化及/或防止形成空隙及其他不連續性，並減少將在導孔1204中形成的銅層1222的量。用於電路導孔之位於導孔1204的底表面1218上的釕襯層1220的厚度可在約 20 埃至約 60 埃的範圍，以將在釕襯層1220及銅層1222中形成空隙及其他不連續性的可能性（例如，藉由減少填充導孔1204所需的銅材料的量）最小化。在一些實施方式中，用於密封環導孔之位於導孔1204的底表面1218上的釕襯層1220的厚度，可為位於電路導孔之底表面1218上的釕襯層1220的厚度的約50%至約80%的範圍（例如，在約16埃至約48埃的範圍）。在一些實施方式中，對於密封環導孔而言，位於底表面1218上的釕襯層1220及位於導孔1204的側壁1216上的釕襯層1220之間的過渡角（transition angle）1228可在約30度至約60度的範圍，作為釕襯層 1220 的保形沉積製程的結果。The thickness of the ruthenium liner 1220 on the bottom surface 1218 of the via 1204 may be greater than the thickness of the ruthenium liner 1220 on the sidewalls 1212, on the bottom surface 1214, and on the sidewalls 1216 to minimize and/or prevent the formation of voids and other discontinuities, and reduce the amount of copper layer 1222 that will be formed in vias 1204. The thickness of the ruthenium liner 1220 on the bottom surface 1218 of the via 1204 for the circuit vias may range from about 20 angstroms to about 60 angstroms to form voids in the ruthenium liner layer 1220 and copper layer 1222 and other The possibility of discontinuities (eg, by reducing the amount of copper material required to fill vias 1204) is minimized. In some embodiments, the thickness of the ruthenium liner 1220 on the bottom surface 1218 of the via hole 1204 for the seal ring via can be approximately the thickness of the ruthenium liner 1220 on the bottom surface 1218 of the circuit via 50% to about 80% range (eg, in the range of about 16 angstroms to about 48 angstroms). In some embodiments, for the seal ring via, the transition angle 1228 between the ruthenium liner 1220 on the bottom surface 1218 and the ruthenium liner 1220 on the sidewalls 1216 of the via 1204 may be at The range of about 30 degrees to about 60 degrees, as a result of the conformal deposition process of the ruthenium liner 1220 .

在一些實施方式中，氧化釕（ruthenium oxide, RuO x）膜被包括在雙鑲嵌結構1200的側壁1212上、底表面1214上、及側壁1216上。在這些示例中，氧化釕膜可促進周圍介電層1210及釕襯層1220之間的黏著性。氧化釕膜可減少及/或防止在沉積釕襯層1220的期間在釕襯層1220中形成不連續性。 In some embodiments, a ruthenium oxide (RuO x ) film is included on the sidewalls 1212 , the bottom surface 1214 , and the sidewalls 1216 of the dual damascene structure 1200 . In these examples, the ruthenium oxide film may promote adhesion between the surrounding dielectric layer 1210 and the ruthenium liner layer 1220 . The ruthenium oxide film may reduce and/or prevent the formation of discontinuities in the ruthenium liner 1220 during deposition of the ruthenium liner 1220 .

蓋層1224可被包括在銅層1222的頂部上。蓋層1224可包括鈷、或另一種金屬材料。可由蓋層1224中的鈷沿著釕襯層1220及銅層1222之間的界面形成鈷襯層1226。具體而言，來自蓋層1224的鈷可在形成蓋層1224的期間沿著釕-銅界面擴散。A capping layer 1224 may be included on top of the copper layer 1222 . The capping layer 1224 may include cobalt, or another metallic material. Cobalt liner 1226 may be formed from cobalt in cap layer 1224 along the interface between ruthenium liner 1220 and copper layer 1222 . Specifically, cobalt from capping layer 1224 may diffuse along the ruthenium-copper interface during formation of capping layer 1224 .

如前文所述，提供第12圖作為示例。其他示例可能與關於第12圖所描述的不同。As previously mentioned, Figure 12 is provided as an example. Other examples may differ from those described with respect to Figure 12.

第13A圖至第13E圖係本文所述的例示性實施方式1300的圖。例示性實施方式1300可為形成第12圖的雙鑲嵌結構1200的示例。在一些實施方式中，半導體製程設備102-116中的一個或多個進行結合第13A圖至第13E圖所述的製程、及/或操作中的一個或多個。如第13A圖所示，雙鑲嵌結構1200可形成在位於下金屬化層1206上方的介電層1210中。蝕刻停止層1208可被包括在介電層1210及下金屬化層1206之間，以促進形成介電層1210中的雙鑲嵌結構1200。13A-13E are diagrams of an exemplary embodiment 1300 described herein. The exemplary embodiment 1300 may be an example of forming the dual damascene structure 1200 of FIG. 12 . In some embodiments, one or more of the semiconductor process equipment 102-116 performs one or more of the processes, and/or operations described in connection with Figures 13A-13E. As shown in FIG. 13A , a dual damascene structure 1200 may be formed in a dielectric layer 1210 overlying a lower metallization layer 1206 . An etch stop layer 1208 may be included between the dielectric layer 1210 and the lower metallization layer 1206 to facilitate formation of the dual damascene structure 1200 in the dielectric layer 1210 .

如第13B圖所示，雙鑲嵌結構1200的溝槽1202及導孔1204可形成在介電層1210中。如前文所述，半導體製程設備102-116的一個或多個可藉由進行導孔先製雙鑲嵌製程、溝槽先製雙鑲嵌製程、或另一種雙鑲嵌製程來形成介電層1210中的溝槽1202及導孔1204。As shown in FIG. 13B , the trenches 1202 and the vias 1204 of the dual damascene structure 1200 may be formed in the dielectric layer 1210 . As previously described, one or more of the semiconductor process tools 102-116 may form the dielectric layer 1210 by performing a via-first dual damascene process, a trench-first dual damascene process, or another dual damascene process. Trenches 1202 and vias 1204 .

如第13C圖所示，釕襯層1220可形成在溝槽1202的側壁1212及底表面1214上，並且可形成在導孔1204的側壁1216及底表面1218上。沉積設備102可藉由進行ALD操作或CVD操作來沉積釕襯層1220。沉積設備102可在溝槽1202的側壁1212及底表面1214上以及導孔1204的側壁1216上形成釕襯層1220至約10埃至約35埃的範圍的厚度。沉積設備102可在導孔1204的底表面1218上形成釕襯層1220至約16埃至約60埃的範圍的厚度。As shown in FIG. 13C , a ruthenium liner 1220 may be formed on the sidewalls 1212 and bottom surfaces 1214 of the trenches 1202 , and may be formed on the sidewalls 1216 and bottom surfaces 1218 of the vias 1204 . The deposition apparatus 102 may deposit the ruthenium liner 1220 by performing an ALD operation or a CVD operation. Deposition apparatus 102 may form a ruthenium liner 1220 to a thickness ranging from about 10 angstroms to about 35 angstroms on sidewalls 1212 and bottom surfaces 1214 of trenches 1202 and on sidewalls 1216 of vias 1204 . The deposition apparatus 102 may form a ruthenium liner 1220 on the bottom surface 1218 of the via 1204 to a thickness ranging from about 16 angstroms to about 60 angstroms.

在一些實施方式中，用於密封環導孔的導孔1204的底表面1218上的釕襯層1220的厚度可為位於電路導孔的底表面1218上的釕襯層1220的厚度的約50%至約80%的範圍（例如，在約16埃至約48埃的範圍）。在一些實施方式中，位於底表面1218上的釕襯層1220與用於密封環導孔之導孔1204的側壁1216上的釕襯層1220之間的過渡角可在約30度至約60度的範圍，作為釕襯層 1220 的超保形沉積製程的結果。In some embodiments, the thickness of the ruthenium liner 1220 on the bottom surface 1218 of the via 1204 for the seal ring via may be about 50% of the thickness of the ruthenium liner 1220 on the bottom surface 1218 of the circuit via to a range of about 80% (eg, in a range of about 16 angstroms to about 48 angstroms). In some embodiments, the transition angle between the ruthenium liner 1220 on the bottom surface 1218 and the ruthenium liner 1220 on the sidewalls 1216 of the vias 1204 for the seal ring vias may be about 30 degrees to about 60 degrees range, as a result of the ultra-conformal deposition process of the ruthenium liner 1220.

如第13D圖所示，銅層1222可形成在位於釕襯層1220上方的雙鑲嵌結構1200中（例如，在導孔1204及溝槽1202中）。可形成銅層1222，使得位於雙鑲嵌結構1200頂部之體積的一部分為蓋層1224保持未填充。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以使銅離子生長銅層1222在位於導孔1204中及溝槽1202中的釕襯層1220上方。可藉由加熱銅層1222以允許銅層1222流動來進行回焊操作。這允許銅層1222填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在一些實施方式中，在鍍膜操作期間加熱雙鑲嵌結構1200，使得回焊操作及鍍膜操作同時進行。在一些實施方式中，可進行多次鍍膜操作及/或多次回焊操作，以用銅層1222填充雙鑲嵌結構1200。As shown in FIG. 13D, a copper layer 1222 may be formed in the dual damascene structure 1200 over the ruthenium liner layer 1220 (eg, in the vias 1204 and trenches 1202). The copper layer 1222 may be formed such that a portion of the volume on top of the dual damascene structure 1200 remains unfilled for the capping layer 1224. The coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause copper ions to grow a copper layer 1222 over the ruthenium liner 1220 in the vias 1204 and in the trenches 1202 . The reflow operation may be performed by heating the copper layer 1222 to allow the copper layer 1222 to flow. This allows the copper layer 1222 to fill any voids or eliminate any islands of material that may have formed during the plating operation. In some embodiments, the dual damascene structure 1200 is heated during the coating operation so that the reflow operation and the coating operation are performed simultaneously. In some embodiments, multiple coating operations and/or multiple reflow operations may be performed to fill the dual damascene structure 1200 with the copper layer 1222 .

如第13E圖所示，可在銅層1222上形成蓋層1224。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以導致鈷離子在銅層1222上方生長蓋層1224。平坦化設備110可在鍍膜操作之後進行CMP操作，以將蓋層1224平坦化。如第13E圖進一步所示，在形成蓋層1224以形成鈷襯層1226期間，蓋層1224中的鈷的一部分可沿著釕襯層1220及銅層1222之間的釕-銅界面擴散。As shown in FIG. 13E, a capping layer 1224 may be formed on the copper layer 1222. The coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause cobalt ions to grow a cap layer 1224 over the copper layer 1222 . The planarization apparatus 110 may perform a CMP operation to planarize the cap layer 1224 after the coating operation. As further shown in FIG. 13E, during the formation of capping layer 1224 to form cobalt liner layer 1226, a portion of the cobalt in capping layer 1224 may diffuse along the ruthenium-copper interface between ruthenium liner layer 1220 and copper layer 1222.

如前文所述，提供第13A圖至第13E圖作為示例。其他示例可能與關於第13A圖至第13E圖描述的不同。As previously mentioned, Figures 13A to 13E are provided as examples. Other examples may differ from those described with respect to Figures 13A-13E.

第14圖係本文所述的例示性雙鑲嵌結構1400的圖。雙鑲嵌結構1400可為可被包括在裝置200中的雙鑲嵌結構248的示例。雙鑲嵌結構1400可包括溝槽1402及導孔1404。導孔1404可連接到下金屬化層1406 ，上述下金屬化層1406可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層1406可包括位於裝置200的BEOL區240中的另一雙鑲嵌結構的溝槽、位於BEOL區240中的單鑲嵌結構的導孔、位於裝置200的MEOL區230中的接觸插塞、或其他類型的內連線。可在下金屬化層1406及位於下金屬化層1406上方的介電層1410之間提供蝕刻停止層1408，以促進雙鑲嵌結構1400的形成。FIG. 14 is a diagram of an exemplary dual damascene structure 1400 described herein. Dual damascene structure 1400 may be an example of dual damascene structure 248 that may be included in device 200 . The dual damascene structure 1400 may include trenches 1402 and vias 1404 . Vias 1404 may be connected to lower metallization layers 1406, which may be formed of copper, cobalt, or other types of metal materials. The lower metallization layer 1406 may include trenches of another dual damascene structure in the BEOL region 240 of the device 200 , vias of a single damascene structure in the BEOL region 240 , contact plugs in the MEOL region 230 of the device 200 , or other types of interconnects. An etch stop layer 1408 may be provided between the lower metallization layer 1406 and the dielectric layer 1410 overlying the lower metallization layer 1406 to facilitate formation of the dual damascene structure 1400 .

雙鑲嵌結構1400可形成在介電層1410中並穿過蝕刻停止層1408。溝槽1402可包括側壁1412及底表面1414。導孔1404也可包括側壁1416及底表面1418。側壁1412、底表面1414、及側壁1416可包括介電層1410圍繞雙鑲嵌結構1400的部分。The dual damascene structure 1400 may be formed in the dielectric layer 1410 and through the etch stop layer 1408 . The trench 1402 may include sidewalls 1412 and a bottom surface 1414 . The via 1404 may also include sidewalls 1416 and a bottom surface 1418 . Sidewalls 1412 , bottom surface 1414 , and sidewalls 1416 may include portions of dielectric layer 1410 surrounding dual damascene structure 1400 .

導孔1404的底表面1418可包括位於導孔1404之下的下金屬化層1406的一部分。在一些實施方式中，導孔1404為電路導孔。在這些實施方式中，導孔1404的底表面1418的寬度對於M0層導孔而言可在約8nm至約12nm的範圍、或者對於M1至M3層導孔（例如，位於M0 層上方的金屬化層）而言可在約10nm至約22nm的範圍。在一些實施方式中，導孔1404為密封環導孔。在這些實施方式中，導孔1404的底表面1418的寬度可在約100nm至約180nm的範圍。Bottom surface 1418 of via 1404 may include a portion of lower metallization layer 1406 underlying via 1404 . In some embodiments, the vias 1404 are circuit vias. In these embodiments, the width of the bottom surface 1418 of the via 1404 may be in the range of about 8 nm to about 12 nm for M0 layer vias, or for M1 to M3 layer vias (eg, metallization over the M0 layer) layer) can be in the range of about 10 nm to about 22 nm. In some embodiments, the pilot hole 1404 is a seal ring pilot hole. In these embodiments, the width of the bottom surface 1418 of the via 1404 may range from about 100 nm to about 180 nm.

氮化鉭（tantalum nitride, TaN）膜1420可被包括在雙鑲嵌結構1400的側壁1412上、底表面1414上、及側壁1416上。氮化鉭膜1420可促進周圍介電層1410及釕 （ruthenium, Ru） 襯層1422之間的黏著性，上述釕襯層1422被包括在雙鑲嵌結構1400的側壁1412、底表面1414、及側壁1416上方以及氮化鉭膜1420上。因此，氮化鉭膜1420在釕襯層1422的沉積期間減少了及/或防止了在釕襯層1422中不連續性的形成。A tantalum nitride (TaN) film 1420 may be included on the sidewalls 1412 , the bottom surface 1414 , and the sidewalls 1416 of the dual damascene structure 1400 . The tantalum nitride film 1420 promotes adhesion between the surrounding dielectric layer 1410 and the ruthenium (Ru) liner 1422 included in the sidewalls 1412 , the bottom surface 1414 , and the sidewalls of the dual damascene structure 1400 1416 and over the tantalum nitride film 1420. Thus, the tantalum nitride film 1420 reduces and/or prevents the formation of discontinuities in the ruthenium liner 1422 during the deposition of the ruthenium liner 1422 .

釕襯層1422可用作銅 （copper, Cu） 層1424的擴散阻障，上述銅層1424填充位於釕襯層1422上方的雙鑲嵌結構1400中（例如，在溝槽1402中及導孔1404中）。因此，釕襯層1422減少了或防止了銅離子擴散到介電層1410及位於介電層1410下方的層中。再者，因為包含氮化鉭膜1420主要是為了用作黏著促進劑（adhesion promoter），而不是銅擴散阻障層，所以釕襯層1422允許氮化鉭膜1420變薄（例如，允許使用更薄的氮化鉭膜）。因為釕的片電阻低於氮化鉭的片電阻，所以氮化鉭膜1420的減小的厚度降低了雙鑲嵌結構1400的片電阻。薄氮化鉭膜1420及釕襯層1422的組合為雙鑲嵌結構1400提供了足夠的銅擴散阻障功能。The ruthenium liner 1422 may serve as a diffusion barrier for the copper (Cu) layer 1424 that fills the dual damascene structure 1400 over the ruthenium liner 1422 (eg, in the trenches 1402 and in the vias 1404 ). ). Thus, the ruthenium liner 1422 reduces or prevents the diffusion of copper ions into the dielectric layer 1410 and the layers below the dielectric layer 1410 . Furthermore, the ruthenium liner 1422 allows the tantalum nitride film 1420 to be thinned (eg, allowing the use of thinner thin tantalum nitride film). The reduced thickness of the tantalum nitride film 1420 reduces the sheet resistance of the dual damascene structure 1400 because the sheet resistance of ruthenium is lower than that of tantalum nitride. The combination of the thin tantalum nitride film 1420 and the ruthenium liner 1422 provides sufficient copper diffusion barrier function for the dual damascene structure 1400 .

位於側壁1412上、底表面1414上、及側壁1416上的氮化鉭膜1420的厚度可在約3埃（以最小化或防止在氮化鉭膜1420中及在釕襯層 1422中的不連續性） 至約8埃（以實現雙鑲嵌結構1400的低片電阻）的範圍。位於側壁1412上、底表面1414上、及側壁1416上之釕襯層1422的厚度可在約10埃（以提供足夠的銅擴散阻障）至約35埃（以實現雙鑲嵌結構1400的低片電阻）的範圍。The thickness of the tantalum nitride film 1420 on the sidewalls 1412, on the bottom surface 1414, and on the sidewalls 1416 may be about 3 angstroms (to minimize or prevent discontinuities in the tantalum nitride film 1420 and in the ruthenium liner 1422 range) to about 8 Angstroms (to achieve low sheet resistance of the dual damascene structure 1400). The thickness of the ruthenium liner 1422 on the sidewalls 1412, on the bottom surface 1414, and on the sidewalls 1416 may range from about 10 angstroms (to provide a sufficient copper diffusion barrier) to about 35 angstroms (to achieve a low profile for the dual damascene structure 1400). resistance) range.

在一些實施方式中，如第14圖中的示例所示，可形成氮化鉭膜1420及釕襯層1422，使得導孔1404的底表面1418省略氮化鉭膜1420及釕襯層1422。在這些實施方式中，銅層1424被包括直接位於導孔1404的底表面1418上，這為雙鑲嵌結構1400提供低接觸電阻。在一些實施方式中，氮化鉭膜1420的殘留量在氮化鉭膜1420的形成期間形成在導孔1404的底表面1418上方，及/或釕襯層1422的殘留量在釕襯層1422的形成期間形成在底表面1418上方。在這些實施方式中，銅層1424形成在氮化鉭膜1420的殘留量及/或釕襯層1422的殘留量上方，上述釕襯層1422位於導孔1404的底表面1418上方。在釕襯層1422的殘留量被包括在底表面1418上的情況下，位於底表面1418上的釕襯層 1422 的厚度可大於0埃並且小於約25埃，以實現雙鑲嵌結構1400的低接觸電阻。在殘留量的氮化鉭膜1420被包括在底表面1418上方殘留量的實施方式中，位於底表面1418上方的氮化鉭膜1420的厚度可大於0埃並且小於約5埃，以將氮化鉭對雙鑲嵌結構1400的接觸電阻的影響最小化。In some embodiments, tantalum nitride film 1420 and ruthenium liner 1422 may be formed such that the bottom surface 1418 of via 1404 omits the tantalum nitride film 1420 and ruthenium liner 1422, as shown in the example of FIG. 14 . In these embodiments, the copper layer 1424 is included directly on the bottom surface 1418 of the via 1404 , which provides low contact resistance for the dual damascene structure 1400 . In some embodiments, residual amounts of tantalum nitride film 1420 are formed over bottom surfaces 1418 of vias 1404 during formation of tantalum nitride film 1420 , and/or residual amounts of ruthenium liner 1422 are Formed over bottom surface 1418 during formation. In these embodiments, the copper layer 1424 is formed over the remainder of the tantalum nitride film 1420 and/or the remainder of the ruthenium liner 1422 over the bottom surface 1418 of the via 1404 . In the case where the residual amount of the ruthenium liner 1422 is included on the bottom surface 1418, the thickness of the ruthenium liner 1422 on the bottom surface 1418 may be greater than 0 angstroms and less than about 25 angstroms to achieve low contact for the dual damascene structure 1400 resistance. In embodiments where a residual amount of tantalum nitride film 1420 is included over the bottom surface 1418, the thickness of the tantalum nitride film 1420 over the bottom surface 1418 may be greater than 0 angstroms and less than about 5 angstroms to nitride the nitride The effect of tantalum on the contact resistance of the dual damascene structure 1400 is minimized.

如前文所述，提供第14圖作為示例。其他示例可能與關於第14圖所描述的不同。As previously mentioned, Figure 14 is provided as an example. Other examples may differ from those described with respect to Figure 14.

第15A圖至第15G圖係本文所述的例示性實施方式1500的圖。例示性實施方式1500可為形成第14圖的雙鑲嵌結構1400的示例。在一些實施方式中，半導體製程設備102-116中的一個或多個進行結合第15A圖至第15G圖所述的製程、及/或操作中的一個或多個。如第15A圖所示，雙鑲嵌結構1400可形成在位於下金屬化層1406上方的介電層1410中。蝕刻停止層1408可被包括在介電層1410及下金屬化層1406之間，以促進形成介電層1410中的雙鑲嵌結構1400。Figures 15A-15G are diagrams of an exemplary embodiment 1500 described herein. The exemplary embodiment 1500 may be an example of forming the dual damascene structure 1400 of FIG. 14 . In some embodiments, one or more of the semiconductor process equipment 102-116 performs one or more of the processes, and/or operations described in connection with FIGS. 15A-15G. As shown in FIG. 15A , a dual damascene structure 1400 may be formed in a dielectric layer 1410 overlying a lower metallization layer 1406 . An etch stop layer 1408 may be included between the dielectric layer 1410 and the lower metallization layer 1406 to facilitate formation of the dual damascene structure 1400 in the dielectric layer 1410 .

如第15B圖所示，雙鑲嵌結構1400的溝槽1402及導孔1404可形成在介電層1410中。如前文所述，半導體製程設備102-116中的一個或多個可藉由進行導孔先製雙鑲嵌製程、溝槽先製雙鑲嵌製程、或另一種雙鑲嵌製程在介電層1410中形成溝槽1402及導孔1404。，As shown in FIG. 15B , the trenches 1402 and the vias 1404 of the dual damascene structure 1400 may be formed in the dielectric layer 1410 . As previously described, one or more of the semiconductor process tools 102-116 may be formed in the dielectric layer 1410 by performing a via-first dual-damascene process, a trench-first dual-damascene process, or another dual-damascene process Trenches 1402 and vias 1404 . ,

如第15C圖所示，可修飾導孔1404的底表面1418，以抵抗或防止在底表面1418上形成氮化鉭膜1420及釕襯層1422。具體而言，預處理設備114可進行預處理操作，以使導孔1404的底表面1418變為非金屬性。預處理操作可包括將導孔1404的底表面1418浸入苯並三唑（benzotriazole, BTA）中一段時間，以在底表面1418上形成非金屬鈍化層1502。底表面1418可浸入BTA中，這導致下金屬化層1406的金屬材料（例如，銅）與BTA之間的錯合物形成鈍化層1502。鈍化層1502中的銅-BTA錯合物防止了或阻止了氮化鉭及釕前驅物被吸收到導孔1404的底表面1418（例如，下金屬化層1406）中。As shown in FIG. 15C , the bottom surface 1418 of the via hole 1404 may be modified to resist or prevent the formation of the tantalum nitride film 1420 and the ruthenium liner 1422 on the bottom surface 1418 . Specifically, the pretreatment device 114 may perform a pretreatment operation to render the bottom surface 1418 of the guide hole 1404 non-metallic. The pretreatment operation may include dipping the bottom surface 1418 of the via 1404 in benzotriazole (BTA) for a period of time to form a non-metallic passivation layer 1502 on the bottom surface 1418 . The bottom surface 1418 may be immersed in the BTA, which results in a complex between the metal material (eg, copper) of the lower metallization layer 1406 and the BTA to form the passivation layer 1502 . The copper-BTA complex in passivation layer 1502 prevents or prevents tantalum nitride and ruthenium precursors from being absorbed into bottom surface 1418 (eg, lower metallization layer 1406 ) of via 1404 .

如第15D圖所示，氮化鉭膜1420可形成在溝槽1402的側壁1412及底表面1414上、以及導孔1404的側壁1416上。沉積設備102可藉由進行ALD操作或CVD操作將氮化鉭膜1420直接沉積到側壁1412上、底表面1414上、及側壁1416上。沉積設備102可在側壁1412上、底表面1414上、及側壁1416上形成氮化鉭膜1420至約3埃至約8埃的範圍的厚度。As shown in FIG. 15D , a tantalum nitride film 1420 may be formed on the sidewalls 1412 and bottom surfaces 1414 of the trenches 1402 and on the sidewalls 1416 of the vias 1404 . The deposition apparatus 102 can deposit the tantalum nitride film 1420 directly onto the sidewalls 1412 , the bottom surface 1414 , and the sidewalls 1416 by performing an ALD operation or a CVD operation. The deposition apparatus 102 may form the tantalum nitride film 1420 on the sidewalls 1412, on the bottom surface 1414, and on the sidewalls 1416 to a thickness ranging from about 3 angstroms to about 8 angstroms.

如前文所述，非金屬鈍化層1502阻擋了或防止了氮化鉭前驅物被吸收到下金屬化層1406中。因此，非金屬鈍化層1502可阻擋或防止氮化鉭膜1420中的氮化鉭前驅物被吸收到導孔1404的底表面1418中。在一些實施方式中，在底表面1418上方形成氮化鉭膜1420的殘留量（例如，小於約5埃）。As previously described, the non-metallic passivation layer 1502 blocks or prevents the tantalum nitride precursor from being absorbed into the lower metallization layer 1406 . Therefore, the non-metal passivation layer 1502 can block or prevent the tantalum nitride precursor in the tantalum nitride film 1420 from being absorbed into the bottom surface 1418 of the via hole 1404 . In some implementations, a residual amount of tantalum nitride film 1420 is formed over bottom surface 1418 (eg, less than about 5 Angstroms).

如第15E圖所示，可在位於溝槽1402之側壁1412及底表面1414上方的氮化鉭膜1420上、以及位於導孔1404之側壁1416上方的氮化鉭膜1420上形成釕襯層1422。沉積設備102可藉由進行ALD操作或CVD操作來沉積釕襯層1422。沉積設備102可在位於溝槽1402的側壁1412及底表面1414上方的氮化鉭膜1420上、以及位於導孔1404之側壁1416上方的氮化鉭膜1420上形成厚度在約10埃至約35埃的範圍的釕襯層1422。As shown in FIG. 15E, a ruthenium liner 1422 may be formed on the tantalum nitride film 1420 over the sidewalls 1412 and bottom surface 1414 of the trench 1402 and over the tantalum nitride film 1420 over the sidewalls 1416 of the via 1404 . The deposition apparatus 102 may deposit the ruthenium liner 1422 by performing an ALD operation or a CVD operation. Deposition apparatus 102 may form a thickness of about 10 angstroms to about 35 angstroms on tantalum nitride film 1420 over sidewalls 1412 and bottom surface 1414 of trench 1402 and over tantalum nitride film 1420 over sidewalls 1416 of via 1404. A ruthenium liner 1422 in the angstrom range.

如前文所述，非金屬鈍化層1502阻擋了或防止了釕前驅物被吸收到下金屬化層1406中。因此，非金屬鈍化層1502可阻擋或防止釕襯層1422沉積在導孔1404的底表面1418上。在一些實施方式中，在底表面1418上形成釕襯層1422的殘留量（例如，小於約25埃）。As previously described, the non-metallic passivation layer 1502 blocks or prevents the ruthenium precursor from being absorbed into the lower metallization layer 1406 . Accordingly, the non-metal passivation layer 1502 may block or prevent the deposition of the ruthenium liner 1422 on the bottom surface 1418 of the via 1404 . In some embodiments, a residual amount of ruthenium liner 1422 is formed on bottom surface 1418 (eg, less than about 25 angstroms).

如第15F圖所示，在形成氮化鉭膜1420之後及在形成釕襯層1422之後，可從導孔1404的底表面1418移除鈍化層1502。電漿設備116可使用氨基電漿、氧基電漿、氫基電漿、或包括另一類型離子的電漿進行電漿處理操作，以從底表面1418移除鈍化層1502。舉例而言，電漿設備116可用氨離子、氧離子、或其他類型的離子轟擊鈍化層1502，以從底表面1418濺擊蝕刻鈍化層1502，這導致底表面1418再次變為金屬性。可進行退火以蒸發鈍化層1502的移除材料，並且可從電漿設備116的處理腔室將蒸發的材料抽真。將導孔1404的底表面1418返回金屬性特性促進了底表面1418的銅或鈷與將要填充在雙鑲嵌結構1400中的銅層1424之間的金屬對金屬黏著性，這最小化或防止了在銅層1424中形成空隙、島狀物、及其他缺陷。As shown in FIG. 15F, after formation of tantalum nitride film 1420 and after formation of ruthenium liner 1422, passivation layer 1502 may be removed from bottom surface 1418 of via 1404. Plasma device 116 may perform a plasma processing operation to remove passivation layer 1502 from bottom surface 1418 using amino plasma, oxygen-based plasma, hydrogen-based plasma, or plasma including another type of ion. For example, plasma device 116 may bombard passivation layer 1502 with ammonia ions, oxygen ions, or other types of ions to sputter etch passivation layer 1502 from bottom surface 1418, which causes bottom surface 1418 to become metallic again. An anneal may be performed to evaporate the removed material of the passivation layer 1502 , and the evaporated material may be evacuated from the processing chamber of the plasma apparatus 116 . Returning the bottom surface 1418 of the via 1404 to metallic properties promotes metal-to-metal adhesion between the copper or cobalt of the bottom surface 1418 and the copper layer 1424 to be filled in the dual damascene structure 1400, which minimizes or prevents the Voids, islands, and other defects are formed in the copper layer 1424 .

如第15G圖所示，銅層1424可形成在雙鑲嵌結構1400的剩餘體積中（例如，在導孔1404及溝槽1402中），使得雙鑲嵌結構1400填充有銅。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以使銅離子在導孔1404及溝槽1402中的釕襯層1422上方生長銅層1424。在一些實施方式中，銅層1424的形成可包括PVD操作，以在釕襯層1422上沉積銅晶種層，然後可在鍍膜操作中將剩餘的銅沉積到銅晶種層上。可藉由加熱銅層1424進行回焊操作，以允許銅層1424流動。這允許銅層1424填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在一些實施方式中，在鍍膜操作期間加熱雙鑲嵌結構1400，使得回焊操作及鍍膜操作同時進行。在一些實施方式中，可進行多次鍍膜操作及/或多次回焊操作，以用銅層1424填充雙鑲嵌結構1400。平坦化設備110可在鍍膜操作之後及回焊操作之後進行CMP操作，以平坦化銅層1424。As shown in FIG. 15G, a copper layer 1424 may be formed in the remaining volume of the dual damascene structure 1400 (eg, in the vias 1404 and trenches 1402) such that the dual damascene structure 1400 is filled with copper. The coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause copper ions to grow a copper layer 1424 over the ruthenium liner 1422 in the vias 1404 and trenches 1402 . In some embodiments, the formation of the copper layer 1424 can include a PVD operation to deposit a copper seed layer on the ruthenium liner layer 1422, and then the remaining copper can be deposited onto the copper seed layer in a plating operation. The reflow operation may be performed by heating the copper layer 1424 to allow the copper layer 1424 to flow. This allows the copper layer 1424 to fill any voids or eliminate any islands of material that may have formed during the plating operation. In some embodiments, the dual damascene structure 1400 is heated during the coating operation so that the reflow operation and the coating operation are performed simultaneously. In some embodiments, multiple coating operations and/or multiple reflow operations may be performed to fill the dual damascene structure 1400 with the copper layer 1424 . The planarization apparatus 110 may perform a CMP operation to planarize the copper layer 1424 after the plating operation and after the reflow operation.

如前文所述，提供第15A圖至第15G圖作為示例。其他示例可能與關於第15A圖至第15G圖所描述的不同。As previously mentioned, Figures 15A to 15G are provided as examples. Other examples may differ from those described with respect to Figures 15A-15G.

第16圖係本文所述的例示性雙鑲嵌結構1600的圖。雙鑲嵌結構1600可為可被包括在裝置200中的雙鑲嵌結構248的示例。雙鑲嵌結構1600可包括溝槽1602及導孔1604。導孔1604可連接到下金屬化層1606，上述下金屬化層1606可由銅、鈷、或其他類型的金屬材料所形成。下金屬化層1606可包括位於裝置200的BEOL區240中的另一雙鑲嵌結構的溝槽、位於BEOL區240中的單鑲嵌結構的導孔、位於裝置200的MEOL區230中的接觸插塞、或其他類型的內連線。可在下金屬化層1606及位於下金屬化層1606上方的介電層1610之間提供蝕刻停止層1608，以促進雙鑲嵌結構1600的形成。FIG. 16 is a diagram of an exemplary dual damascene structure 1600 described herein. Dual damascene structure 1600 may be an example of dual damascene structure 248 that may be included in device 200 . The dual damascene structure 1600 may include trenches 1602 and vias 1604 . Vias 1604 may be connected to lower metallization layer 1606, which may be formed of copper, cobalt, or other types of metal materials. The lower metallization layer 1606 may include trenches of another dual damascene structure in the BEOL region 240 of the device 200 , vias of a single damascene structure in the BEOL region 240 , contact plugs in the MEOL region 230 of the device 200 , or other types of interconnects. An etch stop layer 1608 may be provided between the lower metallization layer 1606 and the dielectric layer 1610 overlying the lower metallization layer 1606 to facilitate formation of the dual damascene structure 1600 .

雙鑲嵌結構1600可形成在介電層1610中並且穿過蝕刻停止層1608。溝槽1602可包括側壁1612及底表面1614。導孔1604也可包括側壁1616及底表面1618。側壁1612、底表面1614、及側壁1616可包括介電層1610圍繞雙鑲嵌結構1600的部分。The dual damascene structure 1600 may be formed in the dielectric layer 1610 and through the etch stop layer 1608 . The trench 1602 may include sidewalls 1612 and a bottom surface 1614 . The vias 1604 may also include sidewalls 1616 and a bottom surface 1618 . Sidewall 1612 , bottom surface 1614 , and sidewall 1616 may include portions of dielectric layer 1610 surrounding dual damascene structure 1600 .

導孔1604的底表面1618可包括位於導孔1604之下的下金屬化層1606的一部分。在一些實施方式中，導孔1604為電路導孔。在這些實施方式中，導孔1604的底表面1618的寬度對於M0層導孔而言可在約8nm至約12nm的範圍、或者對於M1至M3層導孔（例如，M0層上方的金屬化層）而言可在約10nm至約22nm的範圍。在一些實施方式中，導孔1604為密封環導孔。在這些實施方式中，導孔1604的底表面1618的寬度可在約100nm至約180nm的範圍。Bottom surface 1618 of via 1604 may include a portion of lower metallization layer 1606 underlying via 1604 . In some embodiments, vias 1604 are circuit vias. In these embodiments, the width of the bottom surface 1618 of the via 1604 may be in the range of about 8 nm to about 12 nm for M0 layer vias, or for M1 to M3 layer vias (eg, the metallization layer over the M0 layer) ) can be in the range of about 10 nm to about 22 nm. In some embodiments, the pilot hole 1604 is a seal ring pilot hole. In these embodiments, the width of the bottom surface 1618 of the via 1604 may range from about 100 nm to about 180 nm.

氮化鉭（tantalum nitride, TaN）膜1620可被包括在雙鑲嵌結構1600的側壁1612上、底表面1614上、及側壁1616上。氮化鉭膜1620可促進周圍介電層1610及釕 （ruthenium, Ru） 襯層1622之間的黏著性，上述釕襯層1622被包括在雙鑲嵌結構 1600 的側壁 1612、底表面 1614 、及側壁 1616 上方及氮化鉭膜 1620 上。因此，氮化鉭膜 1620 減少了及/或防止了在釕襯層1622的沉積期間在釕襯層1622中不連續性的形成。A tantalum nitride (TaN) film 1620 may be included on the sidewalls 1612 , the bottom surface 1614 , and the sidewalls 1616 of the dual damascene structure 1600 . The tantalum nitride film 1620 promotes adhesion between the surrounding dielectric layer 1610 and the ruthenium (Ru) liner 1622 included in the sidewalls 1612 , the bottom surface 1614 , and the sidewalls of the dual damascene structure 1600 1616 and over the tantalum nitride film 1620. Thus, the tantalum nitride film 1620 reduces and/or prevents the formation of discontinuities in the ruthenium liner 1622 during the deposition of the ruthenium liner 1622.

釕襯層1622可用作銅 （copper, Cu） 層1624的擴散阻障，上述銅層1624填充在位於釕襯層1622上方的雙鑲嵌結構1600中（例如，在溝槽1602中及導孔1604中）。因此，釕襯層1622減少了或防止了銅離子擴散到介電層1610及位於介電層1610下方的層中。再者，因為包含氮化鉭膜1620主要是為了用作黏著促進劑，而不是銅擴散阻障層，所以釕襯層1622允許氮化鉭膜1620變薄（例如，允許使用更薄的氮化鉭膜）。因為釕的片電阻低於氮化鉭的片電阻，所以氮化鉭膜1620的減小的厚度降低了雙鑲嵌結構1600的片電阻。薄氮化鉭膜1620及釕襯層1622的組合為雙鑲嵌結構1600提供了足夠的銅擴散阻障功能。The ruthenium liner 1622 may serve as a diffusion barrier for the copper (Cu) layer 1624 that fills the dual damascene structure 1600 over the ruthenium liner 1622 (eg, in the trenches 1602 and vias 1604 ). middle). Thus, the ruthenium liner 1622 reduces or prevents the diffusion of copper ions into the dielectric layer 1610 and the layers below the dielectric layer 1610 . Furthermore, since the tantalum nitride film 1620 is included primarily to serve as an adhesion promoter, rather than a copper diffusion barrier, the ruthenium liner 1622 allows the tantalum nitride film 1620 to be thinned (eg, allowing the use of thinner nitrides) tantalum film). The reduced thickness of the tantalum nitride film 1620 reduces the sheet resistance of the dual damascene structure 1600 because the sheet resistance of ruthenium is lower than that of tantalum nitride. The combination of the thin tantalum nitride film 1620 and the ruthenium liner 1622 provides sufficient copper diffusion barrier function for the dual damascene structure 1600 .

在一些情況下，當藉由例如CVD的自下而上（bottom-up）沉積製程形成釕襯層1622時，可能難以控制釕襯層1622的厚度。這可增加雙鑲嵌結構1600的片電阻及/或接觸電阻。因此，可藉由包括PVD（例如，濺鍍）操作及CVD操作的兩部分（two-part）製程來形成釕襯層1622，藉由PVD操作以沉積釕襯層1622的第一部分，藉由CVD操作以在第一部分上沉積釕襯層1622的第二部分。兩部分製程可允許在薄氮化鉭膜1620上形成更薄的釕襯層1622（例如，相較於僅有CVD沉積的釕襯層1622），這增加了雙鑲嵌結構1600中的體積（特別是在導孔 1604 中），其可填充銅同時仍然提供足夠的銅擴散阻障功能。In some cases, when the ruthenium liner 1622 is formed by a bottom-up deposition process such as CVD, it may be difficult to control the thickness of the ruthenium liner 1622. This can increase the sheet resistance and/or contact resistance of the dual damascene structure 1600 . Accordingly, the ruthenium liner 1622 can be formed by a two-part process including a PVD (eg, sputtering) operation and a CVD operation, the first portion of the ruthenium liner 1622 is deposited by the PVD operation, and the ruthenium liner 1622 is deposited by CVD Operates to deposit a second portion of the ruthenium liner 1622 over the first portion. The two-part process may allow a thinner ruthenium liner 1622 to be formed on the thin tantalum nitride film 1620 (eg, compared to a CVD-only deposited ruthenium liner 1622), which increases the volume in the dual damascene structure 1600 (especially is in via 1604), which can be filled with copper while still providing sufficient copper diffusion barrier function.

位於側壁1612上、底表面1614上、及側壁1616上的氮化鉭膜1620的厚度可在約5埃（以最小化或防止在氮化鉭膜1620中及釕襯層1622中的不連續性）至約10埃（以實現雙鑲嵌結構1600的低片電阻）的範圍。作為上述兩部分製程的結果，位於溝槽1602的底表面1614上及/或位於導孔1604的底表面1618上的釕襯層1622的厚度，相對於位於溝槽1602的側壁1612上、及位於導孔1604的側壁1616上的釕襯層1622的厚度而言可更大。具體而言，PVD操作可為非共形的，並且可導致釕沉積在底表面1614及/或底表面1618上的量相對於釕沉積在側壁1612及側壁1616的量而言更多。在一些實施方式中，位於導孔1604的底表面1618上的釕襯層1622的厚度可與位於側壁1612及/或側壁1616上的釕襯層1622的厚度相同，這取決於導孔1604的寬度（例如，導孔1604越寬，位於底表面1618上的釕襯層1622與位於側壁1612及側壁1616上的釕襯層1622之間的厚度差異越大）。The thickness of the tantalum nitride film 1620 on the sidewalls 1612, on the bottom surface 1614, and on the sidewalls 1616 may be about 5 angstroms (to minimize or prevent discontinuities in the tantalum nitride film 1620 and in the ruthenium liner 1622 ) to about 10 Angstroms (to achieve the low sheet resistance of the dual damascene structure 1600). As a result of the above two-part process, the thickness of the ruthenium liner 1622 on the bottom surface 1614 of the trench 1602 and/or on the bottom surface 1618 of the via 1604 is relative to the thickness of the ruthenium liner 1622 on the sidewall 1612 of the trench 1602 and on the bottom surface 1618 of the via The thickness of the ruthenium liner 1622 on the sidewalls 1616 of the vias 1604 may be greater. In particular, PVD operations may be non-conformal and may result in a greater amount of ruthenium deposited on bottom surface 1614 and/or bottom surface 1618 relative to the amount of ruthenium deposited on sidewalls 1612 and 1616 . In some embodiments, the thickness of the ruthenium liner 1622 on the bottom surface 1618 of the via 1604 can be the same as the thickness of the ruthenium liner 1622 on the sidewalls 1612 and/or the sidewalls 1616, depending on the width of the via 1604 (For example, the wider the via 1604, the greater the difference in thickness between the ruthenium liner 1622 on the bottom surface 1618 and the ruthenium liner 1622 on the sidewalls 1612 and 1616).

作為示例，位於側壁1612上及位於側壁1616上的釕襯層1622的厚度可在約15埃至約35埃的範圍（例如，以最小化及/或防止釕襯層1622中的不連續性，並提供足夠的銅擴散阻障），位於溝槽1602的底表面1614上的釕襯層1622的厚度可在約20埃至約55埃的範圍，並且位於導孔1604的底表面1618上的釕襯層1622的厚度對於M1層電路導孔而言可在約15埃至約35埃的範圍。作為另一個示例，位於側壁1612上及位於側壁1616上的釕襯層1622的厚度可在約20埃至約45埃的範圍，並且位於底表面1614上及位於底表面1618上的釕襯層1622的厚度對於M1層密封環而言可在約20埃至約55埃的範圍。As an example, the thickness of the ruthenium liner 1622 on the sidewall 1612 and on the sidewall 1616 may range from about 15 angstroms to about 35 angstroms (eg, to minimize and/or prevent discontinuities in the ruthenium liner 1622, and provide a sufficient copper diffusion barrier), the thickness of the ruthenium liner 1622 on the bottom surface 1614 of the trench 1602 may range from about 20 angstroms to about 55 angstroms, and the ruthenium on the bottom surface 1618 of the via 1604 The thickness of the liner 1622 may range from about 15 angstroms to about 35 angstroms for the M1 layer circuit vias. As another example, the thickness of the ruthenium liner 1622 on the sidewalls 1612 and on the sidewalls 1616 may range from about 20 angstroms to about 45 angstroms, and the ruthenium liner layers 1622 on the bottom surface 1614 and on the bottom surface 1618 The thickness of A may range from about 20 angstroms to about 55 angstroms for the M1 layer seal ring.

作為另一個示例，位於側壁1612上及位於側壁1616上的釕襯層1622的厚度可在約5埃至約15埃的範圍（例如，以最小化及/或防止釕襯層1622中的不連續性，並提供足夠的銅擴散阻障），位於溝槽1602的底表面1614上的釕襯層1622的厚度可在約20埃至約55埃的範圍，並且位於導孔1604的底表面1618上的釕襯層1622的厚度可在對於M2層電路導孔而言可在約20埃至約40埃的範圍。作為另一個示例，位於側壁1612上及位於側壁1616上的釕襯層1622的厚度可在約20埃至約45埃的範圍，並且位於底表面1614上及位於底表面1618上的釕襯層1622的厚度對於M2層密封環而言可在約20埃至約55埃的範圍。As another example, the thickness of the ruthenium liner 1622 on the sidewall 1612 and on the sidewall 1616 may range from about 5 angstroms to about 15 angstroms (eg, to minimize and/or prevent discontinuities in the ruthenium liner 1622 ) and provide sufficient copper diffusion barrier), the thickness of the ruthenium liner 1622 on the bottom surface 1614 of the trench 1602 may range from about 20 angstroms to about 55 angstroms and on the bottom surface 1618 of the via 1604 The thickness of the ruthenium liner 1622 may be in the range of about 20 angstroms to about 40 angstroms for M2 layer circuit vias. As another example, the thickness of the ruthenium liner 1622 on the sidewalls 1612 and on the sidewalls 1616 may range from about 20 angstroms to about 45 angstroms, and the ruthenium liner layers 1622 on the bottom surface 1614 and on the bottom surface 1618 The thickness of A may range from about 20 angstroms to about 55 angstroms for an M2 layer seal ring.

作為示例，位於側壁1612上及位於側壁1616上的釕襯層1622的厚度可在約5埃至約15埃的範圍（例如，以最小化及/或防止釕襯層1622中的不連續性，並提供足夠的銅擴散阻障），位於溝槽1602的底表面1614上的釕襯層1622的厚度可在約20埃至約55埃的範圍，並且位於導孔1604的底表面1618上的釕襯層1622的厚度對於M3層電路導孔而言可在約15埃至約35埃的範圍。作為示例，位於側壁1612上及位於側壁1616上的釕襯層1622的厚度可在約20埃至約45埃的範圍，並且位於底表面1614上及位於底表面1618上的釕襯層1622的厚度對於M3層密封環而言可在約20埃至約55埃的範圍。As an example, the thickness of the ruthenium liner 1622 on the sidewall 1612 and on the sidewall 1616 may range from about 5 angstroms to about 15 angstroms (eg, to minimize and/or prevent discontinuities in the ruthenium liner 1622, and provide a sufficient copper diffusion barrier), the thickness of the ruthenium liner 1622 on the bottom surface 1614 of the trench 1602 may range from about 20 angstroms to about 55 angstroms, and the ruthenium on the bottom surface 1618 of the via 1604 The thickness of the liner 1622 may range from about 15 angstroms to about 35 angstroms for the M3 layer circuit vias. As an example, the thickness of the ruthenium liner 1622 on the sidewall 1612 and on the sidewall 1616 may range from about 20 angstroms to about 45 angstroms, and the thickness of the ruthenium liner layer 1622 on the bottom surface 1614 and on the bottom surface 1618 It may be in the range of about 20 angstroms to about 55 angstroms for the M3 layer seal ring.

在一些實施方式中，如第16圖中的示例所示，可形成氮化鉭膜1620，使得導孔1604的底表面1618省略氮化鉭膜1620。在這些實施方式中，釕襯層1622被包括直接位於導孔1604的底表面1618上，這為雙鑲嵌結構1600提供了低接觸電阻。在一些實施方式中，在形成氮化鉭膜 1620 期間，氮化鉭膜1620的殘留量形成在導孔1604的底表面1618上方。在這些實施方式中，釕襯層1622形成在位於導孔1604的底表面1618上方的氮化鉭膜 1620的殘留量上。在氮化鉭膜1620的殘留量被包括在底表面1618上的實施方式中，位於底表面1618上的氮化鉭膜1620的厚度可大於0埃並且小於約 8埃，以最小化氮化鉭對雙鑲嵌結構1600的接觸電阻的影響。In some implementations, as shown in the example of FIG. 16, the tantalum nitride film 1620 may be formed such that the bottom surface 1618 of the via 1604 omits the tantalum nitride film 1620. In these embodiments, ruthenium liner 1622 is included directly on bottom surface 1618 of via 1604, which provides low contact resistance for dual damascene structure 1600. In some embodiments, during the formation of the tantalum nitride film 1620, a residual amount of the tantalum nitride film 1620 is formed over the bottom surface 1618 of the via hole 1604. In these embodiments, a ruthenium liner 1622 is formed over the remainder of the tantalum nitride film 1620 over the bottom surface 1618 of the via 1604. In embodiments where the residual amount of tantalum nitride film 1620 is included on bottom surface 1618, the thickness of tantalum nitride film 1620 on bottom surface 1618 may be greater than 0 angstroms and less than about 8 angstroms to minimize tantalum nitride Influence on the contact resistance of the dual damascene structure 1600 .

如前文所述，提供第16圖作為示例。其他示例可能與關於第16圖所描述的不同。As previously mentioned, Figure 16 is provided as an example. Other examples may differ from those described with respect to FIG. 16 .

第17A圖至第17H圖係本文所述的例示性實施方式1700的圖。例示性實施方式1700可為形成第16圖的雙鑲嵌結構1600的示例。在一些實施方式中，半導體製程設備102-116中的一個或多個進行結合第17A圖至第17H圖所述的製程、及/或操作中的一個或多個。如第17A圖所示，雙鑲嵌結構1600可形成在位於下金屬化層1606上方的介電層1610中。蝕刻停止層1608可被包括在介電層1610及下金屬化層1606之間，以促進形成介電層1610中的雙鑲嵌結構1600。17A-17H are diagrams of an exemplary embodiment 1700 described herein. The exemplary embodiment 1700 may be an example of forming the dual damascene structure 1600 of FIG. 16 . In some embodiments, one or more of the semiconductor process equipment 102-116 performs one or more of the processes, and/or operations described in connection with Figures 17A-17H. As shown in FIG. 17A , a dual damascene structure 1600 may be formed in a dielectric layer 1610 overlying a lower metallization layer 1606 . An etch stop layer 1608 may be included between the dielectric layer 1610 and the lower metallization layer 1606 to facilitate formation of the dual damascene structure 1600 in the dielectric layer 1610 .

如第17B圖所示，可在介電層1610中形成雙鑲嵌結構1600的溝槽1602及導孔1604。如前文所述，半導體製程設備102-116中的一個或多個可藉由進行導孔先製雙鑲嵌製程、溝槽先製雙鑲嵌製程、或另一種雙鑲嵌製程在介電層1610中形成溝槽1602及導孔1604。，As shown in FIG. 17B , trenches 1602 and vias 1604 of the dual damascene structure 1600 may be formed in the dielectric layer 1610 . As previously described, one or more of the semiconductor process tools 102-116 may be formed in the dielectric layer 1610 by performing a via-first dual damascene process, a trench-first dual damascene process, or another dual damascene process Trenches 1602 and vias 1604 . ,

如第17C圖所示，可修飾導孔1604的底表面1618，以抵抗（resist）或防止在底表面1618上形成氮化鉭膜1620及釕襯層1622。具體而言，預處理設備114可進行預處理操作，以使導孔1604的底表面1618變為非金屬性。預處理操作可包括將導孔1604的底表面1618浸入苯並三唑（benzotriazole, BTA）一段時間，以在底表面1618上形成非金屬鈍化層1702。底表面1618可浸入BTA中，這導致下金屬化層1606的金屬材料（例如，銅）及BTA之間的錯合物形成鈍化層1702。鈍化層1702中的銅-BTA錯合物防止了或阻擋了氮化鉭及釕前驅物被吸收到導孔1604的底表面1618（例如，下金屬化層1606）中。As shown in FIG. 17C , the bottom surface 1618 of the via hole 1604 may be modified to resist or prevent the formation of the tantalum nitride film 1620 and the ruthenium liner 1622 on the bottom surface 1618 . Specifically, the pretreatment apparatus 114 may perform a pretreatment operation to render the bottom surface 1618 of the via hole 1604 non-metallic. The pretreatment operation may include dipping the bottom surface 1618 of the via 1604 into benzotriazole (BTA) for a period of time to form a non-metallic passivation layer 1702 on the bottom surface 1618 . The bottom surface 1618 may be immersed in the BTA, which results in a complex between the metal material (eg, copper) of the lower metallization layer 1606 and the BTA to form the passivation layer 1702 . The copper-BTA complex in passivation layer 1702 prevents or blocks tantalum nitride and ruthenium precursors from being absorbed into bottom surface 1618 (eg, lower metallization layer 1606 ) of via 1604 .

如第17D圖所示，氮化鉭膜1620可形成在溝槽1602的側壁1612及底表面1614上、以及導孔1604的側壁1616上。沉積設備102可藉由進行ALD操作或 CVD 操作將氮化鉭膜1620直接沉積到側壁1612、底表面1614、及側壁1616上。沉積設備102可在側壁1612上、底表面1614上、及側壁1616上形成氮化鉭膜1620至約5埃至約10埃的範圍的厚度。As shown in FIG. 17D , a tantalum nitride film 1620 may be formed on the sidewalls 1612 and bottom surfaces 1614 of the trenches 1602 and on the sidewalls 1616 of the vias 1604 . The deposition apparatus 102 can deposit the tantalum nitride film 1620 directly onto the sidewalls 1612, the bottom surface 1614, and the sidewalls 1616 by performing an ALD operation or a CVD operation. The deposition apparatus 102 may form the tantalum nitride film 1620 on the sidewalls 1612, on the bottom surface 1614, and on the sidewalls 1616 to a thickness ranging from about 5 angstroms to about 10 angstroms.

如前文所述，非金屬鈍化層1702阻擋了或防止了氮化鉭前驅物被吸收到下金屬化層1606中。因此，非金屬鈍化層1702可阻擋或防止氮化鉭膜1620中的氮化鉭前驅物被吸收到導孔1604的底表面1618中。在一些實施方式中，在底表面1618上方形成氮化鉭膜1620的殘留量 （例如，小於約8埃）。As previously described, the non-metallic passivation layer 1702 blocks or prevents the tantalum nitride precursor from being absorbed into the lower metallization layer 1606 . Accordingly, the non-metallic passivation layer 1702 can block or prevent the tantalum nitride precursor in the tantalum nitride film 1620 from being absorbed into the bottom surface 1618 of the via 1604 . In some embodiments, a residual amount of tantalum nitride film 1620 is formed over bottom surface 1618 (eg, less than about 8 Angstroms).

如第17E圖所示，在形成氮化鉭膜1620之後，可從導孔1604的底表面1618移除鈍化層1702。電漿設備116可使用氨基電漿、氧基電漿、氫基電漿、或包括另一類型離子的電漿進行電漿處理操作，以從底表面1618移除鈍化層 1702。舉例而言，電漿設備116可用氨離子、氧離子、或其他類型的離子轟擊鈍化層1702，以從底表面1618濺擊蝕刻鈍化層1702，這導致底表面1618再次變為金屬性。可進行退火以蒸發鈍化層 1702 的移除材料，並且可從電漿設備 116 的處理腔室將蒸發的材料抽真空。將導孔1604的底表面1618返回金屬性特性促進了底表面1618的銅或鈷與將要填充在雙鑲嵌結構1600中的釕襯層1622之間的金屬對金屬（metal-to-metal）黏著性，這最小化或防止了在釕襯層1622中形成空隙、島狀物、及其他缺陷。As shown in FIG. 17E, after the tantalum nitride film 1620 is formed, the passivation layer 1702 may be removed from the bottom surface 1618 of the via hole 1604. Plasma device 116 may perform a plasma processing operation to remove passivation layer 1702 from bottom surface 1618 using amino plasma, oxygen-based plasma, hydrogen-based plasma, or plasma including another type of ion. For example, plasma device 116 may bombard passivation layer 1702 with ammonia ions, oxygen ions, or other types of ions to sputter etch passivation layer 1702 from bottom surface 1618, which causes bottom surface 1618 to become metallic again. An anneal may be performed to evaporate the removed material of the passivation layer 1702, and the evaporated material may be evacuated from the processing chamber of the plasma apparatus 116. Returning the bottom surface 1618 of the via 1604 to metallic properties promotes metal-to-metal adhesion between the copper or cobalt of the bottom surface 1618 and the ruthenium liner 1622 to be filled in the dual damascene structure 1600 , which minimizes or prevents the formation of voids, islands, and other defects in the ruthenium liner 1622.

如第17F圖所示，可在位於溝槽1602的側壁1612及底表面1614上方的氮化鉭膜1620上、以及在位於導孔1604的側壁1616上方的氮化鉭膜1620上形成釕襯層1622的第一部分1704。再者，釕襯層1622的第一部分1704可直接形成在導孔1604的底表面1618上（或在底表面1618上方的任何殘留的氮化鉭上）。沉積設備102可藉由進行PVD操作（例如，在電漿處理操作之後）來沉積釕襯層1622的第一部分1704。As shown in FIG. 17F, a ruthenium liner may be formed on the tantalum nitride film 1620 over the sidewalls 1612 and bottom surface 1614 of the trench 1602 and over the tantalum nitride film 1620 over the sidewalls 1616 of the via 1604 1704 of the first part of 1622. Again, the first portion 1704 of the ruthenium liner 1622 may be formed directly on the bottom surface 1618 of the via 1604 (or on any remaining tantalum nitride above the bottom surface 1618). The deposition apparatus 102 may deposit the first portion 1704 of the ruthenium liner 1622 by performing a PVD operation (eg, after a plasma processing operation).

如第17G圖所示，可在位於溝槽1602的側壁1612及底表面1614上方的第一部分1704上、位於導孔1604的側壁1616上方的第一部分1704上、並且在導孔1604的底表面1618上方的釕襯層1622的第一部分1704上形成釕襯層1622的第二部分（例如，剩餘部分）。沉積設備102可藉由進行ALD操作或 CVD 操作來沉積釕襯層1622的剩餘部分。As shown in FIG. 17G , there may be on the first portion 1704 above the sidewalls 1612 and bottom surface 1614 of the trench 1602 , on the first portion 1704 above the sidewall 1616 of the via 1604 , and on the bottom surface 1618 of the via 1604 A second portion (eg, the remainder) of the ruthenium liner 1622 is formed over the first portion 1704 of the ruthenium liner 1622 overlying. The deposition apparatus 102 may deposit the remainder of the ruthenium liner 1622 by performing an ALD operation or a CVD operation.

如第17H圖所示，銅層1624可形成在雙鑲嵌結構1600的剩餘體積中（例如，在導孔1604及溝槽1602中），使得雙鑲嵌結構1600填充有銅。鍍膜設備112可進行鍍膜操作（例如，電鍍操作或無電鍍操作），以使銅離子在導孔1604中及溝槽1602中的釕襯層1622上方生長銅層1624。在一些實施方式中，銅層1624的形成可包括PVD操作，以在釕襯層1622上沉積銅晶種層，然後可在鍍膜操作中將剩餘的銅沉積到銅晶種層上。可藉由加熱銅層1624進行回焊操作，以允許銅層1624流動。這允許銅層1624填充任何空隙或消除在鍍膜操作期間可能已經形成的任何材料島狀物。在一些實施方式中，在鍍膜操作期間加熱雙鑲嵌結構1600，使得回焊操作及鍍膜操作同時進行。在一些實施方式中，可進行多次鍍膜操作及/或多次回焊操作，以用銅層1624填充雙鑲嵌結構1600。平坦化設備110可在鍍膜操作之後及回焊操作之後進行CMP操作，以將銅層1624平坦化。As shown in FIG. 17H, a copper layer 1624 may be formed in the remaining volume of the dual damascene structure 1600 (eg, in the vias 1604 and trenches 1602) such that the dual damascene structure 1600 is filled with copper. Coating apparatus 112 may perform a coating operation (eg, an electroplating operation or an electroless plating operation) to cause copper ions to grow copper layer 1624 in via 1604 and over ruthenium liner 1622 in trench 1602 . In some embodiments, the formation of the copper layer 1624 can include a PVD operation to deposit a copper seed layer on the ruthenium liner layer 1622, and then the remaining copper can be deposited onto the copper seed layer in a plating operation. The reflow operation may be performed by heating the copper layer 1624 to allow the copper layer 1624 to flow. This allows the copper layer 1624 to fill any voids or eliminate any islands of material that may have formed during the plating operation. In some embodiments, the dual damascene structure 1600 is heated during the coating operation so that the reflow operation and the coating operation are performed simultaneously. In some embodiments, multiple coating operations and/or multiple reflow operations may be performed to fill the dual damascene structure 1600 with the copper layer 1624 . The planarization apparatus 110 may perform a CMP operation to planarize the copper layer 1624 after the plating operation and after the reflow operation.

如前文所述，提供第17A圖至第17H圖作為示例。其他示例可能與關於第17A圖至第17H圖所描述的不同。As previously mentioned, Figures 17A to 17H are provided as examples. Other examples may differ from those described with respect to Figures 17A-17H.

第18圖係裝置1800的例示性元件的圖。在一些實施方式中，半導體製程設備102-116及/或晶圓/晶粒運輸設備118中的一個或多個可包括一個或多個裝置1800及/或裝置1800的一個或多個元件。如第18圖所示，裝置1800可包括匯流排（bus）1810、處理器1820、記憶體1830、存儲元件1840、輸入元件1850、輸出元件1860、及通訊元件 1870。FIG. 18 is a diagram of exemplary elements of device 1800. FIG. In some embodiments, one or more of the semiconductor processing equipment 102 - 116 and/or the wafer/die transport equipment 118 may include one or more of the apparatus 1800 and/or one or more elements of the apparatus 1800 . As shown in FIG. 18 , the device 1800 may include a bus 1810 , a processor 1820 , a memory 1830 , a storage element 1840 , an input element 1850 , an output element 1860 , and a communication element 1870 .

匯流排1810包括允許裝置1800的元件之間的有線及/或無線通訊的元件。處理器1820包括中央處理單元（central processing unit）、圖形處理單元（graphics processing unit）、微處理器、控制器、微控制器、數位訊號處理器（digital signal processor）、場域可程式化邏輯閘陣列（field-programmable gate array）、特殊應用積體電路（application-specific integrated circuit）、及/或其他類型的處理元件。處理器1820以硬體（hardware）、韌體（firmware）、及/或硬體及軟體（software）的組合來實施。在一些實施方式中，處理器1820包括一或多個能夠被編程以進行功能的處理器。記憶體1830包括隨機存取記憶體（random access memory）、唯讀記憶體（read only memory）、及/或另一種類型的記憶體（例如，快閃記憶體、磁記憶體（magnetic memory）、及/或光記憶體（optical memory））。Bus bar 1810 includes elements that allow wired and/or wireless communication between elements of device 1800 . The processor 1820 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, and a field programmable logic gate Field-programmable gate arrays, application-specific integrated circuits, and/or other types of processing elements. The processor 1820 is implemented in hardware, firmware, and/or a combination of hardware and software. In some implementations, the processor 1820 includes one or more processors that can be programmed to function. The memory 1830 includes random access memory, read only memory, and/or another type of memory (eg, flash memory, magnetic memory, and/or optical memory).

存儲元件1840存儲與裝置1800操作有關的訊息及/或軟體。舉例而言，存儲元件1840可包括硬碟（hard disk）驅動器（drive）、磁碟（magnetic disk）驅動器、光碟（optical disk）驅動器、固態硬碟（solid state drive）、光碟（compact disc）、數位化多功能光盤（digital versatile disc）、及/或其他類型的非暫時性電腦可讀介質（non-transitory computer-readable medium）。輸入元件1850允許裝置1800能夠接收輸入，例如用戶輸入及/或感測到的輸入。舉例而言，輸入元件1850可包括觸控螢幕顯示器、鍵盤、小鍵盤（keyboard）、鼠標（mouse）、按鈕、麥克風、開關、傳感器、全球定位系統（global positioning system）元件、加速度計（accelerometer）、陀螺儀（gyroscope）、及/或致動器（actuator）。輸出元件1860使裝置1800能夠提供輸出，例如經由顯示器、揚聲器、及/或一個或多個發光二極體。通訊元件1870使裝置1800能夠與其他裝置通訊，例如藉由有線連接及/或無線連接。舉例而言，通訊元件1870可包括接收器、發送器、收發器（transceiver）、調製解調器（modem）、網絡接口卡（network interface card）、及/或天線。The storage element 1840 stores information and/or software related to the operation of the device 1800 . For example, the storage element 1840 may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state drive, a compact disc, A digital versatile disc, and/or other types of non-transitory computer-readable media. Input element 1850 allows device 1800 to receive input, such as user input and/or sensed input. Input elements 1850 may include, for example, touch screen displays, keyboards, keyboards, mice, buttons, microphones, switches, sensors, global positioning system elements, accelerometers , gyroscope, and/or actuator. Output element 1860 enables device 1800 to provide output, eg, via a display, speakers, and/or one or more light emitting diodes. Communication element 1870 enables device 1800 to communicate with other devices, such as through wired and/or wireless connections. For example, communication elements 1870 may include receivers, transmitters, transceivers, modems, network interface cards, and/or antennas.

裝置1800可進行本文描述的一個或多個製程。舉例而言，非暫時性電腦可讀介質（non-transitory computer-readable medium）（例如，記憶體 1830 及/或存儲元件 1840）可存儲一組指令（例如，一個或多個指令、代碼、軟體代碼、及/或程序代碼），以供處理器1820進行。處理器1820可進行一組指令，以進行本文描述的一個或多個製程。在一些實施方式中，由一個或多個處理器1820進行的一組指令，使一個或多個處理器1820及/或裝置1800進行本文描述的一個或多個製程。在一些實施方式中，可使用硬體電路代替指令或與指令結合來進行本文描述的一或多個製程。因此，本文描述的實施方式不限於硬體電路及軟體的任何特定組合。Device 1800 may perform one or more of the processes described herein. For example, a non-transitory computer-readable medium (eg, memory 1830 and/or storage element 1840) may store a set of instructions (eg, one or more instructions, code, software code, and/or program code) for processor 1820 to execute. The processor 1820 may execute a set of instructions to perform one or more of the processes described herein. In some embodiments, a set of instructions performed by one or more processors 1820 cause one or more processors 1820 and/or device 1800 to perform one or more of the processes described herein. In some implementations, hardware circuitry may be used in place of or in combination with instructions to perform one or more of the processes described herein. Accordingly, the embodiments described herein are not limited to any specific combination of hardware circuitry and software.

第18圖中所示之元件的數量及設置作為示例。裝置1800可包括相較於第18圖所示的元件而言更多的元件、更少的元件、不同的元件、或設置不同的元件。額外地或替代地，裝置1800的一組元件（例如，一或多個元件）可進行所述由裝置 1800的另一組元件進行的一或多個功能。The number and arrangement of components shown in Figure 18 are examples. Device 1800 may include more elements, fewer elements, different elements, or a different arrangement of elements than those shown in FIG. 18 . Additionally or alternatively, one group of elements (eg, one or more elements) of device 1800 may perform one or more functions described as performed by another group of elements of device 1800.

第19圖是與形成半導體結構相關聯的例示性製程1900的流程圖。在一些實施方式中，第19圖的一個或多個製程方框可由一個或多個半導體製程設備（例如，半導體製程設備102-116中的一個或多個）進行。額外地或替代地，第19圖的一個或多個製程方框可由裝置1800的一個或多個元件進行，上述裝置1800例如處理器1820、記憶體1830、存儲元件1840、輸入元件1850、輸出元件1860、及/或通訊元件 1870。19 is a flow diagram of an exemplary process 1900 associated with forming a semiconductor structure. In some embodiments, one or more of the process blocks of FIG. 19 may be performed by one or more semiconductor process tools (eg, one or more of semiconductor process tools 102-116). Additionally or alternatively, one or more of the process blocks of Figure 19 may be performed by one or more elements of an apparatus 1800 such as processor 1820, memory 1830, storage element 1840, input element 1850, output element 1860, and/or communication element 1870.

如第19圖所示，製程1900可包括在裝置的一個或多個介電層中形成內連線，其中內連線包括導孔及位於導孔上方的溝槽（方框1910）。舉例而言，如前文所述，半導體製程設備102-116中的一個或多個可在裝置（例如，裝置200）的一個或多個介電層（例如，介電層244、710、910及/或1110）中形成內連線（例如，雙鑲嵌結構248、700、900、及/或1100）。在一些實施方式中，內連線包括導孔（例如，導孔704、904、及/或1104）及位於導孔上方的溝槽（例如，溝槽702、902、及/或1102）。As shown in FIG. 19, process 1900 may include forming interconnects in one or more dielectric layers of the device, wherein the interconnects include vias and trenches over the vias (block 1910). For example, as previously described, one or more of the semiconductor process equipment 102-116 may be in one or more dielectric layers (eg, dielectric layers 244, 710, 910, and 244) of a device (eg, device 200). Interconnects (eg, dual damascene structures 248, 700, 900, and/or 1100) are formed in 1110). In some implementations, the interconnect includes vias (eg, vias 704, 904, and/or 1104) and trenches (eg, trenches 702, 902, and/or 1102) over the vias.

如第19圖進一步所示，製程1900可包括在導孔的側壁上及溝槽的側壁上形成氧化鋅矽（ZnSiO x）阻障（方框1920）。舉例而言，如前文所述，半導體製程設備102-116中的一個或多個可在側壁（例如，側壁716、916、及/或1116）上、以及在溝槽的側壁（例如，側壁712、912、及/或1112）上形成氧化鋅矽（zinc silicon oxide, ZnSiO x）阻障（例如，氧化鋅矽阻障720、920、及/或1120）。 As further shown in FIG. 19, the process 1900 may include forming zinc oxide silicon ( ZnSiOx ) barriers on the sidewalls of the vias and the sidewalls of the trenches (block 1920). For example, as previously described, one or more of the semiconductor process equipment 102 - 116 may be on sidewalls (eg, sidewalls 716 , 916 , and/or 1116 ), as well as on the sidewalls of the trenches (eg, sidewall 712 ) Zinc silicon oxide (ZnSiO x ) barriers (eg, zinc oxide silicon barriers 720 , 920 , and/or 1120 ) are formed thereon.

如第19圖進一步所示，如前文所述，製程1900可包括用銅（copper, Cu）層填充導孔及溝槽（方框1930）。舉例而言，一個或多個半導體製程設備可用銅（copper, Cu）層（例如，銅層722、922、及/或1126）填充導孔及溝槽。As further shown in FIG. 19, as previously described, the process 1900 may include filling the vias and trenches with a copper (Cu) layer (block 1930). For example, one or more semiconductor processing equipment may fill vias and trenches with copper (Cu) layers (eg, copper layers 722, 922, and/or 1126).

製程1900可包括額外的實施方式，例如後文描述的及/或結合本文別處描述的一個或多個其他製程的任何單一實施方式或實施方式的任何組合。Process 1900 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in conjunction with one or more other processes described elsewhere herein.

在第一實施方式中，用銅層填充導孔及溝槽的步驟包括進行原子層沉積（atomic layer deposition, ALD）操作，以沉積銅晶種層（例如，銅晶種層802）於溝槽的側壁上方、導孔的側壁上方、及導孔的底表面上方；及進行電鍍操作，以鋅摻雜的銅材料於銅晶種層上方填充導孔及溝槽；及其中形成氧化鋅矽阻障的步驟包括由一或多個介電層中的二氧化矽（silicon dioxide, SiO 2）及鋅摻雜的銅材料中的鋅形成氧化鋅矽阻障。在第二實施方式中，單獨地或與第一實施方式組合，形成氧化鋅矽阻障層包括進行原子層沉積 （atomic layer deposition, ALD） 操作，以直接沉積鋅層（例如，鋅層924）於溝槽的側壁上、直接沉積於導孔的側壁上、以及直接沉積於導孔的底表面上，其中銅層中的銅使鋅層中的鋅與一或多個介電層中的二氧化矽（silicon dioxide, SiO 2）鍵結，以形成氧化鋅矽阻障。 In the first embodiment, the step of filling the vias and trenches with a copper layer includes performing an atomic layer deposition (ALD) operation to deposit a copper seed layer (eg, copper seed layer 802 ) on the trenches over the sidewall of the via hole, over the sidewall of the via hole, and over the bottom surface of the via hole; and performing an electroplating operation to fill the via hole and the trench over the copper seed layer with a zinc-doped copper material; and form a zinc oxide silicon barrier therein The step of forming the barrier includes forming a zinc oxide silicon barrier from silicon dioxide (SiO 2 ) in one or more dielectric layers and zinc in a zinc doped copper material. In the second embodiment, alone or in combination with the first embodiment, forming a zinc oxide silicon barrier layer includes performing an atomic layer deposition (ALD) operation to directly deposit a zinc layer (eg, zinc layer 924 ) on the sidewalls of the trenches, directly on the sidewalls of the vias, and directly on the bottom surfaces of the vias, wherein the copper in the copper layer combines the zinc in the zinc layer with the two in the one or more dielectric layers. Silicon dioxide (SiO 2 ) bonds to form a zinc oxide silicon barrier.

在第三實施方式中，單獨地或與第一及第二實施方式中的一個或多個組合，進行ALD操作以沉積鋅層的步驟包括進行ALD操作，以沉積鋅層至約3埃至約10埃的範圍的厚度於溝槽的側壁上及導孔的側壁上。在第四實施方式中，單獨地或與第一至第三實施方式中的一個或多個組合，進行ALD操作以沉積鋅層的步驟包括進行ALD操作，以沉積鋅層至小於約10埃的厚度於導孔的底表面上。In a third embodiment, alone or in combination with one or more of the first and second embodiments, the step of performing an ALD operation to deposit a zinc layer includes performing an ALD operation to deposit a zinc layer to a range of from about 3 angstroms to about Thicknesses in the range of 10 Angstroms are on the sidewalls of the trenches and on the sidewalls of the vias. In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the step of performing an ALD operation to deposit a zinc layer includes performing an ALD operation to deposit a zinc layer to a thickness of less than about 10 angstroms thickness on the bottom surface of the guide hole.

在第五實施方式中，單獨地或與第一至第四實施方式中的一個或多個組合，製程1900包括進行原子層沉積（atomic layer deposition, ALD）操作，以直接沉積鋅層（例如，鋅層924）於溝槽的側壁上及直接沉積於導孔的側壁上；及其中形成氧化鋅矽阻障的步驟包括形成釕 （ruthenium, Ru） 晶種層（例如，釕晶種層1122）於鋅層上， 其中釕晶種層中的釕使鋅層中的鋅與一或多個介電層中的二氧化矽（silicon dioxide, SiO 2）鍵結，以形成氧化鋅矽阻障。在第六實施方式中，單獨地或與第一至第五實施方式中的一個或多個組合，形成釕晶種層的步驟包括形成釕晶種層至約5埃至約15埃的範圍的厚度。 In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 1900 includes performing an atomic layer deposition (ALD) operation to directly deposit a zinc layer (eg, A zinc layer 924) is deposited on the sidewalls of the trenches and directly on the sidewalls of the via holes; and the step of forming the zinc oxide silicon barrier includes forming a ruthenium (Ru) seed layer (eg, the ruthenium seed layer 1122) On the zinc layer, wherein the ruthenium in the ruthenium seed layer bonds the zinc in the zinc layer with silicon dioxide (SiO 2 ) in one or more dielectric layers to form a zinc oxide silicon barrier. In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the step of forming a ruthenium seed layer comprises forming a ruthenium seed layer to a range of about 5 angstroms to about 15 angstroms thickness.

儘管第19圖繪示出了製程1900的例示性方框，但是在一些實施方式中，製程1900可包括相較於第19圖中所描繪的那些而言額外的的方框、更少的方框、不同的方框、或不同設置的方框。額外地或替代地，製程1900的兩個或更多方框可並行進行。Although FIG. 19 depicts illustrative blocks of process 1900, in some implementations, process 1900 may include additional blocks, fewer blocks than those depicted in FIG. box, different boxes, or boxes with different settings. Additionally or alternatively, two or more blocks of process 1900 may be performed in parallel.

第20圖是與形成半導體結構相關聯的例示性製程2000的流程圖。在一些實施方式中，第20圖的一個或多個製程方框可由一個或多個半導體製程設備（例如，半導體製程設備102-116中的一個或多個）來進行。額外地或替代地，第20圖的一個或多個製程方框可由裝置1800的一個或多個元件來進行，上述裝置1800例如處理器1820、記憶體1830、存儲元件1840、輸入元件1850、輸出元件1860、及/或通訊元件 1870。FIG. 20 is a flow diagram of an exemplary process 2000 associated with forming a semiconductor structure. In some embodiments, one or more of the process blocks of FIG. 20 may be performed by one or more semiconductor process tools (eg, one or more of semiconductor process tools 102-116). Additionally or alternatively, one or more of the process blocks of FIG. 20 may be performed by one or more elements of apparatus 1800, such as processor 1820, memory 1830, storage element 1840, input element 1850, output element 1860, and/or communication element 1870.

如第20圖所示，製程2000可包括在裝置的一個或多個介電層中形成內連線，其中內連線包括導孔及位於導孔上方的溝槽（方框2010）。舉例而言，如前文所述，半導體製程設備102-116中的一個或多個可在裝置（例如，裝置200）的一個或多個介電層（例如，介電層244、1410及、/或1600）中形成內連線（例如，雙鑲嵌結構248、1400、及/或1600）。在一些實施方式中，內連線包括導孔（例如，導孔1404及/或1604）及位於導孔上方的溝槽（例如，溝槽1402及/或1602）。As shown in FIG. 20, process 2000 may include forming interconnects in one or more dielectric layers of the device, wherein the interconnects include vias and trenches over the vias (block 2010). For example, as previously described, one or more of semiconductor process equipment 102-116 may be in one or more dielectric layers (eg, dielectric layers 244, 1410 and/or) of a device (eg, device 200). or 1600) to form interconnects (eg, dual damascene structures 248, 1400, and/or 1600). In some implementations, the interconnect includes vias (eg, vias 1404 and/or 1604 ) and trenches (eg, trenches 1402 and/or 1602 ) over the vias.

如第20圖中進一步所示，製程2000可包括對導孔的底表面進行預處理操作，以使導孔的底表面變為非金屬性（方框2020）。舉例而言，如前文所述，半導體製程設備102-116中的一個或多個可在導孔的底表面（例如，底表面1418及/或1618）上進行預處理操作，以使得導孔的底表面變得非金屬性。As further shown in FIG. 20, process 2000 may include pre-processing operations on the bottom surface of the via to render the bottom surface of the via non-metallic (block 2020). For example, as previously described, one or more of the semiconductor process tools 102-116 may perform preprocessing operations on the bottom surfaces of the vias (eg, bottom surfaces 1418 and/or 1618) such that the vias are The bottom surface becomes non-metallic.

如第20圖進一步所示，製程2000可包括在預處理操作之後在導孔的側壁及溝槽的側壁上形成氮化鉭（tantalum nitride, TaN）膜（方框2030）。舉例而言，如前文所述，在預處理操作之後，半導體製程設備102-116中的一個或多個可在側壁（例如，側壁1416及/或1616）上形成氮化鉭（tantalum nitride, TaN）膜（例如，氮化鉭膜1420及/或1620）以及在溝槽的側壁（例如，側壁1412及/或1612）上。As further shown in FIG. 20, the process 2000 may include forming a tantalum nitride (TaN) film on the sidewalls of the via holes and the sidewalls of the trenches after the pretreatment operation (block 2030). For example, as previously described, one or more of the semiconductor process tools 102-116 may form tantalum nitride (TaN) on the sidewalls (eg, sidewalls 1416 and/or 1616) after the preprocessing operations ) films (eg, tantalum nitride films 1420 and/or 1620 ) and on the sidewalls of the trenches (eg, sidewalls 1412 and/or 1612 ).

如第20圖進一步所示，製程2000可包括在形成氮化鉭膜之後，在導孔的底表面上進行電漿處理操作，以使得導孔的底表面變成金屬性 （方框2040）。舉例而言，如前文所述，半導體製程設備102-116中的一個或多個可在形成氮化鉭膜之後，對導孔的底表面進行電漿處理操作，使導孔的底表面變金屬性。As further shown in FIG. 20, process 2000 may include, after forming the tantalum nitride film, performing a plasma treatment operation on the bottom surface of the via to render the bottom surface of the via metallic (block 2040). For example, as previously described, one or more of the semiconductor process tools 102-116 may, after forming the tantalum nitride film, perform a plasma treatment operation on the bottom surface of the via to metalize the bottom surface of the via sex.

如第20圖中進一步所示，製程2000可包括在氮化鉭膜上及導孔的底表面上形成釕（ruthenium, Ru）襯層（方框2050）。舉例而言，如前文所述，半導體製程設備102-116中的一個或多個可在氮化鉭膜上及導孔的底表面上形成釕（ruthenium, Ru）襯層（例如，釕襯層1422及/或1622）。As further shown in FIG. 20, process 2000 may include forming a ruthenium (Ru) liner on the tantalum nitride film and on the bottom surface of the via (block 2050). For example, as previously described, one or more of the semiconductor process tools 102-116 may form a ruthenium (Ru) liner (eg, a ruthenium liner on the tantalum nitride film and on the bottom surface of the via hole) 1422 and/or 1622).

如第20圖中進一步所示，製程2000可包括在溝槽中的釕襯層上形成銅（copper, Cu）層（方框2060）。舉例而言，如前文所述，半導體製程設備102-116中的一個或多個可在溝槽中的釕襯層上形成銅（copper, Cu）層（例如，銅層1424及/或1624）。As further shown in FIG. 20, the process 2000 may include forming a copper (Cu) layer on the ruthenium liner in the trench (block 2060). For example, as previously described, one or more of the semiconductor process tools 102-116 may form a copper (Cu) layer (eg, copper layers 1424 and/or 1624) on the ruthenium liner in the trenches .

製程2000可包括額外的實施方式，例如後文描述的及/或結合本文別處描述的一個或多個其他製程的任何單一實施方式或實施方式的任何組合。Process 2000 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in conjunction with one or more other processes described elsewhere herein.

在第一種實施方式中，形成氮化鉭膜的步驟包括形成氮化鉭膜至約3埃至約8埃的範圍的厚度於溝槽的側壁上及導孔的側壁上。在第二實施方式中，單獨地或與第一實施方式組合，形成氮化鉭膜的步驟包括於導孔的底表面上形成氮化鉭膜至小於約5埃的厚度。在第三實施方式中，單獨地或與第一及第二實施方式中的一個或多個組合，形成釕襯層的步驟包括於溝槽的側壁上及導孔的側壁上形成釕襯層至約10埃至約35埃的範圍的厚度。In the first embodiment, the step of forming the tantalum nitride film includes forming the tantalum nitride film to a thickness in the range of about 3 angstroms to about 8 angstroms on the sidewalls of the trenches and the sidewalls of the via holes. In the second embodiment, alone or in combination with the first embodiment, the step of forming the tantalum nitride film includes forming the tantalum nitride film on the bottom surface of the via hole to a thickness of less than about 5 angstroms. In the third embodiment, alone or in combination with one or more of the first and second embodiments, the step of forming a ruthenium liner includes forming a ruthenium liner on the sidewalls of the trenches and on the sidewalls of the vias to Thicknesses ranging from about 10 angstroms to about 35 angstroms.

在第四實施方式中，單獨地或與第一至第三實施方式中的一個或多個組合，形成釕襯層的步驟包括在電漿處理操作之後，進行物理氣相沉積（physical vapor deposition, PVD）操作，以沉積釕襯層的第一部分（例如，第一部分1704）於氮化鉭膜上及導孔的該底表面上；及進行化學氣相沉積（chemical vapor deposition, CVD） 操作或原子層沉積（atomic layer deposition, ALD）操作，以沉積釕襯層的第二部分於釕襯層的第一部分上。在第五實施方式中，單獨地或與第一至第四實施方式中的一個或多個組合，形成釕襯層的步驟包括：於導孔的底表面上形成釕襯層至約15埃至約35埃的範圍的厚度；及於導孔的側壁上形成釕襯層至約5埃至約15埃的範圍的厚度。In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the step of forming the ruthenium liner includes performing physical vapor deposition (physical vapor deposition, after the plasma processing operation) PVD) operation to deposit a first portion of the ruthenium liner (eg, first portion 1704) on the tantalum nitride film and on the bottom surface of the via; and a chemical vapor deposition (CVD) operation or atomic An atomic layer deposition (ALD) operation is performed to deposit a second portion of the ruthenium liner on the first portion of the ruthenium liner. In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the step of forming a ruthenium liner includes forming a ruthenium liner on the bottom surface of the via to a range of about 15 to about 15 angstroms a thickness in the range of about 35 angstroms; and forming a ruthenium liner on the sidewalls of the vias to a thickness in the range of about 5 angstroms to about 15 angstroms.

儘管第20圖繪示出了製程2000的例示性方框，但是在一些實施方式中，製程2000可包括相較於第20圖中所繪示的那些而言額外的方框、更少的方框、不同的方框、或不同設置的方框。額外地或替代地，兩個或製程2000的更多方框可同時進行。Although FIG. 20 depicts illustrative blocks of process 2000, in some implementations, process 2000 may include additional blocks, fewer blocks than those depicted in FIG. 20 box, different boxes, or boxes with different settings. Additionally or alternatively, two or more blocks of process 2000 may be performed concurrently.

因此，本文描述的低電阻銅內連線及用於形成低電阻銅內連線的製造技術，可用於實現銅內連線的低接觸電阻及低片電阻，特別是例如降低氮化鉭（tantalum nitride, TaN）襯層/膜厚度（或排除使用氮化鉭作為銅擴散阻障）及使用釕（ruthenium, Ru）及/或氧化鋅矽（zinc silicon oxide, ZnSiO x）作為銅擴散阻障）。本文所述的銅內連線的低接觸電阻及低片電阻特別是可藉由降低電子裝置的 RC 時間常數及增加電子裝置之間的信號傳播速度等來提高包括此類銅內連線件的電子裝置的電氣性能。 Accordingly, the low-resistance copper interconnects and fabrication techniques for forming low-resistance copper interconnects described herein can be used to achieve low contact resistance and low sheet resistance of copper interconnects, particularly, for example, to reduce tantalum nitride (tantalum) Nitride, TaN) liner/film thickness (or exclude the use of tantalum nitride as copper diffusion barrier and the use of ruthenium (Ru) and/or zinc silicon oxide (ZnSiO x ) as copper diffusion barrier) . The low contact resistance and low sheet resistance of the copper interconnects described herein can improve the performance of components including such copper interconnects, among other things, by reducing the RC time constant of the electronic device and increasing the speed of signal propagation between electronic devices. Electrical performance of electronic devices.

如前文更詳細地描述的，本文描述的一些實施方式提供了一種裝置。裝置包括內連線，被包括於半導體裝置的介電層中，包括接觸插塞。裝置包括氧化釕（ruthenium oxide, RuO x）膜，直接位於接觸插塞的側壁上。裝置包括釕（ruthenium, Ru）襯層，位於接觸插塞的側壁上的氧化釕膜上方及接觸插塞的底表面上方。裝置包括銅（copper, Cu）層，位於接觸插塞中的釕襯層上方。 As previously described in greater detail, some embodiments described herein provide an apparatus. The device includes interconnects included in a dielectric layer of the semiconductor device, including contact plugs. The device includes a ruthenium oxide (RuO x ) film directly on the sidewalls of the contact plugs. The device includes a ruthenium (Ru) liner layer over the ruthenium oxide film on the sidewalls of the contact plug and over the bottom surface of the contact plug. The device includes a copper (Cu) layer over a ruthenium liner in the contact plug.

在一些實施例中，位於接觸插塞的底表面上的釕襯層的厚度大於約0埃且小於約8埃。在一些實施例中，半導體裝置更包括：雙鑲嵌結構，被包括於半導體裝置的另一介電層中，且位於接觸插塞上方，包括：另一釕襯層，位於雙鑲嵌結構的側壁上方及雙鑲嵌結構的底表面上方； 另一銅層，位於另一釕襯層上方；鈷蓋層，位於另一銅層上方；及鈷襯層，位於另一釕襯層及另一銅層之間。在一些實施例中，半導體裝置，更包括：單鑲嵌結構，被包括於半導體裝置的另一介電層中，且位於接觸插塞上方，包括導孔；氮化鉭 （tantalum nitride, TaN） 膜，直接位於導孔的側壁上；另一釕襯層，位於導孔的側壁上的氮化鉭膜上方及導孔的底表面上方；及另一銅層，位於導孔中的另一釕襯層上方。在一些實施例中，氮化鉭膜被包括於導孔的底表面上；及其中位於導孔的底表面上的氮化鉭膜的厚度大於約0埃且小於約5埃。在一些實施例中，位於導孔的側壁上的氮化鉭膜的厚度在約3埃至約8埃的範圍。在一些實施例中，位於導孔的側壁上的釕襯層的厚度在約10埃至約35埃的範圍；及其中位於導孔的該底表面上的釕襯層的厚度在約8埃至約25埃的範圍。In some embodiments, the thickness of the ruthenium liner on the bottom surface of the contact plug is greater than about 0 angstroms and less than about 8 angstroms. In some embodiments, the semiconductor device further includes: a dual damascene structure included in another dielectric layer of the semiconductor device and overlying the contact plugs, including: another ruthenium liner overlying sidewalls of the dual damascene structure and over the bottom surface of the dual damascene structure; another copper layer over the other ruthenium liner; a cobalt capping layer over the other copper layer; and a cobalt underlayer between the other ruthenium liner and the other copper layer between. In some embodiments, the semiconductor device further includes: a single damascene structure included in another dielectric layer of the semiconductor device and located over the contact plugs, including vias; a tantalum nitride (TaN) film , directly on the sidewalls of the vias; another ruthenium lining layer over the tantalum nitride film on the sidewalls of the vias and over the bottom surface of the vias; and another copper layer over the other ruthenium linings in the vias above the layer. In some embodiments, a tantalum nitride film is included on the bottom surface of the via; and wherein the thickness of the tantalum nitride film on the bottom surface of the via is greater than about 0 angstroms and less than about 5 angstroms. In some embodiments, the thickness of the tantalum nitride film on the sidewalls of the via is in the range of about 3 angstroms to about 8 angstroms. In some embodiments, the thickness of the ruthenium liner on the sidewall of the via is in the range of about 10 angstroms to about 35 angstroms; and wherein the thickness of the ruthenium liner on the bottom surface of the via is in the range of about 8 to about 35 angstroms range of about 25 angstroms.

如前文更詳細地描述的，本文描述的一些實施方式提供了一種方法。方法包括形成內連線於裝置的一或多個介電層中，其中內連線包括導孔及位於導孔上方的溝槽。方法包括成氧化鋅矽 （zinc silicon oxide, ZnSiO x）阻障於導孔的側壁上及溝槽的側壁上。方法包括用銅（copper, Cu）層填充導孔及溝槽。 As previously described in greater detail, some embodiments described herein provide a method. The method includes forming interconnects in one or more dielectric layers of the device, wherein the interconnects include vias and trenches over the vias. The method includes forming zinc silicon oxide (ZnSiO x ) barriers on the sidewalls of the via holes and the sidewalls of the trenches. The method includes filling vias and trenches with a copper (Cu) layer.

如前文更詳細地描述的，本文描述的一些實施方式提供了一種方法。方法包括形成內連線於裝置的一或多個介電層中，其中內連線包括導孔及位於導孔上方的溝槽。方法包括進行預處理操作於導孔的底表面上，使導孔的底表面變非金屬性。方法包括在預處理操作之後，形成氮化鉭（tantalum nitride, TaN）膜於導孔的側壁上及溝槽的側壁上。方法包括在形成氮化鉭膜後，進行電漿處理操作於導孔的該底表面上，使導孔的底表面變金屬性。方法包括形成釕（ruthenium, Ru）襯層於氮化鉭膜上及導孔的底表面上。方法包括形成銅（copper, Cu）層於溝槽中的釕襯層上。As previously described in greater detail, some embodiments described herein provide a method. The method includes forming interconnects in one or more dielectric layers of the device, wherein the interconnects include vias and trenches over the vias. The method includes performing a pretreatment operation on the bottom surface of the via hole to render the bottom surface of the via hole non-metallic. The method includes forming a tantalum nitride (TaN) film on the sidewall of the via hole and the sidewall of the trench after the pretreatment operation. The method includes, after forming the tantalum nitride film, performing a plasma treatment operation on the bottom surface of the via hole to make the bottom surface of the via hole metallic. The method includes forming a ruthenium (Ru) lining layer on the tantalum nitride film and on the bottom surface of the via hole. The method includes forming a copper (Cu) layer on the ruthenium liner in the trench.

以上概述數個實施例之特徵，以使本發明所屬技術領域中具有通常知識者可更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解，可輕易地以本發明實施例為基礎，設計或修飾其他製程及結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且可在不違背本發明之精神及範圍下，做各式各樣的改變、取代及替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。The features of several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. It should be understood by those skilled in the art to which the present invention pertains that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same objectives and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various structures can be made without departing from the spirit and scope of the present invention. changes, substitutions and substitutions. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100:例示性環境 102:沉積設備 104:曝光設備 106:顯影設備 108:蝕刻設備 110:平坦化設備 112:鍍膜設備 114:預處理設備 116:電漿設備 118:晶圓/晶粒運輸設備 200:裝置 210:基板 220:FEOL區 222:介電層 224:源極或汲極 226:金屬閘極 230:MEOL區 232:介電層 234:接觸插塞 240:BEOL區 242:介電層 246:單鑲嵌結構 244:介電層 248:雙鑲嵌結構 300:內連線 302:接觸插塞 304:下金屬化層 306:蝕刻停止層 308:介電層 310:側壁 312:底表面 314:氧化釕膜 316:釕襯層 318:銅層 400:例示性實施方式 402:鈍化層 404:蝕刻停止層 406:介電層 408:單鑲嵌結構 410:側壁 412:底表面 414:鈍化層 416:氮化鉭 418:釕襯層 420:銅層 500:內連線 502:接觸插塞 504:下金屬化層 506:蝕刻停止層 508:介電層 510:側壁 512:底表面 514:釕襯層 516:銅層 600:例示性實施方式 700:雙鑲嵌結構 702:溝槽 704:導孔 706:下金屬化層 708:蝕刻停止層 710:介電層 712:側壁 714:底表面 716:側壁 718:底表面 720:氧化鋅矽阻障層 722:銅層 800:例示性實施方式 802:銅晶種層 900:雙鑲嵌結構 902:溝槽 904:導孔 906:下金屬化層 908:蝕刻停止層 910:介電層 912:側壁 914:底表面 916:側壁 918:底表面 920:氧化鋅矽阻障層 922:銅層 924:鋅層 1000:例示性實施方式 1002:銅晶種層 1100:雙鑲嵌結構 1102:溝槽 1104:導孔 1106:下金屬化層 1108:蝕刻停止層 1110:介電層 1112:側壁 1114:底表面 1116:側壁 1118:底表面 1120:氧化鋅矽阻障層 1122:釕晶種層 1124:鋅層 1126:銅層 1200:雙鑲嵌結構 1202:溝槽 1204:導孔 1206:下金屬化層 1208:蝕刻停止層 1210:介電層 1212:側壁 1214:底表面 1216:側壁 1218:底表面 1220:釕襯層 1222:銅層 1224:蓋層 1226:鈷襯層 1228:過渡角 1300:例示性實施方式 1400:雙鑲嵌結構 1402:溝槽 1404:導孔 1406:下金屬化層 1408:蝕刻停止層 1410:介電層 1412:側壁 1414:底表面 1416:側壁 1418:底表面 1420:氮化鉭膜 1422:釕襯層 1424:銅層 1500:例示性實施方式 1502:鈍化層 1600:雙鑲嵌結構 1602:溝槽 1604:導孔 1606:下金屬化層 1608:蝕刻停止層 1610:介電層 1612:側壁 1614:底表面 1616:側壁 1618:底表面 1620:氮化鉭膜 1622:釕襯層 1624:銅層 1700:例示性實施方式 1702:鈍化層 1800:裝置 1810:匯流排 1820:處理器 1830:記憶體 1840:存儲元件 1850:輸入元件 1860:輸出元件 1870:通訊元件 1900:製程 1910,1920,1930:方框 2000:製程 2010,2020,2030,2040,2050,2060:方框 100: Illustrative Environment 102: Deposition equipment 104: Exposure Equipment 106:Development equipment 108: Etching Equipment 110: Flattening equipment 112: Coating equipment 114: Pretreatment equipment 116: Plasma Equipment 118: Wafer/die transport equipment 200: Device 210: Substrate 220: FEOL District 222: Dielectric layer 224: source or drain 226: Metal gate 230: MEOL District 232: Dielectric layer 234: Contact Plug 240: BEOL District 242: Dielectric Layer 246: Single mosaic structure 244: Dielectric Layer 248: Double mosaic structure 300: Inline 302: Contact Plug 304: Lower metallization layer 306: Etch Stop Layer 308: Dielectric layer 310: Sidewall 312: Bottom surface 314: Ruthenium oxide film 316: Ruthenium Liner 318: Copper layer 400: Exemplary Embodiments 402: Passivation layer 404: etch stop layer 406: Dielectric Layer 408: Single mosaic structure 410: Sidewall 412: Bottom surface 414: Passivation layer 416: Tantalum Nitride 418: Ruthenium Liner 420: Copper layer 500: Inline 502: Contact Plug 504: Lower metallization layer 506: Etch Stop Layer 508: Dielectric Layer 510: Sidewall 512: Bottom surface 514: Ruthenium Liner 516: Copper layer 600: Exemplary Embodiments 700: Double mosaic structure 702: Groove 704: Pilot hole 706: Lower metallization layer 708: Etch stop layer 710: Dielectric layer 712: Sidewall 714: Bottom Surface 716: Sidewall 718: Bottom Surface 720: Zinc oxide silicon barrier layer 722: Copper layer 800: Exemplary Embodiments 802: Copper seed layer 900: Double mosaic structure 902: Groove 904: Pilot hole 906: Lower metallization layer 908: Etch Stop Layer 910: Dielectric layer 912: Sidewall 914: Bottom Surface 916: Sidewall 918: Bottom Surface 920: Zinc oxide silicon barrier layer 922: Copper layer 924: Zinc layer 1000: Exemplary Embodiments 1002: Copper seed layer 1100: Double mosaic structure 1102: Groove 1104: Pilot hole 1106: Lower metallization layer 1108: Etch Stop Layer 1110: Dielectric layer 1112: Sidewall 1114: Bottom Surface 1116: Sidewall 1118: Bottom surface 1120: Zinc oxide silicon barrier layer 1122: Ruthenium seed layer 1124: Zinc layer 1126: Copper layer 1200: Double mosaic structure 1202: Groove 1204: Pilot hole 1206: Lower metallization layer 1208: Etch Stop Layer 1210: Dielectric Layer 1212: Sidewall 1214: Bottom Surface 1216: Sidewall 1218: Bottom Surface 1220: Ruthenium Liner 1222: Copper layer 1224: Cover Layer 1226: Cobalt Liner 1228: transition angle 1300: Exemplary Embodiments 1400: Double mosaic structure 1402: Trench 1404: Pilot hole 1406: Lower metallization layer 1408: Etch Stop Layer 1410: Dielectric Layer 1412: Sidewall 1414: Bottom Surface 1416: Sidewall 1418: Bottom Surface 1420: Tantalum nitride film 1422: Ruthenium Liner 1424: Copper Layer 1500: Exemplary Embodiments 1502: Passivation layer 1600: Double mosaic structure 1602: Groove 1604: Pilot hole 1606: Lower metallization layer 1608: Etch Stop Layer 1610: Dielectric Layer 1612: Sidewall 1614: Bottom Surface 1616: Sidewall 1618: Bottom Surface 1620: Tantalum nitride film 1622: Ruthenium Liner 1624: Copper Layer 1700: Exemplary Embodiments 1702: Passivation layer 1800: Device 1810: Busbars 1820: Processor 1830: Memory 1840: Storage element 1850: Input Components 1860: Output Components 1870: Communication Components 1900: Process 1910, 1920, 1930: Box 2000: Process 2010, 2020, 2030, 2040, 2050, 2060: Box

本揭露的各面向從以下詳細描述中配合附圖可最好地被理解。應強調的是，依據業界的標準做法，各種部件並未按照比例繪製且僅用於說明的目的。事實上，為了清楚討論，各種部件的尺寸可任意放大或縮小。 第1圖係在其中可實現本文所述的系統及/或方法的例示性環境的圖。 第2圖係本文所述的例示性電子裝置的一部分的圖。 第3圖係本文所述的例示性內連線的圖。 第4A圖、第4B圖、第4C圖、第4D圖、第4E圖、第4F圖、第4G圖、第4H圖、第4I圖、第4J圖、第4K圖、第4L圖、第4M圖、第4N圖係本文所述的例示性實施方式的圖。 第5圖係本文所述的例示性內連線的圖。 第6A圖、第6B圖、第6C圖、第6D圖係本文所述的例示性實施方式的圖。 第7圖係本文所述的例示性雙鑲嵌結構的圖。 第8A圖、第8B圖、第8C圖、第8D圖、第8E係本文所述的例示性實施方式的圖。 第9圖係本文所述的例示性雙鑲嵌結構的圖。 第10A圖、第10B圖、第10C圖、第10D圖、第10E圖、第10F圖係本文所述的例示性實施方式的圖。 第11圖係本文所述的例示性雙鑲嵌結構的圖。 第12圖係本文所述的例示性雙鑲嵌結構的圖。 第13A圖、第13B圖、第13C圖、第13D圖、第13E圖係本文所述的例示性實施方式的圖。 第14圖係本文所述的例示性雙鑲嵌結構的圖。 第15A圖、第15B圖、第15C圖、第15D圖、第15E圖、第15F圖、第15G圖係本文所述的例示性實施方式的圖。 第16圖係本文所述的例示性雙鑲嵌結構的圖。 第17A圖、第17B圖、第17C圖、第17D圖、第17E圖、第17F圖、第17G圖、第17H圖係本文所述的例示性實施方式的圖。 第18圖係第1圖的一個或多個裝置的例示性元件的圖。 第19圖及第20圖係與形成半導體結構相關的例示性製程的流程圖。 Aspects of the present disclosure are best understood from the following detailed description, taken in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily expanded or reduced for clarity of discussion. FIG. 1 is a diagram of an exemplary environment in which the systems and/or methods described herein may be implemented. FIG. 2 is a diagram of a portion of an exemplary electronic device described herein. Figure 3 is a diagram of an exemplary interconnection described herein. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, 4L, 4M FIG. 4N is a drawing of an exemplary embodiment described herein. Figure 5 is a diagram of an exemplary interconnection described herein. Figures 6A, 6B, 6C, 6D are diagrams of exemplary embodiments described herein. Figure 7 is a diagram of an exemplary dual damascene structure described herein. Figures 8A, 8B, 8C, 8D, 8E are drawings of the exemplary embodiments described herein. Figure 9 is a diagram of an exemplary dual damascene structure described herein. Figures 10A, 10B, 10C, 10D, 10E, 10F are diagrams of exemplary embodiments described herein. Figure 11 is a diagram of an exemplary dual damascene structure described herein. Figure 12 is a diagram of an exemplary dual damascene structure described herein. Figures 13A, 13B, 13C, 13D, 13E are diagrams of exemplary embodiments described herein. Figure 14 is a diagram of an exemplary dual damascene structure described herein. Figures 15A, 15B, 15C, 15D, 15E, 15F, 15G are drawings of exemplary embodiments described herein. Figure 16 is a diagram of an exemplary dual damascene structure described herein. Figures 17A, 17B, 17C, 17D, 17E, 17F, 17G, 17H are drawings of exemplary embodiments described herein. FIG. 18 is a diagram of illustrative elements of one or more of the devices of FIG. 1 . 19 and 20 are flowcharts of exemplary processes associated with forming semiconductor structures.

300:內連線 300: Inline

302:接觸插塞 302: Contact Plug

304:下金屬化層 304: Lower metallization layer

306:蝕刻停止層 306: Etch Stop Layer

308:介電層 308: Dielectric layer

310:側壁 310: Sidewall

312:底表面 312: Bottom surface

314:氧化釕膜 314: Ruthenium oxide film

316:釕襯層 316: Ruthenium Liner

318:銅層 318: Copper layer

Claims (1)

一種半導體裝置，包括： 一內連線，被包括於所述半導體裝置的一介電層中，包括一接觸插塞； 一氧化釕膜，直接位於該接觸插塞的側壁上； 一釕襯層，位於該接觸插塞的側壁上的該氧化釕膜上方及該接觸插塞的一底表面上方；及 一銅層，位於該接觸插塞中的該釕襯層上方。 A semiconductor device, comprising: an interconnect included in a dielectric layer of the semiconductor device, including a contact plug; Ruthenium oxide film, directly on the side wall of the contact plug; a ruthenium liner layer over the ruthenium oxide film on the sidewall of the contact plug and over a bottom surface of the contact plug; and a copper layer over the ruthenium liner in the contact plug.
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