TW202230314A - Detection device for detecting a receiving card removably inserted into an insertion slot of a light-emitting diode display system - Google Patents

Abstract

A detection device for an insertion slot of an LED display system is provided. When a first receiving card is inserted in the insertion slot, the detection device outputs, to a display panel of the LED display system, a first data output with reference to an image signal outputted by the first receiving card. When a second receiving card is inserted in the insertion slot, the detection device outputs a high-impedance signal to the second receiving card to enable the second receiving card to generate an enabling output, generates a second data output with reference to the enabling output and the image signal outputted by the second receiving card, and transmits the second data output to the display panel.

Description

automatic detection device

The present invention relates to a device, and more particularly, to an automatic detection device for detecting an insertion unit of a light-emitting diode display system.

The existing light emitting diode (Light Emitting Diode, LED) display system includes an insertion unit for inserting a receiving card, a signal generating unit, and an LED display unit. The receiving card receives an image signal from an external transmitting system, and transmits the image signal to the signal generating unit through the insertion unit. The signal generating unit performs signal processing on the image signal to generate a data output, and transmits the data output to the LED display unit for image display.

However, in the above structure, the transmitting system and the receiving card must be paired, that is, the transmitting system and the receiving card must be products of the same brand. When the existing LED display system needs to be replaced with a receiving card of a different brand, the LED display system needs to be redesigned, that is, the designer of the LED display system must independently develop a suitable LED display system according to the needs of different brands. As a result, it not only wastes R&D resources, but also increases the inventory pressure on the demand side of the LED display system. Therefore, the existing LED display systems still have room for improvement.

Therefore, the purpose of the present invention is to provide an automatic detection device which can overcome the shortcomings of the prior art.

Therefore, the automatic detection device of the present invention is suitable for detecting an insertion unit in a light-emitting diode display system, and the insertion unit is used for one of a first receiving card and a second receiving card to receive a It is inserted in a detachable manner, and outputs an image signal and an identification signal from the first and second receiving cards correspondingly. When the second receiving card is inserted into the inserting unit, the The insertion unit also outputs a control signal output related to scanning display from the second receiving card, the second receiving card also receives a high impedance signal through the insertion unit, and provides an output through the insertion unit accordingly enable signal output. The automatic detection device includes a detection unit, a buffer unit, and a signal generation unit.

The detection unit is used for receiving an input power supply, and is used for electrically connecting the plug-in unit to receive the identification signal output. The detection unit determines whether the plug-in unit is inserted with the first receiving card or The second receiving card generates a first detection signal and a second detection signal accordingly, and generates a power output according to the first and second detection signals and the input power supply, the first detection signal The phase of the detection signal is opposite to the phase of the second detection signal, and the phase of the first and second detection signals changes with the change of the receiving card inserted in the insertion unit. The voltage value output by the power supply is due to The first and second detection signals vary.

The buffer unit is used for receiving the input power, and for being electrically connected to the insertion unit to receive the control signal output, and electrically connected to the detection unit to receive the power output and the first detection signal, when the insertion When the unit is inserted with the second receiving card, the buffer unit generates the high-impedance signal and a set of enabling signals according to the first detection signal, outputs the high-impedance signal to the insertion unit, and also according to the first detection signal The power output and the first detection signal buffer the control signal output and the set of enabling signals to generate and output a buffered output signal to the display unit.

The signal generating unit is used for receiving the input power, and is used for being electrically connected to the plug-in unit to receive the image signal and the enabling signal output, and is electrically connected to the detecting unit to receive the power output and the second detection signal, when the first receiving card is inserted into the insertion unit, the signal generating unit generates and outputs a first data according to the image signal, the input power, the power output and the second detection signal a display unit for displaying images, when the second receiving card is inserted into the inserting unit, the signal generating unit is based on the image signal, the input power supply, the power supply output, the second detection signal, and the The signal output is enabled to generate and output a second data output to the display unit, so that the display unit performs image display according to the second data output and the buffer output signal.

The effect of the present invention is: using the detection unit to automatically determine whether the insertion unit is inserted with the first receiving card or the second receiving card, and output the first and second detection signals and the power output accordingly , so as to automatically control the buffer unit and the signal generating unit to adjust their own operations accordingly. Therefore, when the light-emitting diode display system needs to be replaced with a different receiving card, the automatic detection device can still support it, so that the light-emitting diode display system can still be supported. The polar body display system can still perform image display, so there is no need to redesign the light emitting diode display system according to different receiving cards as in the prior art.

Referring to FIG. 1 , an embodiment of the automatic detection device 10 of the present invention is suitable for an LED display system 1 . The Light Emitting Diode (LED) display system 1 includes a power supply unit 11 , an insertion unit 12 , a display unit 13 , and other necessary components (not shown). The power supply unit 11 is used to supply an input power Vcc (ie, 5V) and an input voltage Vc (ie, 3.3V) required for the operation of the LED display system 1 and the automatic detection device 10 . The insertion unit 12 is used for one of a first receiving card (not shown) and a second receiving card (not shown) to be inserted in a detachable manner. The first and second receiving cards are respectively used for receiving an image signal Dai from an external transmitting system (not shown), and outputting the image signal Dai and an identification signal Iso through the insertion unit 12 transmitted to the automatic detection device 10 . It should be noted that when the first receiving card is inserted into the insertion unit 12, the logic level of the identification signal output Iso is a logic “0” level. When the insertion unit 12 is inserted with the second receiving card, the logic level of the identification signal output Iso is not the logic "0" level. Therefore, the automatic detection device 10 can detect whether the insertion unit 12 is inserted with the first receiving card or the second receiving card according to the identification signal output Iso, to determine how to adjust the action of its own internal circuit, so as to The image signal Dai generates a first data output Da1 or a second data output Da2, and transmits the first data output Da1 or the second data output Da2 to the display unit 13 for image display. In this embodiment, the display unit 13 is an LED display unit. The first receiving card is a Nova receiving card, and the second receiving card is a Brompton receiving card.

The automatic detection device 10 of this embodiment includes a detection unit 2 , a buffer unit 3 , a signal generation unit 4 , an indicator light unit 5 , and an output unit 6 .

The detection unit 2 is electrically connected to the power supply unit 11 and the insertion unit 12 to receive the input power Vcc and the identification signal output Iso, respectively. The detection unit 2 determines whether the insertion unit 12 is inserted with the first receiving card or the second receiving card according to the identification signal output Iso, and generates a first detection signal D1 and a second detection signal accordingly D2, and according to the first and second detection signals D1, D2 and the input power Vcc, a power output Vo is generated. The phase of the first detection signal D1 is opposite to the phase of the second detection signal D2, and the phases of the first and second detection signals D1, D2 change with the receiving card inserted in the insertion unit 12 and change. The voltage value of the power output Vo varies due to the first and second detection signals D1 and D2.

Further referring to FIG. 2 , in this embodiment, the detection unit 2 includes a detection circuit 21 and a power generation circuit 22 . The power output Vo includes a first power signal Vo1 and a second power signal Vo2. The identification signal output Iso includes a first identification signal Is1 and a second identification signal Is2. When the first receiving card is inserted into the insertion unit 12, the respective logic levels of the first and second identification signals Is1 and Is2 are the logic "0" level. When the insertion unit 12 is inserted with the second receiving card, the first identification signal Is1 is a power signal (ie, 2.5V) related to the second receiving card. The second identification signal Is2 is a command signal indicating that the second receiving card is operable, and its logic level is not the logic "0" level.

The detection circuit 21 is electrically connected to the plug-in unit 12 to receive the first and second identification signals Is1, Is2, and determines that the plug-in unit 12 is plugged in according to the first and second identification signals Is1, Is2 The first receiving card or the second receiving card generates the first and second detection signals D1 and D2 accordingly. In this embodiment, the detection circuit 21 includes a diode 211 , first and second resistors 212 and 213 , first and second capacitors 214 and 215 , and first and second transistors 216 and 217 .

The diode 211 has an anode for receiving the first identification signal Is1 and a cathode for receiving the second identification signal Is2. The first resistor 212 has a first end electrically connected to the cathode of the diode 211 and a second end. The second resistor 213 is electrically connected between the second end of the first resistor 212 and the ground. The first capacitor 214 is electrically connected between the second end of the first resistor 212 and the ground. The first transistor 216 has a first terminal for providing the first detection signal D1 , a second terminal connected to ground, and a control terminal electrically connected to the second terminal of the first resistor 212 . The second capacitor 215 is electrically connected between the first end of the first transistor 216 and the ground. The second transistor 217 has a first terminal for providing the second detection signal D2 , a second terminal connected to ground, and a control terminal electrically connected to the first terminal of the first transistor 216 . In this embodiment, the first and second transistors 216 and 217 are each an N-type MOSFET, wherein the drain, source and gate are the first and second transistors, respectively The first end, the second end and the control end of each of 216, 217.

The power generation circuit 22 is electrically connected to the power supply unit 11 to receive the input power Vcc, and is electrically connected to the detection circuit 21 to receive the first and second detection signals D1 and D2. The power generation circuit 22 generates the first power signal Vo1 according to the input power Vcc and the first detection signal D1, and generates the second power signal Vo2 according to the input power Vcc and the second detection signal D2. In this embodiment, the power generation circuit 22 includes first to fourth resistors 221 ˜ 224 , first and second transistors 225 and 226 , and a voltage regulator 227 .

The first resistor 221 has a first terminal and a second terminal for receiving the first detection signal D1. The second resistor 222 has a first terminal electrically connected to the power supply unit 11 for receiving the input power Vcc, and a second terminal electrically connected to the first terminal of the first resistor 221 . The first transistor 225 has a first terminal that is electrically connected to the first terminal of the second resistor 222 , a second terminal that provides the first power signal Vo1 , and a first terminal that is electrically connected to the second resistor 222 . The control end of the two ends. The third resistor 223 has a first terminal and a second terminal for receiving the second detection signal D2. The fourth resistor 224 has a first terminal electrically connected to the power supply unit 11 for receiving the input power Vcc, and a second terminal electrically connected to the first terminal of the third resistor 223 . The second transistor 226 has a first terminal electrically connected to the first terminal of the fourth resistor 224 , a second terminal, and a control terminal electrically connected to the second terminal of the fourth resistor 224 . The voltage regulator 227 is electrically connected to the power supply unit 11 to receive the input power Vcc, and is electrically connected to the first and second terminals of the second transistor 226 . In this embodiment, the first and second transistors 225 and 226 are respectively a P-type MOSFET, wherein the source, drain and gate are the first and second transistors, respectively The first end, the second end and the control end of each of 225, 226. The regulator 227 is a low-dropout regulator (LDO).

It should be noted that when the first receiving card is inserted into the insertion unit 12, the first transistor 216 is not turned on, and the second transistor 217 is turned on, so that the first detection signal D1 has a high logic level bit, the second detection signal D2 has a low logic level. At this time, the first transistor 225 is not turned on, the second transistor 226 is turned on, the voltage of the first power signal Vo1 is zero, and since the voltage of the input terminal of the voltage regulator 227 is not greater than the voltage of the output terminal, so that The voltage regulator 227 does not operate, so the second transistor 226 provides the second power signal Vo2 at the second end thereof according to the input power Vcc (ie, the voltage of the second power signal Vo2 is 5V). When the insertion unit 12 is inserted with the second receiving card, the first transistor 216 is turned on, and the second transistor 217 is not turned on, so that the first detection signal D1 has a low logic level, the second The detection signal D2 has a high logic level. At this time, the first transistor 225 is turned on, the second transistor 226 is not turned on, the voltage of the input power Vcc is used as the first power signal Vo1, and the voltage regulator 227 steps down according to the input power Vcc to The second power signal Vo2 is generated (ie, the voltage drop of the second power signal Vo2 is 2.5V).

1 to 3, the buffer unit 3 is electrically connected to the insertion unit 12, and is electrically connected to the power supply unit 11 to receive the input power Vcc and the input voltage Vc, and is electrically connected to the detection unit 2 to receive the The power supply outputs the second power signal Vo2 and the first detection signal D1 of Vo. When the inserting unit 12 is inserted with the second receiving card, the second receiving card outputs a control signal Co to the buffer unit 3 via the inserting unit 12 . The control signal output Co is used to control the scanning display of the display unit 13 . The control signal output Co includes a clock signal, a scan signal and a latch signal, but is not limited thereto. When the insertion unit 12 is inserted with the second receiving card, the buffer unit 3 generates a high impedance signal Hs and a set of enable signals according to the first detection signal D1 (the set of enable signals is used to enable The display unit 13 includes binary enable signals OE1, OE2), and outputs the high-impedance signal Hs to the second receiving card via the insertion unit 12, so that the second receiving card provides the high-impedance signal Hs according to the An enable signal output via the interposer unit 12 outputs Eno. Then, the buffer unit 3 further buffers the control signal output Co and the set of enable signals according to the second power signal Vo2 and the first detection signal D1 to generate and output a buffered output signal Bo to the display unit 13. Conversely, when the first receiving card is inserted into the insertion unit 12, the buffer unit 3 generates the set of enabling signals according to the first detection signal D1 and generates a logic “0” level output signal So instead of The high impedance signal Hs, and the buffer unit 3 stops outputting any signal to the display unit 13 according to the first detection signal D1. In this embodiment, the buffer unit 3 includes a control signal generating module 31 and a buffer circuit 32 .

The control signal generating module 31 is electrically connected to the insertion unit 12, and is electrically connected to the power supply unit 11 and the detection circuit 21 of the detection unit 2 to receive the input voltage Vc and the first detection signal D1 respectively . When the second receiving card is inserted into the insertion unit 12, the control signal generating module 31 generates the high impedance signal Hs and the enabling signals OE1 and OE2 according to the first detection signal D1, and generates the high impedance signal Hs and the enabling signals OE1 and OE2. The high impedance signal Hs is output to the insertion unit 12 . When the insertion unit 12 is inserted with the first receiving card, the buffer unit 3 generates the output signal So according to the first detection signal D1 to replace the high impedance signal Hs, and generates the enable signals OE1 and OE2 . In this embodiment, the control signal generating module 31 includes first to fourth resistors 311 - 314 , a capacitor 315 , first and second transistors 316 and 317 , and an enabling signal generating circuit 318 .

The first resistor 311 has a first terminal that is electrically connected to the detection circuit 21 of the detection unit 2 to receive the first detection signal D1, and a second terminal that is grounded. The capacitor 315 is electrically connected between the first end of the first resistor 311 and the ground. The first transistor 316 has a first terminal, a second terminal grounded, and a control terminal electrically connected to the first terminal of the first resistor 311 . The second resistor 312 has a first terminal electrically connected to the power supply unit 11 to receive the input voltage Vc, and a second terminal electrically connected to the first terminal of the first transistor 316 . The third and fourth resistors 313 and 314 each have a first terminal for receiving the input voltage Vc, and a second terminal. The enable signal generating circuit 318 is electrically connected to the first terminal of the first transistor 316 and the second terminals of the third and fourth resistors 313 and 314 and provides the enable signals OE1 and OE2 . The second transistor 317 has a first terminal electrically connected to the insertion unit 12, a second terminal connected to ground, and a detection circuit 21 electrically connected to the detection unit 2 to receive the first detection signal Control terminal of D1. The second transistor 317 is controlled by the first detection signal D1 to provide the high impedance signal Hs or the output signal So at the first end thereof. Each of the first and second transistors 316 and 317 is an N-type MOSFET, wherein a drain, a source and a gate of each of the first and second transistors 316 and 317 are respectively One of the first end, the second end and the control end.

The enabling signal generating circuit 318 includes two enabling signal generators 319 and 310 . Each enable signal generator 319, 310 includes first and second output transistors M1, M2, and an output resistor Ro. In each enable signal generator 319, 310, the first output transistor M1 has a first end electrically connected to a corresponding one of the second ends of the third and fourth resistors 313, 314, a second terminal for providing a corresponding one of the enable signals OE1 and OE2 , and a control terminal electrically connected to the first terminal of the first transistor 316 . The second output transistor M2 has a first end electrically connected to the second end of the first output transistor M1, a second end, and a control end electrically connected to the first end of the first transistor 316 . The output resistor Ro is electrically connected between the second end of the second output transistor M2 and the ground. In this embodiment, the first ends of the first output transistors M1 of the enable signal generators 319 and 310 are electrically connected to the second ends of the third and fourth resistors 313 and 314 respectively. end. The second ends of the first output transistors M1 of the enable signal generators 319 and 310 respectively provide the enable signals OE1 and OE2. The first output transistor M1 is a PNP type bipolar transistor, wherein the emitter, the collector and the base are the first terminal, the second terminal and the control terminal of the first output transistor M1 respectively. The second output transistor M2 is an NPN type bipolar transistor, wherein the collector, the emitter and the base are the first terminal, the second terminal and the control terminal of the second output transistor M2, respectively.

In this embodiment, when the logic level of the first detection signal D1 is a low logic level, the first and second transistors 316 and 317 and the first output transistor M1 are not conductive, and the Wait until the second output transistor M2 is turned on. The second transistor 317 provides the high impedance signal Hs at the first end thereof, and the enable signals OE1 and OE2 each have a low logic level. When the logic level of the first detection signal D1 is a high logic level, the first and second transistors 316 and 317 and the first output transistors M1 are turned on, and the second output transistors M2 Not conducting. The second transistor 317 provides the output signal So at the first end thereof, and each of the enable signals OE1 and OE2 has a high logic level.

The buffer circuit 32 is electrically connected to the power supply unit 11 and the insertion unit 12 to receive the input power Vcc and the control signal output Co respectively, and is electrically connected to the power generation circuit 22 of the detection unit 2 and the detection circuit 21 to respectively receive the second power signal Vo2 and the first detection signal D1, and electrically connect the control signal generating module to receive the enabling signals OE1, OE2. When the insertion unit 12 is inserted with the second receiving card, the buffer circuit 32 is controlled and enabled by the first detection signal D1, and outputs the control signal Co and the enable signals OE1 and OE2 for buffer to generate and output the buffered output signal Bo to the display unit 13 . When the first receiving card is inserted into the insertion unit 12 , the buffer circuit 32 is controlled and disabled by the first detection signal D1 , so that the buffer circuit 32 stops outputting any signal to the display unit 13 .

Referring to FIG. 1 , FIG. 2 and FIG. 4 , the signal generating unit 4 is electrically connected to the power supply unit 11 and the insertion unit 12 to receive the input power Vcc and the image signal Dai respectively, and is electrically connected to the detection unit 2 to Receive the power output Vo and the second detection signal D2. When the insertion unit 12 is inserted with the first receiving card, the signal generating unit 4 generates and outputs the first receiving card according to the image signal Dai, the input power Vcc, the power output Vo and the second detection signal D2 A data output Da1 is sent to the display unit 13 for image display. When the insertion unit 12 is inserted with the second receiving card, the signal generating unit 4 also receives the enable signal output Eno provided by the second receiving card, and outputs Eno according to the image signal Dai, the input power Vcc, The power output Vo, the second detection signal D2, and the enable signal output Eno generate and output the second data output Da2 to the display unit 13, so that the display unit 13 outputs Da2 and the display unit 13 according to the second data The buffered output signal Bo is used for image display. In this embodiment, the enable signal output Eno includes an enable output signal En, and first and second clock signals CLK1 and CLK2. The phase of the first clock signal CLK1 is opposite to that of the second clock signal CLK2. The signal generating unit 4 includes a buffer 41 , a switch 42 , and a flip-flop circuit 43 .

The buffer 41 is electrically connected to the power supply unit 11 and the insertion unit 12 to receive the input power Vcc and the video signal Dai respectively, and is electrically connected to the power generation circuit 22 of the detection unit 2 to receive the second power Signal Vo2. The buffer 41 buffers the video signal Dai to generate a buffered signal Bs. The switch 42 is electrically connected to the power supply unit 11 and the buffer 41 to receive the input power Vcc and the buffer signal Bs respectively, and is electrically connected to the detection circuit 21 of the detection unit 2 to receive the second detection signal D2. The flip-flop circuit 43 is electrically connected to the insertion unit 12 to receive the enable output signal En and the first and second clock signals CLK1 and CLK2 , and is electrically connected to the buffer 41 and the detection unit 2 The power generation circuit 22 receives the buffer signal Bs and the first power signal Vo1 respectively. When the first receiving card is inserted into the insertion unit 12, the switch 42 is controlled and enabled by the second detection signal D2, and the flip-flop circuit 43 outputs Eno because it does not receive the enable signal. In the disabled state, the switch 42 generates the first data output Da1 according to the buffer signal Bs. When the insertion unit 12 is inserted with the second receiving card, the switch 42 is controlled and disabled by the second detection signal D2, and the flip-flop circuit 43 is controlled by the enable output signal En. Yes, at this time, the flip-flop circuit 43 generates the second data output Da2 according to the buffer signal Bs and the first and second clock signals CLK1, CLK2. In this embodiment, the switch 42 is a single pole single throw (SPST) switch. The second data output Da2 includes first and second data signals Da21, Da22. The flip-flop circuit 43 includes first and second flip-flops 431 and 432 . Each of the first and second flip-flops 431 and 432 is a D-type flip-flop.

The first flip-flop 431 is electrically connected to the insertion unit 12 to receive the enable output signal En and the first clock signal CLK1 , and is electrically connected to the buffer 41 and the power generation circuit 22 of the detection unit 2 to receive the buffered signal Bs and the first power signal Vo1 respectively. The first flip-flop 431 is controlled and enabled by the enable output signal En, and generates the first data signal Da21 according to the buffer signal Bs and the first clock signal CLK1. The second flip-flop 432 is electrically connected to the insertion unit 12 to receive the enable output signal En and the second clock signal CLK2 , and is electrically connected to the buffer 41 and the power generation circuit 22 of the detection unit 2 to receive the buffered signal Bs and the first power signal Vo1 respectively. The second flip-flop 432 is controlled and enabled by the enable output signal En, and generates the second data signal Da22 according to the buffer signal Bs and the second clock signal CLK2.

It should be noted that, since the number of data groups in the image signal Dai originally output by the second receiving card (ie, the Brompton receiving card) is not enough, the number of data groups in the second data output Da2 will be insufficient for supply. The display unit 13 is used, so when the detection circuit 21 determines that the second receiving card is inserted into the insertion unit 12, the second receiving card needs to be added through the first and second flip-flops 431 and 432. Data output The number of data sets in Da2. For example, the number of data groups in the image signal Dai originally output by the second receiving card is 12 groups. If the first and second flip-flops 431 and 432 are not passed through, the signal generation unit 4 generates The number of data sets in the second data output Da2 is also only 12 sets. However, by using the first and second flip-flops 431 and 432, the number of data sets in the second data output Da2 can be increased to 24 sets of signal outputs. In this embodiment, it is only taken as an example that the flip-flop circuit 43 includes two flip-flops 431 and 432 , but it is not limited thereto. In other embodiments, the number of flip-flops in the flip-flop circuit 43 may be greater than two.

Referring to FIG. 1 and FIG. 5 , the indicator unit 5 is electrically connected to the power supply unit 11 and the detection unit 2 to receive the input power Vcc and the first and second detection signals D1 and D2 respectively, and according to the The input power Vcc and the first and second detection signals D1 and D2 generate a light-emitting signal output Lo. In this embodiment, the light-emitting signal output Lo includes two light-emitting signals, and the indicator unit 5 includes two light-emitting circuits 51 and 52 .

Each light-emitting circuit 51, 52 is electrically connected to the power supply unit 11 to receive the input power Vcc. The light-emitting circuits 51 and 52 are also electrically connected to the detection unit 2 to receive the first and second detection signals D1 and D2 respectively (ie, each light-emitting circuit 51 and 52 receives the first and second detection signals D1 and D2 respectively). a corresponding one of the measured signals D1 and D2). The light-emitting circuit 51 generates one of the light-emitting signals (ie, a corresponding one of the light-emitting signals) according to the first detection signal D1 and the input power supply Vcc. The light-emitting circuit 52 generates the other one of the light-emitting signals according to the second detection signal D2 and the input power supply Vcc. Each of the light-emitting circuits 51 and 52 includes first to third resistors 511 - 513 , a transistor 514 , and a light-emitting diode 515 .

In each light-emitting circuit 51, 52, the first resistor 511 has a first end electrically connected to the detection unit 2 to receive the corresponding one of the first and second detection signals D1, D2, and a second end. The second resistor 512 has a first end electrically connected to the second end of the first resistor 511 and a second end. The transistor 514 has a first terminal electrically connected to the second terminal of the second resistor 512 , a second terminal connected to ground, and a control terminal electrically connected to the first terminal of the second resistor 512 . The light-emitting diode 515 is used to emit the corresponding one of the light-emitting signals, and has a cathode electrically connected to the first end of the transistor 514 and an anode. The third resistor 513 has a first end electrically connected to the power supply unit 11 for receiving the input power Vcc, and a second end electrically connected to the anode of the light emitting diode 515 . In this embodiment, when the first receiving card is inserted into the insertion unit 12, the first detection signal D1 has a high logic level, and the second detection signal D2 has a low logic level, so that the The light-emitting diode 515 of the light-emitting circuit 52 emits the light-emitting signal. When the insertion unit 12 is inserted with the second receiving card, the first detection signal D1 has a low logic level, and the second detection signal D2 has a high logic level, so that the light-emitting circuit 51 emits light. Diode 515 emits another of the light-emitting signals. The transistors 514 are each a P-type MOSFET, wherein the source, drain and gate are the first terminal, the second terminal and the gate of each of the transistors 514, respectively Control terminal.

The output unit 6 has a first signal input terminal N1 electrically connected to the insertion unit 12 to receive the image signal Dai, and a second signal input terminal electrically connected to the detection unit 2 to receive the first detection signal D1 N2, and a signal output terminal N3 electrically connected to an insertion unit (not shown) of another LED display system (the other LED display system has the same circuit structure as the LED display system 1). In this embodiment, the output unit 6 includes a third receiving card 61 and a switching unit 62 . The third receiving card is a Nova receiving card.

The third receiving card 61 has an input terminal and an output terminal electrically connected to the signal output terminal N3. The switching unit 62 has a first input terminal Q1 electrically connected to the first signal input terminal N1 to receive the image signal Dai, and a second input terminal N2 electrically connected to the second signal input terminal N2 to receive the first detection signal D1 The input terminal Q2, a first output terminal Q3 electrically connected to the input terminal of the third receiving card 61, and a second output terminal Q4 electrically connected to the signal output terminal N3. When the first receiving card is inserted into the insertion unit 12 , the switching unit 62 is controlled by the first detection signal D1 to output the image signal Dai to the third receiving card 61 via the first output terminal Q3 Backup, and output the image signal Dai to the plug-in unit of the other LED display system through the output terminal of the third receiving card 61 and the signal output terminal N3, so as to be inserted by the plug-in unit. Another first receiving card receives the image signal Dai. In this way, when the first receiving card is damaged, the image signal Dai and other related signals can be provided by the third receiving card 61 instead of the first receiving card. When the insertion unit 12 is inserted with the second receiving card, the switching unit 62 is controlled by the first detection signal D1 to output the image signal Dai through the second output terminal Q4 and the signal output terminal N3 to The insertion unit of the other LED display system receives the image signal Dai through another second receiving card inserted by the insertion unit.

To sum up, since the detection unit 2 in this embodiment can automatically determine whether the first receiving card or the second receiving card is inserted in the insertion unit 12, and output the first and second detections accordingly Signals D1, D2 and the power output Vo are used to automatically control the buffer unit 3, the signal generating unit 4 and the output unit 6 to adjust their own operations accordingly. Therefore, when the LED display system 1 needs to be replaced with a receiver of a different brand When the card is received, the automatic detection device 10 can still support, so that the LED display system 1 can still perform image display, and there is no need to redesign the LED display system according to the conventional receiving cards of different brands. It can avoid wasting research and development resources, and at the same time reduce the inventory pressure on the demand side of the LED display system. In addition, using the indicator light unit 5 to generate the light-emitting signal output Lo has the effect of enabling the user to know whether the first receiving card or the second receiving card is currently inserted in the LED display system 1 .

However, the above are only examples of the present invention, and should not limit the scope of implementation of the present invention. Any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the contents of the patent specification are still included in the scope of the present invention. within the scope of the invention patent.

1: LED display system 10: Automatic detection device 11: Power supply unit 12: Plug-in unit 13: Display unit 2: Detection unit 21: Detection circuit 211: Diode 212, 213: first and second resistors 214, 215: first and second capacitors 216, 217: first and second transistors 22: Power generation circuit 221~224: The first to fourth resistors 225, 226: first and second transistors 227: Regulator 3: Buffer unit 31: Control signal generation module 311~314: The first to fourth resistors 315: Capacitor 316, 317: first and second transistors 318: Enable signal generation circuit 319, 310: enable signal generator 32: Buffer circuit 4: Signal generation unit 41: Buffer 42: switch 43: Flip-flop circuit 431, 432: first and second flip-flops 5: Indicator unit 51, 52: Lighting circuit 511~513: 1st to 3rd resistors 514: Transistor 515: Light Emitting Diode 6: Output unit 61: The third receiving card 62: Switch unit Bo: Buffered output signal Bs: buffered signal Co: Control signal output CLK1, CLK2: the first and second clock signals D1, D2: first and second detection signals Da1, Da2: first and second data output Da21, Da22: first and second data signals Dai: video signal Eno: enable signal output En: Enable output signal Hs: high impedance signal Is1, Is2: first and second identification signals Iso: Identification signal output Lo: Lighting signal output M1, M2: first and second output transistors N1, N2: first and second signal input terminals N3: Signal output terminal OE1, OE2: enable signal Q1, Q2: first and second input terminals Q3, Q4: first and second output terminals Ro: output resistance So: output signal Vc: input voltage Vcc: input power Vo: power output Vo1, Vo2: the first and second power supply signals

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: 1 is a block diagram illustrating an embodiment of an automatic detection device of the present invention; 2 is a circuit block diagram illustrating a detection unit of this embodiment; 3 is a circuit block diagram illustrating a buffer unit of this embodiment; FIG. 4 is a block diagram illustrating a signal generating unit of this embodiment; and FIG. 5 is a circuit diagram illustrating an indicator light unit of this embodiment.

1: LED display system

10: Automatic detection device

11: Power supply unit

12: Plug-in unit

13: Display unit

2: Detection unit

3: Buffer unit

4: Signal generation unit

5: Indicator unit

6: Output unit

61: The third receiving card

62: Switch unit

Bo: Buffered output signal

Co: Control signal output

D1, D2: first and second detection signals

Da1, Da2: first and second data output

Dai: video signal

Eno: enable signal output

Hs: high impedance signal

Iso: Identification signal output

Lo: Lighting signal output

N1, N2: first and second signal input terminals

N3: Signal output terminal

Q1, Q2: first and second input terminals

Q3, Q4: first and second output terminals

Vc: input voltage

Vcc: input power

Vo: power output

Claims (12)

An automatic detection device is suitable for detecting an insertion unit in a light-emitting diode display system, the insertion unit is used for one of a first receiving card and a second receiving card to be connected with a detachable It is inserted in a way, and correspondingly outputs an image signal and an identification signal from the first and second receiving cards. When the second receiving card is inserted into the inserting unit, the inserting unit It also outputs a control signal output related to scanning display from the second receiving card, the second receiving card also receives a high impedance signal through the insertion unit, and accordingly provides an enable output through the insertion unit Signal output, the automatic detection device includes: a detection unit for receiving an input power supply and for electrically connecting the plug-in unit to receive the identification signal output, the detection unit judges that the plug-in unit is inserted with the first receiving card according to the identification signal output or the second receiving card, and generate a first detection signal and a second detection signal accordingly, and generate a power output according to the first and second detection signals and the input power supply, the first detection signal The phase of the detection signal is opposite to the phase of the second detection signal, and the phase of the first and second detection signals changes with the change of the receiving card inserted in the insertion unit, and the voltage value output by the power supply because of the first and second detection signals; a buffer unit for receiving the input power and for being electrically connected to the insertion unit to receive the control signal output, and electrically connected to the detection unit to receive the power output and the first detection signal, when the plug When the inserting unit is inserted with the second receiving card, the buffer unit generates the high-impedance signal and a set of enabling signals according to the first detection signal, outputs the high-impedance signal to the inserting unit, and also according to the first detection signal The power output and the first detection signal buffer the control signal output and the set of enabling signals to generate and output a buffered output signal to the display unit; and a signal generating unit for receiving the input power, for being electrically connected to the insertion unit to receive the image signal and the enabling signal output, and electrically connected to the detection unit to receive the power output and the second detection unit When the first receiving card is inserted into the insertion unit, the signal generating unit generates and outputs a first data output according to the image signal, the input power, the power output and the second detection signal to a display unit for image display, when the inserting unit is inserted with the second receiving card, the signal generating unit is based on the image signal, the input power supply, the power supply output, the second detection signal, and The enabling signal is output to generate and output a second data output to the display unit, so that the display unit performs image display according to the second data output and the buffer output signal. The automatic detection device as claimed in claim 1, wherein the detection unit comprises, a detection circuit for electrically connecting the plug-in unit to receive the identification signal output, and judging whether the plug-in unit is inserted with the first receiving card or the second receiving card according to the identification signal output, and generating accordingly the first and second detection signals, and a power generation circuit for receiving the input power and electrically connected to the detection circuit to receive the first and second detection signals, and to generate the first and second detection signals according to the input power and the first and second detection signals Power Output. The automatic detection device according to claim 2, wherein the identification signal output includes a first identification signal and a second identification signal, and the detection circuit includes: a diode having an anode for receiving the first identification signal, and a cathode for receiving the second identification signal, a first resistor having a first end electrically connected to the cathode of the diode, and a second end, a second resistor electrically connected between the second end of the first resistor and ground, a first capacitor electrically connected between the second end of the first resistor and ground, a first transistor having a first terminal for providing the first detection signal, a second terminal for grounding, and a control terminal electrically connected to the second terminal of the first resistor, a second capacitor electrically connected between the first end of the first transistor and ground, and A second transistor has a first terminal for providing the second detection signal, a second terminal for grounding, and a control terminal electrically connected to the first terminal of the first transistor. The automatic detection device of claim 2, wherein the power output includes a first power signal and a second power signal, and the power generation circuit includes, a first resistor having a first end and a second end receiving the first detection signal, a second resistor having a first end for receiving the input power, and a second end electrically connected to the first end of the first resistor, A first transistor having a first end electrically connected to the first end of the second resistor, a second end for providing the first power signal, and a control device for electrically connecting the second end of the second resistor end, a third resistor having a first end and a second end receiving the second detection signal, a fourth resistor, having a first end for receiving the input power, and a second end electrically connected to the first end of the third resistor, a second transistor having a first end electrically connected to the first end of the fourth resistor, a second end, and a control end electrically connected to the second end of the fourth resistor, and a voltage regulator for receiving the input power and electrically connected to the first and second ends of the second transistor, Wherein, when the second transistor is turned on, the second transistor provides the second power signal at the second end according to the input power supply, and when the second transistor is not turned on, the voltage regulator according to the input The power supply is stepped down to generate the second power supply signal. The automatic detection device according to claim 1, wherein the buffer unit comprises: A control signal generating module for electrically connecting the insertion unit and electrically connecting the detection unit to receive the first detection signal, when the insertion unit is inserted with the second receiving card, the control signal The generating module generates the high-impedance signal and the set of enabling signals according to the first detection signal, and outputs the high-impedance signal to the plug-in unit, and a buffer circuit for receiving the input power, and for being electrically connected to the plug-in unit to receive the control signal output, and electrically connected to the detection unit to receive the power output and the first detection signal, and to be electrically connected The control signal generating module receives the set of enabling signals. When the first receiving card is inserted into the insertion unit, the buffer circuit is controlled and disabled by the first detection signal. When the second receiving card is provided, the buffer circuit is controlled and enabled by the first detection signal, and buffers the output of the control signal and the set of enabling signals to generate and output the buffered output signal to the display unit. The automatic detection device as claimed in claim 5, wherein the control signal generating module comprises, a first resistor, having a first terminal electrically connected to the detection unit for receiving the first detection signal, and a second terminal connected to ground, a capacitor, electrically connected between the first end of the first resistor and the ground, a first transistor having a first terminal, a second terminal grounded, and a control terminal electrically connected to the first terminal of the first resistor, a second resistor having a first end for receiving an input voltage, and a second end electrically connected to the first end of the first transistor, The third and fourth resistors each have a first terminal for receiving the input voltage, and a second terminal, an enabling signal generating circuit electrically connecting the first end of the first transistor and the second ends of the third and fourth resistors, and providing the set of enabling signals, and a second transistor, having a first end electrically connected to the insertion unit, a second end connected to ground, and a control end electrically connected to the detection unit to receive the first detection signal, the first The two transistors are controlled by the first detection signal to provide the high impedance signal at the first end thereof. The automatic detection device as claimed in claim 6, wherein the set of enabling signals includes two enabling signals, the enabling signal generating circuit includes two enabling signal generators, and each enabling signal generator includes, a first output transistor having a first terminal electrically connected to a corresponding one of the second terminals of the third and fourth resistors, a second terminal providing a corresponding one of the enabling signals terminal, and a control terminal electrically connected to the first terminal of the first transistor, a second output transistor having a first end electrically connected to the second end of the first output transistor, a second end, and a control end electrically connected to the first end of the first transistor, and An output resistor is electrically connected between the second end of the second output transistor and the ground. The automatic detection device according to claim 1, wherein the power output includes a first power signal and a second power signal, and the signal generating unit includes, a buffer for receiving the input power, and for electrically connecting the insertion unit to receive the image signal, and electrically connecting the detection unit to receive the second power signal, the buffer buffers the image signal to generate a buffered signal, a switch for receiving the input power, electrically connected to the buffer to receive the buffered signal, and electrically connected to the detection unit to receive the second detection signal, the switch is controlled by the second detection signal generating the first data output based on the buffered signal, and a flip-flop circuit for electrically connecting the plug-in unit to receive the enabling signal output, and electrically connecting the buffer and the detection unit to receive the buffer signal and the first power signal respectively, the flip-flop The circuit is controlled and enabled by the enable signal output, and generates the second data output according to the buffer signal and the enable signal output. The automatic detection device of claim 8, wherein the enable signal output includes an enable output signal and first and second clock signals, the second data output includes a first data signal, and a first Two data signals, the flip-flop circuit includes, a first flip-flop, used for being electrically connected to the insertion unit to receive the enable output signal and the first clock signal, and electrically connected to the buffer and the detection unit to receive the buffer signal and the first clock signal respectively a power signal, the first flip-flop is controlled and enabled by the enable output signal, and generates the first data signal according to the buffer signal and the first clock signal, and a second flip-flop for electrically connecting the interposer unit to receive the enable output signal and the second clock signal, and electrically connecting the buffer and the detection unit to receive the buffer signal and the first A power signal, the second flip-flop is controlled and enabled by the enable output signal, and generates the second data signal according to the buffer signal and the second clock signal. The automatic detection device according to claim 1, further comprising: an indicator light unit for receiving the input power and electrically connected to the detection unit to receive the first and second detection signals, and to generate an indicator according to the input power and the first and second detection signals Lighting signal output. The automatic detection device according to claim 10, wherein the light-emitting signal output includes two light-emitting signals, the indicator unit includes two light-emitting circuits, and each light-emitting circuit is used for receiving the input power and electrically connected to the detection unit to receive a corresponding one of the first and second detection signals, and generate a corresponding one of the light-emitting signals according to the corresponding one of the first and second detection signals and the input power , each light-emitting circuit includes, a first resistor, having a first end electrically connected to the detection unit for receiving the corresponding one of the first and second detection signals, and a second end, a second resistor, having a first end electrically connected to the second end of the first resistor, and a second end, a transistor having a first terminal electrically connected to the second terminal of the second resistor, a second terminal connected to ground, and a control terminal electrically connected to the first terminal of the second resistor, a light-emitting diode for emitting the corresponding one of the light-emitting signals, and having a cathode electrically connected to the first end of the transistor, and an anode, and A third resistor has a first end for receiving the input power, and a second end electrically connected to the anode of the light emitting diode. The automatic detection device according to claim 1, further comprising: an output unit, having a first signal input terminal for electrically connecting the insertion unit to receive the image signal, a second signal input terminal for electrically connecting the detection unit to receive the first detection signal, and a is electrically connected to the signal output terminal of another light-emitting diode display system, and includes, a third receiving card, having an input end, and an output end electrically connected to the signal output end, and A switching unit has a first input terminal electrically connected to the first signal input terminal to receive the image signal, a second input terminal electrically connected to the second signal input terminal to receive the first detection signal, and an electrical A first output terminal connected to the input terminal of the third receiving card, and a second output terminal electrically connected to the signal output terminal. When the first receiving card is inserted into the insertion unit, the switching unit is connected to the first receiving card. The detection signal is controlled to output the image signal to the third receiving card through the first output terminal for backup, and output the image signal to the other through the output terminal and the signal output terminal of the third receiving card In a light-emitting diode display system, when the insertion unit is inserted with the second receiving card, the switching unit is controlled by the first detection signal to output the image signal through the second output end and the signal output end to the other LED display system.

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