CN115856718A - Detection circuit and equipment for detecting connector - Google Patents

Abstract

The application provides a detection circuitry and equipment for detecting connector, this detection circuitry includes: the method comprises the following steps: the system comprises a main board and a sub-board, wherein the main board is provided with a first connector and a complex programmable logic device; the daughter board includes: a second connector and a self-oscillation signal generating unit; the complex programmable logic device is connected with a first connector, the first connector is connected with a second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generating unit is connected with a power supply; the self-oscillation signal generating unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; the complex programmable logic device is used for determining whether the second connector connected with the first connector is correct or not according to the received pulse signal and the preset signal corresponding to the first connector, so that the daughter board connector connected with the connector on the mainboard can be determined based on the complex programmable logic device on the mainboard.

Description

Detection circuit and equipment for detecting connector

Technical Field

The present application relates to the field of electronics, and more particularly, to a detection circuit and apparatus for detecting a connector.

Background

At present, in an electronic device, a main board and at least one sub-board may be provided. The main board is connected with the daughter board through a connector.

In the related art, in order to ensure the accuracy of the connection between the connector of the motherboard and the daughter board, that is, to accurately connect the connector of the motherboard to the corresponding connector of the daughter board, the complex programmable logic device on the motherboard generally sends a pulse width modulation signal to the complex programmable logic device on the daughter board connected to the daughter board connector sequentially through the connector of the motherboard and the daughter board connector connected to the motherboard connector. And the complex programmable logic device on the daughter board performs frequency division processing on the received pulse width modulation signal and returns the processed signal to the complex programmable logic device on the mainboard, so that the complex programmable logic device in the mainboard performs detection according to the received signal, and the connection accuracy of the currently connected mainboard connector and the daughter board connector is determined.

However, when there is no complex programmable logic device on the daughter board, adding additional complex programmable logic device is likely to occupy more space, resulting in increased manufacturing cost of the electronic device.

Disclosure of Invention

The application provides a detection circuit and equipment for detecting a connector, which are used for solving the problem that the connector detection needs to be carried out by depending on a complex programmable logic device on a daughter board in the related art.

In a first aspect, the present application provides a detection circuit for detecting a connector, the detection circuit comprising: a main board and a sub-board,

the mainboard is provided with a first connector and a complex programmable logic device; the daughter board includes thereon: a second connector and a self-oscillation signal generating unit;

the complex programmable logic device is connected with the first connector, the first connector is connected with the second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generating unit is connected with a power supply;

the self-oscillation signal generating unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; the complex programmable logic device is used for determining whether a second connector connected with the first connector is correct or not according to the received pulse signal and a preset signal corresponding to the first connector.

In one possible implementation, the self-oscillation signal generating unit includes: the first NOT gate module, the first resistor and the first capacitor;

the input end of the first NOT gate module is respectively connected with the first end of the first resistor and the first end of the first capacitor; the second end of the first capacitor is grounded; the output end of the first NOT gate module is respectively connected with the second end of the first resistor and the second connector; and the power supply end of the first NOT gate module is connected with the power supply.

In one possible implementation, the self-oscillation signal generating unit further includes: a second resistor and a second capacitor;

the first end of the second capacitor is respectively connected with the power supply end of the first NOT gate module and the power supply; the second end of the second capacitor is grounded;

a first end of the second resistor is connected with an output end of the first not gate module and a second end of the first resistor respectively, and a second end of the second resistor is connected with the second connector; and the output end of the first NOT gate module is connected with the second connector through the second resistor.

In a possible implementation manner, the number of the first connectors arranged on the main board is multiple; the daughter board includes thereon: the second connectors are connected with the first connectors in a one-to-one corresponding mode, and the self-oscillation signal generating units are connected with the second connectors in a one-to-one corresponding mode;

the pulse signals correspondingly generated by different self-oscillation signal generating units are different.

In a possible implementation manner, a third connector is arranged on the main board; the daughter board is provided with a fourth connector and a third resistor;

the first input end of the third connector and the first output end of the third connector are respectively connected with the complex programmable logic device; a second output end of the third connector is connected with a first input end of the fourth connector; a first output end of the fourth connector is connected with a first end of the third resistor; a second end of the third resistor is connected with a second input end of the fourth connector, and a second output end of the fourth connector is connected with a second input end of the third connector;

the complex programmable logic device is used for sending a pulse width modulation signal to the fourth connector through the third connector, and the fourth connector is used for returning the pulse width modulation signal received by the second connector to the complex programmable logic device through the third connector;

the complex programmable logic device is further used for determining whether a fourth connector connected with the third connector is correct or not according to the pulse modulation signal sent by the third connector and the pulse width modulation signal returned by the third connector.

In a possible implementation manner, a fifth connector is arranged on the main board; the daughter board is provided with a sixth connector and an inverter circuit;

the first input end of the fifth connector and the first output end of the fifth connector are respectively connected with the complex programmable logic device; a second output end of the fifth connector and a first input end of the sixth connector are respectively connected with the complex programmable logic device; a first output end of the sixth connector is connected with an input end of the inverter circuit, an output end of the inverter circuit is connected with a second input end of the sixth connector, and a second output end of the sixth connector is connected with a second input end of the fifth connector;

the complex programmable logic device is used for sending a pulse width modulation signal to the sixth connector through the fifth connector, and the inverter circuit is used for performing inversion processing on the phase of the pulse width modulation signal and sending the processed signal to the complex programmable logic device through the sixth connector and the fifth connector;

the complex programmable logic device is further used for determining whether a sixth connector connected with the fifth connector is correct according to the pulse modulation signal sent by the fifth connector and the pulse width modulation signal returned by the fifth connector.

In one possible implementation, the inverter circuit includes: the triode, the fourth resistor, the fifth resistor and the sixth resistor;

the first end of the triode is respectively connected with the first end of the fourth resistor and the second input end of the sixth connector; the second end of the fourth resistor is connected with a power supply;

the second end of the triode is respectively connected with the first end of the fifth resistor and the first end of the sixth resistor; the third end of the triode is connected with the second end of the fifth resistor and then grounded; and the second end of the sixth resistor is connected with the first output end of the sixth connector.

In one possible implementation, the inverter circuit includes: the diode, the second NOT gate module, the seventh resistor and the third capacitor;

the anode of the diode is connected with the first output end of the sixth connector; the cathode of the diode is respectively connected with the first end of the seventh resistor, the first end of the third capacitor and the input end of the second NOT gate module; a second end of the seventh resistor and a second end of the third capacitor are connected and then grounded; the power supply end of the second NOT gate module is connected with a power supply; and the output end of the second NOT gate module is connected with the second input end of the sixth connector.

In one possible implementation, the inverter circuit further includes: a fourth capacitor and an eighth resistor;

the first end of the fourth capacitor is connected with the power supply end of the second NOT gate module and the power supply respectively; a second end of the fourth capacitor is grounded;

a first end of the eighth resistor is connected with an output end of the second not gate module; a second end of the eighth resistor is connected with a second input end of the sixth connector; and the output end of the second NOT gate module is connected with the second input end of the sixth connector through the eighth resistor.

In a second aspect, the present application provides an electronic device comprising the detection circuit of any one of the first aspects.

The application provides a detection circuitry and equipment for detecting connector, this detection circuitry includes: the method comprises the following steps: the system comprises a main board and a sub-board, wherein the main board is provided with a first connector and a complex programmable logic device; the daughter board includes thereon: a second connector and a self-oscillation signal generating unit; the complex programmable logic device is connected with the first connector, the first connector is connected with the second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generating unit is connected with a power supply; the self-oscillation signal generating unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; the complex programmable logic device is used for determining whether a second connector connected with the first connector is correct or not according to the received pulse signal and a preset signal corresponding to the first connector. In the application, the self-oscillation signal generating unit can be arranged on the daughter board, and the generated pulse signal is sent to the complex programmable logic device on the mainboard, so that the complex programmable logic device on the mainboard can be compared through detecting the received pulse signal and the preset signal corresponding to the first connector for receiving the pulse signal, and if the comparison result is the same, the first connector is indicated to be accurately connected. Furthermore, the problem that the received signals cannot be processed when no complex programmable logic device exists in the daughter board can be solved through the detection circuit. And furthermore, the problem of large occupied space caused by the need of additionally adding a complex programmable logic device on the daughter board can be avoided. And after the second connector connected with the first connector is identified, the type of the daughter board where the second connector is located can be further determined, and the connection relationship of the connectors between the main board and the daughter board can be further determined.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic structural diagram of a detection circuit provided in the present application;

fig. 2 is a schematic structural diagram of a detection circuit for detecting a connector according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a second detection circuit for detecting a connector according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a third detection circuit for detecting a connector according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a fourth detection circuit for detecting a connector according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a fifth detection circuit for detecting a connector according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a sixth detection circuit for detecting a connector according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an inverter circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a second inverter circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a third inverter circuit according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a seventh detection circuit for detecting a connector according to this embodiment.

Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. The drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the concepts of the application by those skilled in the art with reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application.

Currently, in an electronic device, a main board and at least one sub-board are generally provided. For example, devices on a motherboard are used to implement core functions of an electronic device. The devices on the daughter board are used to implement additional functions of the electronic device. When the motherboard is connected to the daughter board, the motherboard is usually connected to the daughter board in a one-to-one correspondence via a connector of the motherboard.

In the related art, in order to ensure the accuracy of the connection between the motherboard and the connectors of the daughter board, that is, the connectors on the motherboard are correspondingly connected to the daughter board connectors corresponding to the connectors of the motherboard, a detection circuit is provided. As shown in fig. 1, fig. 1 is a schematic structural diagram of a detection circuit provided in the present application. The detection circuit shown in fig. 1 is a schematic circuit structure provided in the related art, as shown in fig. 1, fig. 1 includes a motherboard and a daughter board, where the motherboard includes a first Complex Programmable Logic Device (CPLD), and a connector 1. The daughter board includes a second CPLD thereon, as well as a connector 2. Wherein the connector 1 is connected with the connector 2. In order to detect the accuracy of connection between the connector 1 and the connector 2, that is, whether the connector 2 is a connector on a daughter board to which the connector 1 should be connected, at this time, the first CPLD sequentially passes through the connector 1 and the connector 2, and sends a PWM (Pulse width modulation) signal to the second CPLD, so that the second CPLD performs frequency division processing on the received PWM signal, and returns the processed signal to the first CPLD sequentially passes through the connector 2 and the connector 1. After the first connector receives the processed signal, the ratio of the frequencies of the PWM signal sent by the first connector and the received processed signal is compared, and if the frequency ratio meets the preset requirement, the connection relationship between the connector 1 and the connector 2 is represented correctly. If the preset requirement is not met, the connection relation between the connector 1 and the connector 2 is indicated to be wrong.

However, when the daughter board does not include the second CPLD chip, the accuracy of the connector connection cannot be detected, and if the second CPLD chip is added to the daughter board, the connector easily occupies more space resources, which is not favorable for improving the integration level of the electronic device.

The application provides a detection circuit for detecting a connector, which is used for solving the technical problem.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 2 is a schematic structural diagram of a detection circuit for detecting a connector according to an embodiment of the present application, and as shown in fig. 2, the apparatus includes: the detection circuit includes: the system comprises a main board and a sub-board, wherein the main board is provided with a first connector and a complex programmable logic device; the daughter board includes: a second connector and a self-oscillation signal generating unit; the complex programmable logic device is connected with a first connector, the first connector is connected with a second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generating unit is connected with a power supply; the self-oscillation signal generating unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; the complex programmable logic device is used for determining whether a second connector connected with the first connector is correct or not according to the received pulse signal and a preset signal corresponding to the first connector.

Illustratively, the detection circuit provided in this embodiment includes a main board and a sub board. The daughter board is provided with a self-oscillation signal generating unit, wherein the self-oscillation signal generating unit is connected with the power supply and is used for receiving the power supply signal output by the power supply (indicated by STB in the figure). And when the self-oscillation signal generating unit is in a power supply state, the self-oscillation signal generating unit can generate the pulse signal under the action of no external excitation. And then, the self-oscillation signal generating unit sequentially passes through a second connector on a daughter board connected with the self-oscillation signal generating unit, a first connector on a mainboard connected with the second connector and a complex programmable logic device connected with the first connector, and the generated pulse signal is transmitted to the programmable logic device.

When the programmable logic device receives the pulse signal returned by the first connector, a preset signal corresponding to the first connector is searched, the preset signal is compared with the pulse signal returned by the first connector, and if the pulse signal returned by the first connector is determined to be the same as the preset signal corresponding to the first connector, at this moment, it is determined that the first connector is currently in a connected state, and the second connector connected with the first connector is the connector corresponding to the first connector, namely, the connector connected with the first connector is represented to be correct. If the pulse signal returned by the first connector is determined to be different from the preset signal corresponding to the first connector, it indicates that the current connection mode of the first connector is wrong, that is, the currently connected second connector is not the connector to which the first connector should be connected. It should be noted that the circuit configuration of the self-oscillation signal generating unit in the present embodiment is not particularly limited.

It can be understood that, in this embodiment, the self-oscillation signal generating unit may be disposed on the sub board, and the generated pulse signal may be sent to the complex programmable logic device on the main board, so that the complex programmable logic device on the main board may compare the received pulse signal with a preset signal corresponding to the first connector that receives the pulse signal by detecting the received pulse signal, and if the comparison result is the same, it indicates that the first connector is connected accurately. Furthermore, the problem that the received signals cannot be processed when no complex programmable logic device exists in the daughter board can be solved through the detection circuit. And furthermore, the problem of large occupied space caused by the need of additionally adding a complex programmable logic device on the daughter board can be avoided. And after the second connector connected with the first connector is identified, the type of the daughter board where the second connector is located can be further determined, and the connection relationship of the connectors between the mainboard and the daughter board can be further determined.

In some embodiments, fig. 3 is a schematic structural diagram of a second detection circuit for detecting a connector according to an embodiment of the present disclosure. As shown in fig. 3, in the present embodiment, on the basis of the device configuration shown in fig. 2, the self-oscillation signal generating unit includes: the first NOT gate module, the first resistor and the first capacitor; the input end of the first NOT gate module is respectively connected with the first end of the first resistor and the first end of the first capacitor; the second end of the first capacitor is grounded; the output end of the first NOT gate module is respectively connected with the second end of the first resistor and the second connector; the power supply end of the first NOT gate module is connected with a power supply.

Illustratively, the self-oscillation circuit in the detection circuit provided in the present embodiment is composed of a first not gate module, a first resistor, and a first capacitor. In fig. 3, the first resistor is denoted by R1; the first capacitor is marked by C1, and the first NOT gate module is marked by U1. The input end (marked by a port A in the figure) of the first NOT gate module is connected to the output end (marked by a port Y in the figure) of the first NOT gate module through a first resistor, the input end of the first NOT gate module is also connected with a first capacitor, and the second end of the first capacitor is grounded. In addition, the output end of the first NOT gate module is connected with a second connector on the daughter board. The power supply terminal (denoted by VCC in the figure) of the first not gate module is connected with a power supply source.

When the first not gate module is in a power supply state, at this time, if a signal output by the output end of the first not gate module is at a low level, because the input end of the first not gate module is connected with the output end of the first not gate module through the first resistor, a low level signal received by the input end of the first not gate module carries out level conversion on the received low level signal, and then a high level signal output by the first not gate module. Further, when the first not gate module outputs a high level signal, at this time, the input end of the first not gate module also receives the high level signal output by the first not gate module, and performs level conversion processing on the received high level signal, so that the output end of the first not gate module outputs a low level signal again, and the above process is repeated continuously, thereby forming a pulse signal. In addition, the output end of the first not gate module is also connected with the second connector, so that the second connector can receive the pulse signal output by the first not gate module, and the complex programmable logic device on the mainboard can receive the pulse signal through the second connector and the first connector.

In addition, in this embodiment, the pulse width of the pulse signal generated by the first not gate module may be adjusted by adjusting the resistance value of the first resistor and/or the capacitance value of the first capacitor.

It can be understood that, in the present embodiment, the self-oscillating signal generating unit is composed of the first not gate module, the first resistor, and the first capacitor, and the circuit has a simple structure and is easy to implement, and no external stimulus needs to be input.

In some embodiments, fig. 4 is a schematic structural diagram of a third detection circuit for detecting a connector according to an embodiment of the present application, and as shown in fig. 4, on the basis of the apparatus structure shown in fig. 3, the self-oscillation signal generating unit in this embodiment further includes: a second resistor and a second capacitor; the first end of the second capacitor is connected with the power supply end of the first NOT gate module and the power supply respectively; the second end of the second capacitor is grounded; the first end of the second resistor is respectively connected with the output end of the first NOT gate module and the second end of the first resistor, and the second end of the second resistor is connected with the second connector; the output end of the first NOT gate module is connected with the second connector through a second resistor.

Exemplarily, on the basis of the above-mentioned embodiment, the self-oscillation signal generating unit in the present embodiment further includes a second resistor and a second capacitor, where the second resistor is denoted by R2 and the second capacitor is denoted by C2 in fig. 4. The output end of the first not gate module is connected with the second end of the first resistor and the first end of the second resistor respectively, and the second end of the second resistor is connected with the second connector, so that a pulse signal output by the first not gate module can be transmitted to the input end of the first not gate module through the first resistor on the one hand, and can be transmitted to the second connector through the second resistor on the other hand, and then a current limiting effect can be achieved through the second resistor, so that the phenomenon that a device is damaged due to the fact that the current value of the transmitted signal is large is avoided.

In addition, at the power supply input end of first not gate module, can also connect the second electric capacity, wherein, the first end of second electric capacity is connected with power supply and the power supply input end of first not gate module respectively, and the second end ground connection of second electric capacity, and then can carry out the filtering action to the power supply signal of power supply output to maintain power supply signal's stability, and then ensure the normal work of first not gate module.

It can be understood that, in this embodiment, the second capacitor may be arranged to ensure stability of the power supply signal input to the first not gate module, and further, the second resistor may be arranged to limit the current of the signal output by the first not gate module, so as to ensure safety of the device in the detection circuit.

In some embodiments, fig. 5 is a schematic structural diagram of a fourth detection circuit for detecting connectors according to an embodiment of the present disclosure, and as shown in fig. 5, on the basis of the structure of the detection circuit shown in fig. 2, in this embodiment, the number of the first connectors disposed on the motherboard is plural; the daughter board includes: the second connectors are connected with the first connectors in a one-to-one corresponding mode, and the self-oscillation signal generating units are connected with the second connectors in a one-to-one corresponding mode; the pulse signals correspondingly generated by different self-oscillation signal generating units are different.

For example, on the basis of the apparatus shown in fig. 2, the number of the first connectors connected to the complex programmable logic device in this embodiment may be multiple, and fig. 5 takes 3 first connectors (i.e., the first connector 1, the first connector 2, and the first connector 3 in the figure) as an example for description. At this time, 3 second connectors (i.e., the second connector 1, the second connector 2, and the second connector 3 in the drawing) and 3 self-oscillation signal generating units (i.e., the self-oscillation signal generating unit 1, the self-oscillation signal generating unit 2, and the self-oscillation signal generating unit 3 in the drawing) may also be provided on the daughter board. The first connectors are connected with the second connectors in a one-to-one corresponding mode, and the second connectors are connected with the self-oscillation signal generating units in a one-to-one corresponding mode. Wherein different self-oscillating signal generating units can be used for generating different pulse signals. Furthermore, the complex programmable logic device on the mainboard can determine which second connector is currently connected with the first connector by detecting the pulse signal returned by the first connector, thereby determining the connection accuracy of the first connector.

In some embodiments, fig. 6 is a schematic structural diagram of a fifth detection circuit for detecting a connector according to an embodiment of the present disclosure, as shown in fig. 6, based on the structure of the detection circuit shown in fig. 2, in this embodiment, a third connector is disposed on a motherboard; the daughter board is provided with a fourth connector and a third resistor; the first input end of the third connector and the first output end of the third connector are respectively connected with the complex programmable logic device; the second output end of the third connector is connected with the first input end of the fourth connector; a first output end of the fourth connector is connected with a first end of the third resistor; the second end of the third resistor is connected with the second input end of the fourth connector, and the second output end of the fourth connector is connected with the second input end of the third connector; the complex programmable logic device is used for sending a pulse width modulation signal to the fourth connector through the third connector, and the fourth connector is used for returning the pulse width modulation signal received by the second connector to the complex programmable logic device through the third connector; the complex programmable logic device is also used for determining whether a fourth connector connected with the third connector is correct according to the pulse modulation signal sent by the third connector and the pulse width modulation signal returned by the third connector.

For example, as shown in fig. 6, in this embodiment, the main board may further include a third connector, and the daughter board may be provided with a fourth connector and a third resistor (denoted by R3 in the figure). The first output end of the fourth connector is connected with the third resistor, and the complex programmable logic device on the mainboard can transmit a pulse modulation signal to the first end of the third resistor sequentially through the first input end of the third connector, the second output end of the third connector and the first input end of the fourth connector. After the pulse modulation signal passes through the third resistor, the pulse modulation signal sequentially passes through a second input end of a fourth connector connected with a second end of the third resistor, a second output end of the fourth connector, a second input end of a third connector connected with a second output end of the fourth connector and a first output end of the third connector, and the pulse modulation signal is returned to the complex programmable logic device connected with a first output end of the third connector.

In practical application, the resistance value of the third resistor may be 0 ohm, and further, through the connection relationship among the third connector, the fourth connector and the third resistor, after the complex programmable logic device sends the pulse modulation signal to the third resistor through the third connector and the fourth connector, the pulse modulation signal may be directly returned to the complex programmable logic device.

It will be appreciated that by providing a third resistor at the connector of the daughter board so that the pulse width and duty cycle of the returned pulse modulated signal do not change after the pulse modulated signal is received by the connector, the subsequent complex programmable logic device can determine whether to connect to the fourth connector as shown in the figure by whether the sent signal and the returned signal are the same.

In some embodiments, fig. 7 is a schematic structural diagram of a sixth detection circuit for detecting a connector according to an embodiment of the present disclosure, and as shown in fig. 7, on the basis of the structure of the detection circuit shown in fig. 2, a fifth connector is further disposed on a motherboard; the daughter board is also provided with a sixth connector and an inverter circuit; the first input end of the fifth connector and the first output end of the fifth connector are respectively connected with the complex programmable logic device; the second output end of the fifth connector and the first input end of the sixth connector are respectively connected with the complex programmable logic device; a first output end of the sixth connector is connected with an input end of the inverter circuit, an output end of the inverter circuit is connected with a second input end of the sixth connector, and a second output end of the sixth connector is connected with a second input end of the fifth connector; the complex programmable logic device is used for sending a pulse width modulation signal to the sixth connector through the fifth connector, the phase inverter circuit is used for performing inversion processing on the phase of the pulse width modulation signal, and the processed signal is sent to the complex programmable logic device through the sixth connector and the fifth connector; the complex programmable logic device is also used for determining whether the sixth connector connected with the fifth connector is correct according to the pulse modulation signal sent by the fifth connector and the pulse width modulation signal returned by the fifth connector.

Illustratively, as shown in fig. 7, on the basis of the schematic structural diagram shown in fig. 2, in this embodiment, a fifth connector is further disposed on the main board, and a sixth connector and an inverter circuit are further disposed on the sub board.

The complex programmable logic device on the mainboard can be connected with the first input end of the fifth connector, the second output end of the fifth connector is connected with the first input end of the sixth connector, the first output end of the sixth connector is connected with the phase inverter circuit, and then the complex programmable logic device on the mainboard can sequentially pass through the first input end of the fifth connector, the second output end of the fifth connector and the first input end of the sixth connector to be connected, and the first output end of the sixth connector transmits the pulse modulation signal to the first end of the phase inverter circuit. After the pulse modulation signal passes through the inverter circuit, the pulse modulation signal processed by the inverter circuit is returned to the complex programmable logic device connected with the first output end of the fifth connector through the second input end of the sixth connector connected with the second end of the inverter circuit, the second output end of the sixth connector, the second input end of the fifth connector connected with the second output end of the sixth connector and the first output end of the fifth connector in sequence.

The inverter circuit is used for performing phase inversion processing on the received pulse width modulation signals, namely converting high-level signals in the pulse width modulation signals into low-level signals, converting low-level signals in the pulse width modulation signals into high-level signals, and returning the processed signals to the complex programmable logic device.

When the complex programmable logic device determines that the phase of the signal transmitted by the complex programmable logic device is exactly opposite to that of the received signal, the connected connector can be determined to be the sixth connector shown in the figure.

It can be understood that, in the embodiment, by providing an inverter circuit at the connector of the daughter board, after the pulse modulation signal received by the connector 5, the received pulse modulation signal can be inverted, so as to facilitate the process of inverting the received pulse modulation signal

The subsequent complex programmable logic device can determine whether to connect to the sixth connector shown in the figure by whether the phase between the transmitted signal and the returned signal is opposite.

In some embodiments, fig. 8 is a schematic structural diagram of an inverter circuit provided in the embodiments of the present application, where the inversion is performed

The device circuit includes: the triode, the fourth resistor, the fifth resistor and the sixth resistor; the first end of the triode is respectively connected with the first end of the fourth resistor 0 and the second input end of the sixth connector; the second end of the fourth resistor is connected with a power supply; three poles

The second end of the tube is respectively connected with the first end of the fifth resistor and the first end of the sixth resistor; the third end of the triode is connected with the second end of the fifth resistor and then grounded; and the second end of the sixth resistor is connected with the first output end of the sixth connector.

Illustratively, the inverter circuit provided in the present embodiment may be composed of one transistor and three resistors (i.e., a fourth resistor)

A resistor, a fifth resistor, and a sixth resistor). For example, as shown in fig. 8, the fourth resistor, the fifth resistor 5 and the sixth resistor in fig. 8 are R4, R5 and R6, respectively. The first end of the triode and the first end and the second end of the fourth resistor

And the second input end of the sixth connector is connected and used for outputting the processed pulse width signal to the sixth connector. And a second resistor of the fourth resistor is connected to a power supply (identified by STB in the figure). In addition, the second end of the third connector is connected with the first output end of the sixth connector through a sixth resistor, and is used for receiving the pulse width modulation signal received by the sixth connector.

In addition, the first end of the fifth resistor is respectively connected with the first end of the sixth resistor and the second end of the triode, and the 0 th end of the fifth resistor is connected with the third end of the triode and then grounded.

When the pulse width modulation signal received by the sixth connector is transmitted to the second end of the triode through the sixth resistor, at the moment, the triode can determine whether the triode is conducted or not according to the level of the received pulse width modulation signal; when the pulse width signal received by the second end of the triode is a high level signal, at the moment, the triode is in a conducting state,

the first end of the triode outputs a low level signal; when the pulse width signal received by the second end of the triode is a signal in a low level state 5, at this time, the triode is in a turn-off state (namely, a cut-off state), and the first end of the triode outputs a high level signal.

Furthermore, an inverter circuit is formed by the triode and the three resistors, so that the function of inverting the phase of the received pulse modulation signal is realized.

In one example, the inverter circuit can also be formed by PNP type triodes; or a mos tube may be adopted, and the specific principle can be referred to in the related art, which is not described herein.

In some embodiments, fig. 9 is a schematic structural diagram of a second inverter circuit provided in the embodiments of the present application, where the inverter circuit includes: the inverter circuit includes: the diode, the second NOT gate module, the seventh resistor and the third capacitor; the anode of the diode is connected with the first output end of the sixth connector; the cathode of the diode is respectively connected with the first end of the seventh resistor, the first end of the third capacitor and the input end of the second NOT gate module; the second end of the seventh resistor and the second end of the third capacitor are grounded after being connected; the power supply end of the second NOT gate module is connected with a power supply; and the output end of the second NOT gate module is connected with the second input end of the sixth connector.

Exemplarily, in the present embodiment, an anode of a diode (denoted by D1 in the figure) in the inverter circuit is used for connecting the first output terminal of the sixth connector, and is used for receiving the pulse width modulation signal received by the sixth connector. The cathode of the diode is respectively connected with a first end of a seventh resistor (marked by R7 in the figure), a first end of a third capacitor (marked by C3 in the figure) and an input end (marked by A in the figure) of a second NOT gate module (marked by U2 in the figure), and a second end of the seventh resistor and a second end of the third capacitor are grounded after being connected, wherein the third capacitor and the seventh resistor are used for pulling down the level of the input end of the second NOT gate module when no signal is output at the cathode of the diode. In addition, the power supply end of the second not gate module is connected with the power supply and used for receiving the power supply signal output by the power supply, and the output end of the second not gate module is connected with the second input end of the sixth connector and used for outputting the adjusted signal to the sixth connector.

When the signal level received by the anode of the diode is at a high level, the signal is transmitted to the input end of the second not gate module through the diode, and after being processed by the second not gate module (i.e., the signal level is converted into a low level), the processed signal is transmitted to the sixth connector. When the signal level received by the anode of the diode is low level, the diode is cut off, and at the moment, the level of the input end of the second not gate module is pulled down by the seventh resistor and the third capacitor, so that the second not gate module inputs a high level signal. And when the cathode of the diode does not receive a signal, the second not gate module also inputs a high level signal at the moment.

It is understood that in the present embodiment, the diode, the seventh capacitor, the third resistor, and the second not gate module are provided to form an inverter circuit, so that the subsequent complex programmable logic device can determine whether to connect to the sixth connector by determining whether the phase of the transmitted signal is opposite to that of the returned signal.

In some embodiments, fig. 10 is a schematic structural diagram of a third inverter circuit provided in the embodiments of the present application, and based on the device structure shown in fig. 9, the inverter circuit in this embodiment further includes: a fourth capacitor and an eighth resistor; the first end of the fourth capacitor is connected with the power supply end of the second NOT gate module and the power supply respectively; the second end of the fourth capacitor is grounded; the first end of the eighth resistor is connected with the output end of the second NOT gate module; a second end of the eighth resistor is connected with a second input end of the sixth connector; and the output end of the second NOT gate module is connected with the second input end of the sixth connector through an eighth resistor.

Illustratively, in this embodiment, on the basis of the embodiment shown in fig. 9, the inverter circuit further includes a fourth capacitor (denoted by C4 in the figure) and an eighth resistor (denoted by R8 in the figure).

The first end of the fourth capacitor is connected to the power supply section and the power supply of the second not gate module respectively, and the fourth capacitor is used for filtering the power supply signal output by the power supply so that the second not gate module can receive the stable power supply signal. In addition, the output terminal of the second not gate module may be connected to the second input terminal of the sixth connector through an eighth resistor, wherein the eighth resistor is used for performing a current limiting function so as to protect devices in the circuit.

In some embodiments, the first output terminal of the sixth connector may also be connected to an anode of a diode in the inverter circuit through a ninth resistor to perform a current limiting function.

In some embodiments, the complex programmable logic device in the motherboard may be connected to a baseboard management controller in the electronic device, so that the baseboard management controller may obtain a determination result of whether the connector connection determined by the complex programmable logic device is correct, so that a user may be notified in time. In practical application, the complex programmable logic device and the baseboard management controller can communicate in an IIC manner.

In some embodiments, fig. 11 is a schematic structural diagram of a seventh detection circuit for detecting a connector provided in this embodiment, as shown in fig. 5, on the basis of the schematic structural diagram shown in fig. 5, in this embodiment, a main board may further include a third connector and a fifth connector; the daughter board may further include a sixth connector, a fourth connector, a third resistor, and an inverter circuit, and specific connection relationships may be referred to in the description of the foregoing embodiments. In practical applications, the two pulse width modulation signals sent by the complex programmable logic circuit to the third connector and the fifth connector may be two signals with different duty ratios. For the specific principle of this embodiment, reference may be made to the description in the above embodiments, which is not described herein again.

The present embodiment provides an electronic device including the detection circuit shown in any one of the above embodiments. In practical applications, the electronic device may be a server device.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A detection circuit for detecting a connector, the detection circuit comprising: a main board and a sub-board,

the mainboard is provided with a first connector and a complex programmable logic device; the daughter board includes thereon: a second connector and a self-oscillation signal generating unit;

the complex programmable logic device is connected with the first connector, the first connector is connected with the second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generating unit is connected with a power supply;

the self-oscillation signal generating unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; the complex programmable logic device is used for determining whether a second connector connected with the first connector is correct or not according to the received pulse signal and a preset signal corresponding to the first connector.

2. The detection circuit according to claim 1, wherein the self-oscillating signal generating unit includes: the first NOT gate module, the first resistor and the first capacitor;

the input end of the first not gate module is respectively connected with the first end of the first resistor and the first end of the first capacitor; the second end of the first capacitor is grounded; the output end of the first NOT gate module is respectively connected with the second end of the first resistor and the second connector; and the power supply end of the first NOT gate module is connected with the power supply.

3. The detection circuit according to claim 2, wherein the self-oscillating signal generating unit further comprises: a second resistor and a second capacitor;

the first end of the second capacitor is respectively connected with the power supply end of the first NOT gate module and the power supply; the second end of the second capacitor is grounded;

a first end of the second resistor is connected with an output end of the first not gate module and a second end of the first resistor respectively, and the second end of the second resistor is connected with the second connector; and the output end of the first NOT gate module is connected with the second connector through the second resistor.

4. The detection circuit according to claim 1, wherein the number of the first connectors provided on the main board is plural; the daughter board includes thereon: the second connectors are connected with the first connectors in a one-to-one corresponding mode, and the self-oscillation signal generating units are connected with the second connectors in a one-to-one corresponding mode;

the pulse signals correspondingly generated by different self-oscillation signal generating units are different.

5. The detection circuit of claim 1, wherein a third connector is disposed on the motherboard; the daughter board is provided with a fourth connector and a third resistor;

the first input end of the third connector and the first output end of the third connector are respectively connected with the complex programmable logic device; a second output end of the third connector is connected with a first input end of the fourth connector; a first output end of the fourth connector is connected with a first end of the third resistor; a second end of the third resistor is connected with a second input end of the fourth connector, and a second output end of the fourth connector is connected with a second input end of the third connector;

the complex programmable logic device is used for sending a pulse width modulation signal to the fourth connector through the third connector, and the fourth connector is used for returning the pulse width modulation signal received by the second connector to the complex programmable logic device through the third connector;

and the complex programmable logic device is also used for determining whether a fourth connector connected with the third connector is correct or not according to the pulse modulation signal sent by the third connector and the pulse width modulation signal returned by the third connector.

6. The detection circuit according to claim 1, wherein a fifth connector is provided on the main board; the daughter board is provided with a sixth connector and an inverter circuit;

the first input end of the fifth connector and the first output end of the fifth connector are respectively connected with the complex programmable logic device; a second output end of the fifth connector and a first input end of the sixth connector are respectively connected with the complex programmable logic device; a first output end of the sixth connector is connected with an input end of the inverter circuit, an output end of the inverter circuit is connected with a second input end of the sixth connector, and a second output end of the sixth connector is connected with a second input end of the fifth connector;

the complex programmable logic device is used for sending a pulse width modulation signal to the sixth connector through the fifth connector, and the inverter circuit is used for performing inversion processing on the phase of the pulse width modulation signal and sending the processed signal to the complex programmable logic device through the sixth connector and the fifth connector;

the complex programmable logic device is further used for determining whether a sixth connector connected with the fifth connector is correct according to the pulse modulation signal sent by the fifth connector and the pulse width modulation signal returned by the fifth connector.

7. The detection circuit of claim 6, wherein the inverter circuit comprises: the triode, the fourth resistor, the fifth resistor and the sixth resistor;

the first end of the triode is respectively connected with the first end of the fourth resistor and the second input end of the sixth connector; the second end of the fourth resistor is connected with a power supply;

the second end of the triode is respectively connected with the first end of the fifth resistor and the first end of the sixth resistor; the third end of the triode is connected with the second end of the fifth resistor and then grounded; and the second end of the sixth resistor is connected with the first output end of the sixth connector.

8. The detection circuit of claim 6, wherein the inverter circuit comprises: the diode, the second NOT gate module, the seventh resistor and the third capacitor;

the anode of the diode is connected with the first output end of the sixth connector; the cathode of the diode is respectively connected with the first end of the seventh resistor, the first end of the third capacitor and the input end of the second NOT gate module; a second end of the seventh resistor and a second end of the third capacitor are connected and then grounded; the power supply end of the second NOT gate module is connected with a power supply; and the output end of the second NOT gate module is connected with the second input end of the sixth connector.

9. The detection circuit of claim 8, wherein the inverter circuit further comprises: a fourth capacitor and an eighth resistor;

the first end of the fourth capacitor is respectively connected with the power supply end of the second NOT gate module and the power supply; a second end of the fourth capacitor is grounded;

a first end of the eighth resistor is connected with an output end of the second not gate module; a second end of the eighth resistor is connected with a second input end of the sixth connector; and the output end of the second NOT gate module is connected with the second input end of the sixth connector through the eighth resistor.

10. An electronic device, characterized in that it comprises a detection circuit according to any one of claims 1-9.

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