TW202225964A - A method and a communication interface controller for restoring communication interface interruption - Google Patents

Abstract

A method for restoring communication interface interruption between chips is disclosed. The communication interface includes a data line and a clock line. The method includes detecting whether the signal on the data line or the clock line is interrupted; detecting whether an interruption time of the signal on the data line or the clock line is longer than a predetermined time; determining whether to perform an error recovery action according to whether the interruption time is longer than the predetermined time, so that the data line and the clock line return to an initial state.

Description

Method for recovering interruption of communication interface and communication interface controller

The present invention relates to a method for recovering the interruption of a communication interface, and more particularly, to a method for recovering the interruption of an integrated bus circuit (Inter-Integrated Circuit: I ² C).

During the transmission process of the integrated bus circuit (I ² C), when the serial data (SDA) signal and the serial clock (SCL) signal are interrupted due to external factors, abnormal signal events (such as signal hang ( hang up)), causing the system to stall.

In the existing mechanism, under normal circumstances, the command can be re-issued through the software to make the I ² C restart. However, under certain timings, the bus will still be pulled and cannot be released, resulting in system stagnation and I ² C restarting through software commands.

According to a method for recovering interruption of a communication interface between chips according to an embodiment of the present invention, the communication interface includes a data line and a clock line, and the method includes: detecting whether a signal on the data line or the clock line is interrupted; detecting whether the data line or the time line is interrupted; Whether an interruption time of the signal on the pulse line is greater than a preset time; according to whether the interruption time is greater than the preset time, it is determined whether to perform an error recovery action, so that the data line and the pulse line return to an initial state.

The method as described above, wherein, when the interruption time is greater than the preset time, an error recovery action is performed, including: determining that the data line or the clock line has entered an error state; forcibly releasing the data line and/or the clock line; clearing the entry error All error flags generated during the state; return the data line and the clock line to the initial state, so that the communication interface is ready to transmit the next signal.

In the above method, when it is detected that the data line and the signal on the clock line are not interrupted, it is determined whether the communication interface has completed the transmission of the signal.

In the above method, when it is determined that the communication interface has completed the signal transmission, the signal transmission of the communication interface is stopped, and the data line and the clock line are released, so that the data line and the clock line return to the initial state.

The above method, wherein, when it is determined that the communication interface has not completed the signal transmission, the signal transmission of the communication interface is continued until the communication interface has completed the signal transmission, or it is detected that the signal on the data line or the clock line has been interrupted. , or the interruption time of the signal on the data line or clock line is detected to be longer than the preset time.

In the method as described above, wherein the communication interface is an integrated busbar circuit (Inter-Integrated Circuit: I ² C). The data line is a serial data (SDA) line. The clock line is a serial clock (SCL) line.

According to the communication interface controller of the embodiment of the present invention, the communication interface controller is used for recovering the interruption of a communication interface between chips. The communication interface includes a data line and a clock line. The communication interface controller includes a control unit and a timing unit. The control unit detects whether the signal on the data line or the clock line is interrupted. The timing unit detects whether an interruption time of the signal on the data line or the clock line is greater than a predetermined time. The control unit determines whether to perform an error recovery action according to whether the interruption time detected by the timing unit is greater than the preset time, so that the data line and the clock line return to an initial state.

The communication interface controller as described above, wherein when the interruption time is greater than the preset time, the control unit performs an error recovery action, including: determining that the data line or the clock line has entered an error state; forcibly releasing the data line and/or the clock line ;Clear all error flags generated when entering the error state; return the data line and clock line to the initial state, so that the communication interface is ready to transmit the next signal.

According to the above communication interface controller, when the control unit detects that the signal on the data line and the clock line is not interrupted, it determines whether the communication interface has completed the transmission of the signal.

As in the above communication interface controller, when the control unit determines that the communication interface has completed the signal transmission, it stops the signal transmission of the communication interface, and releases the data line and the clock line, so that the data line and the clock line return to the initial state.

The communication interface controller as described above, wherein the communication interface controller is an integrated bus circuit (Inter-Integrated Circuit: I ² C) controller. The communication interface is an integrated busbar circuit. The data line is a serial data (SDA) line. The clock line is a serial clock (SCL) line.

The invention is described with reference to the accompanying drawings, wherein like reference numerals designate similar or identical elements throughout. The above drawings are not drawn to actual scale, but merely provide an illustration of the present invention. Some aspects of the invention are described below as references to illustrate exemplary applications. This means that many specific details, relationships and methods are set forth to provide a complete understanding of the invention. In any event, one having ordinary knowledge in the relevant art will recognize that the invention may be practiced without one or more of the specific details or otherwise.

In other instances, well-known structures or operations have not been listed in detail to avoid obscuring the invention. The invention is not limited by the recited acts or order of events, as some acts may occur in a different order or concurrently with other acts or events. Furthermore, not all recited acts or events need to be performed in the same way as prior inventions.

FIG. 1 is a flowchart of a method for recovering a communication interface interruption between chips according to an embodiment of the present invention. In some embodiments, the communication interface is an integrated bus circuit (Inter-Integrated Circuit: I ² C) interface, which is a bus widely used for chip-to-chip communication. The I ² C interface includes a serial data (Serial Data: SDA) line and a serial clock (Serial Clock: SCL) line. The serial data line is used to transmit the communication data or address between chips, and the serial clock line is used to transmit the clock signal. As shown in FIG. 1, the method for recovering the interruption of the communication interface (eg, I ² C) of the present invention first starts to transmit data (step S100 ). In some embodiments, in step S100 , the method for recovering the interruption of the communication interface of the present invention transmits a start signal from a master terminal (Master) to a slave terminal (Slave). For example, when step S100 is performed in the method for recovering the interruption of the communication interface of the present invention, the start signal of the I ² C interface may be, for example, the serial data (SDA) line changes from high level to low level, and the serial The column clock (SCL) remains high. When the slave end receives the start signal from the master end, the slave end knows that the master end will start to transmit data.

Next, the method for recovering the interruption of the communication interface (eg, I ² C) of the present invention executes the I ² C data transmission (step S102 ). In some embodiments, the method of the present invention can transmit data from the master to the slave at different transmission rates. For example, the host can operate in standard mode (100 kbit/s), fast mode (400 kbit/s), fast mode (1 Mbit/s), high speed mode (3.4 Mbit/s) Bytes/sec), and Super Fast Mode (5 megabits/sec). In contrast, the method of the present invention can correspondingly adjust the timing of serial data and serial clock to meet the requirements of different transmission rates.

In the method for recovering the interruption of the communication interface of the present invention, in step S104, it is detected whether the signal on the serial clock (SCL) line is interrupted. When it is detected that the signal on the serial clock (SCL) line is not interrupted, the method of the present invention directly proceeds to step S108. When it is detected that the signal on the serial clock (SCL) line is interrupted, the method of the present invention executes step S106. Next, in step S106, the method of the present invention detects whether an interruption time of the signal on the serial clock (SCL) line is greater than a predetermined time, and according to whether the interruption time of the signal on the serial clock (SCL) line is not greater than the preset time, to decide whether to proceed to step S112 or step S108. When the interruption time of the signal on the serial clock (SCL) line is not greater than the preset time in step S106, the method of the present invention executes step S108. When the interruption time of the signal on the serial clock (SCL) line is greater than the preset time in step S106, the method of the present invention executes an error recovery action of steps S112-S118.

When the signal on the serial clock (SCL) line is not interrupted in step S104, or the interruption time of the signal on the serial clock (SCL) line in step S106 is not greater than the predicted time, the method of the present invention executes step S108 . In step S108, the method of the present invention then detects whether the signal on the serial data (SDA) line is interrupted. When it is detected in step S108 that the signal on the serial data (SDA) line is not interrupted, the method of the present invention directly proceeds to step S120. When it is detected in step S108 that the signal on the serial data (SDA) line is interrupted, the method of the present invention executes step S110. Next, in step S110, the method of the present invention detects whether the interruption time of the signal on the serial data (SDA) line is greater than the preset time, and according to whether the interruption time of the signal on the serial data (SDA) line is greater than the preset time , to decide whether to go to step S112 or step S120.

When the interruption time of the signal on the serial data (SDA) line in step S110 is not greater than the preset time, the method of the present invention executes step S120. When the interruption time of the signal on the serial data (SDA) line in step S110 is greater than the preset time, the method of the present invention executes the error recovery actions of steps S112 - S118 . In some embodiments, the preset time in step S106 and step S110 may be 3-5 seconds, but the present invention is not limited thereto. In some embodiments, the method of the present invention may first execute step S108, and when step S108 is "Yes", execute step S110. When step S110 is "No", the method of the present invention executes step S104 and/or step S106 again. In other words, the sequence of step S104 and step S108 in the method of the present invention can be interchanged, so the sequence of step 106 and step S110 can also be adjusted accordingly.

When the interruption time of the signal on the serial clock (SCL) line in step S106 is greater than the preset time, or the interruption time of the signal on the serial data (SDA) line in step S110 is greater than the preset time, the method of the present invention will Perform error recovery actions. In the error recovery action, the method of the present invention executes step S112 to enter an error state. In the error state, the method of the present invention will then execute step S114 to forcibly release the state of the serial data (SDA) line and the serial clock (SCL) line. For example, the method of the present invention will force the voltages of the serial data (SDA) line and the serial clock (SCL) line back to a high level. Afterwards, the method of the present invention executes step S116 to clear the error flag (flag) generated in the error state.

In some embodiments, during the I ² C communication process, when the I ² C controller of the master (Master) or the slave (Slave) finds that the communication is abnormal, such as serial data or serial clock interruption, When data transmission times out, the I ² C controller will generate corresponding error codes or status codes. In other words, the user can know the current I ² C communication status by observing the error code or status code (eg, in the form of a flag) generated by the I ² C controller of the master or slave. The method for recovering the interruption of the communication interface of the present invention clears all error flags in step S116, the purpose of which is to allow the I ² C controller of the master or slave to connect the serial data (SDA) line and/or the serial clock The (SCL) line state returns to an initial state (eg, a pull high state). After that, the method of the present invention can execute step S118 to return to the initial state, and after receiving another start signal, return to step S100 again to continue to perform another round of data transmission.

Returning to FIG. 1 , when it is detected in step S108 that the signal on the serial data (SDA) line is not interrupted, or in step S110 it is detected that the interruption time of the signal on the serial data (SDA) line is not greater than At the preset time, the method of the present invention executes step S120 for confirming that the data transmission has been completed. In some embodiments, the method of the present invention confirms whether there is an end signal in the transmission signal of the I2C interface in step S120. For example, the method of the present invention will confirm whether the serial data (SDA) signal in the I ² C interface changes from a low level to a high level in step S120 and whether the serial clock (SCL) signal remains high. level. When it is confirmed in step S120 that there is an end signal, that is, it is confirmed that the I ² C data transmission has been completed, the method of the present invention continues to execute step S122. When it is confirmed in step S120 that there is no end signal, that is, it is confirmed that the I ² C data transmission is not completed, the method of the present invention returns to step S 102 to continue the I ² C data transmission.

Next, the method of the present invention executes step S122 to stop the data transmission of the I ² C interface. Finally, the method of the present invention executes step S124 to release the state of the serial data (SDA) line and the serial clock (SCL) line. In some embodiments, the method of the present invention pulls the signal of the data (SDA) line and/or the serial clock (SCL) line to a high level, and returns to the step after receiving another start signal S100, for continuing to perform another round of data transmission.

In some embodiments, the method of the present invention executes steps S100 , S102 , S104 , S108 , S120 , S120 , and S122 when there is no external interference (ie, no signal interruption is detected). , and step S124. In other words, if the transmission is not interrupted by external force, the method of the present invention will not execute step S106, step S110, step S112, step S114, step S116, and step S118. In other words, in the case of normal transmission, the method of the present invention will not consume extra time.

In some embodiments, if an external force is involved in the transmission process, such as the serial data (SDA) line or the serial clock (SCL) line is pulled up, the serial data (SDA) signal or serial clock (SCL) ) signal will be pulled up (hang up), resulting in interruption of the transmission and entering into step S106 and step S110. When the interruption time in step S106 or step S110 is greater than the preset time, the method of the present invention will execute steps S112-S118. In some embodiments, during the transmission process, when the serial data (SDA) line or the serial clock (SCL) line is unplugged and reconnected, an action time consumed is longer than the preset time of step S106 or step S110 time, the method of the present invention will execute steps S112-S118. Therefore, the additional time consumed by the method of the present invention will be greater than the preset time.

In some embodiments, during the transmission process, when the serial data (SDA) line or the serial clock (SCL) line is unplugged and reconnected, the action time consumed is less than or equal to the preset time of step S106 or step S110 time, and the serial data (SDA) signal and serial clock (SCL) signal can resume normal transmission, the method of the present invention does not execute steps S112-S118. Therefore, the additional time consumed by the method of the present invention will be less than or equal to the preset time. In some embodiments, during the transmission process, when the serial data (SDA) line or the serial clock (SCL) line is unplugged and reconnected, the action time consumed is less than or equal to the preset time of step S106 or step S110 time, but the time for the serial data (SDA) signal and serial clock (SCL) signal to resume normal transmission is longer than the preset time, the method of the present invention must execute steps S112-S118. Therefore, the additional time consumed by the method of the present invention will be equal to the preset time.

FIG. 2 is a schematic diagram of a communication interface controller 200 according to an embodiment of the present invention. As shown in FIG. 2 , the communication interface controller 200 includes a timing unit 202 , a control unit 204 , a serial data interface 206 , and a serial clock interface 208 . In some embodiments, the communication interface controller 200 is disposed within a chip A. Similarly, another communication interface controller 250 also includes a timing unit 252 , a control unit 254 , a serial data interface 256 , and a serial clock interface 258 . In some embodiments, the communication interface controller 250 is disposed within a chip B. The serial data interface 206 of the communication interface controller 200 is electrically connected to the serial data interface 256 of the communication interface controller 250 through a serial data line SDA. The serial clock interface 208 of the communication interface controller 200 is electrically connected to the serial clock interface 258 of the communication interface controller 250 through a serial clock line SCL. Therefore, the communication interface controller 200 can communicate with the communication interface controller 250 through the I ² C interface. In other words, wafer A can communicate with wafer B.

Since the operating system of the communication interface controller 200 is the same as that of the communication interface controller 250 , the communication interface controller 200 is only used as an example. The control unit 204 of the communication interface controller 200 detects whether the signal on the serial data line SDA or the serial clock line SCL is interrupted, ie, the step S104 or the step S108 in FIG. 1 is executed. Next, when the control unit 204 detects that the signal on the serial data line SDA or the serial clock line SCL is interrupted, the timing unit 202 of the communication interface controller 200 detects the serial data line SDA or the serial clock line Whether the interruption time of the signal on the SCL is greater than a predetermined time, that is, step S106 or step S110 is executed.

Next, the control unit 204 determines whether to perform an error recovery operation according to whether the interruption time detected by the timing unit 202 is greater than the preset time, so that the serial data line SDA or the serial clock line SCL returns to an initial state. In some embodiments, the control unit 204 performs error recovery operations including: determining that the serial data line SDA or the serial clock line SCL has entered an error state (step S112 in FIG. 1 ), forcibly releasing the serial data line SDA, and /or the serial clock line SCL (step S114 in FIG. 1), clear all error flags generated when entering the error state (step S116 in FIG. 1), and connect the serial data line SDA or the serial clock The line SCL returns to the initial state, so that the communication interface (eg, the I ² C interface) is ready to transmit the next signal (step S118 in FIG. 1 ).

In some embodiments, when the control unit 204 detects that the signals of the serial data line SDA and/or the serial clock line SCL are not interrupted (steps S104 and S108 in FIG. 1 are both “No”), the control unit 204 controls The unit 204 determines whether the communication interface has completed the signal transmission (step S120 in FIG. 1 ). When the control unit 204 determines that the communication interface has completed the signal transmission (“Yes” in step S120 in FIG. 1 ), it stops the signal transmission in the communication interface (step S122 in FIG. 1 ), and releases the serial data line SDA or serial The serial clock line SCL (step S124 in FIG. 1 ) returns the serial data line SDA or the serial clock line SCL to the initial state.

In some embodiments, when the timing unit 202 detects that the interruption time of the signals on the serial data line SDA and the serial clock line SCL is not greater than the predetermined time (step S106 and step S110 in FIG. 1 are “No” ”), the control unit 204 determines whether the communication interface has completed the signal transmission (step S120 in FIG. 1 ). In some embodiments, when the timing unit 202 detects that the interruption time of the signal on the serial data line SDA or the serial clock line SCL is longer than a predetermined time (step S106 or step S110 in FIG. 1 is “Yes”) , the control unit 204 executes an error recovery action (steps S112 to S118 in FIG. 1 ).

The method for recovering the interruption of the communication interface and the communication interface controller of the present invention establish an error detection and recovery mechanism in the transmission mechanism of the I ² C interface, so that the hardware (such as the communication interface controllers 200 and 250 in FIG. 2 ) ) During I ² C data transmission, it can continuously detect error status. When it is judged to be in an error state, force all bus bars (such as serial data lines or serial clock lines) to be automatically released and return to the initial state, so that the system (such as chips A, B) can resume I ² C. Data transfer.

Although embodiments of the present invention have been described above, it should be understood that the above are presented by way of example only, and not limitation. Many changes to the above-described exemplary embodiments in accordance with this embodiment can be implemented without departing from the spirit and scope of the invention. Accordingly, the breadth and scope of the present invention should not be limited by the above-described embodiments. Rather, the scope of the invention should be defined by the following claims and their equivalents.

While the above-described invention has been illustrated and depicted by one or more relevant implementations, equivalent changes and modifications will occur to others skilled in the art in light of the above-described specification and drawings. Furthermore, although a particular feature of the embodiments of the invention has been demonstrated by one of the associated implementations, the above-described feature may be combined with one or more other features as may be required and helpful for any known or special Applications.

Unless otherwise defined, all terms (including technical or scientific terms) used herein are generally understood by those of ordinary skill in the art pertaining to the above invention. We should be more aware that the above terms, such as those defined in commonly used dictionaries, should be interpreted as the same in the context of the related art. Unless expressly defined herein, the above terms are not to be construed in an idealized or overly formal sense.

S100, S102, S104: Steps S106, S108, S110: Steps S112, S114, S116: Steps S118, S120, S122: Steps S124: Steps 200: Communication interface controller 202: Timing Unit 204: Control Unit 206: Serial Data Interface 208: Serial Clock Interface SDA: Serial Data Line SCL: Serial Clock Line 250: Communication interface controller 252: Timing Unit 254: Control Unit 256: Serial Data Interface 258: Serial Clock Interface

FIG. 1 is a flowchart of a method for recovering a communication interface interruption between chips according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a communication interface controller according to an embodiment of the present invention.

S100, S102, S104: Steps

S106, S108, S110: Steps

S112, S114, S116: Steps

S118, S120, S122: Steps

S124: Steps

Claims (11)

A method for recovering interruption of a communication interface between chips, the communication interface comprising a data line and a clock line, the method comprising: Detect whether the signal on the data line or the clock line is interrupted; Detecting whether an interruption time of the signal on the data line or the clock line is greater than a preset time; Whether or not to perform an error recovery action is determined according to whether the interruption time is greater than the preset time, so that the data line and the clock line return to an initial state. The method of claim 1, wherein when the interruption time is greater than the preset time, performing the error recovery action includes: determine that the data line or the clock line has entered an error state; forcibly release the data line and/or the clock line; Clear all error flags generated when entering this error state; The data line and the clock line are returned to the initial state, so that the communication interface is ready to transmit the next signal. The method of claim 1, wherein, when it is detected that the signals on the data line and the clock line are not interrupted, it is determined whether the communication interface has completed the signal transmission. The method of claim 1, wherein when it is determined that the communication interface has completed the signal transmission, the signal transmission of the communication interface is stopped, and the data line and the clock line are released, so that the data line and the clock line return to this initial state. The method of claim 1, wherein, when it is determined that the communication interface has not completed the transmission of the signal, the signal transmission of the communication interface is continued until the communication interface has completed the transmission of the signal, or the data line is detected or when The signal on the pulse line has been interrupted, or the interruption time of the signal on the data line or the clock line is detected to be greater than the preset time. The method of claim 1, wherein the communication interface is an integrated bus circuit (Inter-Integrated Circuit: I ² C); the data line is a serial data (SDA) line; and the clock line is a Serial Clock (SCL) line. A communication interface controller is used to restore the interruption of a communication interface between chips, the communication interface includes a data line and a clock line; the communication interface controller includes: a control unit to detect whether the signal on the data line or the clock line is interrupted; a timing unit for detecting whether an interruption time of the signal on the data line or the clock line is greater than a preset time; Wherein, the control unit determines whether to perform an error recovery action according to whether the interruption time detected by the timing unit is greater than the preset time, so that the data line and the clock line return to an initial state. The communication interface controller of claim 7, wherein when the interruption time is greater than the preset time, the control unit performs the error recovery action, including: determine that the data line or the clock line has entered an error state; forcibly release the data line and/or the clock line; Clear all error flags generated when entering this error state; The data line and the clock line are returned to the initial state, so that the communication interface is ready to transmit the next signal. According to the communication interface controller of claim 7, when the control unit detects that the signals on the data line and the clock line are not interrupted, it is determined whether the communication interface has completed the signal transmission. The communication interface controller of claim 9, wherein when the control unit determines that the communication interface has completed the signal transmission, it stops the signal transmission of the communication interface, and releases the data line and the clock line, so that the data line and the clock line returns to the initial state. The communication interface controller of claim 7, wherein the communication interface controller is an integrated bus circuit (Inter-Integrated Circuit: I ² C) controller; the communication interface is an integrated bus circuit; the data line is a serial data (SDA) line; and the clock line is a serial clock (SCL) line.

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