TWI653580B - Mother board with multi master control chips and the method switching the controlling order - Google Patents

Abstract

A motherboard having a multi-master wafer includes a first master chipset, a second master chipset, a controlled hardware, and a basic input-output system. The first master chipset is configured to output a first driving signal including a first data signal. The second master chipset is configured to output a second driving signal. The controlled hardware is driven by the first drive signal or the second drive signal. The basic input and output system includes a basic input and output module and a switching module. When the second master chipset is ready to be activated, the switching module determines that the first master chipset outputs the first data signal, generates a stop signal to the second master chipset, so that the second driver signal is temporarily unable to be issued, and is broken. When the first master chipset no longer outputs the first data signal, an actuation signal is issued to cause the second master chipset to issue a second drive signal.

Description

Motherboard with multi-master wafer and method for switching control sequence

The present invention relates to the field of communication protocols, and more particularly to a motherboard having a multi-master wafer and a method of switching control sequences.

A serial interface of communication sinks on a computer system, usually containing a master chipset and a plurality of controlled hardware. For example, the master chipset may already be a central processing unit (CPU), or other control chip, etc., and the controlled hardware may be a memory chip, a hard disk, or the like. The serial interface includes at least a timing signal (Clock) transmission channel and a data signal (Data) transmission channel, and the main control chip group and the controlled hardware are connected to the serial timing signal transmission channel and the data signal transmission channel. Connected to each other in series. The master chipset can control the controlled hardware by transmitting a transmission position signal, a timing signal, and a data signal.

When only a single master chipset is present, the controlled hardware operation specified in the address signal is actuated by first outputting the address information and subsequently issuing the timing signal (Clock) and the data signal (Data). . However, the demand for computer hardware has increased, and sometimes in order to increase hardware auxiliary operations, such as boosting, overclocking, etc., other master chipsets are usually provided on the serial interface to assist, such as embedded controllers ( Embedded Controller, EC). However, with two master chipsets at the same time, there is a possibility of signal transmission conflicts. For example, since the transmission of the data signal and the timing signal are connected in series, the first master chipset issues a high voltage level to a controlled terminal, and the second master chipset simultaneously issues a low voltage level, which causes Console Making a wrong judgment may even lead to a crash and it is impossible to act. Therefore, solving signal conflicts is a major issue in today's hardware communication serial interface.

In order to solve the problems faced by the prior art, a motherboard having a multi-master wafer is provided herein. A motherboard having a plurality of master wafers includes a first master chipset, a second master chipset, a plurality of controlled hardware, and a basic input/output system (BIOS). The first master chipset is configured to output a plurality of first driving signals, wherein the first driving signal includes a first data signal. The second master chipset is configured to output a plurality of second drive signals. The controlled hardware is electrically connected to the first master chip set and the second master chip set, receives the first driving signal or the second driving signal, and operates according to the first driving signal or the second driving signal. The basic input/output system includes a basic input/output module to switch modules. The basic input/output module is configured to detect the states of the first master chipset, the second master chipset, and the controlled hardware. The switching module is electrically connected to the first main control chip group and the second main control chip group, and detects an operation state of the first main control chip group, and determines whether the first main control chip group outputs the first data signal. When the second master chipset is ready to be activated, the switching module determines that the first master chipset outputs the first data signal, and generates a stop signal to the second master chipset, so that the second driver signal is temporarily unavailable. When the second master chipset is ready to be activated, the switching module determines that the first master chipset no longer outputs the first data signal, and sends an actuation signal to the second master chipset to cause the second driver signal to be emitted.

In some embodiments, the first master chipset includes a central processor and a north bridge chipset. The second master chipset includes an embedded controller and a south bridge chipset.

In some embodiments, a motherboard having a multi-master wafer further includes a comparison circuit. Comparing the circuit connection switching module, the comparison circuit includes a comparator, the comparator including at least a first input terminal, a second input terminal, and a first output terminal. The first input end is electrically connected to the first main control chip set, the second input end is electrically connected to the reference voltage, and the first output end is electrically connected to the switching module. Further, when the first main control chip group outputs the first data signal, the first output end outputs a low voltage level, and when the first main control chip group no longer outputs the first data signal, the first output end outputs a high voltage level . Further, when the switching module receives the low voltage level, a stop signal is generated, and when the switching module receives the high voltage level, an enable signal is generated.

In other embodiments, the comparison circuit includes an AC to DC converter in addition to the comparator. The AC-DC converter includes a third input end and a third output end, wherein the third input end is electrically connected to the first main control chip set, and the third output end is electrically connected to the first input end of the comparator.

In other embodiments, the comparison circuit includes a comparator, an AC to DC converter, and a voltage follower, the voltage follower including a fourth input, a fifth input, and a fourth output. The fourth input end is electrically connected to the first main control chip set, and the fourth output end is electrically connected to the third input end and the fifth input end of the AC-DC converter.

A method for switching the control sequence is further provided. The method for switching the control sequence includes: starting a basic input/output system, performing a system initialization operation; and detecting, by the basic input/output system, the first master chipset and the second master chipset. Actuating state, and detecting whether the first main control chip group outputs the first data signal; when detecting the preparation of the second main control chip group, and determining that the first main control chip group outputs the first data signal, the basic input is The output system generates a stop signal to the second master chipset to stop the second master chipset; and when determining the preparation of the second master chipset, and determining that the first master chipset no longer outputs the first data During the signal, the basic input/output system generates an enable signal to the second master chipset, enabling the second master chipset to operate.

In some embodiments, the method for switching the control sequence further includes: detecting, by the comparison circuit, an actuation state of the first master chipset, the comparison circuit is connected to the basic input/output system, and when the comparison circuit detects the output of the first master chipset When the first data signal is output, the low voltage level is output. When the comparison circuit detects that the first control chip group no longer outputs the first data signal, it outputs a high voltage level. Further, when the basic input/output system receives the low voltage level, a stop signal is generated, and the basic input/output system receives the high voltage level generation enable signal.

Through the basic input/output system as the judgment and comparison mechanism, it is possible to determine whether the secondary master chipset starts to operate according to the output of the data signal of the first master chipset, thereby prioritizing the data signal transmission, thereby avoiding more The master chip simultaneously transmits the data signal, causing a hardware interpretation error, causing an abnormality or crash.

1‧‧‧Board with multi-master wafer

10‧‧‧First master chipset

11‧‧‧Central processor

13‧‧‧Northbridge Chipset

20‧‧‧Second master chipset

15‧‧‧Power Controller

21‧‧‧ embedded controller

23‧‧‧Southbridge Chipset

31‧‧‧System Memory

32‧‧‧ Hard disk

33‧‧‧ keyboard

34‧‧‧ Mouse

35‧‧‧ display

40‧‧‧Basic input and output system

41‧‧‧Switch Module

43‧‧‧Basic input and output modules

45‧‧‧Read-only memory

50‧‧‧Comparative circuit

510‧‧‧ Comparator

511‧‧‧ first input

513‧‧‧ second input

515‧‧‧ first output

520‧‧‧AC DC Converter

521‧‧‧ third input

523‧‧‧ third output

530‧‧‧Voltage follower

531‧‧‧ fourth input

533‧‧‧ fifth input

535‧‧‧ fourth output

Add1‧‧‧first address signal

V _REF ‧‧‧reference voltage

Add2‧‧‧second address signal

C1‧‧‧ capacitor

Clock1‧‧‧ first timing signal

Clock2‧‧‧Second timing signal

Data1‧‧‧First data signal

Data2‧‧‧second data signal

R1, R2, R3, R4, R5‧‧‧ resistors

V _DD1 ‧‧‧first positive voltage

V _DD2 ‧‧‧first positive voltage

V _G1 ‧‧‧second negative voltage

V _G2 ‧‧‧second negative voltage

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

OPA1‧‧‧First Operational Amplifier

OPA2‧‧‧Second Operational Amplifier

S1‧‧‧How to switch control sequences

S10‧‧‧Start basic input/output system and perform system initialization

S20‧‧‧Detecting the actuation state of the first master chipset and the second master wafer

S30‧‧‧ Whether the first master chipset outputs the first data signal

S41‧‧‧ generates an enable signal to activate the second master chipset

S43‧‧‧ generates a stop signal to stop the second master chipset

S51‧‧‧Comparative circuit output high voltage level

S53‧‧‧Comparative circuit output low voltage level

The above and other exemplary embodiments, advantages and features of the present invention will become more apparent from the detailed description of the exemplary embodiments of the invention. A schematic diagram of the unit of the embodiment.

2 is a schematic diagram of a second embodiment of a motherboard having a multi-master wafer.

3 is a schematic diagram of a unit of the comparison circuit of FIG. 2.

4 is a circuit diagram of the comparator of FIG.

FIG. 5 is a schematic diagram of the voltage of the AC-DC converter of FIG.

Figure 6 is a circuit diagram of the voltage follower of Figure 3.

Figure 7 is a flow chart of a method of switching control sequences.

1 is a schematic diagram of a first embodiment of a motherboard having a multi-master wafer. As shown in FIG. 1, the motherboard 1 having a multi-master wafer of the first embodiment includes at least a first master chipset 10, a second master chipset 20, a plurality of controlled hardware, and a basic input/output system. (BIOS) 40. The first master chipset 10 is configured to output a plurality of first driving signals, where the first driving signal includes a first timing signal Clock1, a first data signal Data1, and a first address Signal Add1 and so on. The second master chipset 20 is configured to output a plurality of second driving signals, for example, a second timing signal Clock1, a second data signal Data2, a second address signal Add2, and the like. The controlled hardware, for example, the system memory 31, the hard disk 32, the keyboard 33, the mouse 34, the display 35, and the like, are merely examples, and are not limited thereto. For example, the second master chipset 20 receives the power of the power controller 15, and can output a drive signal to the power controller 15. The controlled hardware is electrically connected to the first master chip set 10 and the second master chip set 20, and receives the first driving signal or the second driving signal, and according to the first driving signals or the second driving signals And act.

The basic input/output system (BIOS) 40 can be stored in the read-only memory 45 and executed as a whole as a hardware. The basic input and output system 40 is electrically coupled to the first master wafer set 10, the second master wafer set 20, and the controlled hardware. The basic input/output system 40 includes a basic input/output module 43 and a switching module 41. The basic input/output module 43 can be combined with a software to detect the states of the first master chip set 10, the second master chip set 20, and the controlled hardware. The switching module 41 is electrically connected to the first main control chip set 10 and the second main control chip set 20, and detects the active state of the first main control chip set 10, and determines whether the first main control chip set 10 outputs the first Data signal Data1. When the second master chipset 20 is ready to be activated, and the first master chipset 10 is determined to output the first data signal Data1, the switching module 41 generates a stop signal to the second master chipset 20 to enable the second driver. The signal is temporarily unavailable. When the second master chipset 20 is ready to be activated, and it is determined that the first master chipset 10 no longer outputs the first data signal Data1, the coincidence signal is sent to the second master chipset 20 to make the second driving signal. issue.

In more detail, the first master wafer set 10 includes a central processing unit 11 and a north bridge chip set 13, and the second master control chip set 20 includes an embedded controller (EC) 21 and a south bridge chip set 23. This is merely an example and is not limited to this.

2 is a schematic diagram of a second embodiment of a motherboard having a multi-master wafer. 3 is a schematic diagram of a unit of the comparison circuit of FIG. 2. as shown in picture 2. In the second embodiment, The motherboard 1 having a multi-master wafer includes at least a first master chip set 10, a second master chip set 20, a plurality of controlled hardware, and a basic input/output system 40 further including a comparison circuit 50. The comparison circuit 50 is electrically connected to the first master chipset 10 and the basic input/output system 40 to assist the basic input/output system 40 to detect whether the first master chipset 10 outputs the first data signal Data1 and provide it as a judgment. Basis. As shown in FIG. 3, comparison circuit 50 may only include comparator 510. In still other embodiments, the comparison circuit 50 can include a comparator 510 and an AC to DC converter 520. In some embodiments, comparison circuit 50 can also include comparator 510, AC to DC converter 520, and voltage follower 530, as described herein.

4 is a circuit diagram of the comparator of FIG. 3. In the embodiment in which the comparison circuit 50 only includes the comparator 510, the comparator 510 is a combination of the first operational amplifier OPA1 and the resistors R1, R2. The first operational amplifier OPA1 includes a first input terminal 511, a second input terminal 513, and a first output terminal 515. The first input end 511 is electrically connected to the first main control chip set 10, the second input end 513 is connected to the reference voltage V _REF , and the first output end 515 is electrically connected to the switching module 41 . The positive and negative electrodes of the first operational amplifier OPA1 are respectively connected to the first positive voltage V _DD1 and the first negative voltage V _G1 . At this time, the first input terminal 511 serves as an input terminal of the comparison circuit 50, and the first output terminal 515 serves as an output terminal of the comparison circuit 50.

When the first master chipset 10 outputs the first data signal Data1, the first output terminal 515 outputs a low voltage level, and when the first master chipset 10 no longer outputs the first data signal Data1, the first Output 515 outputs a high voltage level. When the switching module 41 receives the low voltage level, a stop signal is generated to suspend the output of the second driving signal, and when the switching module 41 receives the high voltage level, an enabling signal is generated to cause the second main control chip. Group 20 transmits a second drive signal.

For example, the first positive voltage V _{DD1 in} FIG. 4 can be set to 5V, the first negative voltage V _G1 is 0V, the reference voltage V _REF is 2.5V, and the reference voltage V _REF can be divided by the first positive voltage V _DD1 . Pressure. When the first master chipset 10 does not output the first data signal Data1, the input voltage Vin input from the first master chipset 10 to the first input terminal 511 is 3.3V, and the input voltage Vin is compared after the comparator amplifier is compared. It is greater than the reference voltage V _REF , and therefore, the output voltage Vout outputted by the first output terminal 515 is at a high voltage level, for example, the first positive voltage V _DD1 (5V). On the other hand, when the first master chipset 10 outputs the first data signal Data1, since the first data signal Data1 has fluctuations in the data level, the input voltage Vin of the first input terminal 511 is about 1.65V. The input voltage Vin is smaller than the reference voltage V _REF after the comparison of the operational amplifier, and therefore, the output voltage Vout outputted by the first output terminal 515 is at a low voltage level, for example, the first negative voltage V _G1 (0 V). In this case, the electrical connections can be connected directly or indirectly. The above is merely an example and is not limited thereto.

FIG. 5 is a schematic diagram of the voltage of the AC-DC converter of FIG. As shown in FIGS. 2 through 5, the comparison circuit 50 can include a comparator 510 and an AC to DC converter 520. As shown in FIG. 5, the AC-DC converter 520 can be an RC circuit in which a resistor R3 and a capacitor C1 are combined, and can be used as a filter. The AC to DC converter 520 includes a third input terminal 521 and a third output terminal 523. The third input end 521 is electrically connected to the first main control chip set 10 and the third output end 523 is electrically connected to the first input end 511. At this time, the third input terminal 521 serves as an input terminal of the comparison circuit 50, and the first output terminal 515 serves as an output terminal of the comparison circuit 50. In this case, the electrical connections can be connected directly or indirectly.

Through the AC-DC converter 520, the AC signal can be taken for a time segment and filtered to form a DC level. Can increase the accuracy of the judgment. Here, if the first master chipset 10 does not output the first data signal Data1, after being filtered by the AC-DC converter 520, the voltage level of 3.3V can be output from the third output terminal 523 to the first input terminal 511. As the input voltage Vin. And if the first master chipset 10 outputs the first data signal Data1, the third loser The output terminal 523 outputs a voltage level of approximately 1.65 V to the first input terminal 511 as an input voltage Vin.

Figure 6 is a circuit diagram of the voltage follower of Figure 3. As shown in FIGS. 2-6, the comparison circuit 50 can include a comparator 510, an AC to DC converter 520, and a voltage follower 530. As shown in FIG. 6, the voltage follower 530 can be a non-inverting amplifying combination circuit in which the comparator 510 is the second operational amplifier OPA2 and the resistors R4, R5. The voltage follower 530 includes a fourth input 531, a fifth input 533, and a fourth output 535. The positive and negative electrodes of the second operational amplifier OPA2 are respectively connected to the second positive voltage V _DD2 and the second negative voltage V _G2 . The fourth input end 531 is electrically connected to the first main control chip set 10 , and the fourth output end 535 is electrically connected to the third input end 521 , and is further electrically connected to the first input end 511 of the comparator 510 . At the same time, the fourth output end 535 is electrically connected to the fifth input end 533. At this time, the fourth input terminal 531 serves as an input terminal of the comparison circuit 50, and the first output terminal 515 serves as an output terminal of the comparison circuit 50. The input of the second operational amplifier OPA2 has substantially no current flowing in, and can be regarded as inductive infinity, and is separated from the signal of the comparator 510 and the AC-DC converter 520 at the back end, so that the input voltage Vin and the output voltage Vout are not electrically connected. Interference, but the voltage level and phase can achieve the effect of synchronization. For example, when the first master chipset 10 does not output the first data signal Data1, the output voltage of the voltage follower 530 is 3.3V, and the first master chipset 10 outputs the first data signal Data1, the voltage follower The output voltage of the 530 is approximately 1.65V.

Figure 7 is a flow chart of a method of switching control sequences. As shown in FIGS. 1 and 7, the method S1 of switching the control sequence includes step S10, step S20, step S30, step S41, and step S43. Step S10 is to start the basic input/output system 40 and perform a system initialization job. Step S20 is that the basic input/output system 40 detects the active state of the first master chipset 10 and the second master wafer 20. At this time, the basic input/output system 40 simultaneously detects whether the first master chipset 10 outputs the first. Data signal Data1.

Step S30 is to determine the first main when the second main control chip set 20 is ready to be activated. Whether the control chip set 10 outputs the first data signal Data1, when it is determined that the first master chipset 10 no longer outputs the first data signal Data1, the process proceeds to step S41, and when it is determined that the first master chipset 10 outputs the first data When the signal Data1 is reached, the process proceeds to step S43. Step S41: The basic input/output system 40 generates an enable signal to the second master chipset 20, and enables the second master wafer 20 to operate. Step S43 is that the basic input/output system 40 generates a stop signal to the second master chipset 20, stops the second master chipset 20 from being activated, and returns to step S20 to detect the first master chipset 10 and the second master again. The operating state of the wafer 20 is controlled.

Still further, in the second embodiment, i.e., the embodiment having the comparison circuit 50, the comparison circuit 50 assists the basic input output system 40 in the determination in step S30. Referring to FIG. 2 and FIG. 7 simultaneously, step S51 and step S53 are further included after step S30. Step S51 is that when the comparison circuit 50 detects that the first master chipset 10 no longer outputs the first data signal Data1, it outputs a high voltage level. The basic input/output system 40 further proceeds to step S41 according to the high voltage level. In step S53, the comparison circuit 50 detects that the first master chipset 10 outputs the first data signal Data1, and outputs a low voltage level. The basic input/output system 40 further proceeds to step S43 according to the low voltage level. In other words, when the basic input-output system 40 receives the low voltage level from the comparison circuit 50, a stop signal is generated to terminate the output of the second drive signal, that is, to cause the second master chipset 20 to return to the pause standby (Idle )status.

Through the basic input/output system as the judgment and comparison mechanism, it is possible to determine whether the secondary master chipset starts to operate according to the output of the data signal of the first master chipset, thereby prioritizing the data signal transmission, thereby avoiding more The master chip simultaneously transmits the data signal, causing a hardware interpretation error, causing an abnormality or crash.

Although the present invention has been described in connection with the exemplary embodiments of the present invention, it is understood that the invention is not to be construed as The spirit and scope of the request.

Claims (8)

A motherboard having a multi-master chip, comprising: a first master chipset for outputting a plurality of first driving signals, wherein the first driving signals include a first data signal; and a second master a chip set for outputting a plurality of second driving signals; a plurality of controlled hardware electrically connected to the first master chip set and the second master chip set, receiving the first driving signals or the like a second driving signal, and actuating according to the first driving signal or the second driving signal; a basic input/output system (BIOS), comprising a basic input/output module, and a switching module, the basic input and output The module is configured to detect a state of the first master chipset, the second master chipset, and the controlled hardware, the switch module electrically connecting the first master chipset and the second Mastering the chipset, detecting the active state of the first master chipset, determining whether the first master chipset outputs the first data signal, and when the second master chipset is ready to be activated, determining The first master chipset outputs the first capital During the signal, the switching module generates a stop signal to the second master chipset, so that the second driver signals are temporarily unavailable, and when the second master chipset is ready to be activated, and determines the first master When the chipset no longer outputs the first data signal, the uniformity signal is sent to the second master chipset to cause the second driver signals to be sent; and a comparison circuit is connected to the switching module, wherein the comparison circuit is When the first main control chip group outputs the first data signal, outputting a low voltage level, and when the first main control chip group no longer outputs the first data signal, outputting a high voltage level, the switching mode When the group receives the low voltage level, a stop signal is generated to suspend the output of the second driving signal, and the second master chipset is suspended. The motherboard of claim 1 , wherein the first master chipset comprises a central processor and a north bridge chipset, the second master chipset includes an embedded controller and a South Bridge chipset. The motherboard of claim 1, wherein the comparison circuit comprises a comparator, the comparator comprising at least a first input terminal, a second input terminal, and a first output terminal, wherein The first input end is electrically connected to the first main control chip set, and the second input end is electrically connected to a reference voltage, and the first output end is electrically connected to the switching module. The motherboard of claim 1 has a multi-master wafer, wherein the enable signal is generated when the switching module receives the high voltage level. The motherboard of claim 3, wherein the comparison circuit further comprises an AC to DC converter, the AC to DC converter comprising a third input and a third output. The third input end is electrically connected to the first main control chip set, and the third output end is electrically connected to the first input end. The motherboard of the multi-master wafer of claim 5 further includes a voltage follower, the voltage follower comprising a fourth input terminal, a fifth input terminal, and a fourth output terminal. The fourth input end is electrically connected to the first main control chip set, and the fourth output end is electrically connected to the third input end and the fifth input end. A method for switching a control sequence includes: starting a basic input/output system, performing a system initialization operation; detecting a first master chip set and a second master chip set by the basic input output system and a comparison circuit Actuating state, and detecting whether the first main control chip group outputs a first data signal, the comparison circuit outputs a low voltage level when the first main control chip group outputs the first data signal, and When the first master chipset no longer outputs the first data signal, outputting a high voltage level; When detecting the preparation of the second master chipset and determining that the first master chipset outputs the first data signal, generating a stop signal to the second master chipset by the basic input/output system, so that The second master chipset stops operating; when it is determined that the second master chipset is ready to operate, and it is determined that the first master chipset no longer outputs the first data signal, the basic input/output system generates a consistent Generating a signal to the second master chipset, enabling the second master chipset to operate; and generating a stop signal to the first when the basic input/output system receives the low voltage level from the comparator circuit The second master chipset suspends the second master chipset operation. The method of switching control sequences according to claim 7, wherein when the basic input/output system receives the low voltage level, the stop signal is generated, and when the basic input/output system receives the high voltage level, generating The enable signal.