TW202220206A - semiconductor device - Google Patents

Abstract

Provided is a semiconductor device having an excellent heat dissipation effect for a crystalline oxide semiconductor layer. This semiconductor device includes: a gate electrode of which at least a part is embedded in a crystalline oxide semiconductor layer; and a heat dissipation part having a higher thermal conductivity than the crystalline oxide semiconductor layer, wherein at least a portion of the heat dissipation part is disposed in the vicinity of an embedded end portion of the gate electrode in the crystalline oxide semiconductor layer and/or at a position deeper than the embedded end portion, and thus the heat dissipation effect for the crystalline oxide semiconductor layer is made more efficient and more excellent.

Description

semiconductor device

The present invention relates to a semiconductor device including a crystalline oxide semiconductor layer.

As a next-generation crystalline oxide semiconductor material capable of achieving high withstand voltage, low loss, and high heat resistance, semiconductor devices using gallium oxide (Ga ₂ O ₃ ) with a large energy gap have been attracting attention. A semiconductor device including a crystalline oxide semiconductor is expected to be applied to a power semiconductor device such as an inverter as a switching element. Also, due to its wide energy gap, it is expected to be used as a light receiving and light receiving device such as an LED or a sensor.

It is known that there are five crystal structures of α, β, γ, δ, and ε in gallium oxide (Non-Patent Document 1). Among them, gallium oxide having a corundum structure has a high energy gap and is attracting attention as a semiconductor material that tends to be suitable for next-generation power devices. However, there is still the following problem: in gallium oxide, the most stable phase is the β-gallia structure, and it is difficult to form a crystal film containing gallium oxide having a corundum structure belonging to the quasi-stable phase without using a special film formation method. , and the problem that the thermal behavior of the crystalline film in a semiconductor device has not been clarified. In this regard, some studies have been conducted on crystalline oxide semiconductor films containing gallium oxide and/or mixed crystals thereof, including film formation of crystalline semiconductors having a corundum structure. For example, Patent Document 1 describes that gallium oxide is mixed with indium, aluminum, or a combination thereof, whereby the energy gap can be controlled, and it is described as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductor means In _X Al _Y Ga _Z O ₃ (0≤X≤2, 0≤Y≤2, 0≤Z≤2, X+Y+Z=1.5～2.5), which can be regarded as internal The same material system with gallium oxide.

In addition, conventionally, there is a problem that the heat generated when a current is applied to the semiconductor element affects the characteristics and life of the semiconductor element. For example, a structure for dissipating heat through a heat dissipation plate has been studied. Patent Document 2 describes a semiconductor device including a pair of metal plates connected to a semiconductor element, and the metal plates function as both electrodes and a heat sink. However, even with such a heat-dissipating structure, the heat-dissipating property of gallium oxide may not be satisfied, and a gallium-oxide-based semiconductor device that can improve the heat-dissipating property more efficiently is still expected. [Prior Art Literature] [Patent Literature]

[Patent Document 1] International Publication WO2014-050793A1 [Patent Document 2] Japanese Patent Laid-Open No. 2007-73743 [Non-patent literature]

[Non-Patent Document 1] R. Roy V.G. Hill, and E. F. Osborn: J. Am. Chem. Soc. 74 (1952) 719

[The problem to be solved by the invention]

An object of the present invention is to provide a semiconductor device having an efficient heat dissipation property for a crystalline oxide semiconductor layer. [Means of Solving Problems]

As a result of detailed studies to achieve the above object, the inventors of the present invention found that a semiconductor device including a crystalline oxide semiconductor layer containing gallium oxide or a mixed crystal thereof and a gate electrode at least partially embedded in the crystalline oxide semiconductor layer Among them, by arranging at least a part of the heat dissipation portion located deeper than the buried end portion of the gate electrode, a semiconductor device having a structure with good heat dissipation efficiency with respect to the crystalline oxide semiconductor layer can be obtained. In addition, the inventors of the present invention completed the present invention after further research after obtaining the above-mentioned findings.

That is, the present invention relates to the following inventions. [1] A semiconductor device comprising a gate electrode at least partially embedded in a crystalline oxide semiconductor layer, and a heat dissipation portion having a thermal conductivity higher than that of the crystalline oxide semiconductor layer, wherein at least a portion of the heat dissipation portion is located in the In the crystalline oxide semiconductor layer, the gate electrode is in the vicinity of the buried end portion and/or at a position deeper than the buried end portion. [2] The semiconductor device according to [1], wherein the buried end portion of the gate electrode is a buried lower end portion. [3] The semiconductor device according to [2], wherein at least a part of the heat dissipation portion is located deeper than the buried lower end portion. [4] The semiconductor device according to [2] or [3], further comprising a deep p layer, at least a part of which is buried in the crystalline oxide semiconductor layer to the same depth as the buried lower end portion or A position deeper than the aforementioned buried lower end. [5] The semiconductor device according to any one of [1] to [4], wherein the heat dissipation portion includes a conductive material. [6] The semiconductor device according to [5], wherein the conductive material is a p-type semiconductor. [7] The semiconductor device according to [6], wherein the p-type semiconductor has a concentration gradient of carrier concentration. [8] The semiconductor device according to [6], wherein in the p-type semiconductor, the carrier concentration increases toward the depth direction. [9] The semiconductor device according to any one of [1] to [8], wherein the crystalline oxide semiconductor layer contains one or more metals selected from the group consisting of gallium, indium, and aluminum. [10] The semiconductor device according to any one of [1] to [9], wherein the crystalline oxide semiconductor layer contains gallium. [11] The semiconductor device according to any one of [1] to [10], which is a normally closed type. [12] The semiconductor device according to any one of [1] to [11], which is a power element. [13] The semiconductor device according to any one of [1] to [11], which is a power module, an inverter, or a converter. [14] The semiconductor device according to any one of [1] to [11], which is a power card. [15] A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [1] to [14]. [Effect of invention]

The semiconductor device of the present invention is excellent in heat dissipation with respect to the crystalline oxide semiconductor layer, and exhibits favorable semiconductor characteristics.

The semiconductor device of the present invention includes a gate electrode at least partially embedded in a crystalline oxide semiconductor layer, and a heat dissipation portion having a thermal conductivity higher than that of the crystalline oxide semiconductor layer, wherein at least a portion of the heat dissipation portion is located in In the crystalline oxide semiconductor layer, the gate electrode is in the vicinity of the buried end portion and/or at a position deeper than the buried end portion.

"Near the buried end of the gate electrode" means a distance close to "the local high temperature caused by electric field concentration from at least a part of the buried gate electrode can be prevented or suppressed", and the periphery of the gate electrode is also included. In addition, it may not be in contact with the gate electrode, or may be located on the entire circumference or part of the circumference of the gate electrode via the gate insulating film. "Buried end" refers to the entire or part of the buried surface of the gate electrode, not only the entire bottom or part of the bottom of the gate electrode, but also the entire or part of the side surface where the gate electrode is buried.

"Position deeper than the buried end" refers to a depth that "can prevent or suppress local high temperature caused by electric field concentration from at least a part of the buried gate electrode", and may not be located directly under the gate electrode However, in the present invention, the buried end portion is preferably the buried lower end portion.

"Buried lower end" refers to the entire bottom or part of the bottom of the aforementioned gate electrode. In addition, when the buried end portion is a buried lower end portion, at least a part of the deep p-layer is buried in the crystalline oxide semiconductor layer to the same depth as the buried lower end portion or a position deeper than the buried lower end portion. It is preferable because the electric field concentration of the crystalline oxide semiconductor layer and the like are moderated well.

The gate electrode is not particularly limited as long as it is an electrode that can control the flow of the main current, and includes a semiconductor region, a diffusion region, an electrode, and the like.

The "heat dissipation portion" is not particularly limited as long as it can release the heat in the crystalline oxide semiconductor layer, and may be layered, partially, or partially connected in a fixed direction. The aforementioned heat dissipation portion includes, for example, a heat dissipation portion composed of a heat dissipation member, a heat dissipation layer, or a cooling portion having a cooling function. The heat dissipation member is not particularly limited as long as the thermal conductivity is higher than that of the crystalline semiconductor layer. In the present invention, the thermal conductivity of the heat dissipating member is preferably 30 W/m·K or more, more preferably 50 W/m·K or more, and most preferably 100 W/m·K or more. Moreover, in this invention, it is also preferable that the said heat dissipation member contains a conductive material. The above-mentioned conductive material is not particularly limited, and it is preferably one whose electrical conductivity is higher than that of the above-mentioned crystalline oxide semiconductor layer. Examples of such a preferred conductive material include a p-type semiconductor and the like. The p-type semiconductor is not particularly limited, but in the present invention, it is preferably a p-type crystalline oxide semiconductor, more preferably, the carrier concentration has a concentration gradient, and it is more preferable that the carrier concentration increases toward the depth direction. By using such a preferable heat dissipating member, more excellent semiconductor characteristics can be exhibited.

The crystalline oxide semiconductor layer usually contains a crystalline oxide semiconductor as a main component. The aforementioned crystalline oxide semiconductor preferably contains gallium, more preferably contains gallium oxide and a mixed crystal thereof as a main component. In addition, the crystal structure and the like of the aforementioned crystalline oxide semiconductor are not particularly limited. As a crystal structure of the said crystalline oxide semiconductor, a corundum structure, a β-gallia structure, a hexagonal structure (for example, an ε-type structure), etc. are mentioned, for example. In the present invention, the crystalline oxide semiconductor preferably has a corundum structure or a β-gallia structure, and more preferably has a corundum structure. The above-mentioned crystalline oxide semiconductor having a corundum structure is not particularly limited, but preferably contains at least one or two or more metals in the third to sixth period of the periodic table, and more preferably contains a metal selected from the group consisting of gallium, indium, At least one of rhodium, iridium and aluminum. The n-type crystalline oxide semiconductor preferably contains at least gallium. The p-type crystalline oxide semiconductor preferably contains at least one selected from iridium and rhodium, and more preferably contains iridium. Examples of the crystalline oxide semiconductor containing gallium include α-Ga ₂ O ₃ or a mixed crystal thereof. Examples of the iridium-containing metal oxide include α-Ir ₂ O ₃ or a mixed crystal thereof (eg, a mixed crystal of iridium oxide and gallium oxide). A crystalline oxide semiconductor layer containing such a preferred crystalline oxide semiconductor as a main component has more excellent crystallinity and heat dissipation properties, and can also improve semiconductor characteristics. In addition, the above-mentioned "main component" means that the crystalline oxide is contained by 50% or more, preferably 70% or more, and more preferably 90% or more, based on the composition ratio in the crystalline oxide semiconductor layer. For example, when the crystalline oxide semiconductor is α-Ga ₂ O ₃ , α-Ga ₂ O ₃ may be contained in such a ratio that the atomic ratio of gallium in the metal element of the crystalline oxide semiconductor layer is 0.5 or more. In the present invention, the atomic ratio of gallium in the metal element of the crystalline oxide semiconductor layer is preferably 0.7 or more, more preferably 0.8 or more. In addition, the aforementioned crystalline oxide semiconductor may be a single crystal or a polycrystal. The crystalline oxide semiconductor is usually in the form of a film, and is not particularly limited as long as the object of the present invention is not inhibited, and may be in the form of a plate, a sheet, a layer, or a laminate including a plurality of layers. .

The aforementioned crystalline oxide semiconductor may contain a dopant. The aforementioned dopant is not particularly limited as long as it does not inhibit the purpose of the present invention. It can be an n-type dopant or a p-type dopant. Examples of the n-type dopant include tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. As said p-type dopant, magnesium, calcium, etc. are mentioned, for example. The concentration of the dopant can be appropriately set, and specifically, for example, it may be about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , and the concentration of the dopant may be, for example, about 1×10 ¹⁷ . Low concentration below /cm ³ . Furthermore, according to the present invention, the dopant may be contained in a high concentration of about 1×10 ²⁰ /cm ³ or more.

For example, the above-mentioned crystalline oxide semiconductor can be obtained more appropriately by performing epitaxial crystal growth by the atomization CVD method or the atomization/epitaxy method.

<Crystalline substrate> The aforementioned crystal substrate is not particularly limited as long as it does not inhibit the purpose of the present invention, and may be a known substrate. It may be an insulator substrate, a conductive substrate, or a semiconductor substrate. It can be a single crystal substrate or a polycrystalline substrate. As the crystal substrate, for example, a substrate containing, as a main component, a crystal product having a corundum structure is exemplified. In addition, the above-mentioned "main component" refers to what contains 50% or more of the above-mentioned crystallized product in terms of the composition ratio in the substrate, preferably 70% or more, and more preferably 90% or more. Examples of the crystal substrate having the corundum structure include a sapphire substrate, an α-type gallium oxide substrate, and the like.

In the present invention, the aforementioned crystal substrate is preferably a sapphire substrate. As said sapphire substrate, a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, an r-plane sapphire substrate, etc. are mentioned, for example. In addition, the aforementioned sapphire substrate may have an off-angle. The aforementioned off angle is not particularly limited, but may be, for example, 0.01° or more, preferably 0.2° or more, and more preferably 0.2° to 12°. In the aforementioned sapphire substrate, the crystal growth plane is preferably a-plane, m-plane or r-plane, and a c-plane sapphire substrate having an off angle of 0.2° or more is also preferred. In addition, the thickness of the said crystal substrate is not specifically limited, Usually, 10-20 mm is preferable, and 10-1000 micrometers is more preferable.

Further, the crystal substrate may have a shape including at least a first crystal axis and a second crystal axis, or may form grooves corresponding to the first crystal axis and the second crystal axis. As a suitable shape of the said crystal substrate, a circle, a triangle, a quadrangle (for example, a rectangle, a trapezoid, etc.), a polygon, such as a pentagon or a hexagon, a fan shape, etc. are mentioned, for example.

In addition, in the present invention, other layers such as a buffer layer and a stress relaxation layer may be provided on the crystal substrate. As the buffer layer, a layer composed of a metal oxide having the same crystal structure as the crystal structure of the aforementioned crystalline substrate or the aforementioned crystalline oxide semiconductor can be mentioned. Moreover, as a stress relaxation layer, an ELO mask layer etc. are mentioned.

The method for growing the epitaxial crystal is not particularly limited as long as the object of the present invention is not inhibited, and a known method may be used. As the epitaxial crystal growth method, for example, CVD method, MOCVD method, MOVPE method, atomization CVD method, atomization/epitaxy method, MBE method, HVPE method, pulse growth method, ALD method, etc. are mentioned. In the present invention, the above-mentioned epitaxial crystal growth is preferably performed by the atomized CVD method or the atomized/epitaxial method.

The aforementioned atomized CVD method or atomization/epitaxy method is carried out by atomizing a raw material solution containing a metal (atomizing step), floating the droplets and supporting the obtained atomized droplets with a carrier gas It is transported to the vicinity of the aforementioned crystalline substrate (transportation step), and then the aforementioned atomized droplets are subjected to thermal reaction (film formation step).

(raw material solution) The raw material solution is not particularly limited as long as it contains a metal as a film-forming raw material and can be atomized, and may contain an inorganic material or an organic material. The aforementioned metal may be a metal element or a metal compound, and is not particularly limited as long as it does not hinder the purpose of the present invention, and may be selected from the group consisting of gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), Aluminum (Al), Gold (Au), Silver (Ag), Platinum (Pt), Copper (Cu), Iron (Fe), Manganese (Mn), Nickel (Ni), Palladium (Pd), Cobalt (Co), Ruthenium (Ru), Chromium (Cr), Molybdenum (Mo), Tungsten (W), Tantalum (Ta), Zinc (Zn), Lead (Pb), Rhenium (Re), Titanium (Ti), Tin (Sn), One or more metals among magnesium (Mg), calcium (Ca), and zirconium (Zr), etc., but in the present invention, it is preferable that the above-mentioned metals include at least one of the third to sixth periods of the periodic table. One or more metals, more preferably at least one selected from the group consisting of gallium, indium, rhodium, iridium and aluminum, and most preferably at least gallium. In addition, in the present invention, the aforementioned metals preferably include gallium, indium and/or aluminum. By using such a preferable metal, the aforementioned crystalline oxide semiconductor film which is more suitable for use in semiconductor devices and the like can be formed.

In the present invention, as the raw material solution, one obtained by dissolving or dispersing the metal in the form of a complex or a salt in an organic solvent or water can be suitably used. As a form of a complex, an acetylacetone complex, a carbonyl complex, an ammonia complex, a hydride complex, etc. are mentioned, for example. Examples of the salt form include organic metal salts (eg, metal acetate, metal oxalate, metal citrate, etc.), metal sulfide, metal nitrate, metal phosphate, metal halide (eg, metal halide). chloride metal salt, bromide metal salt, iodide metal salt, etc.) and the like.

The solvent of the raw material solution is not particularly limited as long as it does not hinder the object of the present invention, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the aforementioned solvent is preferably water-containing.

Moreover, additives, such as a hydrohalic acid and an oxidizing agent, may be mixed with the said raw material solution. As said hydrohalic acid, hydrobromic acid, hydrochloric acid, hydroiodic acid, etc. are mentioned, for example. Examples of the oxidizing agent include hydrogen peroxide (H ₂ O ₂ ), sodium peroxide (Na ₂ O ₂ ), barium peroxide (BaO ₂ ), and benzyl peroxide (C ₆ H ₅ CO) ₂ O _2nd class peroxide, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid or nitrobenzene and other organic peroxides, etc.

The aforementioned raw material solution may also contain a dopant. The aforementioned dopant is not particularly limited as long as it does not inhibit the purpose of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, and niobium, and p-type dopants such as magnesium and calcium. The concentration of the dopant is usually about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , and the concentration of the dopant may be as low as about 1×10 ¹⁷ /cm ³ or less, for example. Furthermore, according to the present invention, the dopant may be contained at a high concentration of about 1×10 ²⁰ /cm ³ or more.

(Atomization step) The aforementioned atomization step is to prepare and adjust the metal-containing raw material solution, and atomize the aforementioned raw material solution to float the droplets to generate atomized droplets. The mixing ratio of the aforementioned metals is not particularly limited, but is preferably 0.0001 mol/L to 20 mol/L relative to the entire raw material solution. The atomization method is not particularly limited as long as the raw material solution can be atomized, and may be a conventional atomization method, but in the present invention, an atomization method using ultrasonic vibration is preferred. The mist used in the present invention floats in the air. For example, it is more preferable that the mist is not blown in the form of a spray, but has an initial velocity of zero and can be transported as a gas floating in space. The droplet size of the mist is not particularly limited, and may be droplets of about several mm, preferably 50 μm or less, and more preferably 1 to 10 μm.

(shipping step) In the aforementioned transporting step, the aforementioned atomized droplets are transported to the aforementioned substrate by the aforementioned carrier gas. The type of carrier gas is not particularly limited as long as the object of the present invention is not inhibited, and examples thereof include oxygen, ozone, inert gas (for example, nitrogen, argon, etc.), reducing gas (hydrogen gas, synthesis gas, etc.) and the like. example. In addition, one type of carrier gas may be used, or two or more types may be used, and a dilution gas (for example, a 10-fold dilution gas, etc.) which changes the carrier gas concentration may be further used as the second carrier gas. In addition, the supply location of the carrier gas may be not only one location but two or more locations. The flow rate of the carrier gas is not particularly limited, but is preferably 1 LPM or less, and more preferably 0.1 to 1 LPM.

(film formation step) In the film formation step, the atomized droplets are reacted to form a film on the crystal substrate. The above-mentioned reaction is not particularly limited as long as it is a reaction of forming a film from the above-mentioned atomized liquid droplets, but in the present invention, a thermal reaction is preferred. The thermal reaction is not particularly limited as long as the atomized liquid droplets are reacted with thermal energy, and the reaction conditions and the like are not particularly limited as long as the object of the present invention is not inhibited. In this step, the thermal reaction is usually carried out at a temperature higher than or equal to the evaporation temperature of the solvent of the raw material solution, preferably not higher than the temperature, more preferably 650°C or lower. In addition, the thermal reaction can be carried out in any environment of vacuum, non-oxygen environment, reducing gas environment and oxygen environment, as long as the object of the present invention is not hindered, and it can be carried out under atmospheric pressure, under pressure and under reduced pressure. In the present invention, it is preferably carried out under atmospheric pressure from the viewpoints that the calculation of the evaporation temperature is simpler and the equipment and the like can be simplified. In addition, the film thickness can be set by adjusting the film-forming time.

The film forming apparatus 601 to which the present invention is applied will be described below with reference to the drawings. The film forming apparatus 601 shown in FIG. 14 includes: a carrier gas device 622a for supplying a carrier gas; a flow rate control valve 623a for adjusting the flow rate of the carrier gas sent from the carrier gas device 622a; and a carrier gas (dilution) device 622b for supplying a carrier gas (diluting) Flow control valve 623b, in order to adjust the flow rate of the carrier gas (dilution) sent from the carrier gas (dilution) device 622b; Mist generation source 624, containing raw material solution 624a; Container 625, put into water 625a; Ultrasonic vibration A film-forming chamber 630; a supply pipe 627 made of quartz connected to the film-forming chamber 630 from a mist generating source 624; and a heating plate (heater) 628 provided in the film-forming chamber 630 . The base plate 603 is provided on the heating plate 628 .

Then, as shown in FIG. 14, the raw material solution 624a is accommodated in the mist generation source 624. Next, the substrate 603 is used, which is placed on the heating plate 628 , and the heating plate 628 is operated to increase the temperature in the film forming chamber 630 . Next, the flow regulating valve 623 (623a, 623b) is opened, and the carrier gas is supplied from the carrier gas source (the carrier gas device 622a and the carrier gas (diluting) device 622b) into the film forming chamber 630, and the film forming chamber 630 is fully replaced by the carrier gas. After the environment is changed, adjust the flow rate of carrier gas and the flow rate of carrier gas (dilution) respectively. Next, the ultrasonic vibrator 626 is vibrated, and the vibration is transmitted to the raw material solution 624a through the water 625a, whereby the raw material solution 624a is micronized to generate atomized droplets 624b. The atomized droplets 624b are introduced into the film formation chamber 630 by the carrier gas, and transported to the substrate 603 , and then the atomized droplets 624b are thermally reacted in the film formation chamber 630 under atmospheric pressure to form a film on the substrate 603 .

In addition, it is also preferable to use the atomizing CVD apparatus (film forming apparatus) 602 shown in FIG. 15 . The atomized CVD apparatus 602 of FIG. 15 includes: a stage 621 on which a substrate 603 is placed; a carrier gas supply device 622a for supplying a carrier gas; a flow rate control valve 623a for adjusting the flow rate of the carrier gas sent from the carrier gas supply device 622a; The carrier gas (dilution) supply device 622b supplies the carrier gas (dilution); the flow regulating valve 623b is used to adjust the flow rate of the carrier gas sent from the carrier gas (dilution) supply device 622b; the mist generation source 624 accommodates the raw material solution 624a Container 625 is put into water 625a; Ultrasonic vibrator 626 is installed on the bottom surface of container 625; Supply pipe 627 is made up of the quartz tube of inner diameter 40mm; Heater 628 is located in the peripheral portion of supply pipe 627; and the exhaust port 629 to exhaust the thermally reacted mist, droplets and exhaust gas. The mounting table 621 is made of quartz, and the surface on which the substrate 603 is mounted is inclined with respect to the horizontal plane. The supply tube 627 serving as the film forming chamber and the stage 621 are both made of quartz, thereby preventing impurities from the device from being mixed into the film formed on the substrate 603 . This atomizing CVD apparatus 602 can be operated in the same manner as the aforementioned film forming apparatus 601 .

If the above-mentioned preferable film forming apparatus is used, the above-mentioned crystalline oxide semiconductor can be more easily formed on the crystal growth surface of the above-mentioned crystal substrate. In addition, the aforementioned crystalline oxide semiconductor is usually formed by epitaxial growth.

The aforementioned crystalline oxide semiconductor can be used for a semiconductor device, especially a power element. Examples of semiconductor devices formed using the aforementioned crystalline oxide semiconductor include metal semiconductor field effect transistor (MESFET), high electron mobility transistor (HEMT), metal oxide semiconductor field effect transistor (MOSFET), electrostatic induction Transistor (SIT), Junction Field Effect Transistor (JFET), Insulated Gate Bipolar Transistor (IGBT), etc. In the present invention, the crystalline oxide semiconductor can be used in a semiconductor device according to expectations such as peeling off the crystalline oxide semiconductor from the crystalline substrate.

In addition, the aforementioned semiconductor device can be applied to a horizontal element (horizontal element) in which electrodes are formed on one side of a semiconductor layer, and a vertical element (vertical element) having electrodes on both sides of the front and rear sides of the semiconductor layer, respectively. ), wherein the present invention is preferably used for vertical elements. Preferred examples of the aforementioned semiconductor devices include, for example, metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), metal oxide semiconductor field effect transistors (MOSFETs), and electrostatic induction transistors (SITs). ), Junction Field Effect Transistor (JFET), Insulated Gate Bipolar Transistor (IGBT), etc.

Preferred examples of the aforementioned semiconductor device when the crystalline oxide semiconductor of the present invention is applied to an n-type semiconductor layer (n+-type semiconductor layer, n-type semiconductor layer, etc.) and p-type semiconductor layer will be described below using drawings, but the present invention is not limited to Examples of such.

FIG. 1 shows a perspective cross-sectional view of a semiconductor device 100 including a laminate 50 including a crystalline oxide semiconductor layer and a gate electrode 13 at least partially embedded in the laminate 50 . In addition, for the convenience of viewing the structure around the gate electrode, the oblique lines showing the cross-sectional view are omitted. The semiconductor device 100 of FIG. 1 includes at least a first crystalline oxide semiconductor layer 1 of a first conductivity type, a second crystalline oxide semiconductor layer 2 disposed on the first crystalline oxide semiconductor layer 1 , and a second crystalline oxide semiconductor layer 2 formed on the first crystalline oxide semiconductor layer 1 . The third crystalline oxide semiconductor layer 3 of the second conductivity type on the crystalline oxide semiconductor layer 2 further includes an insulating film (interlayer insulating film) 25, a drain electrode 26, and the like. In addition, the semiconductor device 100 has the deep p layer 6 located outside in order to prevent the destruction of the insulating film 12 , which has a surface in contact with the second surface 3 b of the third crystalline oxide semiconductor layer 3 and is partially embedded in the second surface 3 b of the third crystalline oxide semiconductor layer 3 . 2 in the crystalline oxide semiconductor layer 2 and located outside the gate electrode 13 . As shown in FIG. 1 , the deep p layers 6 at the two outer positions are arranged so as to sandwich the gate electrode.

The material of the electrode can also be a known electrode material. Examples of the aforementioned electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni , Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag and other metals or their alloys, tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO ) and other metal oxide conductive films, organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures and laminates of these. The formation method of the electrodes is not particularly limited, and may be appropriately selected from wet methods such as printing methods, spray methods, and coating methods, vacuum evaporation methods, sputtering methods, ion implantation methods, and other physical methods in consideration of suitability with the aforementioned materials. A method among chemical methods such as CVD method, plasma CVD method, etc. is formed on the aforementioned substrate.

The semiconductor device 100 includes: a first electrode 26 (drain electrode) electrically connected to the first crystalline oxide semiconductor layer 1; an insulating film 12 disposed on the inner surface of the trench 11; and a second electrode 13 (gate electrode) serving as a gate electrode. electrode), arranged on the inner side surface of the trench 11, and arranged on the insulating film 12; and a third electrode 24 (source electrode), which is electrically connected to the third crystalline oxide semiconductor layer 3.

FIG. 2 is an evaluation result of simulating the heat distribution generated around the gate electrode 13 when a current is applied to the semiconductor device 100 including the crystalline oxide semiconductor layer. And the inside of the laminated body 50 containing a crystalline oxide semiconductor layer becomes high temperature. Specifically, as shown in FIG. 2 , in the second crystalline oxide semiconductor layer 2 (n- type semiconductor layer) serving as the crystalline oxide semiconductor layer, the temperature below the gate electrode 13 is particularly high.

FIG. 3 is a schematic diagram showing a semiconductor device having a heat dissipation structure. The semiconductor device of FIG. 3 is different from FIG. 1 in that it has a heat dissipation portion 21 . The semiconductor device 200 includes a laminate 50 including the crystalline oxide semiconductor layer 1 ; a gate electrode 13 , at least a part of which is embedded in the laminate 50 ; Location. The heat dissipation portion 21 is located below the embedded end portion 13 b of the gate electrode 13 . The heat dissipation portion 21 is embedded in the inside of the second crystalline oxide semiconductor layer 2 (n- type semiconductor layer). The heat dissipation portion 21 is located closer to the gate electrode than the deep p-layer 6 at the outer side in a plan view. That is, at least a part of the heat dissipation portion 21 overlaps with the gate electrode in plan view.

Furthermore, the semiconductor device 200 may have the first semiconductor region 4 (source region) disposed on the third crystalline oxide semiconductor layer 3 (p-type semiconductor layer), and the carrier density of which is higher than that of the second crystalline oxide semiconductor layer 3 The carrier density of the material semiconductor layer 2 (n-type semiconductor layer); the second semiconductor region 5 (contact region), which is arranged on the third crystalline oxide semiconductor layer 3 (p-type semiconductor layer), has a high carrier density carrier density in the third crystalline oxide semiconductor layer 3 (p-type semiconductor layer). The gate electrode 13 extends in a first direction (depth direction) and a second direction having an angle with respect to the first direction, the first direction penetrating from the first surface 4a of the first semiconductor region 4 (source region) to the opposite side. The second surface 4b further penetrates from the first surface 3a of the third crystalline oxide semiconductor layer 3 (p-type semiconductor layer) to the second surface 3b on the opposite side. According to the design of the semiconductor device, the second direction may be oblique or may be perpendicular to the first direction. When the center of the heat dissipation portion 21 is arranged at the position where the first direction (depth direction) of the gate electrode intersects with the dummy extension line of the buried lower end portion 6b of the deep p layer 6, the crystalline oxide semiconductor layer can be more efficiently dissipated inside the crystalline oxide semiconductor layer. of thermal diffusion. In addition, as another embodiment, the heat dissipation portion 21 may also have a surface in contact with the deep p layer 6 . When the heat dissipation portion 21 is thermally connected to the deep p-layer 6, the heat trapped in the crystalline oxide semiconductor layer can be more efficiently released to the outside of the semiconductor device. In addition, "thermal connection" refers to, for example, a configuration in which the deep p layer and the heat dissipation portion are directly or indirectly (through a medium having a higher thermal conductivity than air) in contact with each other to transfer the heat of the deep p layer to the heat dissipation portion. FIG. 3 shows that the gate electrode extends in the first direction and the direction perpendicular to the first direction (the longitudinal direction of the semiconductor device in FIG. 3 ). The buried end portion 13b of the gate electrode 13 extends in the second direction as a buried end face, and the heat dissipation portion 21 located below the buried end face of the gate electrode 13 may be arranged to extend in the second direction along the buried end face of the gate electrode 13 . Moreover, as shown in the cross-sectional view of FIG. 4 , the heat dissipation parts 21 may be integrally provided, and as shown in FIG. 8 , two or more heat dissipation parts 21 may be adjacently provided or arranged separately from each other. In addition, FIG. 4 is a diagram schematically showing a cross-section obtained by cutting the semiconductor device of FIG. 3 on a plane including the IV-IV line and parallel to the longitudinal direction of the semiconductor device 200 . 8 is a diagram schematically showing a cross-section obtained by cutting the semiconductor device of FIG. 7 on a plane including the VIII-VIII line and parallel to the longitudinal direction of the semiconductor device 400 . In addition, when the semiconductor device 200 is a metal oxide semiconductor field effect transistor (MOSFET), the crystalline oxide semiconductor layer 1 is an n-type semiconductor layer. When the semiconductor device is an insulated gate bipolar transistor (IGBT), the crystalline oxide semiconductor layer 1 is a p+ type semiconductor layer.

The material of the heat dissipation portion 21 may be a conventional material, but the thermal conductivity of the heat dissipation portion 21 must be higher than that of the crystalline oxide semiconductor layer embedded in the heat dissipation portion. For example, when the main component of the first crystalline oxide semiconductor layer 2 is gallium oxide, the heat dissipation portion 21 contains a material having higher thermal conductivity than gallium oxide. For example, the heat dissipation portion 21 may also include high thermal conductivity metals (eg, aluminum or copper), metal compounds and/or metal oxides, and may also include high thermal conductivity materials such as silicide, polysilicon, and graphite. The heat dissipation portion 21 may also have conductivity.

The heat dissipation portion 21 may contain impurities of the second conductivity type (p-type). The concentration of the second conductivity type impurity may be different between the position near the first surface 21a of the heat dissipation portion 21 closer to the gate electrode and the position near the second surface 21b opposite to the first surface 21a. In the heat dissipation part 21, the density|concentration may become high toward the 1st direction (depth direction). The second surface 21b of the heat dissipation portion 21 is preferably positioned deeper than the second surface 6b of the deep p-layer 6 at the outer position.

FIG. 5 is another schematic diagram showing a semiconductor device having a heat dissipation structure. The semiconductor device of FIG. 5 differs from the semiconductor device of FIG. 3 in that the heat dissipation portion 21 has the first concentration region 23 and the second concentration region 22 . In the semiconductor device 300 , the heat dissipation portion 21 disposed below the buried end portion 13 b of the gate electrode may have a first concentration region 23 (p−) and a second conductivity type impurity concentration higher than that of the first concentration region 23 . Area 22(p). FIG. 6 is a schematic view showing a cross-section of the semiconductor device of FIG. 5 at a plane including the VI-VI line and parallel to the longitudinal direction of the semiconductor device 300 . As shown in the cross-sectional view of FIG. 6 , the heat-dissipating portion 21 may be integrally formed. As shown in the cross-sectional view of FIG. 2 directions) adjacent to or apart, but as shown in the simulation evaluation result in FIG. The inside of the laminate 50 can efficiently diffuse heat inside the oxide semiconductor layer.

FIG. 7 is another schematic diagram showing a semiconductor device having a heat dissipation structure. The semiconductor device 400 has at least two surfaces including the buried end portion 13 b of the gate electrode, and the heat dissipation portion 21 thermally connected via the insulating film 12 . The heat dissipation portion 21 has a concave portion extending in the second direction on the upper surface. The concave portion of the heat dissipation portion 21 may also constitute a part of the trench 11, and the lower portion including the buried end portion 13b of the gate electrode is separated from the heat dissipation portion by the insulating film 12. 21 Links. The width of the heat dissipation portion 21 may also be narrowed toward the bottom surface. In addition, the second crystalline oxide semiconductor layer 2 may have two or more current diffusion regions arranged between the heat dissipation portions of the second conductivity type. In addition, in FIG. 7, the upper end portion 13a of the gate electrode is not buried in the trench, but in the present invention, the upper end portion 13a of the gate electrode is preferably buried in the trench.

FIG. 9 is another schematic diagram showing a semiconductor device having a heat dissipation structure. The semiconductor device 500 has at least two surfaces including the buried end portion 13 b of the gate electrode, and the heat dissipation portion 21 thermally connected via the insulating film 12 . The heat sink 21 has a concave portion extending in the second direction on the upper surface. The concave portion of the heat sink 21 may also constitute a part of the trench 11 , and the lower part including the buried end portion 13 b of the gate electrode is connected to the heat sink 21 via the insulating film 12 . . The heat dissipation portion 21 may contain impurities of the second conductivity type (p-type), and the impurity concentration of the second conductivity type may be different between the upper surface of the heat dissipation portion 21 having the recess and the bottom surface of the heat dissipation portion 21 . In the heat dissipation part 21, the density|concentration may become high toward the 1st direction (depth direction). FIG. 10 is a schematic view showing a cross section of the semiconductor device of FIG. 9 cut along a plane including the X-X line and parallel to the longitudinal direction of the semiconductor device 500 . As shown in the cross-sectional view of FIG. 10 , the heat dissipation parts 21 may be integrally provided, and as shown in FIG. 8 , two or more heat dissipation parts 21 may be adjacently provided or arranged separately from each other. The first concentration region 23 of the heat dissipation portion 21 is located closer to the side surface of the trench than the second concentration region 22 . When a voltage is applied to the second electrode 13, the first concentration region forms an inversion layer at a position close to the side surface of the trench.

3 shows the case where α-Ga _{2 O 3 is used for the crystalline oxide semiconductor layer and p-type oxide semiconductor (α-Ir 2 O 3 or Mg-doped α-Ga 2 O 3 ) is used for} the heat dissipation portion , FIG. 5, FIG. 7 and FIG. 9 of the semiconductor device shown in FIG. 9 heat distribution around each gate electrode, the results did not produce a high temperature portion shown in FIG. 2 . From this, it can be seen that according to the present invention, local temperature increase due to electric field concentration from at least a part of the buried gate electrode can be prevented or suppressed, and the semiconductor characteristics are excellent.

The formation means of each layer of the semiconductor device is not particularly limited as long as the object of the present invention is not inhibited, and conventional means may be used. For example, a method of patterning by a photolithography method after forming a film by a vacuum deposition method, a CVD method, a sputtering method, or various coating techniques, or a method of directly patterning using a printing technique or the like.

The aforementioned semiconductor device is particularly useful for power elements, and is particularly suitable for use as a normally-off semiconductor device. In the present invention, it is expected that the crystalline oxide semiconductor can be used for a semiconductor device by peeling off the crystalline oxide semiconductor from the crystalline substrate by a conventional means, and can be suitably used as a vertical element. In addition, the aforementioned semiconductor device is suitable for any of a horizontal element (horizontal element) in which an electrode is formed on one side of a semiconductor layer, and a vertical element (vertical element) having electrodes on both sides of the front and rear sides of the semiconductor layer, respectively. One, wherein the present invention is preferably used for vertical elements. Preferred examples of the aforementioned semiconductor devices include, for example, metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), metal oxide semiconductor field effect transistors (MOSFETs), and electrostatic induction transistors (SITs). ), Junction Field Effect Transistor (JFET), Insulated Gate Bipolar Transistor (IGBT), etc. In the present invention, an insulated gate type semiconductor device (eg, MOSFET or IGBT, etc.) or a semiconductor device with a Schottky gate (eg, MESFET, etc.) is preferable, and MOSFET or IGBT is more preferable.

In addition to the above-mentioned matters, the semiconductor device of the present invention can be appropriately used as a power module, an inverter, or a converter using a conventional method, and can be preferably used, for example, in a semiconductor system using a power supply device. . The aforementioned power supply device can be fabricated from the aforementioned semiconductor device by connecting to a wiring pattern or the like using a conventional method, or can be fabricated as the aforementioned semiconductor device. In FIG. 11 , a power supply system 170 is formed by using a plurality of the aforementioned power supply devices 171 and 172 and a control circuit 173 . The aforementioned power supply system, as shown in FIG. 12 , can be used for the system device 180 by combining the electronic circuit 181 with the power supply system 182 . In addition, an example of a power supply circuit diagram of the power supply device is shown in FIG. 13 . FIG. 13 shows the power supply circuit of the power supply device composed of the power circuit and the control circuit. The inverter 192 (composed of MOSFETs A to D) switches the DC voltage at high frequency to convert the DC voltage into AC, and then the transformer 193 is used for insulation. The voltage is transformed and rectified by the rectifying MOSFET194 (A to B'), and then smoothed by the DCL195 (smoothing coils L1 and L2) and a capacitor, and a DC voltage is output. At this time, the output voltage is compared with the reference voltage by the voltage comparator 197, and the inverter 192 and the rectifier MOSFET 194 are controlled by the PWM control circuit 196 to obtain a desired output voltage.

In the present invention, the semiconductor device is preferably a power card, and more preferably includes a cooler and an insulating member, and the cooler is disposed on both sides of the semiconductor layer at least across the insulating member, preferably two of the semiconductor layer. A heat dissipation layer is respectively provided on the sides, and the coolers are respectively provided on the outer side of the heat dissipation layer through at least the insulating member. FIG. 16 shows a power card of one of the preferred embodiments of the present invention. The power card shown in FIG. 16 is a double-sided cooling type power card 201, which includes a refrigerant pipe 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin portion 209, a semiconductor wafer 301a, and a metal thermally conductive plate (protruding terminal portion) 302b, a heat sink and an electrode 303, a metal thermally conductive plate (protruding terminal portion) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The cross section in the thickness direction of the refrigerant pipe 202 has a plurality of flow paths 222 divided by a plurality of partition walls 221 extending in the flow path direction at predetermined intervals. According to this preferred power card, higher heat dissipation can be achieved, and higher reliability can be satisfied.

The semiconductor chip 301a is bonded to the inner main surface of the thermally conductive metal plate (protruding terminal portion) 302b with the solder layer 304, and the thermally conductive metal plate (protruding terminal portion) 303b is bonded to the remaining main surface of the semiconductor wafer 301a with the solder layer 304, so that the The collector surface and the emitter electrode surface of the IGBT and the anode electrode surface and the cathode electrode surface of the freewheeling diode are connected in so-called anti-parallel connection. As a material of the metal thermally conductive plates (protruding terminal parts) 302b and 303b, Mo, W, etc. are mentioned, for example. The metal thermally conductive plates (protruding terminal portions) 302b and 303b have a thickness difference to absorb the thickness difference of the semiconductor chip 301a, thereby making the outer surfaces of the metal thermally conductive plates 302b and 303b flat.

The resin sealing portion 209 is made of, for example, epoxy resin, and covers and seals the side surfaces of the metal thermally conductive plates 302 b and 303 b , and the semiconductor wafer 301 a is sealed by the resin sealing portion 209 . However, the outer principal surfaces of the metal heat-conducting plates 302b and 303b, that is, the contact and heat-receiving surfaces, are completely exposed. Metal heat-conducting plates (protruding terminal portions) 302b and 303b protrude from the resin sealing portion 209 to the right in FIG. 16, and the gate (control) of the semiconductor chip 301a on which the IGBT is formed, for example, is a control electrode terminal 305 of a so-called lead frame terminal. The electrode surface is connected to the control electrode terminal 305 .

The insulating plate 208 serving as the insulating spacer is made of, for example, an aluminum nitride film, but other insulating films may also be used. The insulating plate 208 completely coats the metal heat-conducting plates 302b and 303b and is closely attached to them, but the insulating plate 208 can also only be in contact with the metal heat-conducting plates 302b and 303b, or can be coated with excellent heat-conducting materials such as silicone grease, or can be applied in various ways. engage. In addition, the insulating layer may be formed by ceramic spraying or the like, the insulating plate 208 may be bonded to the metal heat-conducting plate, and the refrigerant pipe may be bonded or formed thereon.

The refrigerant pipe 202 is produced by cutting into a required length a plate material formed by forming an aluminum alloy by a pultrusion method or an extrusion method. The cross section in the thickness direction of the refrigerant pipe 202 has a plurality of flow paths 222 divided by a plurality of partition walls 221 extending in the flow path direction with a predetermined interval therebetween. The spacer 203 may be a soft metal plate such as a solder alloy, or may be a film formed on the contact surfaces of the metal thermally conductive plates 302b and 303b by coating or the like. The surface of the soft spacer 203 is easily deformed to reduce thermal resistance in accordance with the slight unevenness or warpage of the insulating plate 208 and the slight unevenness or warpage of the refrigerant pipe 202 . In addition, conventional grease or the like excellent in thermal conductivity may be applied to the surface of the spacer 203 or the like, and the spacer 203 may be omitted. [Industrial Availability]

The semiconductor device of the present invention can be used in all fields, such as compound semiconductor electronic elements, electronic parts/electrical equipment parts, optical/electronic imaging related devices, and industrial components, and is especially applicable to power elements including oxide semiconductor layers.

1: First crystalline oxide semiconductor layer 2: Second crystalline oxide semiconductor layer 3: Third crystalline oxide semiconductor layer 3a: the first surface of the third crystalline oxide semiconductor layer 3b: the second surface of the third crystalline oxide semiconductor layer 4: 1st semiconductor region 4a: The first surface of the first semiconductor region 4b: The second side of the first semiconductor region 5: Second semiconductor region 6: Deep p-layer at outer position 6b: Buried lower end of deep p-layer 11: Groove 12: Insulating film 13: Gate electrode 13a: Upper end of gate electrode 13b: Buried lower end of gate electrode 21: heat dissipation department 21a: Side 1 21b: Side 2 22: The second concentration area 23: The first concentration area 24: Source electrode 25: Insulating film (interlayer insulating film) 26: drain electrode 50: Laminate 100: Semiconductor Devices 170: Power System 171: Power supply unit 172: Power supply unit 173: Control circuit 180: System installation 181: Electronic Circuits 182: Power System 192: reverser 193: Transformer 194: Rectifier MOSFET 195: DCL 196: PWM control circuit 197: Voltage Comparator 200: Semiconductor Devices 201: Two-sided cooling power card 202: Refrigerant pipe 203: Spacer 208: Insulation board (insulation spacer) 209: Sealing Resin Department 221: Dividing Wall 222: flow path 300: Semiconductor Devices 301a: Semiconductor wafers 302b: Metal thermal conductive plate (protruding terminal part) 303: Heat sinks and electrodes 303b: Metal thermal conductive plate (protruding terminal part) 304: Welding layer 305: Control electrode terminal 308: Bonding Wire 400: Semiconductor Devices 500: Semiconductor Devices 601: Atomization device (film forming device) 602: Atomization device (film forming device) 603: Substrate 621: Mounting Table 622a: Carrier gas supply 622b: Carrier gas (dilution) supply device 623a: Flow control valve 623b: Flow regulating valve 624: Mist generation source 624a: raw material solution 625: Container 625a: Water 626: Ultrasonic Vibrator 627: Supply Tube 628: Heater 629: exhaust port 630: Film forming chamber D: depth W: interval

FIG. 1 is a schematic perspective cross-sectional view showing a semiconductor device having a laminate including a crystalline oxide semiconductor layer. [ Fig. 2] Fig. 2 shows an evaluation result obtained by simulating the heat distribution generated around the gate electrode when a current is applied to the semiconductor device of Fig. 1 . 3 is a perspective cross-sectional view schematically showing a preferred example of a semiconductor device having a heat dissipation structure. FIG. 4 is a diagram schematically showing a cross section of the semiconductor device of FIG. 3 . 5 is a perspective cross-sectional view schematically showing a preferred example of a semiconductor device having a heat dissipation structure. FIG. 6 is a diagram schematically showing a cross section of the semiconductor device of FIG. 5 . 7 is a perspective cross-sectional view schematically showing a preferred example of a semiconductor device having a heat dissipation structure. FIG. 8 is a diagram schematically showing a cross section of the semiconductor device of FIG. 7 . 9 is a perspective cross-sectional view schematically showing a preferred example of a semiconductor device having a heat dissipation structure. FIG. 10 is a diagram schematically showing a cross section of the semiconductor device of FIG. 9 . [ Fig. 11 ] A diagram schematically showing a preferred example of a power supply system. [ Fig. 12 ] A diagram schematically showing a preferred example of a power supply circuit diagram of a power supply device. [ Fig. 13 ] A diagram schematically showing a preferred example of a power supply circuit diagram of a power supply device. FIG. 14 is a schematic diagram showing a film formation apparatus (atomized CVD apparatus) used for formation of a crystalline oxide semiconductor layer. FIG. 15 is a schematic diagram showing a film formation apparatus (atomized CVD apparatus) used for formation of a crystalline oxide semiconductor layer. [ Fig. 16 ] A diagram schematically showing a preferred example of a power card.

1: First crystalline oxide semiconductor layer

2: Second crystalline oxide semiconductor layer

3: Third crystalline oxide semiconductor layer

3a: the first surface of the third crystalline oxide semiconductor layer

6: Deep p-layer at outer position

7: p-type semiconductor layer (channel layer)

11: Groove

16: p+ type semiconductor layer

24: Source electrode

25: Insulating film (interlayer insulating film)

26: drain electrode

D: depth

W: interval

Claims (15)

A semiconductor device comprising at least a part of a gate electrode embedded in a crystalline oxide semiconductor layer, and a heat dissipation part having a thermal conductivity higher than that of the crystalline oxide semiconductor layer, wherein at least a part of the heat dissipation part is located in the In the crystalline oxide semiconductor layer, in the vicinity of the buried end portion of the gate electrode and/or at a position deeper than the buried end portion. The semiconductor device according to claim 1, wherein the buried end portion of the gate electrode is a buried lower end portion. The semiconductor device according to claim 2, wherein at least a part of the heat dissipation portion is located deeper than the embedded lower end portion. The semiconductor device according to claim 2 or 3, further comprising a deep p layer, at least a part of which is buried in the crystalline oxide semiconductor layer to the same depth as the buried lower end portion or a depth greater than that of the buried lower end portion deeper position. The semiconductor device of any one of claims 1 to 4, wherein the heat dissipation portion includes a conductive material. The semiconductor device of claim 5, wherein the conductive material is a p-type semiconductor. The semiconductor device of claim 6, wherein the p-type semiconductor has a concentration gradient of carrier concentration. The semiconductor device according to claim 6, wherein in the p-type semiconductor, the carrier concentration becomes higher toward the depth direction. The semiconductor device according to any one of claims 1 to 8, wherein the crystalline oxide semiconductor layer contains one or more metals selected from the group consisting of gallium, indium, and aluminum. The semiconductor device according to any one of claims 1 to 9, wherein the crystalline oxide semiconductor layer contains gallium. The semiconductor device according to any one of claims 1 to 10, which is a normally closed type. The semiconductor device according to any one of claims 1 to 11, which is a power element. The semiconductor device according to any one of claims 1 to 11, which is a power module, an inverter or a converter. The semiconductor device according to any one of claims 1 to 11, which is a power card. A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 14.

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