TW202213316A - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided, which includes a driving transistor, a light emission element, a light emission control circuit, a compensation circuit, a reset circuit, and a writing circuit. The light emission control circuit is configured to selectively conduct a first terminal and a second terminal of the driving transistor respectively to a first power node and the light emission element. The compensation circuit is configured to conduct a reference power node and a control terminal of the driving transistor through the first terminal and the second terminal of the driving transistor. The reset circuit and the compensation circuit are configured to cooperatively conduct the reference power node and a reset power node through the first terminal, the second terminal, and the control terminal of the driving transistor. The writing circuit is configured to control, by capacitive coupling, a voltage of the control terminal of the driving transistor.

Description

pixel circuit

The present disclosure relates to a pixel circuit, especially a pixel circuit capable of adjusting the threshold voltage compensation time.

Organic Light Emitting Diode (OLED) displays are favored by consumers due to their advantages of self-luminescence, wide viewing angle, high contrast, and low power consumption. Organic light emitting diode pixel circuits typically include multiple thin film transistors (TFTs) that act as switches or current sources. Due to process factors, the threshold voltage of each thin film transistor will be different, which may cause uneven brightness of the display screen. Therefore, OLED pixel circuits are usually designed to self-compensate for threshold voltage variations. The traditional threshold voltage compensation method is to provide a current path through the target thin film transistor to detect and record the threshold voltage of the target thin film transistor at one end of the capacitor, while the data line provides a voltage to the other end of the capacitor to stabilize the capacitance across the capacitor. pressure. However, in the aforementioned compensation method, only one row of pixel circuits can perform compensation at the same time, so it is not suitable for high-resolution displays.

The present disclosure provides a pixel circuit including a driving transistor, a light-emitting unit, a light-emitting control circuit, a compensation circuit, a reset circuit, and a writing circuit. The light-emitting control circuit is used for selectively conducting a first terminal and a second terminal of the driving transistor to a first power terminal and a light-emitting unit, respectively. The compensation circuit is used for connecting a reference power terminal with a control terminal of the driving transistor through the first terminal and the second terminal of the driving transistor. The reset circuit is used together with the compensation circuit to connect the reference power terminal with a reset power terminal through the first terminal, the second terminal and the control terminal of the driving transistor. The writing circuit is used for controlling the voltage of the control terminal of the driving transistor through capacitive coupling.

One of the advantages of the above embodiment is that the time length for compensating the threshold voltage of the driving transistor is not limited by the writing time of the data voltage.

The embodiments of the present disclosure will be described below in conjunction with the relevant drawings. In the drawings, the same reference numbers refer to the same or similar elements or method flows.

FIG. 1 is a functional block diagram of a pixel circuit 100 according to an embodiment of the present disclosure. The pixel circuit 100 includes a driving transistor Td, a lighting control circuit 110 , a compensation circuit 120 , a reset circuit 130 , a writing circuit 140 and a lighting unit 150 . The driving transistor Td, the light emitting unit 150 and the light emitting control circuit 110 are coupled to each other in series. A part of the light emitting control circuit 110 is coupled between the first terminal of the driving transistor Td and the first power terminal 101, wherein the first power terminal 101 is used for providing the first operating voltage OVDD. Another part of the light-emitting control circuit 110 is coupled between the second end of the driving transistor Td and the light-emitting unit 150 . The light-emitting control circuit 110 is configured to selectively conduct the first terminal and the second terminal of the driving transistor Td to the first power terminal 101 and the light-emitting unit 150 , respectively. The light-emitting unit 150 is coupled between the driving transistor Td and the second power terminal 102, wherein the second power terminal 102 is used for providing the second operating voltage OVSS.

In some embodiments, the light emitting unit 150 is implemented by an organic light emitting diode (OLED) or a micro light emitting diode (Micro LED), and the light emitting unit 150 is coupled to the driving transistor Td and the driving transistor Td and the cathode respectively with its anode and cathode. The second power terminal 102 .

The compensation circuit 120 is coupled to the reference power terminal 103 , the first terminal of the driving transistor Td, the second terminal of the driving transistor Td and the control terminal (ie the second node N2 ) of the driving transistor Td, wherein the reference power terminal 103 Used to provide the reference voltage Vref. The compensation circuit 120 is used to connect the reference power terminal 103 with the control terminal of the driving transistor Td through the first terminal of the driving transistor Td and the second terminal of the driving transistor Td. That is, the compensation circuit 120 is used to generate the current flowing from the reference power terminal 103 through the first terminal of the driving transistor Td and the second terminal of the driving transistor Td to the control terminal of the driving transistor Td, so as to record the driving transistor Td the critical voltage.

The reset circuit 130 is coupled between the control terminal (ie, the second node N2 ) of the driving transistor Td and the reset power terminal 104 , wherein the reset power terminal 104 is used for providing the reset voltage Vini. The reset circuit 130 is used to connect the reference power terminal 103 with the reset power terminal 104 through the first terminal, the second terminal and the control terminal of the driving transistor Td together with the compensation circuit 120 . That is, the compensation circuit 120 and the reset circuit 130 are simultaneously enabled to reset the voltage of the internal nodes of the pixel circuit 100 .

The writing circuit 140 is coupled between the control terminal (ie, the second node N2 ) of the driving transistor Td and the data line 105 , wherein the data line 105 is used for providing the data voltage Vdata, and the data voltage Vdata is used for specifying the light-emitting unit 150 The resulting grayscale value (brightness). The writing circuit 140 is used for indirectly transmitting the data voltage Vdata to the control terminal of the driving transistor Td through capacitive coupling, and the writing circuit 140 and the compensation circuit 120 are not enabled simultaneously. In this way, when a plurality of pixel circuits 100 are applied in a display panel and arranged in a plurality of columns, a plurality of the pixel circuits 100 in the plurality of columns can perform the threshold voltage detection operation in parallel.

Referring to FIG. 1 again, the detailed structure of each circuit block in the pixel circuit 100 will be described below. The light emission control circuit 110 includes a first transistor T1 and a second transistor T2, wherein the first transistor T1 and the second transistor T2 each include a first terminal, a second terminal and a control terminal. The first terminal and the second terminal of the first transistor T1 are respectively coupled to the first power terminal 101 and the first terminal of the driving transistor Td. The first end and the second end of the second transistor T2 are respectively coupled to the second end of the driving transistor Td and the light emitting unit 150 (eg, the anode end of the light emitting unit 150 ), wherein the first transistor T1 and the second transistor T1 The control terminals of T2 are all used for receiving the light-emitting control signal EM.

The compensation circuit 120 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a first capacitor C1, wherein the third transistor T3, the fourth transistor T4 and the fifth transistor T5 all include a first terminal , the second terminal and the control terminal. The first terminal and the second terminal of the third transistor T3 are respectively coupled to the reference power terminal 103 and the first node N1. The first end and the second end of the fourth transistor T4 are respectively coupled to the first node N1 and the first end of the driving transistor Td. The first end and the second end of the fifth transistor T5 are respectively coupled to the control end and the second end of the driving transistor Td, wherein the control ends of the third transistor T3, the fourth transistor T4 and the fifth transistor T5 Both are used for receiving the first control signal S1. The first capacitor C1 is coupled between the first power terminal 101 and the first node N1.

The reset circuit 130 includes a sixth transistor T6, and the sixth transistor T6 includes a first terminal, a second terminal and a control terminal. The first terminal and the second terminal of the sixth transistor T6 are respectively coupled to the control terminal of the driving transistor Td and the reset power terminal 104 . The control end of the sixth transistor T6 is used for receiving the second control signal S2.

The writing circuit 140 includes a seventh transistor T7 and a second capacitor C2, wherein the seventh transistor T7 includes a first terminal, a second terminal and a control terminal. The first end and the second end of the seventh transistor T7 are respectively coupled to the data line 105 and the first node N1. The control terminal of the seventh transistor T7 is used for receiving the third control signal S3. The second capacitor C2 is coupled between the first node N1 and the control terminal of the driving transistor Td.

In some embodiments, the transistors in the pixel circuit 100 can be implemented with various suitable P-type transistors, such as P-type thin film transistors, P-type MOSFETs, or P-type bipolar transistors, etc. Wait.

FIG. 2 is a simplified waveform diagram of a plurality of control signals provided to the pixel circuit 100 in an embodiment. As shown in FIG. 2 , the operation flow of the pixel circuit 100 includes a reset stage 210 , a compensation stage 220 , a writing stage 230 and a light-emitting stage 240 , which are executed in sequence. time) is executed. 3A to 3D are schematic diagrams illustrating equivalent circuit operations of the pixel circuit 100 in the reset stage 210 , the compensation stage 220 , the writing stage 230 , and the light-emitting stage 240 , respectively. The operation flow of the pixel circuit 100 will be described below with reference to FIG. 2 in conjunction with FIGS. 3A to 3D. The transistors marked with a cross indicate that it is in an off state, and the transistors that are not marked with a cross indicate that it is in an off state. On state.

First, please refer to Figure 2 and Figure 3A. In the reset phase 210, the first control signal S1 and the second control signal S2 are at a logic high level (eg, a low voltage that can turn on the P-type transistor), and the third control signal S3 and the light-emitting control signal The signal EM is a logic low level (eg, a high voltage that can turn off the P-type transistor). Therefore, the first transistor T1 , the second transistor T2 and the seventh transistor T7 are turned off, and the remaining transistors in the pixel circuit 100 are turned on. At this time, the reference power terminal 103 and the reset power terminal 104 are connected to each other through the current path 310 marked by the dotted line in FIG. 3A to reset the voltage of the first node N1 and the voltage of the control terminal of the driving transistor Td (hereinafter referred to as the control terminal voltage Vg).

《公式1》 Next, please refer to Figure 2 and Figure 3B. In the compensation stage 220, the first control signal S1 is at a logic high level, and the second control signal S2, the third control signal S3 and the lighting control signal EM are at a logic low level. Therefore, the first transistor T1 , the second transistor T2 , the sixth transistor T6 and the seventh transistor T7 are turned off, and the remaining transistors in the pixel circuit 100 are turned on. At this time, the reference power supply terminal 103 and the control terminal of the driving transistor Td are connected to each other through the current path 320 marked by the dotted line in FIG. 3B, so that the control terminal voltage Vg in the compensation stage 220 can be represented by the following "Equation 1", where the symbol "Vth" represents the threshold voltage of the driving transistor Td.

"Formula 1"

That is, the threshold voltage of the driving transistor Td is recorded at the control terminal of the driving transistor Td in the compensation stage 220 .

《公式2》 Please refer to Figure 2 and Figure 3C. In the data writing stage 230 , the third control signal S3 has a logic high level, and the first control signal S1 , the second control signal S2 and the lighting control signal EM have a logic low level. Therefore, only the driving transistor Td and the seventh transistor T7 are turned on, and the remaining transistors in the pixel circuit 100 are turned off. At this time, the data voltage Vdata is transmitted to the first node N1 through the seventh transistor T7, and the voltage variation of the first node N1 is transmitted to the control terminal of the driving transistor Td due to capacitive coupling, so that the control terminal The voltage Vg in the writing phase 230 can be represented by the following "Equation 2".

"Formula 2"

《公式3》 Please refer to Figure 2 and Figure 3D. In the light-emitting stage 240, the light-emitting control signal EM has a logic high level, and the first control signal S1, the second control signal S2 and the third control signal S3 have a logic low level. Therefore, the first transistor T1 , the second transistor T2 and the driving transistor Td are turned on, and the remaining transistors in the pixel circuit 100 are turned off. At this time, the driving transistor Td will provide the driving current Id to the light emitting unit 150 so that the light emitting unit 150 can generate corresponding brightness, wherein the magnitude of the driving current Id can be represented by the following "Equation 3".

"Formula 3"

It can be seen from the above that the magnitude of the driving current Id is almost independent of the threshold voltage of the driving transistor Td, so it is hardly affected by the variation of the threshold voltage of the driving transistor Td. Therefore, the pixel matrix formed by the pixel circuit 100 can provide uniform brightness.

In addition, since the pixel circuit 100 does not need to use the voltage provided by the data line 105 in the compensation stage 220, the multi-column pixel circuit 100 of the pixel matrix formed by the pixel circuit 100 can execute the compensation stage 220 in parallel, thereby speeding up one frame of pictures update speed. Therefore, the pixel circuit 100 is suitable for high resolution or high frame rate display applications.

FIG. 4 is a functional block diagram of a pixel circuit 400 according to an embodiment of the present disclosure. The pixel circuit 400 is similar to the pixel circuit 100 in FIG. 1 , except that the pixel circuit 400 replaces the reset circuit 130 with a reset circuit 430 . The reset circuit 430 includes a sixth transistor T6 and an eighth transistor T8, wherein the sixth transistor T6 and the eighth transistor T8 include a first terminal, a second terminal and a control terminal, respectively. The first terminal and the second terminal of the sixth transistor T6 are respectively coupled to the control terminal of the driving transistor Td and the reset power terminal 104 . The control end of the sixth transistor T6 is used for receiving the second control signal S2. The first terminal and the second terminal of the eighth transistor T8 are respectively coupled to the reset power terminal 104 and the light-emitting unit 150 (eg, the anode of the light-emitting unit 150 ). The control terminal of the eighth transistor T8 is used for receiving the third control signal S3.

The control signal waveforms in the aforementioned FIG. 2 are also applicable to the pixel circuit 400 . That is, the operation process of the pixel circuit 100 is similar to that of the pixel circuit 400 , the difference is that the eighth transistor T8 of the pixel circuit 400 is turned on in the reset stage 210 to reset the light-emitting unit 150 . The remaining connection methods, components, implementations, and advantages of the pixel circuit 100 described above are all applicable to the pixel circuit 400 , and are not repeated here for the sake of brevity.

FIG. 5 is a functional block diagram of a pixel circuit 500 according to an embodiment of the present disclosure. The pixel circuit 500 is similar to the pixel circuit 100 in FIG. 1 , except that the compensation circuit 120 is replaced by the compensation circuit 520 in the pixel circuit 500 . The difference between the compensation circuit 520 and the compensation circuit 120 is that the first end and the second end of the fourth transistor T4 of the compensation circuit 520 are respectively coupled to the first end of the driving transistor Td and the reference power supply end 103 . The control signal waveforms in the above-mentioned FIG. 2 are also applicable to the pixel circuit 500 . Therefore, the remaining connection methods, components, implementations, and advantages of the pixel circuit 100 described above are all applicable to the pixel circuit 500, and are not repeated here for the sake of brevity.

In some embodiments, the reset circuit 130 of the pixel circuit 500 can be replaced with the reset circuit 430 of FIG. 4 .

In some embodiments, the control signal waveforms shown in FIG. 6 are applicable to the pixel circuits 100 , 400 and 500 . In this case, the control terminal of the third transistor T3 of the pixel circuits 100, 400 and 500 is used to receive the first control signal S1; the control terminal of the fourth transistor T4 of the pixel circuits 100, 400 and 500 is used to receive the first control signal S1. and the control terminal of the fifth transistor T5 for receiving the fourth control signal S4, wherein the first control signal S1 is different from the fourth control signal S4.

FIG. 7 is a functional block diagram of a pixel circuit 700 according to an embodiment of the present disclosure. The pixel circuit 700 is similar to the pixel circuit 100 in FIG. 1 , except that the compensation circuit 120 is replaced by the compensation circuit 720 in the pixel circuit 700 . The difference between the compensation circuit 720 and the compensation circuit 120 is that the first end and the second end of the third transistor T3 of the compensation circuit 720 are respectively coupled to the first end of the driving transistor Td and the reference power supply end 103 , and the compensation circuit The control terminal of the third transistor T3 of 720 is used for receiving the first control signal S1. The control signal waveforms in FIG. 2 above are also applicable to the pixel circuit 700 . Therefore, the remaining connection methods, components, implementations, and advantages of the pixel circuit 100 described above are all applicable to the pixel circuit 700 , and for the sake of brevity, they will not be repeated here.

In some embodiments, the reset circuit 130 of the pixel circuit 700 can be replaced with the reset circuit 430 of FIG. 4 .

In the foregoing embodiments, the transistors in the pixel circuits 100 , 400 , 500 and 700 are implemented by P-type transistors, but the present disclosure is not limited thereto. One or more of the first to sixth transistors T1 to T6 of the pixel circuits 100 , 400 , 500 and 700 may also be implemented by N-type transistors instead.

To sum up, the pixel circuits 100 , 400 , 500 and 700 do not need to use the voltage provided by the data line 105 when compensating for the threshold voltage of the driving transistor Td. Therefore, the length of time for the pixel circuits 100, 400, 500 and 700 to compensate the threshold voltage of the driving transistor Td is not limited by the writing time of the data voltage Vdata, so that multiple columns in the pixel matrix formed can perform compensation in parallel , while making the pixel circuits 100, 400, 500 and 700 suitable for high resolution or high frame rate display applications.

Certain terms are used in the specification and claims to refer to particular elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The description and the scope of the patent application do not use the difference in name as a way of distinguishing elements, but use the difference in function of the elements as a basis for distinguishing. The "comprising" mentioned in the description and the scope of the patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.

In addition, unless otherwise specified in the specification, any term in the singular also includes the meaning in the plural.

The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made according to the claims of the present disclosure shall fall within the scope of the present disclosure.

100,400,500,700: pixel circuit 101: The first power terminal 102: The second power terminal 103: Reference power terminal 104: Reset the power terminal 105: Data line 110: Lighting control circuit 120,520,720: Compensation circuit 130,430: Reset Circuit 140: Write circuit 150: Lighting unit Td: drive transistor T1: first transistor T2: Second transistor T3: The third transistor T4: Fourth transistor T5: Fifth transistor T6: sixth transistor T7: seventh transistor T8: Eighth transistor C1: first capacitor C2: second capacitor S1: The first control signal S2: The second control signal S3: The third control signal EM: Illumination control signal N1: the first node N2: second node Vg: control terminal voltage OVDD: The first working voltage OVSS: Second operating voltage Vref: reference voltage Vini: reset voltage Vdata: data voltage 210: Reset Phase 220: Compensation Phase 230: write phase 240: Glow Stage Id: drive current 310, 320: Current Path

FIG. 1 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure. FIG. 2 is a simplified waveform diagram of a plurality of control signals provided to the pixel circuit in one embodiment. FIG. 3A is a schematic diagram of the equivalent circuit operation of the pixel circuit in the reset stage. FIG. 3B is a schematic diagram of the equivalent circuit operation of the pixel circuit in the compensation stage. FIG. 3C is a schematic diagram of the equivalent circuit operation of the pixel circuit in the writing stage. FIG. 3D is a schematic diagram of the equivalent circuit operation of the pixel circuit in the light-emitting stage. FIG. 4 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure. FIG. 5 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure. FIG. 6 is a simplified waveform diagram of a plurality of control signals provided to the pixel circuit in one embodiment. FIG. 7 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure.

100: pixel circuit

101: The first power terminal

102: The second power terminal

103: Reference power terminal

104: Reset the power terminal

105: Data line

110: Lighting control circuit

120: Compensation circuit

130: reset circuit

140: Write circuit

150: Lighting unit

Td: drive transistor

T1: first transistor

T2: Second transistor

T3: The third transistor

T4: Fourth transistor

T5: Fifth transistor

T6: sixth transistor

T7: seventh transistor

C1: first capacitor

C2: second capacitor

S1: The first control signal

S2: The second control signal

S3: The third control signal

EM: Illumination control signal

N1: the first node

N2: second node

OVDD: The first working voltage

OVSS: Second operating voltage

Vref: reference voltage

Vini: reset voltage

Vdata: data voltage

Claims (10)

A pixel circuit, including: a drive transistor; a light-emitting unit; a light-emitting control circuit for selectively conducting a first terminal and a second terminal of the driving transistor to a first power terminal and the light-emitting unit, respectively; a compensation circuit for connecting a reference power terminal with a control terminal of the driving transistor through the first terminal and the second terminal of the driving transistor; a reset circuit, configured to conduct the reference power terminal with a reset power terminal through the first terminal, the second terminal and the control terminal of the driving transistor together with the compensation circuit; and a writing circuit for controlling the voltage of the control terminal of the driving transistor through capacitive coupling. The pixel circuit of claim 1, wherein the light-emitting control circuit comprises: a first transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal and the second terminal of the first transistor are respectively coupled to the first power terminal and the driving power terminal the first end of the crystal; a second transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal and the second terminal of the second transistor are respectively coupled to the second terminal of the driving transistor With the light-emitting unit, the control end of the first transistor and the control end of the second transistor are used for receiving a light-emitting control signal. The pixel circuit of claim 1, wherein the compensation circuit comprises: a third transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal and the second terminal of the third transistor are respectively coupled to the reference power terminal and a first node ; a fourth transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal and the second terminal of the fourth transistor are respectively coupled to the first node and the driving transistor the first end of ; A fifth transistor including a first end, a second end and a control end, wherein the first end and the second end of the fifth transistor are respectively coupled to the control end and the control end of the driving transistor the second end of the drive transistor; and A first capacitor is coupled between the first power terminal and the first node. The pixel circuit of claim 1, wherein the compensation circuit comprises: a third transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal and the second terminal of the third transistor are respectively coupled to the reference power terminal and a first node ; a fourth transistor including a first end, a second end and a control end, wherein the first end and the second end of the fourth transistor are respectively coupled to the first end of the driving transistor and the reference power terminal; A fifth transistor including a first end, a second end and a control end, wherein the first end and the second end of the fifth transistor are respectively coupled to the control end and the control end of the driving transistor the second end of the drive transistor; and A first capacitor is coupled between the first power terminal and the first node. The pixel circuit of claim 3 or 4, wherein the control terminal of the third transistor is used to receive a first control signal, the control terminal of the fourth transistor and the control terminal of the fifth transistor The control terminal is used for receiving another signal different from the first control signal. The pixel circuit of claim 1, wherein the compensation circuit comprises: a third transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal and the second terminal of the third transistor are respectively coupled to the first terminal of the driving transistor with the reference power supply terminal; a fourth transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal and the second terminal of the fourth transistor are respectively coupled to a first node and the driving transistor the first end of ; A fifth transistor including a first end, a second end and a control end, wherein the first end and the second end of the fifth transistor are respectively coupled to the control end and the control end of the driving transistor the second end of the drive transistor; and A first capacitor is coupled between the first power terminal and the first node. The pixel circuit of claim 3, 4 or 6, wherein the control terminal of the third transistor, the control terminal of the fourth transistor and the control terminal of the fifth transistor are used to receive a the first control signal. The pixel circuit of claim 1, wherein the reset circuit comprises: a sixth transistor including a first end, a second end and a control end, wherein the first end and the second end of the sixth transistor are respectively coupled to the control end and the control end of the driving transistor The reset power terminal, the control terminal of the sixth transistor is used for receiving a second control signal. The pixel circuit of claim 1, wherein the writing circuit comprises: a seventh transistor including a first end, a second end and a control end, wherein the first end and the second end of the seventh transistor are respectively coupled to a data line and a first node, The control terminal of the seventh transistor is used for receiving a third control signal; and A second capacitor is coupled between the first node and the control terminal of the driving transistor. The pixel circuit as described in any one of claims 1 to 4, 6, and 8 to 9, further comprising: An eighth transistor is coupled between the light-emitting unit and the reset power terminal for selectively turning on the light-emitting unit and the reset power terminal.

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