TW202211328A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202211328A
TW202211328A TW110117011A TW110117011A TW202211328A TW 202211328 A TW202211328 A TW 202211328A TW 110117011 A TW110117011 A TW 110117011A TW 110117011 A TW110117011 A TW 110117011A TW 202211328 A TW202211328 A TW 202211328A
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Taiwan
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semiconductor
insulating layer
dummy
pad
pads
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TW110117011A
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English (en)
Inventor
朴相天
李榮敏
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南韓商三星電子股份有限公司
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Publication of TW202211328A publication Critical patent/TW202211328A/zh

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Abstract

本發明提供一種半導體封裝，包含：第一結構，具有第一絕緣層以及穿透第一絕緣層且安置於第一絕緣層的一個表面上的第一電極接墊及第一虛設接墊；第二結構，具有含有接合至第一絕緣層的一個表面的另一表面的第二絕緣層以及穿透第二絕緣層且安置於第二絕緣層的另一表面上的第二電極接墊及第二虛設接墊，第二電極接墊分別接合至第一電極接墊，且第二虛設接墊分別接合至第一虛設接墊。在半導體封裝中，一個表面及另一表面上的第一虛設接墊及第二虛設接墊與第一絕緣層及第二絕緣層的每單位面積的表面積的比朝向第一結構及第二結構的側面逐漸減小。

Description

半導體封裝
本發明概念的實例實施例是關於一種半導體封裝。
隨著電子工業的發展，對電子組件的高功能性、高速度以及小型化的需求不斷增大。根據此趨勢，愈來愈多地使用將若干半導體晶片堆疊且安裝於單個半導體基板上或將多個封裝堆疊於一個封裝上的半導體封裝方法。然而，隨著待堆疊的半導體晶片的連接接墊變得更精細，其中堆疊半導體晶片的半導體封裝的可靠性可能降低。
實例實施例提供一種具有改良的可靠性的半導體封裝。
根據實例實施例，半導體封裝包含：第一結構，包含第一絕緣層、第一電極接墊以及第一虛設接墊，第一虛設接墊在第一絕緣層的表面上圍繞第一電極接墊，其中第一電極接墊及第一虛設接墊穿透第一絕緣層，第一電極接墊具有20微米或小於20微米的間距，且第一絕緣層的表面上的第一虛設接墊與第一絕緣層的每單位面積的表面積的比朝向第一結構的側面逐漸減小；以及第二結構，包含第二絕緣層、第二電極接墊以及第二虛設接墊，第二絕緣層接合至第一絕緣層，其中第二虛設接墊在接合至第一絕緣層的表面的第二絕緣層的表面上圍繞第二電極接墊，其中第二電極接墊及第二虛設接墊穿透第二絕緣層以使得第二電極接墊分別接合至第一電極接墊，且第二虛設接墊分別接合至第一虛設接墊，且第二絕緣層的表面上的第二虛設接墊與第二絕緣層的每單位面積的表面積的比朝向第二結構的側面逐漸減小。
根據實例實施例，半導體封裝包含：下部結構，包含在其第一區域及第二區域中的上部絕緣層，其中第二區域包圍第一區域，第一區域包含穿透上部絕緣層的上部電極接墊，第二區域包含穿透上部絕緣層的上部虛設接墊，其中第二區域中的上部虛設接墊與上部絕緣層的每單位面積的表面積的比朝向下部結構的側面減小；以及半導體晶片，包含下部絕緣層、下部電極接墊以及下部虛設接墊，下部絕緣層與上部絕緣層接觸且耦接至上部絕緣層，其中下部電極接墊及下部虛設接墊穿透下部絕緣層以使得下部電極接墊及下部虛設接墊分別與上部電極接墊及上部虛設接墊接觸且耦接至上部電極接墊及上部虛設接墊。
根據實例實施例，半導體封裝包含下部結構；以及在下部結構上的多個半導體晶片，多個半導體晶片包含：具有前表面及後表面的第一半導體晶片，其中上部絕緣層、上部電極接墊以及上部虛設接墊在其後表面上，其中第一半導體晶片的後表面上的上部虛設接墊與上部絕緣層的每單位面積的表面積的比朝向第一半導體晶片的側面逐漸減小，以及第二半導體晶片，與第一半導體晶片直接接觸，第二半導體晶片具有前表面及後表面，其中下部絕緣層、下部電極接墊以及下部虛設接墊在其前表面上以使得下部絕緣層與上部絕緣層彼此接觸及耦接，下部電極接墊與上部電極接墊彼此接觸及耦接，且下部虛設接墊與上部虛設接墊彼此接觸及耦接，其中第二半導體晶片的前表面上的下部虛設接墊與下部絕緣層的每單位面積的表面積的比朝向第二半導體晶片的側面逐漸減小。
在下文中，將參考附圖詳細地描述本揭露的各種實例實施例。
將參考圖1至圖3描述根據本揭露的實例實施例的半導體封裝。圖1為說明根據本揭露的實例實施例的半導體封裝的側橫截面圖，且圖2為圖1的部分’A’的放大圖。圖3為說明安置於圖1的上部部分上的半導體晶片的接合表面的平面圖。
參考圖1，半導體封裝1A可包含下部結構100及下部結構100上的半導體晶片200。半導體晶片200可為記憶體半導體晶片或邏輯半導體晶片。舉例而言，記憶體半導體晶片可為諸如動態隨機存取記憶體（dynamic random access memory；DRAM）或靜態隨機存取記憶體（static random access memory；SRAM）的揮發性記憶體晶片或諸如相變隨機存取記憶體（phase-change random access memory；PRAM）、磁阻式隨機存取記憶體（magnetoresistive random access memory；MRAM）、鐵電隨機存取記憶體（ferroelectric random access memory；FeRAM）或電阻式隨機存取記憶體（resistive random access memory；RRAM）的非揮發性記憶體晶片，且邏輯半導體晶片可為微處理器、類比裝置或數位信號處理器。
在實例實施例中，下部結構100可為與半導體晶片200不同的下部半導體晶片。然而，實例實施例不限於此。舉例而言，下部結構100可為中介層。
參考圖1及圖2，下部結構100可包含上部絕緣層190、上部電極接墊195A以及上部虛設接墊195D。半導體晶片200可包含與上部絕緣層190接觸且耦接至上部絕緣層190的半導體下部絕緣層250、與上部電極接墊195A接觸且耦接至上部電極接墊195A的半導體下部電極接墊255A以及與上部虛設接墊195D接觸且耦接至上部虛設接墊195D的半導體下部虛設接墊255D。半導體晶片200可包含側面201S。
上部電極接墊195A及半導體下部電極接墊255A可在彼此接觸的同時耦接，且可由例如銅或其類似者的導電材料形成。
上部虛設接墊195D及半導體下部虛設接墊255D可在彼此接觸的同時耦接，且可由例如銅或其類似者的導電材料形成。具體言之，上部虛設接墊195D及半導體下部虛設接墊255D可由銅、鎳、金以及銀或其合金中的任一者形成。
上部絕緣層190及半導體下部絕緣層250可在彼此接觸的同時耦接，且可由例如氧化矽的絕緣材料形成。然而，上部絕緣層190及半導體下部絕緣層250不僅由氧化矽形成，還可由SiCN或其類似者形成。
半導體封裝1A可更包含安置於下部結構100上且覆蓋半導體晶片200的模製層310。
半導體封裝1A可更包含在下部結構100下方的基底10及實體地連接基底10及下部結構100的連接結構50。基底10可為印刷電路板、中介層或半導體晶片。連接結構50可為焊球或凸塊。
參考圖1至圖3，上文所描述的半導體晶片200可具有與下部結構100接觸的前表面201F及安置於前表面201F的相對側上的後表面201B。半導體晶片200的前表面201F可與下部結構100接觸且耦接至下部結構100。半導體晶片200的側面201S可自後表面201B的邊緣在實質上垂直於後表面201B的方向上延伸。
半導體晶片200可包含半導體本體210、半導體本體210下方的半導體內部電路區域235、半導體內部電路區域235下方的半導體下部絕緣層250、半導體下部電極接墊255A以及半導體下部虛設接墊255D。
半導體本體210可為半導體基板，且半導體內部電路區域235可安置於半導體本體210的前表面210f上。
半導體內部電路區域235可包含半導體內部電路215及電連接半導體內部電路215及半導體下部電極接墊255A的半導體內部佈線240。半導體內部電路215及半導體內部佈線240可安置於半導體內部絕緣層245中。
半導體下部電極接墊255A及半導體下部虛設接墊255D可各自穿透半導體下部絕緣層250且與半導體下部絕緣層250一起形成共面的前表面201F。
參考圖3，半導體下部電極接墊255A可配置於作為半導體晶片200的前表面201F的中心區域的第一區域A1中。半導體下部虛設接墊255D可配置於作為第一區域A1的圓周區域的第二區域A2中。
參考圖4A，半導體下部電極接墊255A可配置成以具有實質上相同距離的第一間距P1彼此間隔開，且各自可具有實質上相同大小的第一大小D1。在實例實施例中，第一間距P1可在20微米或小於20微米的範圍內，例如在10微米至20微米的範圍內。間距可與相鄰圖案（諸如相鄰線）之間的距離（諸如相鄰圖案的中心線之間的距離）相對應。間距可與週期性距離（例如相鄰圖案的中心線之間的重複距離）相對應；然而實例實施例不限於此，且間距可與僅兩個相鄰圖案之間的中心對中心距離相對應。
另外，半導體下部虛設接墊255D可配置成具有自第一區域A1與第二區域A2之間的邊界朝向半導體晶片200的側面201S逐漸減小的大小D2、大小D3以及大小D4，且可配置成以相同第一間距P1與半導體下部電極接墊255A間隔開。
以此方式，由於半導體下部虛設接墊255D朝向半導體晶片200的側面201S變得愈來愈小，因此作為半導體下部虛設接墊255D與半導體下部絕緣層250的每單位面積的表面積的比的接墊密度可自與第一區域A1的邊界朝向半導體晶片200的側面201S逐漸減小。舉例而言，半導體下部虛設接墊255D與半導體下部絕緣層250的每單位面積的表面積的比可自與第一區域A1的邊界朝向半導體晶片200的側面201S逐漸減小如0.1、0.09以及0.08。因此，在滿足半導體下部虛設接墊255D與半導體下部絕緣層250的每單位面積的表面積的比朝向半導體晶片200的側面201S逐漸減小的條件的範圍內，可對半導體下部虛設接墊255D的大小及間距進行各種修改。舉例而言，可在0.06微米至0.1微米的範圍內選擇半導體下部虛設接墊255D的大小，且可在0.3微米至0.5微米的範圍內選擇半導體下部虛設接墊255D的間距。此外，當半導體晶片200的大小為1公分×1公分且半導體下部電極接墊255A的大小為10微米時，可配置約30,000個半導體下部虛設接墊255D。
圖4B說明圖4A中所說明的部分’B’中的第一區域A1及第二區域A2的接墊密度。可見，第一區域A1的接墊密度具有恆定密度值H，但第二區域A2的接墊密度逐步地逐漸減小。
圖5及圖6為說明半導體下部虛設接墊的各種修改實例的圖。
圖5說明第二區域A2中的半導體下部虛設接墊1255D的大小D1固定且間距P2、間距P3以及間距P4逐漸增大的情況。因此，第二區域A2的接墊密度可自第一區域A1與第二區域A2之間的邊界朝向半導體晶片1200的側面1201S逐漸減小。在第一區域A1中，半導體下部電極接墊1255A之間的間距P1及半導體下部電極接墊1255A與半導體下部虛設接墊1255D之間的距離可實質上相同。
圖6說明一實例，其中在第二區域A2中，半導體下部虛設接墊2255D的大小D6、大小D7以及大小D8逐漸減小且間距P6、間距P7以及間距P8亦逐漸減小，第二區域A2中的接墊密度自第一區域A1與第二區域A2之間的邊界朝向半導體晶片2200的側面2201S逐漸減小。接墊密度隨著半導體下部虛設接墊2255D的間距P6、間距P7以及間距P8減小而增大，但由於半導體下部虛設接墊2255D的大小D6、大小D7以及大小D8的減小而導致的接墊密度減小大於由於間距P6、間距P7以及間距P8的減小而導致的接墊密度增大，且因此接墊密度逐漸減小。
圖1中所描述的下部結構100可為下部結構100A，所述下部結構100A包含下部本體110、下部本體110下方的下部保護絕緣層165及下部連接接墊170A、下部本體110上的下部內部電路區域135以及下部內部電路區域135上的上部絕緣層190、上部電極接墊195A以及上部虛設接墊195D。上部電極接墊195A及上部虛設接墊195D可分別直接連接至半導體晶片200的半導體下部電極接墊255A及半導體下部虛設接墊255D。因此，上部電極接墊195A及上部虛設接墊195D可配置成分別與半導體晶片200的半導體下部電極接墊255A及半導體下部虛設接墊255D相對應。由於上部電極接墊195A及上部虛設接墊195D的配置與上文所描述的半導體晶片200的半導體下部電極接墊255A及半導體下部虛設接墊255D相同，因此將省略其詳細描述。
下部本體110可為諸如矽基板的半導體基板。下部內部電路區域135可安置於下部本體110的前表面110F上，且下部保護絕緣層165及下部連接接墊170A可安置於下部本體110的後表面110B上。
下部結構100A可包含穿透下部本體110且電連接下部連接接墊170A及上部電極接墊195A的貫穿電極結構120。貫穿電極結構120可包含由諸如銅的導電材料形成的貫穿電極130及包圍貫穿電極130的側面的絕緣隔片125。
下部內部電路區域135可包含下部內部電路115及電連接下部內部電路115與上部電極接墊195A的下部內部佈線140。下部內部電路115及下部內部佈線140可安置於下部內部絕緣層145中。
因此，下部結構100A可為包含面向半導體晶片200的下部內部電路區域135的半導體晶片。
圖7為說明圖3中所說明的半導體晶片的修改實例的平面圖，且圖8為圖7的部分’C’的放大圖。圖7說明其中配置有半導體下部電極接墊3255A的多個第一區域A3及第一區域A4安置於一個半導體晶片3200的前表面3201F上的情況。即使當多個第一區域A3及第一區域A4安置於一個半導體晶片3200上時，安置在半導體晶片3200的邊緣處的第二區域A5的第一部分A5A的接墊密度（亦即，半導體下部虛設接墊3255D與半導體下部絕緣層3250的每單位面積的表面積的比）自第一區域A3與第一區域A4之間的邊界朝向半導體晶片3200的側面3201S逐漸減小的事實與上述實例實施例相同。然而，安置於第一區域A3與第一區域A4之間的第二區域A5的第二部分A5B的接墊密度可逐漸減小且接著增大。
具體言之，如圖8中所說明，當以相同間距配置半導體下部虛設接墊3255D時，半導體下部虛設接墊3255D的大小可在第一區域A3與第一區域A4之間逐漸減小且接著增大。
接著，將參考圖9及圖10描述根據本揭露的實例實施例的半導體封裝的修改實例。圖9為說明根據本揭露的實例實施例的半導體封裝的橫截面圖，且圖10為圖9的部分’D’的放大圖。
參考圖9及圖10，半導體封裝1B可包含基底10、藉由基底10上的連接結構50耦接至基底10的下部結構100以及下部結構100上的多個半導體晶片500。半導體封裝1B可更包含覆蓋多個半導體晶片500的側面501S的模製層610。
在實例實施例中，基底10可為印刷電路板或半導體晶片。
在實例實施例中，下部結構100可與圖1中所描述的下部結構相同。
在實例實施例中，多個半導體晶片500可包含一或多個下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C，以及一或多個下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C上的上部半導體晶片500D。
在實例實施例中，在多個下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C的情況下，多個下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C可具有相同形狀或相同結構。
多個半導體晶片500中的每一者可包含半導體本體510、半導體本體510下方的半導體內部電路區域535、半導體內部電路區域535下方的半導體下部絕緣層550、半導體下部電極接墊555A以及半導體下部虛設接墊555D。半導體本體510可為諸如矽基板的半導體基板。半導體內部電路區域535可包含半導體內部電路515及電連接半導體內部電路515與半導體下部電極接墊555A的半導體內部佈線540。半導體內部電路515及半導體內部佈線540可安置於半導體內部絕緣層545中。
在多個半導體晶片500中，下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C中的每一者可更包含半導體本體510上的半導體上部絕緣層590、半導體上部電極接墊595A以及半導體上部虛設接墊595D。在多個半導體晶片500中，下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C中的每一者可更包含半導體本體510與半導體上部絕緣層590之間的半導體保護絕緣層570。
由於半導體上部電極接墊595A及半導體上部虛設接墊595D的配置與上述實例實施例相同，因此將省略其詳細描述。另外，半導體下部電極接墊555A及半導體下部虛設接墊555D的配置與上述實例實施例相同，將省略其詳細描述。
下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C中的每一者可更包含穿透半導體本體510及電連接半導體下部電極接墊555A與半導體上部電極接墊595A的半導體貫穿電極結構520。貫穿電極結構520可包含由諸如銅的導電材料形成的貫穿電極530，以及包圍貫穿電極530的側面的絕緣隔片525。
在半導體晶片500中，相對位於下方的半導體晶片的半導體上部絕緣層590與相對位於上方的半導體晶片的半導體下部絕緣層550可在彼此接觸的同時耦接，且相對位於下方的半導體上部電極接墊595A與相對位於上方的半導體晶片的半導體下部電極接墊555A可在彼此接觸的同時耦接。因此，可依序堆疊半導體晶片500以使得半導體上部絕緣層590與半導體下部絕緣層550在彼此接觸的同時耦接，且半導體上部電極接墊595A與半導體下部電極接墊555A在彼此接觸的同時耦接。
下部半導體晶片500A、下部半導體晶片500B以及下部半導體晶片500C當中的最下部半導體晶片500A可在與下部結構100接觸的同時耦接。舉例而言，最下部半導體晶片500A的半導體下部絕緣層550可在與下部結構100的上部絕緣層190接觸的同時耦接，最下部半導體晶片500A的半導體下部電極接墊555A可在與下部結構100的上部電極接墊195A接觸的同時耦接，且最下部半導體晶片500A的半導體下部虛設接墊555D可在與下部結構100的上部虛設接墊195D接觸的同時耦接。
由於根據本發明概念的實例實施例的半導體封裝包含上述下部結構以及半導體晶片100及半導體晶片200，因此可改良接合製程中的可靠性。
當其上安置有具有精細間距的電極接墊的半導體晶片接合至諸如焊球或凸塊的連接結構時，可發生電極接墊由於連接結構而短路的擠出現象。因此，在其上安置有具有精細間距的電極接墊的半導體晶片中，在無額外連接結構的情況下使用表面處理及直接接合電極接墊及絕緣層的表面的方法。在此情況下，當待接合的表面上存在階差時，半導體晶片的黏合力可減小或在接合表面上可出現空隙，從而導致不良接合。為了減小（或替代地防止）此接合失敗，可執行化學機械研磨（chemical mechanical polishing；CMP）製程作為平坦化製程以減小待接合的半導體晶片的接合表面之間的階差。然而，當時對接合表面執行CMP製程時，可以比由氧化矽形成的絕緣層更高的移除速率移除由導電材料形成的電極接墊。因此，可出現腐蝕現象，其中相對較大數目的電極接墊安置於接合表面上的區域為凹面的，且其中電極接墊相對較小的區域為凸面的，從而導致接合表面上的階差。
相反，在一或多個實例實施例中，為了減輕在CMP製程期間在接合表面上出現階差，虛設接墊可安置於未安置電極接墊的第二區域A2中，且可調整虛設接墊的大小及距離以使得虛設接墊與絕緣層的每單位面積的表面積的比隨著距第一區域A1的距離增大而逐漸減小，因此可減輕在CMP製程期間由於取決於面積的移除速率的差異而導致的腐蝕現象的出現。因此，相較於未安置虛設接墊的情況，在CMP製程期間發生的階差的大小可降低至例如59.8%。
接著，將參考圖11及圖16描述根據本揭露的實例實施例的形成半導體封裝的方法的實例實施例。圖11為說明根據本揭露的實例實施例的形成半導體封裝的方法的實例的製程流程圖，且圖12至圖16為說明根據本揭露的實例實施例的形成半導體封裝的方法的實例的橫截面圖。
參考圖11及圖12，在操作S10中，電極接墊255A及虛設接墊255D可形成於具有以晶片區域CA為單位的晶片區域CA的半導體晶圓WA上。舉例而言，電極接墊255A可形成於作為晶片區域CA的中心區域的第一區域A1中，且虛設接墊255D可形成於作為晶片區域CA的圓周區域的第二區域A2中。半導體晶圓WA可在藉由載體基板1000上的黏著層1010附接至載體基板1000的同時提供。
參考圖11及圖13，在操作S20中，覆蓋下部電極接墊255A及下部虛設接墊255D的下部絕緣層250可形成於半導體晶圓WA上。
參考圖11及圖14，在操作S30中，可平坦化下部絕緣層250的表面以使得下部電極接墊255A及下部虛設接墊255D暴露。可使用CMP製程來執行平坦化。下部虛設接墊255D可安置於下部電極接墊255A周圍，且在CMP製程中，可減輕安置有下部電極接墊255A的區域與未安置下部電極接墊255A的區域（例如，切割道）之間的移除速率的差異。因此，可抑制（或替代地，防止）其中未安置有下部電極接墊255A的區域可為凸面的腐蝕現象的出現。
參考圖11及圖15，覆蓋下部絕緣層250、下部電極接墊250A以及下部虛設接墊255D的保護層1100可形成於半導體晶圓WA上。保護層1100可在藉由切割半導體晶圓WA形成半導體晶片的製程中保護下部絕緣層250、下部電極接墊250A以及下部虛設接墊255D。
參考圖11、圖16以及圖17，在操作S40中，可藉由在半導體晶圓WA的晶片區域CA之間切割而形成半導體晶片200。可使用鋸切裝置1300切割半導體晶圓WA。可移除留存於半導體晶片200上的保護層1100。
在操作S50中，半導體晶片200可與載體基板1000的黏著層1010分離，且分離的半導體晶片200可接合至基底晶圓WB。
基底晶圓WB可包含上部絕緣層190及上部接墊195。半導體晶片200的下部絕緣層250可在與上部絕緣層190接觸的同時耦接，且半導體晶片200的下部電極接墊255與下部虛設接墊255D可在與上部電極接墊195A及上部虛設接墊195D接觸的同時耦接。
將半導體晶片200接合至基底晶圓WB可將半導體晶片200置放於基底晶圓WB上，且可在高於室溫的熱大氣（例如，約200℃至約300℃的熱大氣）下，藉由將壓力施加至半導體晶片200，在將基底晶圓WB的上部接墊195及上部虛設接墊195D接合及耦接至半導體晶片200的下部電極接墊255A及下部虛設接墊255D的同時將基底晶圓WB的上部絕緣層190接合及耦接至半導體晶片200的下部絕緣層250。此處，熱大氣的溫度可在受限於約200℃至約300℃的同時不同地改變。上部接墊195、上部虛設接墊195D、下部電極接墊255A以及下部虛設接墊255D可經由金屬擴散彼此接合，且半導體晶片200的上部絕緣層190及下部絕緣層250可經由共價接合彼此接合。
參考圖1及圖11，在操作S60中，可在半導體晶片200之間切割基底晶圓WB。在切割基底晶圓WB之前，方法可更包含形成覆蓋半導體晶片200的模製層310。因此，亦可在切割基底晶圓WB的同時切割模製層310。
在操作S70中，經切割基底晶圓WB的部分可安裝於下部結構100上。因此，可形成如圖1中所描述的半導體封裝1A。
根據本發明概念的實例實施例，下部結構100可視為位置相對較低的下部晶片，且半導體晶片200可視為位置相對較高的上部晶片。可提供包含在彼此直接接觸的同時耦接的接墊195A、接墊195D與接墊255A、接墊255D以及由在彼此直接接觸的同時耦接的絕緣層190及絕緣層250耦接的下部晶片100與上部晶片200的半導體封裝。
根據本發明概念的實例實施例，有可能提供包含在彼此直接接觸的同時耦接的接墊及在彼此直接接觸的同時耦接的絕緣層的半導體封裝。因此，接墊及絕緣層可耦接晶片。此類接墊及絕緣層可耦接晶片或晶片與中介層，由此減小半導體封裝的厚度。
根據本發明概念的實例實施例，待直接耦接的晶片可包含其中虛設接墊圍繞其中配置有電極接墊的區域配置的區域。其中配置有虛設接墊的區域可藉由在堆疊半導體晶片之前在平坦化半導體晶片的表面的製程中減小半導體晶片的表面上的階差來提高其中堆疊有半導體晶片的半導體封裝的可靠性。
本揭露的各種及有益優勢及效應不限於上述描述，且在描述本揭露的特定實例實施例期間可更易於理解。
本揭露不限於上文描述的實施例及附圖，但意欲受限於隨附申請專利範圍。因此，所屬技術領域中具有通常知識者將可能在不脫離申請專利範圍中所描述的本發明概念的情況下進行各種類型的替代、修改以及改變，且所述各種類型的替代、修改以及改變屬於本揭露的範疇。
1A、1B:半導體封裝 10:基底 50:連接結構 100、100A:下部結構 110:下部本體 110B、201B:後表面 101F、110F、201F、210F、3201F:前表面 115:下部內部電路 120、520:貫穿電極結構 125、525:絕緣隔片 130、530:貫穿電極 135:下部內部電路區域 140:下部內部佈線 145:下部內部絕緣層 165:下部保護絕緣層 170A:下部連接接墊 190、590:上部絕緣層 195A、595A:上部電極接墊 195D、195D-1、195D-2、195D-3、595D:上部虛設接墊 200、500、1200、2200、3200:半導體晶片 201S、501S、1201S、2201S、3201S:側面 210、510:半導體本體 215、515:半導體內部電路 235、535:半導體內部電路區域 240、540:半導體內部佈線 245、545:半導體內部絕緣層 250、550、1250、2250、3250:半導體下部絕緣層 255A、555A、1255A、2255A、3255A-1、3255A-2:半導體下部電極接墊 255D、255D-1、255D-2、255D-3、555D、1255D、2255D、3255D、3255D-1、3255D-2、3255D-3、3255D-4、3255D-5:半導體下部虛設接墊 310、610:模製層 500A、500B、500C:下部半導體晶片 500D:上部半導體晶片 570:半導體保護絕緣層 1000:載體基板 1010:黏著層 1100:保護層 1300:鋸切裝置 ‘A’、'B'、'C'、'D':部分 A1、A3、A4:第一區域 A2、A5:第二區域 A5A:第一部分 A5B:第二部分 CA:晶片區域 D1、D2、D3、D4、D5、D6、D7、D8:大小 H:恆定密度值 P1、P2、P3、P4、P5、P6、P7、P8:間距 S10、S20、S30、S40、S50、S60、S70:操作 WA:半導體晶圓 WB:基底晶圓
自結合附圖進行的以下詳細描述，將更清楚地理解本發明概念的上述及其他態樣、特徵以及優勢，其中： 圖1為說明根據本揭露的實例實施例的半導體封裝的側橫截面圖。 圖2為圖1的部分’A’的放大圖。 圖3為說明安置於圖1的上部部分上的半導體晶片的接合表面的平面圖。 圖4A為圖3的部分’B’的放大圖。 圖4B為說明圖4A的接墊密度的曲線圖。 圖5及圖6為圖4A的修改實例。 圖7為說明圖3中所說明的半導體晶片的修改實例的平面圖。 圖8為圖7的部分’C’的放大圖。 圖9為說明根據本揭露的實例實施例的半導體封裝的側橫截面圖。 圖10為圖9的部分’D’的放大圖。 圖11為說明根據本揭露的實例實施例的形成半導體封裝的方法的實例實施例的製程流程圖。 圖12至圖17為說明根據本揭露的實例實施例的形成半導體封裝的方法的實例實施例的橫截面圖。
1A:半導體封裝
10:基底
50:連接結構
100:下部結構
190:上部絕緣層
195A:上部電極接墊
195D:上部虛設接墊
200:半導體晶片
250:半導體下部絕緣層
255A:半導體下部電極接墊
255D:半導體下部虛設接墊
310:模製層
A1:第一區域
A2:第二區域
‘A’:部分

Claims (20)

  1. 一種半導體封裝，包括： 第一結構，包含第一絕緣層、第一電極接墊以及第一虛設接墊，所述第一虛設接墊在所述第一絕緣層的表面上圍繞所述第一電極接墊，其中所述第一電極接墊及所述第一虛設接墊穿透所述第一絕緣層，所述第一電極接墊具有20微米或小於20微米的間距，且所述第一絕緣層的所述表面上的所述第一虛設接墊與所述第一絕緣層的每單位面積的表面積的比朝向所述第一結構的側面逐漸減小；以及 第二結構，包含第二絕緣層、第二電極接墊以及第二虛設接墊，所述第二絕緣層接合至所述第一絕緣層，其中所述第二虛設接墊在接合至所述第一絕緣層的所述表面的所述第二絕緣層的表面上圍繞所述第二電極接墊，其中所述第二電極接墊及所述第二虛設接墊穿透所述第二絕緣層以使得所述第二電極接墊分別接合至所述第一電極接墊，且所述第二虛設接墊分別接合至所述第一虛設接墊，且所述第二絕緣層的所述表面上的所述第二虛設接墊與所述第二絕緣層的每單位面積的表面積的比朝向所述第二結構的側面逐漸減小。
  2. 如請求項1所述的半導體封裝，其中所述第一虛設接墊的大小與所述第二虛設接墊的大小相對應。
  3. 如請求項2所述的半導體封裝，其中所述第一虛設接墊的所述大小及所述第二虛設接墊的所述大小為0.06微米至0.1微米，且所述第一虛設接墊與所述第二虛設接墊兩者的間距均為0.3微米至0.5微米。
  4. 如請求項1所述的半導體封裝，其中所述第一虛設接墊各自具有相同第一間距，且所述第一虛設接墊的大小朝向所述第一結構的所述側面逐漸減小。
  5. 如請求項1所述的半導體封裝，其中所述第一虛設接墊具有相同大小，而所述第一虛設接墊的間距朝向所述第一結構的所述側面逐漸增大。
  6. 如請求項1所述的半導體封裝，其中所述第一虛設接墊中的每一者的大小小於所述第一電極接墊的大小。
  7. 如請求項1所述的半導體封裝，其中 所述第一電極接墊及所述第一虛設接墊具有相同大小，且 所述第一電極接墊中的每一者的所述間距相同，而所述第一虛設接墊的間距大於所述第一電極接墊中的每一者的所述間距。
  8. 如請求項1所述的半導體封裝，其中所述第二結構具有比所述第一結構更大的寬度。
  9. 如請求項1所述的半導體封裝，其中所述第一虛設接墊與所述第一絕緣層的每單位面積的所述表面積的所述比朝向所述第一結構的所述側面逐步減小。
  10. 一種半導體封裝，包括： 下部結構，包含在其第一區域及第二區域中的上部絕緣層，其中所述第二區域包圍所述第一區域，所述第一區域包含穿透所述上部絕緣層的上部電極接墊，所述第二區域包含穿透所述上部絕緣層的上部虛設接墊，其中所述第二區域中的所述上部虛設接墊與所述上部絕緣層的每單位面積的表面積的比朝向所述下部結構的側面減小；以及 半導體晶片，包含下部絕緣層、下部電極接墊以及下部虛設接墊，所述下部絕緣層與所述上部絕緣層接觸且耦接至所述上部絕緣層，其中所述下部電極接墊及所述下部虛設接墊穿透所述下部絕緣層以使得所述下部電極接墊及所述下部虛設接墊分別與所述上部電極接墊及所述上部虛設接墊接觸且耦接至所述上部電極接墊及所述上部虛設接墊。
  11. 如請求項10所述的半導體封裝，其中所述下部結構具有比所述半導體晶片更大的寬度。
  12. 如請求項10所述的半導體封裝，其中 所述半導體晶片包含半導體本體及在所述半導體本體下方的半導體內部電路區域，且 所述下部絕緣層、所述下部電極接墊以及所述下部虛設接墊在所述半導體內部電路區域下方。
  13. 如請求項10所述的半導體封裝，其中 所述下部結構包含下部本體及在所述下部本體上的下部內部電路區域，且 所述上部絕緣層、所述上部電極接墊以及所述上部虛設接墊在所述下部內部電路區域上。
  14. 如請求項10所述的半導體封裝，其中所述下部結構更包含下部本體及穿透所述下部本體且電連接至所述上部電極接墊的貫穿電極。
  15. 如請求項14所述的半導體封裝，其中所述下部本體為矽基板。
  16. 如請求項10所述的半導體封裝，更包括： 模製層，在所述下部結構上且覆蓋所述半導體晶片的側面。
  17. 如請求項10所述的半導體封裝，其中所述下部結構為中介層。
  18. 如請求項10所述的半導體封裝，其中所述半導體晶片為第一半導體晶片，且所述下部結構為與所述第一半導體晶片不同的第二半導體晶片。
  19. 一種半導體封裝，包括： 下部結構；以及 多個半導體晶片，在所述下部結構上，所述多個半導體晶片包含： 第一半導體晶片，具有前表面及後表面，其中上部絕緣層、上部電極接墊以及上部虛設接墊在其所述後表面上，其中所述第一半導體晶片的所述後表面上的所述上部虛設接墊與所述上部絕緣層的每單位面積的表面積的比朝向所述第一半導體晶片的側面逐漸減小，以及 第二半導體晶片，與第一半導體晶片直接接觸，所述第二半導體晶片具有前表面及後表面，其中下部絕緣層、下部電極接墊以及下部虛設接墊在其所述前表面上以使得所述下部絕緣層與所述上部絕緣層彼此接觸及耦接，所述下部電極接墊與所述上部電極接墊彼此接觸及耦接，且所述下部虛設接墊與所述上部虛設接墊彼此接觸及耦接，其中所述第二半導體晶片的所述前表面上的所述下部虛設接墊與所述下部絕緣層的每單位面積的表面積的比朝向所述第二半導體晶片的側面逐漸減小。
  20. 如請求項19所述的半導體封裝，其中所述第一半導體晶片及所述第二半導體晶片具有相同寬度。
TW110117011A 2020-09-08 2021-05-12 半導體封裝 TW202211328A (zh)

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