TW202211198A - Display apparatus and display circuit - Google Patents

Abstract

A display apparatus includes a display panel, a gate driver, and a timing controller. The display panel includes an update region. The gate driver is coupled to the display panel via plural gate lines extending along a row direction. The timing controller is coupled to the gate driver. The timing controller includes a partial update circuit. The partial update circuit is configured to: select plural update gate lines corresponding to the update region from the gate lines; and choose a power normal mode or a power saving mode to supply power according to the number of pixels of the update region along the row direction and the number of the update gate lines when driving the update gate lines.

Description

Display device and display circuit

The present invention relates to a display device and a display circuit, and in particular, to a picture updating method of the display device.

Partial update function is often used in electronic shelf labels (Electronic Shelf Label, ESL), electronic paper displays (Electronic Paper Displays, EPD), electronic ink displays (E Ink Display), mobile devices, TVs, monitors and other display ICs The purpose of the application is to turn on only part of the gate lines if only the residential area of the display screen changes, so as to reduce the power consumption by using the driving method of locally updating the screen.

An object of the present disclosure is to provide a display device including a display panel, a gate driver, a timing controller and a power module. The display panel contains the updated update area. The gate driver is coupled to the display panel through a plurality of gate lines, wherein the plurality of gate lines extend along the column direction of the display panel. The timing controller is coupled to the gate driver, and the timing controller includes part of the update circuit. The power module is coupled to the timing controller and the gate driver to supply power to the timing controller and the gate driver. The partial update circuit of the timing controller is used for: selecting a plurality of update gate lines corresponding to the update area of the display panel from a plurality of gate lines; and when driving a plurality of update gate lines, according to the update area in the column direction The number of pixels and the total number of multiple update gate lines are used to control the power module to supply power in a normal power supply mode or a power saving mode.

In some embodiments, part of the update circuit of the timing controller is further used to: select a plurality of non-update gate lines other than the update gate lines from the plurality of gate lines; and drive a plurality of non-update gate lines When connected, control the power module to supply power in a power-saving mode.

In some embodiments, the number of pixels and the total number of bars are provided to the partial update circuit by a timing controller.

In some embodiments, when the plurality of update gate lines are driven, when the number of pixels is less than the threshold of the number of pixels and when the total number of the plurality of update gate lines is greater than the threshold of the number of update gate lines, the partial update circuit controls the power module Power is supplied in power saving mode.

In some embodiments, when driving a plurality of update gate lines, when the number of pixels is not less than the pixel number threshold or when the total number of the plurality of update gate lines is not greater than the number threshold, the partial update circuit controls the power supply The module is powered in the normal power supply mode.

In some embodiments, the threshold value of the number of pixels and the threshold value of the number of bars are provided to the partial update circuit by the timing controller.

The purpose of the present disclosure is to further provide a display circuit including a gate driver, a timing controller and a power module. The gate driver is coupled to the display panel through a plurality of gate lines, wherein the plurality of gate lines extend along the column direction of the display panel. The timing controller is coupled to the gate driver, and the timing controller includes part of the update circuit. The power module is coupled to the timing controller and the gate driver to supply power to the timing controller and the gate driver. The partial update circuit of the timing controller is used for: selecting a plurality of update gate lines corresponding to an updated update area of the display panel from a plurality of gate lines; and when driving a plurality of update gate lines, according to the update area The number of pixels in the column direction and the total number of multiple update gate lines control the power module to supply power in a normal power supply mode or a power saving mode.

In some embodiments, part of the update circuit of the timing controller is further used to: select a plurality of non-update gate lines other than the update gate lines from the plurality of gate lines; and drive a plurality of non-update gate lines When connected, control the power module to supply power in a power-saving mode.

In some embodiments, the number of pixels and the total number of bars are provided to the partial update circuit by a timing controller.

In some embodiments, when the plurality of update gate lines are driven, when the number of pixels is less than the threshold of the number of pixels and when the total number of the plurality of update gate lines is greater than the threshold of the number of update gate lines, the partial update circuit controls the power module Power is supplied in power saving mode.

In some embodiments, when driving a plurality of update gate lines, when the number of pixels is not less than the pixel number threshold or when the total number of the plurality of update gate lines is not greater than the number threshold, the partial update circuit controls the power supply The module is powered in the normal power supply mode.

In some embodiments, the threshold value of the number of pixels and the threshold value of the number of bars are provided to the partial update circuit by the timing controller.

In order to make the above-mentioned features and advantages of the present disclosure more obvious and easy to understand, the following embodiments are given and described in detail in conjunction with the accompanying drawings as follows.

Embodiments of the present invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustration only, and are not intended to limit the scope of the present invention.

FIG. 1 is a block diagram of a display device 100 according to an embodiment of the present disclosure. The display device 100 includes a display panel 110 and a display circuit 101 . The display circuit 101 includes a source driver 120 , a gate driver 130 , a timing controller 140 and a power module 150 . The power module 150 is coupled to the source driver 120 , the gate driver 130 and the timing controller 140 , and the power module 150 is used to supply power to the source driver 120 , the gate driver 130 and the timing controller 140 respectively, so as to enable the display device 100 can function normally.

In the embodiment of the present disclosure, the display device 100 can be an electronic shelf label (Electronic Shelf Label, ESL), an electronic paper display (Electronic Paper Displays, EPD), an electronic ink display (E Ink Display), a mobile device, a television, a display and other display devices.

The source driver 120 is coupled to the display panel 110 through a plurality of source lines SL1 , SL2 , . . . , SLm, each of which extends along the row direction of the display panel 110 . . The gate driver 130 is coupled to the display panel through a plurality of gate lines GL1, GL2, . . . , GLn, wherein the gate lines GL1, GL2, . . . , GLn extend along the column direction of the display panel.

The timing controller 140 is coupled to the source driver 120 and the gate driver 130 . The timing controller 140 controls the source driver 120 and the gate driver 130 to drive a plurality of pixels on the display panel 110 . Specifically, the display panel 110 includes a plurality of pixels (not shown) arranged in m rows and n columns in a matrix shape, and each pixel is correspondingly connected to a source line and a gate line. When a picture is to be displayed on the display panel 110, the timing controller 140 controls the source driver 120 and the gate driver 130, so that the source driver 120 provides the data signal corresponding to the picture to the corresponding pixel through the source line, And the gate driver 130 sequentially provides pulse signals to the corresponding pixels through the gate lines, so that the thin film transistors of the corresponding pixels are electrically turned on.

The present disclosure is directed to how to better adjust the power supply of the power module 150 when only a partial block of the display screen on the display panel 110 is changed, so as to achieve a more power saving effect. The display panel 110 includes the updated update area PU. In other words, among the displayed pictures on the display panel 110, only the pictures in the update area PU will be changed, and the pictures other than the update area PU will not be changed.

The timing controller 140 includes a partial update circuit 142 , and the partial update circuit 142 is used to control the image update method of the display panel 110 of the display device 100 , so as to better adjust the power supply of the power module 150 to achieve a more power saving effect. FIG. 2 is a flowchart of a method 1000 for updating a screen of the display device 100 according to an embodiment of the present disclosure. The screen update method 1000 includes steps 1100-1600.

In step 1100, the size information of the update area PU is pre-stored in the timing controller 140, and the timing controller 140 provides the size information for the partial update circuit 142 to perform subsequent determination. FIG. 3 is a schematic diagram of the size information of the update area PU of the display panel 110 according to an embodiment of the present disclosure. In FIG. 3 , the width of the update area PU, that is, the number of pixels covered by the update area PU in the column direction of the display panel 110 is represented by x'. For example, the number of pixels in the column direction of the display panel 110 is 160, and the number of pixels covered by the update area PU in the column direction of the display panel 110 is 40, then x' is 40, and the above values are only examples description, and the present invention is not limited thereto. In FIG. 3 , the height of the update area PU, that is, the total number of gate lines corresponding to the update area PU in the row direction of the display panel 110 is represented by y'. In the embodiment of the present disclosure, the partial update circuit 142 of the timing controller 140 selects a plurality of gate lines corresponding to the update region PU in the row direction of the display panel 110 from the plurality of gate lines GL1 ˜GLn (herein These gate lines are referred to as "update gate lines" in this paper), and a plurality of gate lines other than the update gate lines are selected from the plurality of gate lines GL1~GLn (in this paper, these gate lines are referred to as line is called the "non-refresh gate line"). For example, if n is 320, that is, there are 320 gate lines in total, and the update gate lines corresponding to the update area PU in the row direction of the display panel 110 are GL41-GL80, then y' is 40, and many The non-updated gate lines are GL1 ˜ GL40 and GL81 ˜ GL320 . The above-mentioned values are only examples, and the present invention is not limited thereto. The numerical information of x' and y' is stored in the timing controller 140 in advance, so that the timing controller 140 can provide the numerical information for the partial update circuit 142 to perform subsequent judgment.

In step 1200, the timing controller 140 provides a pixel number threshold M and a bar number threshold N, the pixel number threshold M and the bar number threshold N are preset thresholds, and can be set as suitable value. In the embodiment of the present disclosure, a register of the timing controller 140 can provide the pixel number threshold M and the bar number threshold N for the partial update circuit 142 to perform subsequent determination.

In step 1300, the partial update circuit 142 determines whether the gate line currently providing the pulse signal to the corresponding pixel is the update gate line or the non-update gate line, that is, the partial update circuit 142 determines whether the current drive update gate is pole line, if yes, it means that the gate line that currently provides the pulse signal to the corresponding pixel is the updated gate line, and then goes to step 1400; if no, it means that the gate line that currently provides the pulse signal to the corresponding pixel is the gate line If the pole line is a non-updated gate line, step 1600 is entered.

In step 1400, the partial update circuit 142 determines whether the number of pixels x' covered by the update area PU in the column direction of the display panel 110 is less than the pixel number threshold M and whether the total number of update gate lines y' is greater than the number threshold. value N. If the number of pixels x' is less than the threshold M of the number of pixels and the total number y' of the updated gate lines is greater than the threshold N of the number of lines, then go to step 1600. If the pixel number x' is not less than the pixel number threshold M or the total number y' of the updated gate lines is not greater than the number threshold N, then go to step 1500.

In step 1500, the partial update circuit 142 transmits a control signal to the power module 150 to control the power module 150 to supply power in a power normal status. Specifically, in step 1500, the power supply of the power supply module 150 will not be adjusted, that is, the power supply module 150 is maintained in the normal power supply mode to supply power. In other words, in step 1500, part of the update circuit 142 may not transmit the control signal to the power module 150, so that the power module 150 maintains the normal power supply mode for power supply.

In step 1600, the partial update circuit 142 transmits a control signal to the power module 150 to control the power module 150 to supply power in a power saving status. For example, if the determination result in step 1300 is NO, it means that the gate line that currently provides the pulse signal to the corresponding pixel is a non-update gate line, that is, the corresponding pixel currently receiving the pulse signal is the picture The pixels that will not be changed, therefore, go to step 1600, and the partial update circuit 142 controls the power module 150 to supply power in a power saving mode to save the power consumption of the source driver 120, so as to achieve a more power saving effect. For example, if the determination result in step 1400 is yes, it means that the picture to be updated in the update area PU only needs a relatively low driving capacity. Therefore, in step 1600, the partial update circuit 142 controls the power module 150 to The power saving mode is used to supply power to save the power consumption of the source driver 120 to achieve a more power saving effect.

In the embodiment of the present disclosure, the power saving mode of the power module 150 in step 1600 may be, for example, (1) reducing the pulse frequency modulation (PFM) on the flexible printed circuit board connected to the timing controller 140 )/the drive capability of the output current of the drive signal (DRV) of the pulse width modulation (PWM) boost element circuit to adjust the supply capability of the source power supply (on/off voltage (VGH/VGL) of the gate driver 130 ), Or, (2) lengthen the minimum charge off time of the PFM/PWM boost element circuit to adjust the supply capability of the source power supply (VGH/VGL), or, (3) reduce the operational amplifier of the source driver 120 ( The bias current of OP), etc., or, alternatively, can be a matching combination of the above-mentioned methods. It should be noted that the above-mentioned implementation of the power saving mode of the power module 150 is only an example, and the present disclosure does not limit the implementation of the power saving mode of the power module 150, as long as the power supply of the power module 150 can be adjusted to Any power supply technical means to achieve a more power saving effect can be used as an implementation manner of the power saving mode of the power module 150 .

In addition, the display panel 110 shown in FIG. 3 includes only one update area PU is only an example, and the screen update method 1000 of the display device 100 proposed in the present disclosure can also be applied to applications where the display panel 110 includes multiple update areas.

In view of the above, the present disclosure provides a display device and a display circuit. When only a partial block of a display image on a display panel is changed, the power supply of a power supply module is better adjusted through a partial update circuit of a timing controller, so as to achieve a higher level of performance. Power saving effect.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures, thereby achieving the same objectives and/or achieving the same advantages as the embodiments described herein . Those skilled in the art should also understand that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

100: Display device 101: Display circuit 110: Display panel 120: source driver 130: Gate driver 140: Timing Controller 142: Partial update circuit 150: Power Module 1000: Screen update method 1100~1600: Steps GL1, GL2, GL41, GL80, GL320, GLn: gate line PU: update area SL1, SL2, SLm: source line x': number of pixels y': total number of bars

A better understanding of aspects of the present disclosure can be obtained from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased in order to clarify the discussion. 1 is a block diagram of a display device according to an embodiment of the present disclosure. 2 is a flowchart of a method for updating a screen of a display device according to an embodiment of the present disclosure. 3 is a schematic diagram of the size information of the update area of the display panel according to an embodiment of the present disclosure.

100: Display device

101: Display circuit

110: Display panel

120: source driver

130: Gate driver

140: Timing Controller

142: Partial update circuit

150: Power Module

GL1, GL2, GLn: gate line

PU: update area

SL1, SL2, SLm: source line

Claims (12)

A display device, comprising: a display panel containing an update area being updated; a gate driver coupled to the display panel through a plurality of gate lines, wherein the gate lines extend along a column direction of the display panel; a timing controller coupled to the gate driver, wherein the timing controller includes a portion of the update circuit; and a power module coupled to the timing controller and the gate driver to supply power to the timing controller and the gate driver; The part of the update circuit of the timing controller is used for: selecting a plurality of update gate lines corresponding to the update region of the display panel from the gate lines; and When driving the update gate lines, the power module is controlled to be in a normal power supply mode or a power saving mode according to a number of pixels in the update region in the column direction and a total number of the update gate lines to supply power. The display device of claim 1, wherein the part of the update circuit of the timing controller is further used to: selecting from the gate lines a plurality of non-refresh gate lines other than the refresh gate lines; and When driving the non-updated gate lines, the power module is controlled to supply power in the power saving mode. The display device of claim 1, wherein the number of pixels and the total number of bars are provided to the partial update circuit by the timing controller. The display device of claim 1, wherein when the update gate lines are driven, when the number of pixels is less than a pixel number threshold and when the total number of the update gate lines is greater than a threshold , the part of the update circuit controls the power module to supply power in the power saving mode. The display device of claim 4, wherein when the update gate lines are driven, when the number of pixels is not less than the pixel number threshold or when the total number of the update gate lines is not greater than the number When the threshold value is reached, the partial update circuit controls the power module to supply power in the normal power supply mode. The display device of claim 4, wherein the pixel number threshold and the bar number threshold are provided to the partial update circuit by the timing controller. A display circuit, comprising: a gate driver coupled to a display panel through a plurality of gate lines, wherein the gate lines extend along a column direction of the display panel; a timing controller coupled to the gate driver, wherein the timing controller includes a portion of the update circuit; and a power module coupled to the timing controller and the gate driver to supply power to the timing controller and the gate driver; The part of the update circuit of the timing controller is used for: selecting from the gate lines a plurality of update gate lines corresponding to an update region of the display panel being updated; and When driving the update gate lines, the power module is controlled to be in a normal power supply mode or a power saving mode according to a number of pixels in the update region in the column direction and a total number of the update gate lines to supply power. The display circuit of claim 7, wherein the part of the update circuit of the timing controller is further used to: selecting from the gate lines a plurality of non-refresh gate lines other than the refresh gate lines; and When driving the non-updated gate lines, the power module is controlled to supply power in the power saving mode. The display circuit of claim 7, wherein the number of pixels and the total number of bars are provided to the partial update circuit by the timing controller. The display circuit of claim 7, wherein when the update gate lines are driven, when the number of pixels is less than a pixel number threshold and when the total number of the update gate lines is greater than a threshold , the part of the update circuit controls the power module to supply power in the power saving mode. The display circuit of claim 10, wherein when the update gate lines are driven, when the number of pixels is not less than the pixel number threshold or when the total number of the update gate lines is not greater than the number When the threshold value is reached, the partial update circuit controls the power module to supply power in the normal power supply mode. The display circuit of claim 10, wherein the pixel number threshold and the bar number threshold are provided to the partial update circuit by the timing controller.

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