TW202203372A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202203372A
TW202203372A TW110123550A TW110123550A TW202203372A TW 202203372 A TW202203372 A TW 202203372A TW 110123550 A TW110123550 A TW 110123550A TW 110123550 A TW110123550 A TW 110123550A TW 202203372 A TW202203372 A TW 202203372A
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Taiwan
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source
drain
dielectric
features
layer
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TW110123550A
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林大鈞
葉冠麟
林俊仁
潘國華
江木吉
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台灣積體電路製造股份有限公司
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Publication of TW202203372A publication Critical patent/TW202203372A/zh

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Abstract

一種半導體裝置，包括第一主動區及第二主動區，佈設於基板之上。第一源極/汲極部件成長於第一主動區之上。第二源極/汲極部件成長於第二主動區之上。層間電介質(ILD)佈設於第一源極/汲極部件及第二源極/汲極部件周圍。隔離結構垂直延伸穿越ILD。隔離結構分離第一源極/汲極部件及第二源極/汲極部件。

Description

半導體裝置
總體而言，本揭露係關於半導體裝置；特定而言，係關於半導體裝置的隔離結構，用以防止源極/汲極部件之間非因故意的相互融合。
半導體積體電路(IC)產業經歷了指數性的成長。IC材料及設計的技術進展，造就了多個IC世代，其中每一世代具有比前一世代更小且更複雜的電路。在IC的發展進程中，功能密度(亦即每一晶片區域中相互連接的裝置數量)總體而言呈現成長，而幾何大小(亦即使用一種製造製程可造出的最小部件(或線))則縮小。總體而言，此一縮小(scaling down)進程藉由增加生產效率及降低相關成本，提供了許多優點。此一縮小進程亦增加了處理及製造IC的複雜度。
例如，隨著半導體裝置持續縮小，相鄰電晶體之間的間隔逐漸縮小。此種小間隔可能導致相鄰電晶體之間的磊晶(epitaxial)源極/汲極特徵相互融合，導致相鄰電晶體之間的短路現象。短路情形為吾人欲避免的，因其可能降低裝置效能，或甚至導致裝置故障。
因此，儘管習知的半導體裝置製造方法總體而言尚稱適當，然而該等方法並非在所有面向上皆令人滿意。
本揭露之一態樣係關於一種半導體裝置。此裝置包括第一主動區及第二主動區，佈設於基板之上。第一源極/汲極部件成長於第一主動區之上。第二源極/汲極部件成長於第二主動區之上。層間電介質(ILD)佈設於第一源極/汲極部件及第二源極/汲極部件周圍。隔離結構垂直延伸穿越ILD，並分離第一源極/汲極部件及第二源極/汲極部件。
本揭露之另一態樣係關於一種半導體裝置。此裝置包括多個主動區，佈設於基板之上；多個閘極結構，佈設於主動區之上；以及多個源極/汲極，分別磊晶成長於各主動區之上。各源極/汲極中，至少有一第一源極/汲極在剖面圖中具有非對稱式側面形狀。
本揭露之又一態樣係關於一種半導體裝置之製造方法。此方法包括在基板上形成第一主動區及第二主動區；分別在第一主動區及第二主動區之上磊晶成長第一源極/汲極部件及第二源極/汲極部件；在第一源極/汲極部件及第二源極/汲極部件之上形成材料層；蝕刻穿越材料層的開口，此開口分離第一源極/汲極部件及第二源極/汲極部件；以及以一種或多種介電材料填充開口。
下文之揭露提供多種不同實施例或範例，用於實施本揭露的不同特徵。下文將敘述部件及佈局的特定範例，以簡化本揭露。當然，該等特定部件及佈局僅為範例，而非意圖限制。例如，下文中「一第一特徵形成於一第二特徵之上」的敘述，可包括該第一及第二特徵形成直接接觸的實施例，亦可包括該第一及第二特徵之間尚有額外特徵形成，使該第一及第二特徵並不直接接觸的實施例。此外，本揭露可能在各範例中重複參考編號及/或字母。此一重複是為了敘述簡潔及清晰起見，而其自身並不決定所述各實施例及/或配置之間的關係。
此外，本揭露之下文中，一特徵「位於另一特徵之上」、「連接至」另一特徵、或「耦接至」另一特徵等敘述，可包括該等特徵形成直接接觸的實施例，亦可包括尚有額外特徵插入該等特徵之間形成，使該等特徵並不直接接觸的實施例。此外，空間相關詞彙，例如「低於」、「高於」、「水平」、「垂直」、「在...之上」、「在...之下」、「上方」、「下方」、「頂部」、「底部」等，以及該等詞彙之衍生詞彙(例如「水平地」、「向下地」、「向上地」等)，在本揭露中是為了方便表示一特徵與另一特徵之間的關係而使用的。該等空間關係詞彙乃意圖涵蓋包含該等特徵的裝置的不同方向。又，當一數值或一數值範圍以「約」、「近似」等詞彙敘述時，此種詞彙乃意圖包括含有所述數值的一合理範圍內的數值，例如所述數值的正負10%範圍以內，或本發明所屬領域具技術之人所理解的其他數值。例如，詞彙「約5奈米」包含4.5奈米至5.5奈米的尺寸範圍。
總體而言，本揭露係關於半導體裝置；特定而言，係關於場效電晶體(FET)，例如平面FET、三維鰭式場效電晶體(FinFET)、或環繞式閘極(GAA)裝置。本揭露之一態樣，包括形成隔離結構，以電性隔離磊晶成長源極/汲極部件及鄰近電晶體。此一結果可提升裝置產量、可靠度及/或效能，詳見下文。
第1A圖及第1B圖分別顯示積體電路(IC)裝置90的一部分的三維透視圖及俯視圖。IC裝置90可為IC製程中製造的中間裝置、或該中間裝置的一部分，包括靜態隨機存取記憶體(SRAM)及/或其他邏輯電路、被動部件，例如電阻、電容及電感、以及主動部件，例如p型FET(PFET)、n型FET(NFET)、 FinFET、金屬氧化物半導體場效電晶體(MOSFET)、互補式金屬氧化物半導體(CMOS)電晶體、雙極性電晶體、高電壓電晶體、高頻電晶體、及/或記憶體單元。除非另有聲明，否則本揭露不限於任何特定數量的裝置或裝置區域，亦不限於任何特定裝置配置。例如，儘管圖示的IC裝置90為三維FinFET裝置，然而本揭露的概念亦可適用於平面FET裝置或GAA裝置。
參見第1A圖，IC裝置90包括基板110。基板110可包括元素(單一元素)半導體，例如矽(Si)、鍺(Ge)及/或其他合適材料；化合物半導體，例如碳化矽(SiC)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)及/或其他合適材料；合金半導體，例如矽鍺(SiGe)、磷化砷鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)、砷磷化鎵銦(GaInAsP)及/或其他合適材料。基板110可為單層材料，具有統一的成分。或者，基板110可包括多個材料層，具有適合IC裝置製造的相似或不同成分。在一範例中，基板110可為絕緣層上覆矽(SOI)基板，具有半導體矽層，形成於氧化矽層之上。在另一範例中，基板110可包括導體層、半導體層、介電層、其他層，或上述各層之結合。多個摻雜區域，例如源極/汲極區域，可形成於基板110之中或之上。摻雜區域可以n型摻雜物進行摻雜，例如磷(P)或砷(As)，及/或以p型摻雜物進行摻雜，例如硼(B)，依設計需求而定。摻雜區域可直接形成於基板110之上、於p型井(p-well)結構中、於n型井(n-well)結構中、雙井(dual-well)結構中、或使用抬升式(raised)結構。摻雜區域的形成可藉由注入摻雜物原子、原位(in-situ)摻雜磊晶成長及/或其他合適技術進行。
三維的主動區(active region)120形成於基板110上。主動區120為伸長的鰭狀結構，向上突出基板110。因此，下文中，主動區120可替換地稱為「鰭式結構120」。鰭式結構120可使用合適製程製造，包括微影製程(photolithography)及蝕刻(etch)製程。微影製程可包括形成覆蓋基板110的光阻(photoresist)層、將光阻曝光於一圖案(pattern)下、進行曝光後的烘烤(bake)製程、以及對光阻進行顯影(develop)以形成包括光阻的遮罩元件(未圖示)。遮罩元件隨後用於蝕刻深入基板110的凹槽，使鰭式結構120留在基板110上。此一蝕刻製程可包括乾蝕刻、溼蝕刻、反應離子蝕刻(RIE)及/或其他合適製程。在某些實施例中，鰭式結構120的形成可藉由雙重圖案化(patterning)或多重圖案化製程進行。一般而言，雙重圖案化或多重圖案化製程合併微影製程及自對準(self-aligned)製程，使圖案得以形成為具有例如小於使用單一直接微影製程所能得到的間距(pitch)。例如，一薄層可形成於基板上，並以微影製程圖案化。間隔物(spacer)在圖案化層的旁邊以自對準製程形成。該薄層隨後被移除，且剩餘的間隔物或心軸(mandrel)可隨後用於圖案化鰭式結構120。
IC裝置90亦包括源極/汲極特徵122，形成於鰭式結構120之上。源極/汲極特徵122可包括磊晶層，磊晶成長於鰭式結構120之上。隨著裝置尺寸日益縮小，此等源極/汲極特徵122可能相互融合，儘管其原應保持分離。本發明克服此一問題，詳見下文。
IC裝置90更包括隔離結構130，形成於基板110之上。隔離結構130電性分離IC裝置90的不同部件。隔離結構130可包括氧化矽(SiO2 )、氮化矽(SiN)、氮氧化矽(SiON)、摻雜氟矽玻璃(FSG)、低k值介電材料、及/或其他合適材料。在某些實施例中，隔離結構130可包括淺溝槽隔離(STI)特徵。在一實施例中，隔離結構130是在形成鰭式結構120時，藉由蝕刻基板110中的溝槽(trench)而形成的。該等溝槽隨後可以前文所述的隔離材料填充，隨後進行化學機械平坦化(CMP)製程。其他隔離結構，例如場區氧化層(field oxide)、矽局部氧化(LOCOS)、及/或其他合適結構，亦可作為隔離結構130實施。或者，隔離結構130可包括多層結構，例如具有一個或多個熱氧化物襯墊(liner)層。
IC裝置90亦包括閘極結構140，形成於每一鰭式結構120的通道區域的三個側面之上，並與鰭式結構120接合。閘極結構140可為虛設(dummy)閘極結構(例如包含氧化物閘極電介質及多晶矽閘極電極)，或可為高k值金屬閘極(HKMG)結構，包含高k值閘極電介質及金屬閘極電極，其中HKMG結構是經由替換虛設閘極結構形成的。雖未在圖式中繪出，然而閘極結構140可包括額外的材料層，例如鰭式結構120之上的內界面層(interfacial layer)、覆蓋層(capping layer)、其他合適層，或上述各層之組合。
參見第1B圖，多個鰭式結構120的方向為沿X方向縱向，而多個閘極結構140的方向為沿Y方向縱向，亦即總體而言垂直於鰭式結構120。在多個實施例中，IC裝置90包括額外的特徵，例如沿閘極結構140的側壁佈設的閘極間隔物、佈設於閘極結構140之上的硬遮罩(hard mask)層、及多種其他特徵。
亦應注意，下文所述之本揭露各態樣可適用於多通道裝置，例如環繞式閘極(GAA)裝置。第1C圖顯示範例GAA裝置150的三維透視圖。為了敘述的一致性及明確性起見，第1C圖及第1A圖與第1B圖中的相似部件將以相同代號標記。例如，主動區如鰭式結構120，沿Z方向垂直向上突出基板110。隔離結構130提供鰭式結構120之間的電性隔離。閘極結構140位於鰭式結構120之上，以及隔離結構130之上。遮罩155位於閘極結構140之上，而閘極間隔物160位於閘極結構140的側壁。覆蓋層165形成於鰭式結構120之上，以在形成隔離結構130時，保護鰭式結構120不受氧化作用影響。
多個奈米結構170佈設於每一鰭式結構120之上。奈米結構170可包括奈米片(nano-sheet)、奈米管(nano-tube)或奈米線(nano-wires)，或沿X方向水平延伸的其他種類奈米結構。奈米結構170位於閘極結構140之下的部分，可作為GAA裝置150的通道。介電內間隔物(dielectric inner spacer)175可佈設於奈米結構170之間。此外，儘管為簡潔起見而未顯示於圖式中，然而每一奈米結構170可被閘極電介質及閘極電極環形包覆。在圖示之範例中，奈米結構170位於閘極結構140之外的部分，可作為GAA裝置150的源極/汲極特徵。然而，在某些實施例中，連續的源極/汲極特徵可磊晶成長於鰭式結構120位於閘極結構140之外的部分。儘管如此，導電性的源極/汲極接點180可形成於該等源極/汲極特徵之上，以提供電性連結予該等源極/汲極特徵。層間電介質(ILD)185形成於隔離結構130之上，並環繞閘極結構140及源極/汲極接點180。
關於製造GAA裝置的更多詳述，見於美國專利10,164,012號，標題為Semiconductor Device and Manufacturing Method Thereof ，公告於2018年12月25日；以及美國專利10,361,278號，標題為Method of Manufacturing a Semiconductor Device and a Semiconductor Device ，公告於2019年7月23日；以及美國專利9,887,269號，標題為 Multi-Gate Device and Method of Fabrication Thereof，公告於2018年2月6日；上述每一文獻之全部揭露內容，特此參照併入本文件。儘管本揭露係關於鰭式結構或FinFET裝置，然而其亦可同等地適用於GAA裝置。
第2A圖至第21A圖及第2B圖至第21B圖顯示IC裝置200在不同製造階段中的剖面側面圖。第2A圖至第21A圖對應於沿X方向的剖面，例如沿第1A圖中的切線A-A’。因此，第2A圖至第21A圖可稱為「X切面圖」。第2B圖至第21B圖對應於沿Y方向的剖面，例如沿第1A圖中的切線B-B’。因此，第2B圖至第21B圖可稱為「Y切面圖」。為了敘述的一致性及明確性起見，第2A圖至第21A圖及第2B圖至第21B圖中出現的相似部件將以相同代號標記。
參見第2A圖至第2B圖，IC裝置200包括前文所述的基板110(參見第1A-1C圖)，例如矽基板。該基板包括多個主動區，例如前文所述的鰭式結構120(參見第1A圖至第1B圖)。每一鰭式結構120沿X方向橫向延伸，並在Y方向上以隔離結構130彼此隔開。
如第2A圖所示，IC裝置200亦包括虛設(dummy)閘極結構210，佈設於基板110之上。每一虛設閘極結構210可包括虛設閘極介電層及多晶矽閘極電極，且該等虛設閘極結構210將於下文所述的閘極替換製程中被移除。多個硬遮罩(hard mask) 220佈設於虛設閘極結構210之上。硬遮罩220可用於在一個或多個圖案化製程中定義虛設閘極結構210。閘極間隔物240形成於虛設閘極結構210及硬遮罩220的側壁上。每一閘極間隔物240可包括介電材料，例如氮化矽(SiN)、氮化碳化矽(SiCN)、或氮氧碳化矽(SiCON)。
可對IC裝置200進行磊晶成長製程260，以磊晶成長FinFET電晶體的源極/汲極部件122。源極/汲極部件122成長於鰭式結構120之上(如第2B圖所示)，且位於虛設閘極結構210之間(如第2A圖所示)。此等源極/汲極部件122可屬於不同電晶體。作為如第2B圖所示的非限制性範例，源極/汲極部件122A及122B屬於第一n型FET(NFET)，源極/汲極部件122C及122D屬於第二NFET，源極/汲極部件122E屬於第一p型FET(PFET)，而源極/汲極部件122F屬於第二PFET。
具有源極/汲極部件122A及122B成長其上的鰭式結構120，彼此以間隔270隔開。相同特徵亦適用於源極/汲極部件122C及122D。在某些實施例中，間隔270的範圍介於約20奈米(nm)至約32奈米之間。間隔270的此一範圍被配置以促進源極/汲極部件122A及122B相互融合(以及源極/汲極部件122C及122D相互融合)，此種融合為理想的，因該等源極/汲極部件屬於同一電晶體。相對地，具有源極/汲極部件122B及122C成長其上的鰭式結構120，彼此以大於間隔270的間隔271隔開。在某些實施例中，間隔271的範圍介於約50奈米至約100奈米之間。在某些實施例中，間隔271與間隔270的比例範圍介於約1.5:1至約20:1之間。又如第2B圖所示，該等源極/汲極部件(例如源極/汲極部件122B)的最外側尖端，以距離275突出最近的鰭式結構120的側面。換言之，距離275指示了源極/汲極部件橫向突出於其所依附的鰭式結構120的程度。在某些實施例中，距離275與間隔271的比例範圍介於約1:2.5至約1:25之間。
源極/汲極部件122B及122C的物理性分離為理想的，因該等源極/汲極部件屬於不同電晶體，應保持物理性及電性分離。然而，隨著電晶體尺寸日漸縮小，較大的間隔271(相較於間隔270而言)仍可能無法保證相鄰電晶體的源極/汲極部件122B及122C之間的物理性分離。有時，源極/汲極部件122B及122C可能成長至大於預期的大小，可能導致源極/汲極部件122B及122C非因故意地相互融合。例如，當距離275與間隔271的比例接近約1:2時，相鄰電晶體的源極/汲極部件可能處於相互融合的風險之下，即使該等源極/汲極部件原應保持分離。製程變異(例如對準及覆蓋控制)可能進一步加劇此一問題。
相似地，源極/汲極部件122E及122F可能因其所依附的鰭式結構120之間的間隔273縮小而相互融合，即使源極/汲極部件122E及122F原應保持相互物理性分離，因該等源極/汲極部件來自不同PFET。源極/汲極部件122B及122C的融合、或源極/汲極部件122E及122F的融合，可能導致原應相互電性隔離的電晶體之間的短路，而降低效能及/或減低IC裝置200的產量。
亦應注意，短路不僅可能發生於相鄰的NFET之間(例如源極/汲極部件122B及122C之間)或相鄰的PFET之間(例如源極/汲極部件122E及122F之間)，亦可能發生於彼此相鄰的NFET及PFET之間。例如，具有源極/汲極部件122D及122E成長其上的鰭式結構120之間以間隔272隔開。間隔272被配置為大於間隔271，以防止源極/汲極部件122D及122E之間的融合。然而，日漸縮小的裝置尺寸，以及潛在的製程變異，可能在某些裝置中導致源極/汲極部件122D(來自NFET)及122E(來自PFET)之間的融合，儘管間隔272足夠大，而可在多數裝置中防止此一融合。相同地，相鄰的NFET及PFET裝置之間此種非因故意之融合亦為吾人所欲避免的，因其可能降低裝置效能或減低產量。
為了克服前文所述的此種非因故意之源極/汲極融合，本揭露將於有相互融合之虞的源極/汲極部件之間實施電性隔離結構。此等電性隔離結構可於製造過程中的不同階段實施，詳見下文。
請參見第3A圖及第3B圖，對IC裝置200進行犧牲層形成製程300，以形成犧牲層310。犧牲層形成製程300可包括旋轉塗佈(spin coating)製程、或沉積製程，例如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)，或上述製程之組合。在某些實施例中，犧牲層310包括光阻材料。在其他實施例中，犧牲層310包括介電材料，例如氧化物材料。犧牲層310形成於虛設閘極結構210、閘極間隔物240及源極/汲極部件122之上，並覆蓋虛設閘極結構210、閘極間隔物240及源極/汲極部件122。
請參見第4A圖及第4B圖，對IC裝置200進行蝕刻製程330，以形成開口(亦稱凹陷或溝槽)340及341。開口340垂直延伸穿越犧牲層310，並「分割」了NFET的源極/汲極部件122B及122C的融合部分。開口341垂直延伸穿越犧牲層310，並「分割」了PFET的源極/汲極部件122E及122F的融合部分。換言之，蝕刻製程330亦移除了源極/汲極部件122B-122C及122E-122F的部分，使該等源極/汲極部件不再相互物理性接觸。在某些實施例中，每一開口340及341可具有梯形的側面形狀，其中開口340及341在頂部具有最大寬度，且開口340及341往下方延伸越深處的寬度越窄。應注意，由於第4A圖的剖面位置之故，開口340及341在第4A圖中並非直接可見。應注意，在某些其他實施例中，若源極/汲極部件122D及122E應保持相互電性分離，則開口亦可在源極/汲極部件122D及122E之間被蝕刻，以防止源極/汲極部件122D及122E之間可能的融合。
請參見第5A圖及第5B圖，對IC裝置200進行移除製程360，以移除犧牲層310。在犧牲層310包括光阻材料的實施例中，移除製程360可包括去光阻(photoresist stripping)或灰化(ashing)製程。在犧牲層310包括介電材料的實施例中，移除製程360可包括一個或多個蝕刻製程。如第5B圖所示，在移除製程360進行後，源極/汲極部件122B及122C會相互分離，如同源極/汲極部件122E及122F。應注意，每一源極/汲極部件122B、122C、122E及122F皆具有受蝕刻製程330影響而導致的非對稱性側面形狀。此一非對稱性側面形狀為本揭露中的IC裝置200的其中一種獨特物理特徵，見下文詳述。
請參見第6A圖及第6B圖，對IC裝置200進行沉積製程380，以形成介電層400。沉積製程380可包括CVD、PVD、ALD，或上述製程之組合。在某些實施例中，介電層400為層間電介質(ILD)，亦稱為「ILD0層」。作為非限制性範例，介電層400可包括低k值電介質(例如介電常數低於氧化矽(介電常數約為3.9)的介電材料)。在其他實施例中，介電層400可包括氧化矽、氮化矽、碳化矽，或上述材料之組合。如第6B圖所示，介電層400佈設於源極/汲極部件122B及122C之間的部分，提供二者之間的物理性及電性隔離，而介電層400佈設於源極/汲極部件122E及122F之間的部分，亦提供二者之間的物理性及電性隔離。
應注意，在沉積製程380後，可進行平坦化(planarization)製程，例如化學機械平坦化(CMP)製程，以暴露虛設閘極結構210，並平坦化介電層400的上方表面。例如，如第6A圖所示，虛設閘極結構210的上方表面可大致上與介電層400的上方表面共平面。
請參見第7A圖至第7B圖，對IC裝置200進行閘極替換製程420，以將虛設閘極結構210替換為高k值金屬閘極(HKMG)結構440。虛設閘極結構210可以蝕刻製程移除，在介電層400中留下開口(溝槽)。此等開口或溝槽隨後以HKMG結構440的金屬閘極電極填充。在某些實施例中，若虛設閘極結構210包括虛設閘極介電層(例如氧化矽閘極電介質)，則該虛設閘極介電層亦將被高k值閘極介電層替換，以作為HKMG結構440的一部分。因此，每一HKMG結構440可包括高k值閘極電介質及金屬閘極電極。高k值閘極電介質的範例材料包括氧化鉿(HfO2 )、氧化鋯(ZrO2 )、氧化鋁(Al2 O3 )、二氧化鉿-氧化鋁合金、矽氧化鉿(HfSiO)、氮氧矽化鉿(HfSiON)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)，或上述材料之組合。金屬閘極電極可包括一個或多個功函數(work function)金屬層，以及一個或多個填充金屬層。功函數金屬層可被配置為調節個別電晶體的功函數。功函數金屬層的範例材料包括氮化鈦(TiN)、鈦鋁(TiAl)、氮化鉭(TaN)、碳化鈦(TiC)、碳化鉭(TaC)、碳化鎢(WC)、氮化鋁鈦(TiAlN)、鋯鋁(ZrAl)、鎢鋁(WAl)、鉭鋁(TaAl)、鉿鋁(HfAl)，或上述材料之組合。填充金屬層可作為閘極電極層的主要導電部分。在某些實施例中，HKMG結構440可包括額外層，例如界面間層(interfacial layer)、覆蓋層(capping layer)、擴散/阻障層(diffusion/barrier layer)，或其他適用層。
在HKMG結構440於溝槽中形成，以替換虛設閘極結構210後，亦可進行回蝕(etch-back)及CMP製程，以降低HKMG結構440及介電層400的高度，並平坦化HKMG結構440的上方表面及介電層400的上方表面。應注意，HKMG結構440在第7B圖中並非直接可見，因第7B圖中所示的剖面是沿剖線B-B’切取的，而剖線B-B’位於HKMG結構440之外。
請參見第8A圖及第8B圖，進行源極/汲極接點形成製程460，以形成源極/汲極接點480。例如，可進行一個或多個蝕刻製程，以選擇性移除介電層400位於源極/汲極部件122A-122F上方的部分，進而形成源極/汲極接點溝槽。導電材料例如鎢(W)、鈦(Ti)、鈷(Co)、鋁(Al)、銅(Cu)或上述材料之組合，可隨後沉積，以填充源極/汲極接點溝槽，進而形成源極/汲極接點480。其中一個源極/汲極接點480將源極/汲極部件122A及122B電性耦接，另一源極/汲極接點480將源極/汲極部件122C及122E電性耦接，又另一源極/汲極接點480佈設於源極/汲極部件122F之上。
請參見第9A圖及第9B圖，進行沉積製程490，以在源極/汲極接點480之上及HKMG結構440之上形成介電層500。沉積製程490可包括CVD、PVD、ALD，或上述製程之組合。在某些實施例中，介電層500為另一層間電介質，亦稱為「ILD1層」，因其佈設於較ILD0層高一層之處。作為非限制性範例，介電層500可包括低k值電介質、氧化矽、氮化矽，或上述材料之組合。
額外的製造製程可於隨後進行，以完成IC裝置200的製造。例如，可形成延伸穿越介電層500的閘極接點及/或源極/汲極導通孔(via)，以提供電性連接至HKMG結構440及/或源極/汲極接點480，且包含導通孔及金屬線的額外金屬化層(metallization layer)可形成於介電層500之上。IC裝置200亦可能經歷測試(testing)或封裝(packaging)製程。為簡明起見，此等額外製程於本文中不再贅述。
第9B圖顯示IC裝置200的獨特物理特徵：源極/汲極部件的非對稱性。例如，如第9B圖所示，源極/汲極部件122C在其「左側」具有最外側部分510，而源極/汲極部件122D在其「右側」具有最外側部分511。最外側部分510及最外側部分511具有不同的物理剖面側面形狀，因源極/汲極部件122C的左側在蝕刻製程330中被蝕刻，而源極/汲極部件122D的右側在蝕刻製程330中並未被蝕刻。在某些實施例中，最外側部分510可近似於一直線、或一相對平坦的邊緣，亦可能具有某種程度的傾斜，因溝槽340(參見第4B圖)傾斜、或具有梯形的上寬下窄側面形狀。相對地，最外側部分511具有帶尖角的側面形狀，或至少具有某種程度的弧形突出，此一突出為磊晶成長所致。因此，作為合併的單一結構，源極/汲極部件122C及122D具有非對稱性側面形狀，因最外側部分510及511的形狀彼此不同。相同情況亦見於源極/汲極部件122A及122B的合併結構中。此外，源極/汲極部件122E及122F亦皆具有形狀為一直線或平坦邊緣的最外側部分515、以及形狀為帶有尖角或弧形邊緣的另一最外側部分516。換言之，源極/汲極部件122E自身具有非對稱性側面形狀，源極/汲極部件122F亦同。
然而，應注意，依據本揭露所製造的IC裝置，並非必須具有非對稱性側面形狀。在本揭露的某些實施例中，一源極/汲極部件(或多個相互融合的源極/汲極部件)的「左側」及「右側」皆可被蝕刻，進而使結構具有對稱性源極/汲極部件，其中左側最外側部分及右側最外側部分皆具有直線或相對平坦的邊緣形狀。
前文參見第2A圖與第2B至9A圖與第9B圖的敘述，是關於本揭露的第一實施例，其中融合的源極/汲極部件122在ILD0(亦即介電層400)形成之前被分離。第10A圖與第10B至13A圖與第13B圖是關於本揭露的第二實施例，其中融合的源極/汲極部件122在介電層400(亦即ILD0)形成之後、但在HKMG結構440形成之前被分離。本揭露此一第二實施例將於下文詳述。為了敘述的一致性及明確性起見，在第一實施例及第二實施例中出現的相似部件將以相同代號標記。
請參見第10A圖及第10B圖，源極/汲極部件122已以前文所述的磊晶成長製程260(參見第2A圖及第2B圖)磊晶成長。因此，第二實施例進行沉積製程380，而非形成犧牲層310(如第一實施例中所進行者)，以形成介電層400(亦即ILD0)。在此一製造階段中，融合的源極/汲極部件122A-122B、122C-122D、以及122E-122F尚未被分離。介電層400形成於源極/汲極部件122A至122E的周圍，如第10B圖所示。
請參見第11A圖及第11B圖，進行蝕刻製程520，以形成開口540及541。開口540垂直延伸穿越介電層400，並「分離」NFET的源極/汲極部件122B及122C的融合部分。開口541垂直延伸穿越介電層400，並「分離」PFET的源極/汲極部件122E及122F的融合部分。換言之，蝕刻製程520亦移除源極/汲極部件122B-122C及122E-122F的部分，使源極/汲極部件122B-122C及122E-122F不再彼此物理性接觸。應注意，由於第11A圖的剖面位置，故開口540及541在第11A圖中並非直接可見。
應注意，相較於第一實施例中的開口340及341(垂直蝕刻穿越犧牲層310，如第4B圖所示)，開口540及541具有較短的高度以及較小的深寬比(aspect ratio)，其中「深寬比」指開口高度(在Z方向上)以及開口寬度(在Y方向上)的比例。較小的深寬比使製程控制略為容易，例如使控制開口540-541的位置較為容易。
請參見第12A圖及第12B圖，對IC裝置200進行一個或多個沉積製程550，以分別在開口540及541中形成隔離結構560及561。沉積製程550可包括CVD製程、PVD製程、ALD製程，或上述製程之組合。隔離結構560及561可包括介電材料，例如氮化矽。在某些實施例中(例如圖示之實施例)，隔離結構561及561可分別包括襯墊(liner)570及571。換言之，襯墊570及571首先藉由沉積製程550沉積進入開口540及541。隔離結構560及561的其餘部分於稍後沉積進入開口540及541，分別沉積於襯墊570及571之上。在此一「雙層」結構中，襯墊570及571可包括具有良好黏著(adhesion)特性的介電材料，且隔離結構560及561的其餘部分可包括具有快速空隙填充(gap filling)效能的材料。在某些實施例中，襯墊570及571可包括氧化矽，而隔離結構560及561的其餘部分可包括氮化矽。
無論隔離結構560及561是以單層結構或雙層結構實施，皆可在源極/汲極部件122B及122C之間、以及源極/汲極部件122E及122F之間，提供有效的電性及物理性隔離。因此，可防止相鄰的源極/汲極部件之間欲避免的融合。
請參見第13A圖及第13B圖，對IC裝置200進行前述參見第7A圖至第9A圖及第7B圖至第9B圖的製程，包括閘極替換製程420，以將虛設閘極結構210替換為HKMG結構440、源極/汲極接點形成製程460，以形成源極/汲極接點480、以及沉積製程490，以形成介電層500(亦即ILD1)。由於此等製程已在第一實施例中詳述，故在第二實施例中不再贅述。
第14A圖至第17A圖及第14B圖至第17B圖是關於本揭露的第三實施例，其中融合的源極/汲極部件122在形成HKMG結構440以替換虛設閘極結構210之後、但在源極/汲極接點480形成之前被分離。本揭露此一第三實施例將於下文詳述。為了敘述的一致性及明確性起見，在第一實施例、第二實施例及第三實施例中出現的相似部件將以相同代號標記。
請參見第14A圖及第14B圖，源極/汲極部件122已以前文所述的磊晶成長製程260(參見第2A圖及第2B圖)磊晶成長。如前述第二實施例中所進行者，第三實施例進行沉積製程380，以形成介電層400(亦即ILD0)。隨後進行閘極替換製程420，以將虛設閘極結構210替換為HKMG結構440。在此一製造階段中，融合的源極/汲極部件122A-122B、122C-122D及122E-122F尚未被分離，如第14B圖所示。
請參見第15A圖及第15B圖，進行前述蝕刻製程520，以形成垂直延伸穿越介電層400的開口540及541。相同地，開口540「分離」NFET的源極/汲極部件122B及122C的融合部分，而開口541「分離」PFET的源極/汲極部件122E及122F的融合部分。開口540及541亦具有較第一實施例中的開口340及341小的深寬比，而此一較小的深寬比使更佳的製程控制得以進行。相同地，由於第15A圖的剖面位置，故開口540及541在第15A圖中並非直接可見。
請參見第16A圖及第16B圖，對IC裝置200進行前述一個或多個沉積製程550，以分別在開口540及541中形成隔離結構560及561。沉積製程550可包括CVD製程、PVD製程、ALD製程，或上述製程之組合。隔離結構560及561可包括介電材料，例如氮化矽、氧化矽、氮氧化矽、氮氧碳化矽、碳化矽、高k值介電材料(例如氧化鉿)、或低k值介電材料(例如多孔材料)。又，如前文所述，隔離結構560及561可分別包括襯墊570及571，由不同於隔離結構560及561其餘部分的材料製成。無論何種情況，隔離結構560及561皆可在源極/汲極部件122B及122C之間、以及源極/汲極部件122E及122F之間，有效地提供電性隔離及物理性隔離。因此，可防止吾人欲避免的相鄰源極/汲極部件之間彼此融合的情況。
請參見第17A圖及第17B圖，對IC裝置200進行前述參見第7A圖至第9A圖及第7B圖至第9B圖的製程，包括源極/汲極接點形成製程460，以形成源極/汲極接點480、以及沉積製程490，以形成介電層500(亦即ILD1)。由於此等製程已在前文第一實施例中詳述，故在第三實施例中不再贅述。
第18A圖至第20A圖及第18B圖至第20B圖是關於本揭露的第四實施例，其中融合的源極/汲極部件122在源極/汲極接點480形成之後、但在額外的金屬化層(例如形成於源極/汲極接點480之上的導通孔)形成之前被分離。本揭露此一第四實施例將於下文詳述。為了敘述的一致性及明確性起見，在第一實施例、第二實施例、第三實施例及第四實施例中出現的相似部件將以相同代號標記。
請參見第18A圖及第18B圖，源極/汲極部件122已磊晶成長，介電層400(亦即ILD0)已形成，虛設閘極結構210已被替換為HKMG結構440，源極/汲極接點480已形成，且介電層500(亦即ILD1)亦已形成。在此一製造階段中，融合的源極/汲極部件122A-122B、122C-122D及122E-122F尚未被分離，如第18B圖所示。
請參見第19A圖及第19B圖，進行蝕刻製程600，以形成開口610及611，垂直延伸穿越介電層500，並穿越介電層400。相較於前述第二實施例及第三實施例中的開口540及541，第四實施例中的開口610及611深度較深，因開口610及611必須延伸穿越介電層500及400二者。換言之，開口610及611具有較開口540及541大的深寬比。然而，開口610及611仍可具有小於第一實施例中的開口340及341(如第4B圖所示)的深寬比。無論何種情況，開口610「分離」NFET的源極/汲極部件122B及122C的融合部分，而開口611「分離」PFET的源極/汲極部件122E及122F的融合部分。由於第18A圖的剖面位置，故開口610及611在第19A圖中並非直接可見。
請參見第20A圖及第20B圖，進行一個或多個沉積製程630。此一個或多個沉積製程630可相似於前述一個或多個沉積製程550。換言之，此一個或多個沉積製程630分別在開口610及611中形成隔離結構640及641。相似於隔離結構560及561，隔離結構640及641可包括氮化矽、氧化矽、氮氧化矽、氮氧碳化矽、碳化矽、高k值介電材料、或低k值介電材料。隔離結構640及641亦皆可具有單層結構或雙層結構(例如分別包括襯墊650及651)。隔離結構640及641可在源極/汲極部件122B及122C之間、以及源極/汲極部件122E及122F之間，有效地提供電性隔離及物理性隔離。因此，可防止吾人欲避免的相鄰源極/汲極部件之間彼此融合的情況。
在前文第一實施例至第四實施例的敘述中，IC裝置200為FinFET形式。然而，本揭露中的進步性概念亦可適用於多通道裝置，例如相似於第1C圖中的環繞式閘極(GAA)裝置150的GAA裝置。第21A圖及第21B圖顯示本揭露一實施例，其中IC裝置200為GAA裝置形式。第21A圖顯示一X剖面圖，其中剖面沿第1C圖中的剖線A-A’切取，而第21B圖顯示一Y剖面圖，其中剖面沿第1C圖中的剖線B-B’切取。相同地，為了敘述的一致性及明確性起見，在第21A-21B圖及前述FinFET實施例中出現的相似部件將以相同代號標記。
如第21A圖中的X剖面圖所示，IC裝置200包括多個奈米結構170，如前文所述(參見第1C圖)。每一奈米結構170沿X方向延伸，且可包括奈米片層、奈米管、奈米線，或某些其他形式的奈米結構。每一奈米結構170具有被HKMG閘極結構440環狀圍繞的區域，其中每一HKMG結構440包括高k值閘極電介質及包含金屬的閘極電極。奈米結構170中的此等區域作為電晶體的通道區域，因此每一電晶體包括多個通道(因每一電晶體中具有多個奈米結構170)。如第21B圖所示，隔離結構640物理性隔離NFET中的源極/汲極部件122G及122H，而隔離結構641物理性隔離PFET中的源極/汲極部件122E及122F。應注意，隔離結構640及641是依據前述FinFET第四實施例製造的(例如形成於源極/汲極接點480形成之後)。然而，FinFET第一、第二及第三實施例亦可適用於本文所述的GAA裝置。為簡明起見，不再贅述。
第22圖顯示本揭露另一實施例，其中氣隙(air gap)或空腔(void)形成於隔離結構中。例如，以FinFET第四實施例為例，隔離結構640及641可分別具有氣隙700及氣隙701固定於其中。氣隙700及701可藉由在開口610及611中填充空隙填充特性不佳的材料而形成，該材料隨後可分別將氣隙700及701固定於隔離結構640及641之內。氣隙700及701可有助於降低寄生電容值(parasitic capacitance)，因空氣具有接近1的低介電常數。應注意，氣隙700及701可形成於前述四種FinFET實施例的隔離結構中，亦可形成於GAA實施例的隔離結構中。
應注意，本揭露中的隔離結構並不必須形成於所有種類的IC裝置之中，或遍及整個晶圓。反之，隔離結構可在主動區之間的間隔較小(例如相鄰電晶體的鰭式結構之間的間隔較小)的IC裝置中選擇性地形成，其可位於晶圓上的某一區域，而在晶圓上的其他區域則無。例如，一晶圓可包括第一區域，其中IC裝置具有相對較小的主動區間隔、以及第二區域，其中IC裝置具有相對較大的主動區間隔。因此，第一區域中的源極/汲極部件具有較高的非因故意相互融合風險，而第二區域中的源極/汲極部件則否。因此，前述隔離結構可選擇性地形成於第一區域，而不形成於第二區域。
IC裝置200可在多種IC應用中實施，包括記憶體裝置，例如靜態隨機存取記憶體(SRAM)裝置。就此而言，第23圖為一範例電路圖，顯示單埠(single-port)SRAM單元(例如1位元SRAM單元)800。單埠SRAM單元800包括上拉式(pull-up)電晶體PU1及PU2；下拉式(pull-down)電晶體PD1及PD2；以及傳送閘(pass-gate)電晶體PG1及PG2。如電路圖所示，上拉式電晶體PU1及PU2為p型電晶體，而下拉式電晶體PG1、PG2、PD1及PD2為n型電晶體。依據本揭露的各種態樣，傳送閘電晶體PG1、PG2及下拉式PD1、PD2以較上拉式電晶體PU1及PU2窄的間隔物實施。由於SRAM單元800在圖示實施例中包括六個電晶體，故其亦可稱為「六電晶體(6T) SRAM單元」。
上拉式電晶體PU1及下拉式電晶體PD1的汲極相互耦接，且上拉式電晶體PU2及下拉式電晶體PD2的汲極相互耦接。上拉式電晶體PU1及下拉式電晶體PD1與上拉式電晶體PU2及下拉式電晶體PD2交叉耦接(cross-coupled)，以形成第一資料鎖存器(data latch)。上拉式電晶體PU2及下拉式電晶體PD2的閘極相互耦接，並耦接至上拉式電晶體PU1及下拉式電晶體PD1的汲極，以形成第一儲存節點SN1；而上拉式電晶體PU1及下拉式電晶體PD1的閘極相互耦接，並耦接至上拉式電晶體PU2及下拉式電晶體PD2的汲極，以形成互補第一儲存節點SNB1。上拉式電晶體PU1及PU2的源極耦接至電源電壓VCC (亦稱為Vdd )，而下拉式電晶體PD1及PD2的源極耦接至電壓VSS ，其在某些實施例中可為電性接地。
第一資料鎖存器的第一儲存節點SN1經由傳送閘電晶體PG1耦接至位元線(bit line)BL，而互補第一儲存節點SNB1經由傳送閘電晶體PG2耦接至互補位元線BLB。第一儲存節點SN1及互補第一儲存節點SNB1為互補節點，通常處於相反的邏輯位準(邏輯高電位或邏輯低電位)。傳送閘電晶體PG1及PG2的閘極耦接至字元線(word line)WL。SRAM裝置，例如SRAM單元800，可使用「平面」電晶體裝置實施，以FinFET裝置及/或GAA裝置實施。
第24圖依據本揭露的實施例顯示積體電路製造系統900。製造系統900包括多個實體902、904、906、908、910、912、914、916...N，以通訊網路918相互連接。通訊網路918可為單一網路、或可為多個不同網路，例如內部網路(intranet)及網際網路(Internet)，且可包括有線及無線通訊通道。
在一實施例中，實體902代表服務系統，用於生產協作；實體904代表使用者，例如產品工程師，對關注的產品進行監控；實體906代表工程師，例如製程工程師，控制製程及相關的製造方法、或設備工程師，對製程工具的狀態及設定進行監控或調節；實體908代表測量工具，用於IC測試及測量；實體910代表半導體製程工具，例如極紫外光微影製程(EUV)工具，用於進行微影製程(lithography)，以定義SRAM裝置的閘極間隔物；實體912代表虛擬測量模組，與製程工具910相關；實體914代表先進製程控制模組，與製程工具910以及其他額外的製程工具相關；而實體916代表取樣模組，與製程工具910相關。
每一實體可與其他實體互動，並可提供積體電路製造、製程控制及/或運算能力予其他實體，及/或自其他實體接收上述能力。每一實體亦可包括一個或多個電腦系統，用於進行運算及執行自動化技術(automation)。例如，實體914的先進製程控制模組可包括多個電腦硬體，具有軟體指令編碼於其中。此等電腦硬體可包括硬碟、隨身碟、CD-ROM、隨機存取記憶體(RAM)、顯示裝置(例如顯示器)、輸入/輸出裝置(例如滑鼠及鍵盤)。該等軟體指令可以任何合適的程式語言寫成，且可被設計為執行特定任務。
積體電路製造系統900使各實體間得以互動，以進行積體電路(IC)製造，以及IC製造的先進製程控制。在一實施例中，先進製程控制包括依據測量結果，調整一種製程工具適用於相關晶圓的製程狀態、設定及/或製造方法。
在另一實施例中，測量結果是由對已通過製程的晶圓中的一個子集合進行測量而得的，該晶圓子集合是依據最佳化取樣率取樣而得，其中最佳化取樣率基於製程品質及/或產品品質而定。在又一實施例中，測量結果是由對該已通過製程晶圓子集合中的選定場(field)及點(point)進行測量而得的，該等場及點是依據最佳化取樣場/點取樣而得，其中最佳化取樣場/點基於製程品質及/或產品品質的各種特性而定。
IC製造系統900提供的其中一種性能，可在設計、工程、製程、測量、以及先進製程控制等領域中，使協作及資訊存取得以進行。IC製造系統900提供的另一種性能，可整合設備之間的系統，例如測量工具及製程工具之間。此一整合使設備得以相互協調彼此的運作。例如，整合測量工具及製程工具，可使生產資訊更有效率地整合進製造過程或先進製程控制(APC)模組內，且可使來自線上或以測量工具現場(in site)測得的晶圓資料整合進相關的製程工具中。
第25圖為一流程圖，依據本揭露一實施例，顯示一方法1000，用於製造半導體裝置。方法1000包括操作1010，用於在基板上形成第一主動區及第二主動區。
方法1000包括操作1020，用於磊晶成長第一源極/汲極部件及第二源極/汲極部件，分別成長於第一主動區及第二主動區之上。
方法1000包括操作1030，用於在第一源極/汲極部件及第二源極/汲極部件之上形成材料層。
方法1000包括操作1040，用於蝕刻穿越材料層的開口。此開口分離第一源極/汲極部件及第二源極/汲極部件。
方法1000包括操作1050，用於以一種或多種介電材料填充開口。
在某些實施例中，第一源極/汲極部件及第二源極/汲極部件在磊晶成長之後相互融合。
在某些實施例中，操作1050包括以單一種類的介電材料填充開口。
在某些實施例中，操作1050包括：在開口中沉積介電襯墊，其中該介電襯墊部分填充該開口；以及沉積介電材料於介電襯墊之上，其中該介電材料完全填充該開口。
在某些實施例中，操作1030包括形成犧牲層作為材料層。方法1000更可包括下列操作：在犧牲層中蝕刻開口後，移除犧牲層；在犧牲層移除後，形成層間電介質(ILD)在第一源極/汲極部件及第二源極/汲極部件之上及周圍；在ILD形成後，在基板上形成包含金屬的閘極結構；並在形成包含金屬的閘極結構後，在第一源極/汲極部件之上形成第一源極/汲極接點，以及在第二源極/汲極部件之上形成第二源極/汲極接點。在某些實施例中，犧牲層的形成包括形成光阻層，作為犧牲層。
在某些實施例中，操作1030包括形成層間電介質(ILD)作為材料層。方法1000更可包括下列操作：在填充開口後，在基板上形成包含金屬的閘極結構；並在形成包含金屬的閘極結構後，在第一源極/汲極部件之上形成第一源極/汲極接點，以及在第二源極/汲極部件之上形成第二源極/汲極接點。
在某些實施例中，操作1030包括形成層間電介質(ILD)作為材料層。方法1000更可包括下列操作：在蝕刻開口前，在基板上形成包含金屬的閘極結構；並在以一種或多種介電材料填充開口後，在第一源極/汲極部件之上形成第一源極/汲極接點，以及在第二源極/汲極部件之上形成第二源極/汲極接點。
在某些實施例中，操作1030包括形成層間電介質(ILD)作為材料層。方法1000更可在蝕刻開口前包括下列操作：在基板上形成包含金屬的閘極結構；以及在第一源極/汲極部件之上形成第一源極/汲極接點，並在第二源極/汲極部件之上形成第二源極/汲極接點。開口的蝕刻在第一源極/汲極接點及第二源極/汲極接點形成後進行。
應注意，方法1000可在操作1010-1050之前、之中或之後包括其他進一步的操作。例如，方法1000可包括形成虛設閘極結構、將虛設閘極結構替換為HKMG結構、形成額外的金屬化層等操作。為簡明起見，此等額外步驟不再贅述。
前述先進微影製程、方法及材料，可用於多種應用中，包括鰭式場效電晶體(FinFET)。例如，鰭式結構可被圖案化，以在各特徵之間產生相對較近的間隔，與前文揭露適配。此外，用於形成FinFET的鰭式結構的間隔物(或稱心軸(mandrel))，可依據前文揭露處理。亦應注意，本揭露之前述各態樣，可適用於多通道裝置，例如環繞式閘極(GAA)裝置。儘管本揭露係關於鰭式結構或FinFET裝置，然而其亦可等同地適用於GAA裝置。
總而言之，本揭露在不同電晶體的磊晶成長源極/汲極部件之間形成介電隔離結構。在某些實施例中，此一介電隔離結構可藉由在源極/汲極部件周圍形成犧牲層、蝕刻穿越犧牲層的開口，其中該開口分離該等源極/汲極部件、移除犧牲層、並在源極/汲極部件周圍形成介電層(亦即ILD0)而形成。形成於源極/汲極部件之間的介電層的一部分，將作為介電隔離結構。在某些其他實施例中，此一介電隔離結構可藉由在源極/汲極部件周圍形成介電層(亦即ILD0)、蝕刻穿越介電層的開口，其中該開口分離該等源極/汲極部件、並以一個或多個介電層填充開口而形成。填充開口的介電層，將作為介電隔離結構。在此等實施例中，開口可在HKMG結構形成之前被蝕刻，或在HKMG結構形成之後、源極/汲極接點形成之前被蝕刻，或在源極/汲極接點形成之後被蝕刻。
在某些源極/汲極部件之間形成此一介電隔離結構，相較於習知裝置，可提供多種優點。然而，應注意，並非所有優點皆於本文中述及，不同實施例可提供不同優點，且任一實施例並不必然具有特定優點。優點之一，在於可防止欲避免的短路。詳細而言，隨著半導體的特徵尺寸(feature size)日益縮小，相鄰電晶體之間的源極/汲極部件(磊晶成長於主動區之上)可能相互融合。例如，一第一電晶體的源極/汲極部件可能與一第二電晶體的源極/汲極部件融合，即使該第一電晶體及第二電晶體的源極/汲極部件原應保持物理性分離。此一融合可能因源極/汲極部件所依附的主動區(例如鰭式結構)之間的距離縮短而發生。因此，容許誤差的空間可能十分小。當源極/汲極部件成長至大於預期的尺寸、或其位置因製程變異而稍微移位時，某些源極/汲極部件可能相互融合，即使其原應保持分離。融合的源極/汲極部件導致短路，可能導致裝置效能降低及/或產量減少。在此，藉由在源極/汲極部件之間形成隔離結構，應保持分離的源極/汲極部件可確實保持分離。如此，可防止欲避免的短路情形。其他優點可包括與現有製程的相容性(包括FinFET及GAA製程)，以及易實施性及低成本。
本揭露之一態樣係關於一種半導體裝置。此裝置包括第一主動區及第二主動區，佈設於基板之上。第一源極/汲極部件成長於第一主動區之上。第二源極/汲極部件成長於第二主動區之上。層間電介質(ILD)佈設於第一源極/汲極部件及第二源極/汲極部件周圍。隔離結構垂直延伸穿越層間電介質，並分離第一源極/汲極部件及第二源極/汲極部件。
在某些實施例中，第一源極/汲極部件及第二源極/汲極部件皆具有非對稱性側面形狀剖面(asymmetrical profile cross-sectional view)。在某些實施例中，第一源極/汲極部件及第二源極/汲極部件皆在第一側面具有第一最外側部分，並在第二側面具有第二最外側部分，且第一最外側部分的形狀與第二最外側部分的形狀不同。在某些實施例中，第一最外側部分的形狀近似於一直線，而第二最外側部分的形狀近似於一尖角。
在某些實施例中，至少一個第一源極/汲極部件及第二源極/汲極部件包括多個相互融合的磊晶源極/汲極特徵。
在某些實施例中，隔離結構包括介電襯墊，與第一源極/汲極部件及第二源極/汲極部件直接接觸；以及介電區段，佈設於介電襯墊之上。在某些實施例中，介電襯墊及介電區段具有不同的材料組成。
在某些實施例中，此半導體裝置為FinFET裝置。
在某些實施例中，此半導體裝置為環繞式閘極(GAA)裝置。
本揭露之另一態樣係關於一種半導體裝置。此半導體裝置包括多個主動區，佈設於基板之上；多個閘極結構，佈設於主動區之上；以及多個源極/汲極，分別磊晶成長於各主動區之上。各源極/汲極中，至少有一第一源極/汲極在剖面圖中具有非對稱式側面形狀。
在某些實施例中，非對稱式側面形狀是由第一源極/汲極的第一最外側部分及第一源極/汲極的第二最外側部分定義的，其中第一最外側部分具有平坦的邊緣，而第二最外側部分具有突出的尖角。
本揭露之又一態樣係關於一種半導體裝置之製造方法。此製造方法包括在基板上形成第一主動區及第二主動區；分別在第一主動區及第二主動區之上磊晶成長第一源極/汲極部件及第二源極/汲極部件；在第一源極/汲極部件及第二源極/汲極部件之上形成材料層；蝕刻出穿越材料層的開口，此開口分離第一源極/汲極部件及第二源極/汲極部件；以及以一種或多種介電材料填充開口。
在某些實施例中，第一源極/汲極部件及第二源極/汲極部件在磊晶成長後相互融合。
在某些實施例中，填充開口的操作包括以單一種類的介電材料填充開口。
在某些實施例中，填充開口的操作包括：在開口中沉積介電襯墊，其中介電襯墊部分填充開口；以及沉積介電材料於介電襯墊之上，其中介電材料完全填充開口。
在某些實施例中，材料層的形成包括形成犧牲層作為材料層，且其中此方法更包括：在犧牲層中蝕刻開口後，移除犧牲層；在犧牲層移除後，在第一源極/汲極部件及第二源極/汲極部件之上及周圍形成層間電介質(ILD)；在ILD形成後，在基板上形成包含金屬的閘極結構；以及在包含金屬的閘極結構形成後，在第一源極/汲極部件之上形成第一源極/汲極接點，並在第二源極/汲極部件之上形成第二源極/汲極接點。在某些實施例中，犧牲層的形成包括形成光阻層作為犧牲層。
在某些實施例中，材料層的形成包括形成層間電介質(ILD)作為材料層，且其中此方法更包括：在填充開口後，在基板上形成包含金屬的閘極結構；以及在形成包含金屬的閘極結構後，在第一源極/汲極部件之上形成第一源極/汲極接點，並在第二源極/汲極部件之上形成第二源極/汲極接點。
在某些實施例中，材料層的形成包括形成層間電介質(ILD)作為材料層，且其中此方法更包括：在蝕刻開口前，在基板上形成包含金屬的閘極結構；以及在以一種或多種介電材料填充開口後，在第一源極/汲極部件之上形成第一源極/汲極接點，並在第二源極/汲極部件之上形成第二源極/汲極接點。
在某些實施例中，材料層的形成包括形成層間電介質(ILD)作為材料層，且其中此方法更包括在蝕刻開口前，進行以下操作：在基板上形成包含金屬的閘極結構；在第一源極/汲極部件之上形成第一源極/汲極接點，並在第二源極/汲極部件之上形成第二源極/汲極接點；其中開口的蝕刻在第一源極/汲極接點及第二源極/汲極接點形成後進行。
上文概述了數個實施例的特徵，使本發明所屬領域具技術之人可對本揭露之各態樣達到更佳的理解。本發明所屬領域具技術之人應注意到，其人可輕易地基於本揭露，對其他製程及結構進行設計或改良，以實行本文所述各實施例的目的，或達到與本文所述各實施例相同的優點。 本發明所屬領域具技術之人亦應認識到，此等等效結構並不脫離本揭露的精神及範圍，且其人可對本揭露進行各種改造、替換及改良，而不脫離本揭露的精神及範圍。
90:積體電路裝置 110:基板 120:主動區 122:源極/汲極特徵 130:隔離結構 140:閘極結構 150:環繞式閘極裝置 155:遮罩 160:閘極間隔物 165:覆蓋層 170:奈米結構 175:介電內間隔物 180:源極/汲極接點 185:層間電介質 200:IC裝置 210:虛設閘極結構 220:硬遮罩 240:閘極間隔物 260:磊晶成長製程 122A-122F:源極/汲極部件 270, 271, 272:間隔 275:距離 300:犧牲層形成製程 310:犧牲層 273:間隔 330:蝕刻製程 340, 341:開口 360:移除製程 380:沉積製程 400:介電層 420:閘極替換製程 440:高k值金屬閘極結構 460:源極/汲極接點形成製程 480:源極/汲極接點 490:沉積製程 500:介電層 510, 511, 515, 516:最外側部分 520:蝕刻製程 540, 541:開口 550:沉積製程 560, 561:隔離結構 570, 571:襯墊 600:蝕刻製程 610, 611:開口 630:沉積製程 640, 641:隔離結構 650, 651:襯墊 122G, 122H:源極/汲極部件 700, 701:氣隙 800:單埠靜態隨機存取記憶體單元 BL:位元線 BLB:互補位元線 WL:字元線 PU1, PU2:上拉式電晶體 PD1, PD2:下拉式電晶體 PG1, PG2:傳送閘電晶體 SN1:第一儲存節點 SNB1:互補第一儲存節點 900:積體電路製造系統 902-916, N:實體 918:通訊網路 1000:方法 1010-1050:操作
本揭露之各態樣，於閱讀下列詳述，並搭配附隨之圖式一同閱讀後，可達最佳之理解。應注意，依據本揭露所屬產業的慣常作法，各特徵並未依比例繪製，且各圖式僅作為示意之用。事實上，為敘述清晰起見，各特徵的尺寸可任意放大或縮小。 第1A圖為一透視圖，依據本揭露的多種態樣，顯示鰭式場效電晶體(FinFET)形式的IC裝置。 第1B圖為一平面俯視圖，依據本揭露的多種態樣，顯示鰭式場效電晶體形式的IC裝置。 第1C圖為一透視圖，依據本揭露的多種態樣，顯示環繞式閘極(GAA)裝置形式的IC裝置。 第2A圖至第21A圖、第2B圖至第21B圖及第22圖為剖面圖，依據本揭露的多種態樣，顯示IC裝置在各製造階段的多個實施例。 第23圖為一電路圖，依據本揭露的多種態樣，顯示靜態隨機存取記憶體(SRAM)單元。 第24圖為一方塊圖，依據本揭露的多種態樣，顯示一種製造系統。 第25圖為一流程圖，依據本揭露的多種態樣，顯示一種製造半導體裝置的方法。
1000:方法
1010-1050:操作

Claims (1)

  1. 一種半導體裝置，包括： 一第一主動區及一第二主動區，佈設於一基板之上； 一第一源極/汲極部件，成長於該第一主動區之上； 一第二源極/汲極部件，成長於該第二主動區之上； 一層間電介質，佈設於該第一源極/汲極部件及該第二源極/汲極部件周圍；以及 一隔離結構，垂直延伸穿越該層間電介質，且分離該第一源極/汲極部件及該第二源極/汲極部件。
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