TW202201905A - Input receiver - Google Patents
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本發明是有關於一種輸入接收器,且特別是有關於一種採用多級反相器電路結構的輸入接收器。The present invention relates to an input receiver, and more particularly, to an input receiver using a multi-stage inverter circuit structure.
隨著科技的發展,消費型的電子裝置逐漸被普及,半導體裝置已成為電子裝置中重要的元件。在動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)等半導體裝置中具備接收來自外部的輸入信號的輸入接收器。作為輸入接收器,一般使用將輸入信號與參考電壓進行比較,並根據其電壓差而生成放大信號的差動型之放大器電路。With the development of science and technology, consumer electronic devices are gradually popularized, and semiconductor devices have become important components in electronic devices. A semiconductor device such as a dynamic random access memory (DRAM) includes an input receiver that receives an input signal from the outside. As an input receiver, a differential amplifier circuit is generally used that compares an input signal with a reference voltage and generates an amplified signal based on the voltage difference.
近年來,除了DRAM的功耗日益降低之外,DRAM的存取速度也不斷提升。在習知的傳統設計中,可以透過配置在輸入接收器的輸出級的分路電阻(shunt resistance)來使輸入接收器在高速的環境下也能正確地動作。然而,由於漏電流影響,使用分路電阻會造成額外的功耗,從而降低DRAM整體的效能。In recent years, in addition to the decreasing power consumption of DRAM, the access speed of DRAM is also increasing. In the known conventional design, the input receiver can operate correctly even in a high-speed environment by configuring the shunt resistance at the output stage of the input receiver. However, the use of shunt resistors will cause additional power consumption due to leakage current, thereby reducing the overall performance of the DRAM.
本發明提供一種輸入接收器,可利用與放大器電路並聯於相同節點之間的反相器電路結構來代替傳統設計中的分路電阻。The present invention provides an input receiver that can replace the shunt resistor in the conventional design with an inverter circuit structure connected in parallel with the amplifier circuit between the same nodes.
本發明的輸入接收器包括第一電流源電路、第二電流源電路、第一軌對軌放大器電路、第一反相器電路以及第二反相器電路。第一電流源電路耦接於操作電壓與第一節點之間,根據第一偏壓信號調整通過第一節點的操作電流。第二電流源電路耦接於第二節點與接地電壓之間,根據第二偏壓信號調整通過第二節點的接地電流。第一軌對軌放大器電路耦接於第一節點與第二節點之間。第一軌對軌放大器電路接收輸入信號,並將輸入信號與參考電壓進行比較,據以輸出放大信號。第一反相器電路與第一軌對軌放大器電路並接於第一節點與第二節點之間。第一反相器電路被配置為接收放大信號,且提供反相信號。第二反相器電路耦接於操作電壓與接地電壓之間。第二反相器電路被配置為根據反相信號產生輸出信號。The input receiver of the present invention includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit is coupled between the operating voltage and the first node, and adjusts the operating current passing through the first node according to the first bias signal. The second current source circuit is coupled between the second node and the ground voltage, and adjusts the ground current passing through the second node according to the second bias signal. The first rail-to-rail amplifier circuit is coupled between the first node and the second node. The first rail-to-rail amplifier circuit receives the input signal and compares the input signal with a reference voltage to output an amplified signal accordingly. The first inverter circuit and the first rail-to-rail amplifier circuit are connected in parallel between the first node and the second node. The first inverter circuit is configured to receive the amplified signal and provide an inverted signal. The second inverter circuit is coupled between the operating voltage and the ground voltage. The second inverter circuit is configured to generate an output signal based on the inverted signal.
基於上述,在本發明的輸入接收器中,反相器電路與軌對軌放大器電路並接於兩個節點之間。由於反相器電路可用以操作在與軌對軌放大器電路所輸出的放大信號相同的電壓擺幅,輸入接收器在高速的環境下也能正確地動作,並且同時兼顧操作速度與功耗。Based on the above, in the input receiver of the present invention, the inverter circuit and the rail-to-rail amplifier circuit are connected in parallel between two nodes. Since the inverter circuit can be used to operate at the same voltage swing as the amplified signal output by the rail-to-rail amplifier circuit, the input receiver operates correctly in high-speed environments, while compromising operating speed and power consumption.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.
圖1繪示本發明一實施例的輸入接收器的方塊示意圖,而圖2繪示圖1實施例的輸入接收器的電路示意圖。請同時參照圖1與圖2,輸入接收器100適用於DRAM及靜態隨機存取記憶體(Static Random Access Memory,SRAM)等揮發性記憶體元件、亦適用於快閃記憶體、相變化記憶體、電阻式記憶體等非揮發性記憶體元件或其他需要對輸入信號的邏輯準位進行判讀的電路元件。在本實施例中,輸入接收器100包括第一電流源電路110、第二電流源電路120、第一軌對軌放大器電路130、第一反相器電路140以及第二反相器電路150。FIG. 1 is a schematic block diagram of an input receiver according to an embodiment of the present invention, and FIG. 2 is a schematic circuit diagram of the input receiver according to the embodiment of FIG. 1 . Please refer to FIG. 1 and FIG. 2 at the same time, the
第一電流源電路110耦接於操作電壓VDD與第一節點ND1之間。第一電流源電路110可根據第一偏壓信號pbias調整通過第一節點ND1的操作電流IDD。如圖2所示,第一電流源電路110包括由電晶體PS1所構成的電流源,其根據第一偏壓信號pbias提供操作電流IDD。The first
第二電流源電路120耦接於第二節點ND2與接地電壓VSS之間。第二電流源電路120可根據第二偏壓信號nbias調整通過第二節點ND2的接地電流ISS。如圖2所示,第二電流源電路120包括由電晶體NS1所構成的電流源以及致能電晶體NE1。電晶體NS1根據第二偏壓信號nbias而提供接地電流ISS。致能電晶體NE1在第二節點ND2與接地電壓VSS之間的電路路徑上與電晶體NS1串接,並且根據致能信號En導通或斷開。致能信號En表示輸入接收器100是否被致能。舉例來說,當致能信號En為低邏輯準位時,致能電晶體NE1斷開,輸入接收器100無法運作。當致能信號En為高邏輯準位時,致能電晶體NE1導通,輸入接收器100即可進行運作。在本實施例中,致能電晶體NE1耦接於電晶體NS1與接地電壓VSS之間,而在另一實施例中,致能電晶體NE1亦可耦接於第二節點ND2與電晶體NS1之間,本發明並不依此為限。The second
第一軌對軌(Rail-to-Rail)放大器電路130耦接於第一節點ND1與第二節點ND2之間。第一軌對軌放大器電路130用以接收輸入信號IN,並將輸入信號IN與參考電壓VREF進行比較,據以輸出放大信號Rcv_n。The first rail-to-
第一軌對軌放大器電路130包括第一差動放大器電路132及第二差動放大器電路134。如圖2所示,第一差動放大器電路132及第二差動放大器電路134為互補電路組態,也就是說,P型場效電晶體與N型場效電晶體的配置方式彼此相反。The first rail-to-
更詳細來說,第一差動放大器電路132包括第一P型場效電晶體P1、第二P型場效電晶體P2、第一N型場效電晶體N1以及第二N型場效電晶體N2。第一P型場效電晶體P1與第二P型場效電晶體的第一端共通地耦接至第一節點ND1。第一P型場效電晶體P1的控制端接收輸入信號IN。第二P型場效電晶體P2的控制端接收參考電壓VREF。第一N型場效電晶體N1的第一端耦接第一P型場效電晶體P1的第二端。第二N型場效電晶體N2的第一端耦接第二P型場效電晶體P2的第二端。第二N型場效電晶體N2與第一N型場效電晶體N1的第二端共通地耦接至第二節點ND2。第一N型場效電晶體N1與第二N型場效電晶體N2的控制端共通地耦接至第二N型場效電晶體N2的第一端。其中,操作電壓VDD例如為1.5伏特,參考電壓VREF例如為操作電壓VDD的二分之一。In more detail, the first
第二差動放大器電路134包括第三P型場效電晶體P3、第四P型場效電晶體P4、第三N型場效電晶體N3以及第四N型場效電晶體N4。第三P型場效電晶體P3與第四P型場效電晶體P4的第一端共通地耦接至第一節點ND1。第三P型場效電晶體P3與第四P型場效電晶體P4的控制端共通地耦接至第三P型場效電晶體P3的第二端。第三P型場效電晶體P3的第二端耦接至第二N型場效電晶體N2的第一端。第四P型場效電晶體P4的第二端耦接第一N型場效電晶體N1的第一端。第三N型場效電晶體N3的第一端耦接第三P型場效電晶體P3的第二端。第三N型場效電晶體N3與第四N型場效電晶體N4的第二端共通地耦接至第二節點ND2。第三N型場效電晶體N3的控制端接收參考電壓VREF。第四N型場效電晶體的第一端耦接第四P型場效電晶體P4的第二端,並且在第四N型場效電晶體的第一端上可提供放大信號Rcv_n。第四N型場效電晶體N4的控制端接收輸入信號IN。The second
第一軌對軌放大器電路130可利用參考電壓VREF作為基準來檢測出輸入信號IN為高邏輯準位還是低邏輯準位。當輸入信號IN的電壓增加時,第一P型場效電晶體P1的導通電阻變大,第四N型場效電晶體N4的導通電阻變小,從而可拉低在第四N型場效電晶體N4的第一端上所提供的放大信號Rcv_n的電壓。The first rail-to-
另一方面,當參考電壓VREF的電壓增加時,第二P型場效電晶體P2的導通電阻變大,第三N型場效電晶體N3的導通電阻變小,從而使第一N型場效電晶體N1的控制端的電壓變小、第四P型場效電晶體P4的控制端的電壓變小。如此一來,可拉高在第四N型場效電晶體N4的第一端上所提供的放大信號Rcv_n的電壓。基於上述操作原理,當輸入信號IN大於參考電壓VREF時,放大信號Rcv_n的電壓會被拉低,以輸出作為低邏輯準位的放大信號Rcv_n。當輸入信號IN小於參考電壓VREF時,放大信號Rcv_n的電壓會被拉高,以輸出作為高邏輯準位的放大信號Rcv_n。On the other hand, when the voltage of the reference voltage VREF increases, the on-resistance of the second P-type field effect transistor P2 becomes large, and the on-resistance of the third N-type field effect transistor N3 becomes small, so that the first N-type field effect transistor N3 becomes small. The voltage of the control terminal of the effect transistor N1 is reduced, and the voltage of the control terminal of the fourth P-type field effect transistor P4 is reduced. In this way, the voltage of the amplified signal Rcv_n provided on the first end of the fourth N-type field effect transistor N4 can be pulled up. Based on the above operating principle, when the input signal IN is greater than the reference voltage VREF, the voltage of the amplified signal Rcv_n will be pulled down to output the amplified signal Rcv_n as a low logic level. When the input signal IN is lower than the reference voltage VREF, the voltage of the amplification signal Rcv_n will be pulled up to output the amplification signal Rcv_n as a high logic level.
第一反相器電路140例如為CMOS反相器,與第一軌對軌放大器電路130並接於第一節點ND1與第二節點ND2之間。第一反相器電路140的輸入端接收放大信號Rcv_n。第一反相器電路140的輸出端提供反相信號Rcv_t。The
第二反相器電路150也是例如為CMOS反相器。與第一反相器電路140不同的是,第二反相器電路150耦接於操作電壓VDD與接地電壓VSS之間。於本實施例中,第二反相器電路150接收反相信號Rcv_t,據以產生並輸出輸出信號OUT。輸出信號OUT的電壓擺幅範圍等於操作電壓VDD。The
在本發明的輸入接收器100中,放大信號Rcv_n以及反相信號Rcv_t的電壓擺幅範圍取決於第一節點ND1的電壓準位sp以及第二節點ND2的電壓準位sn(顯示於圖3中)。第一軌對軌放大器電路130可根據輸入信號IN產生與輸入信號IN相位相反而將電壓擺幅範圍放大至電壓準位sp與電壓準位sn之間的放大信號Rcv_n。第一反相器電路140可根據放大信號Rcv_n產生與輸入信號IN相位相同而將電壓擺幅範圍維持在電壓準位sp與電壓準位sn之間的反相信號Rcv_t。In the
圖3A至圖3E繪示本發明一實施例的輸入接收器的信號波形示意圖。請同時參照圖2及圖3A至圖3E,在本實施例中,如圖3A所示,輸入信號IN的佔空比(duty ratio)為50%,電壓準位sp與電壓準位sn的平均值維持在操作電壓VDD的二分之一(等同於參考電壓VREF)。在理想的情況下,如圖3B至圖3C所示,放大信號Rcv_n及反相信號Rcv_t的佔空比皆與輸入信號IN的佔空比相同。舉例來說,操作電壓VDD為1.5伏特,接地電壓VSS為0伏特,電壓準位sp為1.0伏特,電壓準位sn為0.5伏特,但本發明並不以此為限。3A to 3E are schematic diagrams of signal waveforms of an input receiver according to an embodiment of the present invention. Please refer to FIG. 2 and FIGS. 3A to 3E at the same time. In this embodiment, as shown in FIG. 3A , the duty ratio of the input signal IN is 50%, and the average of the voltage level sp and the voltage level sn The value is maintained at one-half the operating voltage VDD (equivalent to the reference voltage VREF). In an ideal situation, as shown in FIGS. 3B to 3C , the duty cycle of the amplified signal Rcv_n and the inverted signal Rcv_t is the same as the duty cycle of the input signal IN. For example, the operating voltage VDD is 1.5 volts, the ground voltage VSS is 0 volts, the voltage level sp is 1.0 volts, and the voltage level sn is 0.5 volts, but the invention is not limited thereto.
實際上,放大信號Rcv_n的準位上升時間與準位下降時間會取決於製程變異而不同。舉例來說,當製作出來的P型場效電晶體的臨界電壓較高,且N型場效電晶體的臨界電壓較低時,如圖3D所示,第一軌對軌放大器電路130所提供的放大信號Rcv_n的上升斜率變小,且下降斜率變大,從而導致放大信號Rcv_n的佔空比會小於50%,產生佔空比不均(duty broken)的情況。Actually, the level rise time and level fall time of the amplified signal Rcv_n may be different depending on the process variation. For example, when the threshold voltage of the fabricated P-type field effect transistor is high, and the threshold voltage of the N-type field effect transistor is low, as shown in FIG. 3D , the first rail-to-
於本實施例中,由於第一反相器電路140與第一軌對軌放大器電路130的製程條件相同,因此第一反相器電路140所提供的反相信號Rcv_t的斜率也會隨著放大信號Rcv_n變化。如圖3E所示,反相信號Rcv_t的下降斜率變大,反相信號Rcv_t的上升斜率變小,從而可以補償放大信號Rcv_n的佔空比減少的部分。如此一來,反相信號Rcv_t的佔空比又可以恢復成與輸入信號IN的佔空比相同的50%。In this embodiment, since the process conditions of the
之後,第二反相器電路150可根據反相信號Rcv_t產生與輸入信號IN相位相反而將電壓擺幅範圍放大至操作電壓VDD與接地電壓VSS之間的輸出信號OUT。基於上述,本發明實施例的輸入接收器100可採用與第一軌對軌放大器電路130並聯於第一節點ND1與第二節點ND2之間的第一反相器電路140來代替傳統設計中的分路電阻,藉此對放大信號Rcv_n的佔空比不均進行補償,從而在高速的環境下也能正確地動作。Afterwards, the
在本發明的輸入接收器100中,可以更包括偏壓信號產生器。偏壓信號產生器用以產生第一偏壓信號pbias以及第二偏壓信號nbias。藉由適當地配置第一偏壓信號pbias以及第二偏壓信號nbias,可將電壓準位sp與電壓準位sn的平均值維持在等於參考電壓VREF。In the
舉例來說,圖4繪示本發明一實施例的偏壓信號產生器的電路示意圖。在圖4中,偏壓信號產生器200包括第三電流源電路210、第四電流源電路220、第二軌對軌放大器電路230、第三反相器電路240以及運算放大器電路250。For example, FIG. 4 is a schematic circuit diagram of a bias signal generator according to an embodiment of the present invention. In FIG. 4 , the
第三電流源電路210耦接於操作電壓VDD與第三節點ND3之間。如圖4所示,第三電流源電路210包括電晶體PS2、電晶體PS3及電流源IS,以藉由由電晶體PS2、PS3所構成的電流鏡提供電流至第三節點ND3。第三電流源電路210可根據電流源IS所產生的電流提供第一偏壓信號pbias。The third
第四電流源電路220耦接於第四節點ND4與接地電壓VSS之間。第四電流源電路220可根據第二偏壓信號nbias調整通過第四節點ND4的電流。如圖4所示,第四電流源電路220包括由電晶體NS2所構成的電流源以及致能電晶體NE2。電晶體NS2根據第二偏壓信號nbias而提供通過第四節點ND4的電流。致能電晶體NE2在第四節點ND4與接地電壓VSS之間的電路路徑上與電晶體NS2串接,並且根據致能信號En導通或斷開。致能信號En表示偏壓信號產生器200是否被致能。舉例來說,當致能信號En為低邏輯準位時,致能電晶體NE2斷開,偏壓信號產生器200無法運作。當致能信號En為高邏輯準位時,致能電晶體NE2導通,偏壓信號產生器200即可進行運作。在本實施例中,致能電晶體NE2耦接於電晶體NS2與接地電壓VSS之間,而在另一實施例中,致能電晶體NE2亦可耦接於第四節點ND4與電晶體NS2之間,本發明並不依此為限。The fourth current source circuit 220 is coupled between the fourth node ND4 and the ground voltage VSS. The fourth current source circuit 220 may adjust the current through the fourth node ND4 according to the second bias signal nbias. As shown in FIG. 4 , the fourth current source circuit 220 includes a current source formed by a transistor NS2 and an enabling transistor NE2 . The transistor NS2 provides a current through the fourth node ND4 according to the second bias signal nbias. The enable transistor NE2 is connected in series with the transistor NS2 on the circuit path between the fourth node ND4 and the ground voltage VSS, and is turned on or off according to the enable signal En. The enable signal En indicates whether the
第二軌對軌放大器電路230耦接於第三節點ND3與第四節點ND4之間。第二軌對軌放大器電路230包括第三差動放大器電路232及第四差動放大器電路234。如圖4所示,第三差動放大器電路232及第四差動放大器電路234為互補電路組態。The second rail-to-
更詳細來說,第三差動放大器電路232包括第五P型場效電晶體P5、第六P型場效電晶體P6、第五N型場效電晶體N5以及第六N型場效電晶體N6。第三差動放大器電路232與第一差動放大器電路132幾乎相同,差別在於第三差動放大器電路232的第五P型場效電晶體P5的控制端接收參考電壓VREF。In more detail, the third
第四差動放大器電路234包括第七P型場效電晶體P7、第八P型場效電晶體P8、第七N型場效電晶體N7以及第八N型場效電晶體N8。第四差動放大器電路234與第二差動放大器電路134幾乎相同,差別在於第四差動放大器電路234的第八N型場效電晶體N8的控制端接收參考電壓VREF,並且第八N型場效電晶體N8的第一端提供比較信號CMP給運算放大器電路250及第五P型場效電晶體P5與第六P型場效電晶體P6之間的節點。基於上述電路的配置,第二軌對軌放大器電路230可根據參考電壓VREF輸出比較信號CMP至運算放大器電路250。The fourth
第三反相器電路240例如為CMOS反相器,與第二軌對軌放大器電路230並接於第三節點ND3與第四節點ND4之間。第三反相器電路240的輸入端也接收參考電壓VREF。The
運算放大器電路250的非反相輸入端接收參考電壓VREF。運算放大器電路250的反相輸入端接收比較信號CMP。運算放大器電路250的輸出端輸出第二偏壓信號nbias至第四電流源電路220。基於上述電路的配置,偏壓信號產生器200可產生適當的第一偏壓信號pbias以及第二偏壓信號nbias,以將電壓準位sp與電壓準位sn的平均值維持在參考電壓VREF。The non-inverting input of the
圖5繪示本發明另一實施例的輸入接收器的電路示意圖。在本實施例中,輸入接收器300包括第一電流源電路310、第二電流源電路320、第一軌對軌放大器電路330以及第一反相器電路340。上述元件的功能係與前述實施例中對應元件的功能相同或相似,故其詳細內容在此不再贅述。FIG. 5 is a schematic circuit diagram of an input receiver according to another embodiment of the present invention. In this embodiment, the
與上述實施例不同的是,在本實施例中,輸入接收器300在第二反相器電路360與第一反相器電路340之間更包括第四反相器電路350,且以第二反相器電路360取代第二反相器電路150。如圖5所示,第四反相器電路350包括第九P型場效電晶體P9、第十P型場效電晶體P10、第九N型場效電晶體N9以及第十N型場效電晶體N10。第九P型場效電晶體P9的第一端接收操作電壓VDD。第九P型場效電晶體P9的控制端接收接地電壓VSS。第十P型場效電晶體P10的第一端耦接第九P型場效電晶體P9的第二端。第十P型場效電晶體P10的第二端提供中間信號INT。第十P型場效電晶體控制端接收反相信號Rcv_t。第九N型場效電晶體N9的第一端耦接第十P型場效電晶體P10的第二端。第九N型場效電晶體N9的控制端接收反相信號Rcv_t。第十N型場效電晶體N10的第一端耦接第九N型場效電晶體N9第二端。第十N型場效電晶體N10的第二端耦接至接地電壓VSS。第十N型場效電晶體N10的控制端接收操作電壓VDD。Different from the above embodiment, in this embodiment, the
如圖5所示,第二反相器電路360包括第十一P型場效電晶體P11、第十二P型場效電晶體P12、第十一N型場效電晶體N11以及第十二N型場效電晶體N12。第十一P型場效電晶體P11的第一端接收操作電壓VDD。第十一P型場效電晶體P11的控制端耦接第二節點ND2。第十二P型場效電晶體P12的第一端耦接第十一P型場效電晶體P11的第二端。第十二P型場效電晶體P12的第二端提供輸出信號OUT。第十二P型場效電晶體的控制端接收中間信號INT。第十一N型場效電晶體N11的第一端耦接第十二P型場效電晶體N12的第二端。第十一N型場效電晶體N11的控制端接收中間信號INT。第十二N型場效電晶體N12的第一端耦接第十一N型場效電晶體N11的第二端。第十二N型場效電晶體N12的第二端耦接至接地電壓VSS。第十二N型場效電晶體N12的控制端耦接第一節點ND1。基於上述,本發明實施例的輸入接收器300新增了第四反相器電路350。如此一來,反相器電路結構又增加了一級,藉此獲得更好的性能。此外,用以提供輸出信號OUT的第二反相器電路360更受控於第二節點ND2以及第一節點ND1的電壓,可降低其電壓擺幅。As shown in FIG. 5 , the
綜上所述,在本發明的輸入接收器中,反相器電路與軌對軌放大器電路並接於兩個節點之間。反相器電路可用以對軌對軌放大器電路所輸出的放大信號進行補償,以使反相器電路所輸出反相信號的佔空比可以恢復成與輸入至軌對軌放大器電路的信號的佔空比相同。藉此,可使輸入接收器在高速的環境下也能正確地動作,並且同時兼顧操作速度與功耗。To sum up, in the input receiver of the present invention, the inverter circuit and the rail-to-rail amplifier circuit are connected in parallel between two nodes. The inverter circuit can be used to compensate the amplified signal output by the rail-to-rail amplifier circuit, so that the duty cycle of the inverted signal output by the inverter circuit can be restored to the duty cycle of the signal input to the rail-to-rail amplifier circuit. Empty ratio is the same. Thereby, the input receiver can be operated correctly even in a high-speed environment, and both the operation speed and the power consumption can be taken into consideration.
100、300:輸入接收器
110、310:第一電流源電路
120、320:第二電流源電路
130、330:第一軌對軌放大器電路
132:第一差動放大器電路
134:第二差動放大器電路
140、340:第一反相器電路
150、360:第二反相器電路
200:偏壓信號產生器
210:第三電流源電路
220:第四電流源電路
230:第二軌對軌放大器電路
232:第三差動放大器電路
234:第四差動放大器電路
240:第三反相器電路
250:運算放大器電路
350:第四反相器電路
CMP:比較信號
IDD:操作電流
IN:輸入信號
INT:中間信號
IS:電流源
ISS: 接地電流
N1~N12:第一~第十二N型場效電晶體
ND1:第一節點
ND2:第二節點
ND3:第三節點
ND4:第四節點
NE1、NE2:致能電晶體
NS1~NS2、PS1~PS3:電晶體
nbias:第二偏壓信號
OUT:輸出信號
P1~P12:第一~第十二P型場效電晶體
pbias:第一偏壓信號
Rcv_n:放大信號
Rcv_t:反相信號
sn、sp:電壓準位
VDD:操作電壓
VREF:參考電壓
VSS:接地電壓100, 300:
圖1繪示本發明一實施例的輸入接收器的方塊示意圖。 圖2繪示圖1實施例的輸入接收器的電路示意圖。 圖3A至圖3E繪示本發明一實施例的輸入接收器的信號波形示意圖。 圖4繪示本發明一實施例的偏壓信號產生器的電路示意圖。 圖5繪示本發明另一實施例的輸入接收器的電路示意圖。FIG. 1 is a block diagram illustrating an input receiver according to an embodiment of the present invention. FIG. 2 is a schematic circuit diagram of the input receiver of the embodiment of FIG. 1 . 3A to 3E are schematic diagrams of signal waveforms of an input receiver according to an embodiment of the present invention. FIG. 4 is a schematic circuit diagram of a bias signal generator according to an embodiment of the present invention. FIG. 5 is a schematic circuit diagram of an input receiver according to another embodiment of the present invention.
100:輸入接收器100: Input receiver
110:第一電流源電路110: The first current source circuit
120:第二電流源電路120: Second current source circuit
130:第一軌對軌放大器電路130: First Rail-to-Rail Amplifier Circuit
140:第一反相器電路140: First inverter circuit
150:第二反相器電路150: Second inverter circuit
IDD:操作電流IDD: operating current
IN:輸入信號IN: input signal
ISS:接地電流ISS: Earth Current
ND1:第一節點ND1: first node
ND2:第一節點ND2: first node
nbias:第二偏壓信號nbias: the second bias signal
OUT:輸出信號OUT: output signal
pbias:第一偏壓信號pbias: first bias signal
Rcv_n:放大信號Rcv_n: Amplified signal
Rcv_t:反相信號Rcv_t: inverted signal
VDD:操作電壓VDD: operating voltage
VREF:參考電壓VREF: reference voltage
VSS:接地電壓VSS: ground voltage
Claims (12)
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US7558125B2 (en) * | 2006-12-15 | 2009-07-07 | Micron Technology, Inc. | Input buffer and method with AC positive feedback, and a memory device and computer system using same |
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