KR20180026835A - Input circuit and semiconductor device the same - Google Patents

Abstract

The present technology relates to an input circuit. The input circuit includes a first buffer part driven in response to an enable signal and an internal bias, compares a reference voltage and an external signal, and generates a first comparison signal and a second comparison signal; and a second buffer part which generates the internal bias, is driven in response to the enable signal and the internal bias, compares the reference voltage and the external signal, and generates the first comparison signal and the second comparison signal. The current of the first buffer part and the threshold voltage and the current of the second buffer part may be adjusted according to the internal bias. Accordingly, the threshold voltage and current of the input circuit can be optimized according to changes in the reference voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit and a semiconductor device including the input circuit.

This patent document relates to semiconductor design techniques, and more specifically to an input circuit and a semiconductor device including the same.

A semiconductor device uses an input circuit as an interface for converting a signal applied from the outside into a usable level in an internal circuit.

The input circuit may be provided at an input terminal such as an address, data, a clock signal, a control signal, or the like. The input circuit can be designed in consideration of the operating voltage of the semiconductor device, the reference voltage level, and the swing width of the input signal.

Further, the input circuit is operated by a current source which is generated based on the operating voltage. The input circuit must be capable of outputting a desired level irrespective of changes in operating conditions such as a change in the level of an externally applied signal, an operation voltage or a change in a reference voltage level.

1 is a diagram illustrating an input circuit included in a semiconductor device according to a related art.

1, a differential amplifier 110 for generating first and second output signals OIN and OREF by differentially amplifying an input signal IN and a reference voltage VREF and a differential amplifier 110 for generating first and second output signals OIN and OREF, And a current sink unit 120 for controlling the amount of current flowing.

This type of input is called a pseudo-differential input. The input signals IN and VREF of the differential type can have an asymmetric waveform because the reference voltage VREF does not swing and the output signals OREF and OIN of the receiving buffer circuit also have asymmetric waveforms I have.

The differential amplifier 110 includes a first resistance element R1 between a power supply voltage VDD and a second output node OREF and a second resistance element between the power voltage VDD and the first output node OIN A first NMOS transistor N1 and a reference voltage VREF for forming a current path between the second output node OREF and the common node COMN in response to the input signal IN, And a second NMOS transistor N2 for generating a current path between the first output node OIN and the common node COMN in response.

The current sink unit 120 may include a third NMOS transistor N3 connected between the common mode COMN and the ground voltage VSS.

The current sink unit 120 adjusts the amount of current sinking from the differential amplifier 110 to the ground voltage VSS in response to the enable signal EN to control the amount of current flowing to the differential amplifier 110 can do.

On the other hand, a termination scheme is applied to a receiving buffer circuit for signal transmission in order to speed up signal transmission. The termination scheme can be divided into a center tap termination (CTT) and a high tap termination (HTT).

Here, the center tap termination is a method of increasing or decreasing the level of the signal to be transmitted by a predetermined level based on the voltage level corresponding to half of the power supply voltage, and the high tap termination is a method of reducing the level of the signal to be transmitted by a certain level .

When the center tap termination scheme is applied to the receiving buffer circuit, no problem occurs. However, when the high tap termination scheme is applied to the receiving buffer circuit, There is a possibility of occurrence. As the reference voltage VREF changes, the first resistive element Rl and the second resistive element R2 must be reduced in size in order to operate in a region where the level of the reference voltage VREF is high. In such a case, It may be difficult to obtain a high gain. In other words, under the high-tab termination condition, since the reference voltage VREF changes, a period in which the first and second output signals OIN and OREF are not normally output may occur, and the reference voltage VREF may be high Level, it may be difficult to secure a high gain.

A problem to be solved by embodiments of the present invention is to provide a semiconductor device capable of optimizing a threshold voltage and an amount of current of an input circuit in accordance with a change in a reference voltage.

An input circuit according to an embodiment of the present invention includes a first buffer unit driven in response to an enable signal and an internal bias to generate a first comparison signal and a second comparison signal by comparing a reference voltage and an external signal; And a second buffer unit for generating the internal bias and being driven in response to the enable signal and the internal bias to generate the first comparison signal and the second comparison signal by comparing the reference voltage and the external signal The amount of current of the first buffer unit and the threshold voltage and current of the second buffer unit may be adjusted according to the internal bias.

Preferably, the first buffer unit includes: a current source unit for receiving a power supply voltage in response to the internal bias and supplying a source current to the output node; A comparator for comparing the reference voltage with the external signal to generate the first and second comparison signals; And a sync unit driven in response to the enable signal.

Advantageously, the current source portion includes first and second PMOS transistors for receiving the internal bias at a gate input, and may optimize an amount of current passing through the first and second PMOS transistors.

Preferably, the second buffer unit comprises: a sink unit driven in response to the enable signal; A comparator for receiving the internal bias as a body bias and for comparing the reference voltage and the external signal to generate the first and second comparison signals; And a bias generator for generating the internal bias.

Preferably, the comparator may include third and fourth PMOS transistors receiving the internal bias as a body bias, and may adjust a threshold voltage of the third and fourth PMOS transistors.

A semiconductor device according to an embodiment of the present invention includes: an input circuit for receiving an external signal and generating an internal signal; And an internal circuit operable to receive the internal signal, wherein the input circuit is driven in response to an enable signal and an internal bias to generate a first comparison signal and a second comparison signal by comparing a reference voltage and an external signal, A first buffer unit for buffering data; And a second buffer unit for generating the internal bias and being driven in response to the enable signal and the internal bias to generate the first comparison signal and the second comparison signal by comparing the reference voltage and the external signal The amount of current of the first buffer unit and the threshold voltage and current of the second buffer unit may be adjusted according to the internal bias.

According to the input circuit and the semiconductor device according to the embodiments of the present invention, since the self-bias is internally generated according to the supply voltage even when the reference voltage changes, the threshold voltage and the current amount of the buffer circuit can be optimized, can do.

1 is a diagram illustrating an input circuit included in a semiconductor device according to a related art.
2 is a configuration diagram illustrating an input circuit according to an embodiment of the present invention.
3 is a circuit diagram showing the input circuit shown in Fig.
4 is a configuration diagram showing a semiconductor device according to an embodiment of the present invention.
5 is a configuration diagram showing a semiconductor device according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It is provided to fully inform the category.

2 is a block diagram showing an input circuit 20 according to an embodiment of the present invention.

Referring to FIG. 2, the input circuit 20 may include a first buffer unit 210 and a second buffer unit 230. The first and second buffer units 210 and 220 operate according to an enable signal EN and an internal bias VBIAS and receive an internal signal (not shown) by receiving a reference voltage VREF and an external signal IN, Lt; / RTI > Here, the enable signal EN may be used as a signal for driving the sink current of the first and second buffer units 210 and 220, and the internal bias VBIAS may be applied to the first and second buffer units 210 and 210 And 220, respectively. The reference voltage VREF may be supplied from inside the semiconductor device or from outside the semiconductor device. For example, the reference voltage VREF may vary from 0.7 VDD to 0.9 VDD of the external power supply voltage VDD according to the operating environment.

The first buffer unit 210 is driven according to an enable signal EN and an internal bias VBIAS and receives a reference voltage VREF and an external signal IN to generate a first comparison signal (not shown) A comparison signal (not shown) can be generated.

The second buffer unit 220 is driven according to an enable signal EN and an internal bias VBIAS and receives a reference voltage VREF and an external signal IN to generate a first comparison signal and a second comparison signal can do. The second buffer unit 220 may include a bias generation unit 221 for generating an internal bias VBIAS. Here, the internal bias VBIAS is proportional to the power supply voltage VDD and may be inversely proportional to the reference voltage VREF. The internal bias VBIAS may be related to the threshold voltage of the comparator (not shown) May be inversely proportional.

The internal bias VBIAS is controlled in accordance with the voltage level of the power supply voltage VDD even when the reference voltage VREF is changed so that the amount of current of the current source unit (not shown) provided in the first buffer unit 210, It is possible to optimize the threshold voltage of the input transistor (not shown) constituting the comparator (not shown) in the buffer unit 220 and the amount of current of the active load (not shown).

Fig. 3 is a circuit diagram showing the input circuit 20 shown in Fig.

Referring to FIG. 3, the input circuit 20 may include a first buffer unit 310 and a second buffer unit 320.

The first buffer unit 310 is driven in response to the internal bias VBIAS and the enable signal EN and compares the reference voltage VREF with the external signal IN to generate a first comparison signal OREF, And may be configured to generate a comparison signal OIN.

The first buffer unit 310 may include a current source unit 311, a comparing unit 312, and a sink unit 313.

The current source unit 311 may include a first PMOS transistor P1 and a second PMOS transistor P2.

The first PMOS transistor P1 is driven in response to the internal bias VBIAS and may be configured to receive the supply voltage VDD and supply the source current to the first comparison signal OREF output node. The second PMOS transistor P2 is driven in response to the internal bias VBIAS and may be configured to receive the supply voltage VDD and supply the source current to the second comparison signal OIN output node.

On the other hand, the current source unit 311 may be an active load.

The comparator 312 may include a fourth NMOS transistor N4 and a fifth NMOS transistor N5.

The fourth NMOS transistor N4 may be connected between the output node of the first comparison signal OREF and the sink unit 313 and receive the external signal IN. The fifth NMOS transistor N5 may be connected between the second comparison signal OIN output node and the sink unit 313 and configured to receive the reference voltage VREF.

The sink section 313 may include a sixth NMOS transistor N6 connected between the comparing section 312 and an end of the ground voltage VSS and driven in response to the enable signal EN. That is, the sink unit 313 is configured to operate with the enable signal EN as a sink current.

When the input circuit 20 is enabled, for example, when the enable signal EN is enabled to the high level, the sixth NMOS transistor N6 constituting the sync section 313 can be turned on. The internal bias VBIAS may be internally generated through the second buffer unit 320 to be described later and the internal bias VBIAS may be generated by the first and second PMOS transistors 311, P1, and P2, respectively. Therefore, the current source unit 311 and the sink unit 313 constituting the first buffer unit 310 operate normally regardless of the fluctuation of the external environment and the decrease of the operating voltage, so that the reference voltage VREF and the external signal IN) to generate the first and second comparison signals OREF and OIN.

The first buffer unit 310 outputs the level of the second comparison signal OIN to a level higher than the level of the first comparison signal OREF when the level of the external signal IN is higher than the level of the reference voltage VREF can do. The level of the second comparison signal OIN is lower than the level of the first comparison signal OREF when the level of the external signal IN is lower than the level of the reference voltage VREF Level output.

Meanwhile, since the first buffer unit 310 changes the internal resistance (VBIAS) according to the external environment such as voltage, temperature, and process change by changing the existing resistance load to the PMOS load operated by the internal bias (VBIAS) And the amount of current passing through the second PMOS transistor (P1, P2) can be optimized according to the situation.

The second buffer unit 320 may include a source unit 321_1, a sink unit 321_2, a comparator 322, a bias generator 323, and an active load 324.

The source portion 321_1 and the sink portion 321_2 are configured to operate with the inverted enable signal ENB and the enable signal EN as a sink current, respectively. The source portion 321_1 may include a third PMOS transistor P3 connected between the power supply voltage VDD and the comparator 322 and receiving the inverted enable signal ENB. The sink section 321_2 may include an eighth NMOS transistor N8 connected between the active load 324 and an end of the ground voltage VSS and receiving the enable signal EN.

When the input circuit 20 is enabled, for example, when the enable signal EN becomes a high level, the inverted enable signal ENB may be at a low level, thereby causing the source portion 321_1, The third PMOS transistor P3 and the ninth NMOS transistor N9 constituting the NMOS transistor 321_2 may be turned on.

The second buffer unit 320 outputs the level of the second comparison signal OIN to a level higher than the level of the first comparison signal OREF when the level of the external signal IN is higher than the level of the reference voltage VREF can do. The level of the second comparison signal OIN is lower than the level of the first comparison signal OREF when the level of the external signal IN is lower than the level of the reference voltage VREF Level output.

The comparator 322 may include a fourth PMOS transistor P4 and a fifth PMOS transistor P5.

The fourth PMOS transistor P4 may be connected between the source portion 321_1 and the first comparison signal OREF and configured to receive the external signal IN. The fifth PMOS transistor P5 may be connected between the source portion 321_1 and the second comparison signal OIN and configured to receive the reference voltage VREF.

Meanwhile, the comparator 322 may receive the internal bias VBIAS as a body bias.

The third and fourth resistors R3 and R4 may include a third resistor R3 and a fourth resistor R4 and the third resistor R3 and the fourth resistor R4 may include first and second comparison signals OREF, OIN) output node to generate an internal bias VBIAS by dividing the voltage across the first and second comparison signals OREF and OIN. Here, the internal bias VBIAS may be in a proportional relationship in which the voltage level of the power source voltage VDD rises as the voltage level of the power source voltage VDD increases, and may be in inverse proportion to the voltage level of the reference voltage VREF, And may be proportional to the threshold voltage across the fourth and fifth PMOS transistors P4 and P5 constituting the comparator 322. [

That is, when the driving voltage, that is, the power source voltage VDD is sufficiently high, the internal bias VBIAS becomes sufficiently high and the body biases of the fourth and fifth PMOS transistors P4 and P5 constituting the comparator 320 are high, 4 and the fifth PMOS transistors P4 and P5 are also increased, so that normal operation can be performed.

In contrast, when the power supply voltage VDD is sufficiently low, the internal bias VBIAS becomes sufficiently low, and the body biases of the fourth and fifth PMOS transistors P4 and P5 constituting the comparator 322 become low, The threshold voltages of the five PMOS transistors P4 and P5 also become low. In other words, even if the driving voltage, that is, the power supply voltage VDD is at a low level and the reference voltage VREF is at a high level, the circuit of the second buffer unit 320 can operate normally.

In summary, when the voltage level of the power supply voltage VDD is low, the reference voltage VREF may be high. In this case, by adjusting the PMOS load, that is, the body bias of the comparator 322, It is possible to control the transistors P4 and P5 to be driven so as to widen the operation region thereof.

The active load 324 may include a seventh NMOS transistor N7 and an eighth NMOS transistor N8. Each of the seventh and eighth NMOS transistors N7 and N8 may be connected between the bias generator 323 and the sink 321_2 and may be driven by receiving the internal bias VBIAS. On the other hand, the active load 324 can perform the current sink operation.

The enable signal EN, the external signal IN and the reference voltage VREF input to the first buffer unit 310 and the second buffer unit 320 are the same signal and the first comparison signal OREF, And the second comparison signal OIN may also be the same signal output to the same node.

4 is a configuration diagram of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, the semiconductor device may include an input circuit 410 and an internal circuit 420.

The input circuit 410 may generate the internal signal OUT by receiving the external signal IN.

The internal circuit 420 may receive the internal signal OUT and perform a desired operation. Where the internal circuitry 420 may comprise a semiconductor memory device. The semiconductor memory device may be a volatile memory device such as a DRAM, or a non-volatile memory device such as a FLASH memory or a resistive memory.

As the input circuit 410, the input circuit described in Figs. 2 and 3 may be used. That is, the input circuit 410 self-generates and uses the internal bias VBIAS optimized for the corresponding situation even if the reference voltage VREF changes, so that the amount of current passing through the PMOS load of the N type 310 is adjusted And optimize the threshold voltage of the input PMOS transistor of the P-type 320. In this case, That is, even if the reference voltage is changed, the optimum buffer circuit corresponding to the change in the reference voltage can be operated to ensure the reliability of the semiconductor device.

5 is a configuration diagram of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 5, the semiconductor device may include a controller 510 and a memory device 520.

The memory device 520 may include an input circuit 521 and a memory core 522 and the memory core 522 may include a memory cell array 522_1. The memory device 520 may be, but is not limited to, a volatile memory device such as a DRAM, or a non-volatile memory device such as flash memory, resistive memory.

The memory core 522 may include various components, not shown, that can write and read data to the memory cell array 522_1. For example, the memory core 522 may include an address decoder, a write circuit portion, and a read circuit portion.

The memory device 520 may receive a clock signal CLK, a command CMD, an address ADD and data (DATA) from the controller 510, (DATA) stored in the memory 522_1 to the controller 510.

The input circuit 521 includes a clock buffer 521_1 for converting the clock signal CLK provided from the controller 510 into an internal clock signal, a command buffer 521_2 for converting the command CMD into an internal command, An address buffer 521_3 for converting address ADD into an internal address, a data buffer 521_4 for converting data DATA into internal data, and the like.

Each or at least one of the buffers such as the clock buffer 521_1, the command buffer 521_2, the address buffer 521_3, and the data buffer 521_4 can be configured using the input circuit described with reference to FIGS.

Therefore, each or at least one of the buffers such as the clock buffer 521_1, the command buffer 521_2, the address buffer 521_3, and the data buffer 521_4 constituting the input circuit 521 is in a state Type input PMOS transistor can be optimized by optimizing the amount of current passing through the N-type PMOS load in accordance with the situation and by optimizing the threshold voltage of the P-type input PMOS transistor by using an internal bias (VBIAS) . ≪ / RTI > In other words, even if the reference voltage is changed, the optimum buffer circuit corresponding to the change in the reference voltage can be operated to ensure the reliability of the semiconductor device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Will be clear to those who have knowledge of.

210: a first buffer unit
220: second buffer unit
221:

Claims (14)

A first buffer unit driven in response to an enable signal and an internal bias to generate a first comparison signal and a second comparison signal by comparing a reference voltage and an external signal; And
And a second buffer for generating the internal bias and generating the first comparison signal and the second comparison signal by being driven in response to the enable signal and the internal bias to compare the reference voltage and the external signal However,
Wherein an amount of current of the first buffer unit and a threshold voltage and an amount of current of the second buffer unit are adjusted according to the internal bias.
The method according to claim 1,
Wherein the first buffer unit comprises:
A current source unit for receiving a power supply voltage in response to the internal bias and supplying a source current to an output node;
A comparator for comparing the reference voltage with the external signal to generate the first and second comparison signals; And
And a sink unit driven in response to the enable signal,
/ RTI >
3. The method of claim 2,
Wherein the current source portion includes first and second PMOS transistors for receiving the internal bias at a gate input, and wherein the input circuitry optimizes an amount of current passing through the first and second PMOS transistors.
The method according to claim 1,
Wherein the second buffer unit comprises:
A sink unit driven in response to the enable signal;
A comparator for receiving the internal bias as a body bias and for comparing the reference voltage and the external signal to generate the first and second comparison signals; And
A bias generator for generating the internal bias,
/ RTI >
5. The method of claim 4,
Wherein,
And third and fourth PMOS transistors receiving the internal bias with a body bias, wherein the threshold voltages of the third and fourth PMOS transistors are adjusted.
5. The method of claim 4,
Wherein the bias generator comprises:
And a first and a second resistor connected between the first and second comparison signal output nodes to divide the voltage of the output node to generate the internal bias.
The method according to claim 1,
Wherein each of the first and second buffer units comprises:
Wherein the first comparison signal has a lower level than the second comparison signal when the level of the external signal is higher than the level of the reference voltage.
The method according to claim 1,
Wherein each of the first and second buffer units comprises:
Wherein the first comparison signal has a higher level than the second comparison signal when the level of the external signal is lower than the level of the reference voltage.
An input circuit for receiving an external signal and generating an internal signal; And
And an internal circuit that operates by receiving the internal signal,
Wherein the input circuit comprises:
A first buffer unit driven in response to an enable signal and an internal bias to generate a first comparison signal and a second comparison signal by comparing a reference voltage and an external signal; And
And a second buffer for generating the internal bias and generating the first comparison signal and the second comparison signal by being driven in response to the enable signal and the internal bias to compare the reference voltage and the external signal However,
Wherein a current amount of the first buffer portion and a threshold voltage and an amount of current of the second buffer portion are adjusted according to the internal bias.
10. The method of claim 9,
Wherein the first buffer unit comprises:
A current source unit for receiving a power supply voltage in response to the internal bias and supplying a source current to an output node;
A comparator for comparing the reference voltage with the external signal to generate the first and second comparison signals; And
A sink unit for driving the enable signal as a sink current;
.
11. The method of claim 10,
Wherein the current source portion includes first and second PMOS transistors for receiving the internal bias at a gate input and for optimizing an amount of current passing through the first and second PMOS transistors.
10. The method of claim 9,
Wherein the second buffer unit comprises:
A sink unit for driving the enable signal as a sink current;
A comparator for receiving the internal bias at the body body ground and for comparing the reference voltage with the external signal to generate the first and second comparison signals; And
A bias generator for generating the internal bias,
.
13. The method of claim 12,
And third and fourth PMOS transistors receiving the internal bias with a body bias, wherein the threshold voltages of the third and fourth PMOS transistors are adjusted.
13. The method of claim 12,
Wherein the bias generator comprises:
And first and second resistors connected between the first and second comparison signal output nodes to divide the voltage of the output node to generate the internal bias.

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