TW202201268A - Fingerprint collection module circuit, chip and electronic device - Google Patents

Abstract

The present application provides a fingerprint collection circuit, a fingerprint collection chip and an electronic device. The fingerprint acquisition circuit includes a pixel array sensing circuit and an amplification circuit. The pixel array sensing circuit includes a number of pixel circuits. Each of the pixel circuit includes a first metal layer, a second metal layer, a third metal layer, and a substrate layer. The first metal layer is used to detect user’s fingerprint information. The second metal layer and the third metal layer are set between the first metal layer and the substrate layer, and a total projection of the second metal layer and the third metal layer on the substrate layer covers the projection of the first metal layer on substrate layer, thus isolating the first metal layer from the substrate layer. When touched by the finger, the first metal layer generates a fingerprint signal, and the amplification circuit enlarges the fingerprint signal. The present application can improve accuracy of fingerprint signal detection.

Description

Fingerprint collection circuit, chip and electronic equipment

The present application relates to the field of wireless communication technologies, and in particular, to a fingerprint collection circuit, a chip and an electronic device having a fingerprint collection chip.

The previous fingerprint acquisition circuit structure is complex, and the fingerprint signal is easily interfered by external signals, which affects the accuracy of sensing. For example, there is a parasitic capacitance between the metal layer and the substrate layer of the fingerprint collecting circuit in the fingerprint collecting circuit, which will affect the accuracy of the fingerprint signal sensing by the fingerprint collecting circuit. In addition, when the existing fingerprint acquisition circuit uses a high-gain amplifier to amplify the fingerprint signal, the sensitivity is not high.

In view of this, a fingerprint collection circuit and electronic device are provided to improve the detection accuracy of fingerprint signals.

An embodiment of the present application provides a fingerprint acquisition circuit, which includes a graphic element array sensing circuit and an amplifying circuit that are connected to each other. The graphic element array sensing circuit includes a plurality of graphic element circuits, and each graphic element circuit includes a first metal layer, a second A metal layer, a third metal layer, and a substrate layer, the first metal layer is used for detecting fingerprints, and the second metal layer and the third metal layer are disposed on the first metal layer and the substrate Between the bottom layers, the projection of the second metal layer and the third metal layer on the substrate layer covers the projection of the first metal layer on the substrate layer, so as to isolate the first metal layer from the substrate layer. After the layer is touched by a finger, a fingerprint signal is generated, and the amplifying circuit is used for amplifying the fingerprint signal.

In some embodiments of the present application, the picture element array sensing circuit includes a first switch group and a second switch group, and the first switch group includes a first sub-switch, a second sub-switch, and a third sub-switch, so The second switch group includes a first sub-switch, a second sub-switch, and a third sub-switch, the first metal layer is connected to the second metal layer, and the second metal layer is connected by the first switch group The first sub-switch is connected to the power supply voltage and is connected to the ground terminal through the first sub-switch of the second switch group, the first metal layer is connected to the third metal layer, and the third metal layer is The second sub-switch of the first switch group is connected to the power supply voltage and the second sub-switch of the second switch group is connected to the first reference voltage, and the first metal layer is connected to the first reference voltage through the second sub-switch of the second switch group. The third sub-switch of a switch group is connected to the power supply voltage and is connected to the amplifier circuit through the third sub-switch of the second switch group.

In some embodiments of the present application, the amplifying circuit includes an operational amplifier and a feedback loop, the operational amplifier includes a non-inverting input terminal, an inverting input terminal and an output terminal, the non-inverting input terminal and the first reference voltage In connection, the output voltage of the output terminal is adjusted by adjusting the first reference voltage.

In some embodiments of the present application, the resistor is connected to the inverting input terminal through the second sub-switch of the second switch group, and the output terminal is connected to the inverting terminal through the feedback loop. input connection.

In some embodiments of the present application, the feedback loop includes a feedback capacitor, a third switch group and a fourth switch group, and the upper plate of the feedback capacitor is connected to the first sub-switch of the third switch group through the first sub-switch of the third switch group. The second reference voltage is connected, the lower plate of the feedback capacitor is connected to the power supply voltage through the second sub-switch of the third switch group, and the upper plate of the feedback capacitor is connected through the fourth switch group The first sub-switch is connected to the reverse input terminal, the lower plate of the feedback capacitor is connected to the output terminal through the second sub-switch of the fourth switch group, and the reverse input terminal is connected by The third sub-switch of the third switch group is connected to the output end.

In some embodiments of the present application, the fingerprint collection circuit further includes a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit provides the first reference voltage and the second reference voltage.

In some embodiments of the present application, the fingerprint collection circuit provides a first timing control signal, a second timing control signal, a third timing control signal and a fourth timing control signal, the first timing control signal and the The second timing control signal is a clock signal with a phase difference of 180 ^° , the third timing control signal Φ1 and the fourth timing control signal Φ2 are non-overlapping clock signals with a phase difference of 180 ^° , and the first timing The control signal is used to control the opening and closing and closing of the first sub-switch, the second sub-switch and the third sub-switch of the third switch group, and the second timing control signal is used to control the first sub-switch of the fourth switch group. The opening and closing and closing of a sub-switch and the second sub-switch, the third timing control signal is used to control the opening and closing and closing of the first sub-switch, the second sub-switch and the third sub-switch of the first switch group , the fourth timing control signal is used to control the opening, closing and closing of the first sub-switch, the second sub-switch and the third sub-switch of the second switch group.

In some embodiments of the present application, the working steps of the fingerprint collection circuit are:

(a) Initial stage; the first timing control signal is at a high level, the second timing control signal is at a low level, and the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are at the same time is turned on, the first sub-switch and the second sub-switch of the fourth switch group are simultaneously disconnected;

(b) Scanning stage: the first timing control signal is at a low level, the second timing control signal is at a high level, and the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group The sub-switches are turned off at the same time, and the first sub-switch and the second sub-switch of the fourth switch group are turned on at the same time;

(c) Precharge stage: the third timing control signal is high, the first sub-switch, the second sub-switch, and the third sub-switch of the first switch group are turned on at the same time, and the fourth timing control signal is low level, the first sub-switch, the second sub-switch, and the third sub-switch of the second switch group are turned off simultaneously;

(d) In the charge transfer stage, the third timing control signal changes from a high level to a low level, and the first sub-switch, the second sub-switch, and the third sub-switch of the first switch group are turned off at the same time, so the The fourth timing control signal changes from a low level to a high level, and the first sub-switch, the second sub-switch and the third sub-switch of the second switch group are turned on at the same time.

In some embodiments of the present application, the fingerprint acquisition circuit further includes an analog-to-digital conversion circuit, the primitive array sensing circuit performs one fingerprint sampling, and the analog-to-digital conversion circuit performs multiple analog-to-digital conversions; The element array sensing circuit performs multiple sampling, and the analog-to-digital conversion circuit performs one analog-to-digital conversion; or the image element array sensing circuit performs multiple sampling, and the analog-to-digital conversion circuit performs multiple analog-to-digital conversions.

Embodiments of the present application further provide a fingerprint chip, which integrates the fingerprint collection circuit provided above.

The embodiment of the present application further provides an electronic device, and the electronic device adopts the fingerprint chip provided above.

In the present application, the second metal layer and the third metal layer are arranged between the first metal layer and the substrate layer to isolate the first metal layer from the substrate layer, thereby reducing the generation of parasitic capacitance between the first metal layer and the substrate layer , which improves the detection accuracy of fingerprint signals.

In order to more clearly understand the above objects, features and advantages of the embodiments of the present application, the present application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the features in the embodiments of the present application may be combined with each other unless there is conflict.

In the following description, many specific details are set forth in order to fully understand the embodiments of the present application, and the described embodiments are a part of the embodiments of the present application, but not all of the embodiments.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field belonging to the embodiments of the present application. The terms used in the specification of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application.

Please refer to FIG. 1 , which shows a system frame of a fingerprint collection circuit 1 in an embodiment of the present application. In this embodiment, the fingerprint collection circuit 1 includes a digital-to-analog conversion circuit 11 , a picture element array sensing circuit 12 , an amplification circuit 13 , a buffer 14 and an analog-to-digital conversion circuit 15 . The digital-to-analog conversion circuit 11 is connected to the picture element array sensing circuit 12 for providing a reference voltage for the picture element array sensing circuit 12 . In this embodiment, the digital-to-analog conversion circuit 11 can provide the first reference voltage V _REF and the second reference voltage V _{DC_OS} for the pixel array sensing circuit 12 and the column sensing circuit 12 . The primitive array sensing circuit 12 scans according to a certain timing control to detect the fingerprint signal of the user. The amplifying circuit 13 is connected to the picture element array sensing circuit 12, and is used for amplifying the detected fingerprint signal. The buffer 14 is connected to the amplifying circuit 13 for temporarily storing the amplified fingerprint signal. The analog-to-digital conversion circuit 15 is connected to the temporary register 14, and is used for digital-to-analog conversion and output of the amplified fingerprint signal. In this embodiment, since the digital-to-analog conversion circuit 11 , the buffer 14 and the analog-to-digital conversion circuit 15 are circuit structures existing in the field, and the present application does not describe the digital-to-analog conversion circuit 11 , the buffer 14 and the analog-to-digital conversion circuit 15 The circuit structure is improved. The digital-to-analog conversion circuit 11 , the buffer 14 and the analog-to-digital conversion circuit 15 are not described in detail in the present application, and only the improvement scheme of the pixel array induction circuit 12 and the amplifying circuit 13 of the present application is described in detail below.

In this embodiment, the picture element array sensing circuit 12 includes a picture element circuit 121 with m rows and n columns, where m and n are positive integers. In this embodiment, since the structure and working principle of each picture element circuit 121 in the picture element array sensing circuit 12 are the same, this application only introduces the circuit structure of a single picture element circuit 121 . Please refer to FIG. 2 , which is a circuit structure diagram of the primitive circuit 121 in an embodiment of the present invention. The primitive circuit 121 includes a first metal layer 1211 , a second metal layer 1212 , a third metal layer 1213 , and a substrate layer 1214 . In this embodiment, the first metal layer 1211 is used to detect the user's fingerprint. When the user's finger touches the first metal layer 1211, since the human body itself is a good conductor, it can be regarded as the ground terminal GND, and a first parasitic capacitance C is formed in the effective contact area between the user's finger and the first metal layer 1211 The _finger uses the first parasitic capacitance C _finger signal as the fingerprint signal for detecting the fingerprint of the finger. In this implementation manner, the distances from the valleys and ridges of the fingerprint to the first metal layer 1211 are different, and the size of the first parasitic capacitance C _finger is different accordingly. Therefore, the first parasitic capacitance C _finger is used as the sensor for detecting the fingerprint of the finger. fingerprint signal. In this embodiment, the fingerprint signal is the charge amount of the first parasitic capacitance C _finger .

After the finger touches the first metal layer 1211, C _finger is generated between the first metal layer 1211 and the ground terminal GND, and a second parasitic capacitance C _pex is formed between the first metal layer 1211 and the substrate layer 1214, so that the first metal layer 1211 The total parasitic capacitance to the substrate layer (GND), C _top =C ₁ +C ₂ , is expressed as wherein C ₁ is the first parasitic capacitance C _finger , and C ₂ is the second parasitic capacitance C _pex . In this way, the capacitance sensed from the first metal layer 1211l includes not only the first parasitic capacitance C _finger , but also the second parasitic capacitance C _pex . To improve the fingerprint detection accuracy, it is desirable that the first parasitic capacitance C _finger is infinitely close to the total parasitic capacitance C _top , and the closer the second parasitic capacitance C _{pex is} to zero, the better. In order to reduce the influence of the second parasitic capacitance C _pex on the detection accuracy of fingerprints, the present application provides a second metal layer 1212 and a third metal layer 1213 between the first metal layer 1211 and the substrate layer 1214 to connect the first metal layer 1211 to the substrate layer 1214. The substrate layer 1214 is isolated, and the projection of the second metal layer 1212 and the third metal layer 1213 on the substrate layer 1214 covers the projection of the first metal layer 1211 on the substrate layer 1214 to eliminate the formation between the first metal layer 1211 and the substrate layer 1214 The second parasitic capacitance C _pex improves the detection accuracy of the fingerprint signal. Specifically, the first metal layer 1211 and the second metal layer 1212 are spaced apart, and the first capacitor 21 is formed between the first metal layer 1211 and the second metal layer 1212 . The first metal layer 1211 and the third metal layer 1213 are spaced apart, and the second capacitor 22 is formed between the first metal layer 1211 and the third metal layer 1213 .

Please refer to FIG. 3 , which is a schematic diagram of a specific connection between the pixel array sensing circuit 12 and the amplifying circuit 13 in an embodiment of the present application. In this embodiment, the first metal layer 1211 forms a first parasitic capacitance C _finger with the human body regarded as GND. The first capacitor 21 is a parasitic capacitor formed between the first metal layer 1211 and the second metal layer 1212 . The primitive array sensing circuit 12 includes a first switch group, a second switch group, and a resistor 1218 . The first switch group includes a first sub-switch Φ11, a second sub-switch Φ12, and a third sub-switch Φ13. The second switch group includes a first sub-switch Φ21, a second sub-switch Φ22, and a third sub-switch Φ23.

The first metal layer 1211 is connected (electrically connected) to the second metal layer 1212 and forms the first capacitor 21 . The second metal layer 1212 is connected to the power supply voltage V _DD through the first sub-switch Φ11 of the first switch group, and the second metal layer 1212 is connected to the ground terminal GND through the first sub-switch Φ21 of the second switch group.

The first metal layer is connected (electrically connected) to the third metal layer 1213 and forms the second capacitor 22 . The third metal layer 1213 is connected to the power supply voltage V _DD through the second sub-switch Φ12 of the first switch group, and is connected to the first reference voltage V _REF through the second sub-switch Φ22 of the second switch group.

The third sub-switch Φ13 of the first switch group of the first metal layer 1211 is connected to the power supply voltage V _DD and is connected to the amplifier circuit connection 13 through the third sub-switch Φ23 of the second switch group. Specifically, the first metal layer 1211 is connected to one end of the resistor 1218 . The other end of the resistor 1218 is connected to the power supply voltage V _DD through the third sub-switch Φ13 of the first switch group, and is connected to the amplifier circuit 13 through the second sub-switch Φ23 of the second switch group.

In this embodiment, the amplifying circuit 13 is used to amplify the fingerprint signal detected by the fingerprint collecting circuit 1 . In this embodiment, the amplifier circuit 13 includes an operational amplifier 131 and a feedback loop 132 . The operational amplifier 131 includes a non-inverting input terminal 1311 , an inverting input terminal 1312 and an output terminal 1313 . The non-inverting input terminal 1311 is connected to the first reference voltage V _REF . The resistor 1218 is connected to the inverting input terminal 1312 through the second sub-switch Φ23 of the second switch group. The output terminal 1313 is connected to the inverting input terminal 1312 through the feedback loop 132 .

In this embodiment, the feedback loop 132 includes a feedback capacitor C _FB , a third switch group and a fourth switch group. The third switch group includes a first sub-switch rst_a1, a second sub-switch rst_a2, and a third sub-switch rst_a3. The fourth switch group includes a first sub-switch rst_b1 and a second sub-switch rst_b2. The upper plate of the feedback capacitor C _FB is connected to the second reference voltage V _{DC_OS} through the first sub-switch rst_a1 of the third switch group. The lower plate of the feedback capacitor C _FB is connected to the power supply voltage V _DD through the second sub-switch rst_a2 of the third switch group. The upper plate of the feedback capacitor C _FB is connected to the reverse input terminal 1312 through the first sub-switch rst_b1 of the fourth switch group. The lower plate of the feedback capacitor C _FB is connected 1313 to the output terminal through the second sub-switch rst_b2 of the fourth switch group. The reverse input terminal 1312 is also connected to the output terminal 1313 through the third sub-switch rst_a3 of the third switch group.

Please refer to FIG. 4 , which is a sequence diagram of fingerprint collection performed by the fingerprint collection circuit 1 in an embodiment of the present application. The fingerprint collection circuit 1 provides a first timing control signal reset_a, a second timing control signal reset_b, a third timing control signal Φ1 and a fourth timing control signal Φ2. The first timing control signal reset_a and the second timing control signal reset_b are clock signals with a phase difference of 180 ^° . The third timing control signal Φ1 and the fourth timing control signal Φ2 are non-overlapping clock signals with a phase difference of 180 ^° .

The first timing control signal reset_a is used to control the opening, closing and closing of the first sub-switch rst_a1 , the second sub-switch rst_a2 and the third sub-switch rst_a3 of the third switch group. The timings of opening, closing and closing of the first sub-switch rst_a1 , the second sub-switch rst_a2 , and the third sub-switch rst_a3 of the third switch group are exactly the same. The second timing control signal reset_b is used to control the opening and closing and closing of the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group. The timings of switching on and off of the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are exactly the same. The third timing control signal Φ1 is used to control the opening, closing and closing of the first sub-switch Φ11 , the second sub-switch Φ12 , and the third sub-switch Φ13 of the first switch group. The opening, closing and closing timings of the first sub-switch Φ11 , the second sub-switch Φ12 , and the third sub-switch Φ13 of the first switch group are the same. The fourth timing control signal Φ2 is used to control the opening, closing and closing of the first sub-switch Φ21 , the second sub-switch Φ22 , and the third sub-switch Φ23 of the second switch group. The first sub-switch Φ21 , the second sub-switch Φ22 , and the third sub-switch Φ23 of the second switch group are turned on and off at the same timing.

The working process of the fingerprint collection circuit 1 of the present application will be described in detail below with reference to FIG. 4 and FIG. 3 . The working process includes the following stages.

計算得到，其中，V_CFB1 表示回饋電容C_FB 兩端電壓。回饋電容C_FB 的電荷根據公式

計算得到，其中，C_FB 為回饋電容C_FB 的電容量，Q_CFB1 為回饋電容C_FB 的電荷量，V_{DC_OS} 為第二參考電壓。a) In the initial stage, the first timing control signal reset_a is at a high level, and the second timing control signal reset_b is at a low level. At this time, the first sub-switch rst_a1, the second sub-switch rst_a2, the third sub-switch rst_a1, and the third sub-switch rst_a2 of the third switch group The sub-switches rst_a3 are turned on at the same time, and the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are turned off at the same time. The output terminal 1313 of the operational amplifier is connected to the inverting input terminal 1312, and the operational amplifier 131 has a buffer structure, Vn=VREF. The upper plate of the feedback capacitor C _FB is connected to the second reference voltage V _{DC_OS} , the lower plate is connected to the power supply voltage V _DD , and the voltage of the feedback capacitor C _FB is based on the formula

Calculated, where, V _CFB1 represents the voltage across the feedback capacitor C _FB . The charge of the feedback capacitor C _FB is calculated according to the formula

It is obtained by calculation, wherein, C _FB is the capacitance of the feedback capacitor C _FB , Q _CFB1 is the charge amount of the feedback capacitor C _FB , and V _{DC_OS} is the second reference voltage.

計算得到，其中，V_OUT 為表示運算放大器131的輸出端1313的輸出電壓，V_REF 為第一參考電壓。回饋電容C_FB 的電荷根據公式

計算得到。b) In the scanning phase, the first timing control signal reset_a is at a low level, and the second timing control signal reset_b is at a high level. At this time, the first sub-switch rst_a1, the second sub-switch rst_a2, the third sub-switch rst_a2 and the third sub-switch of the third switch group The switches rst_a3 are turned off at the same time, and the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are turned on at the same time. The upper plate of the feedback capacitor C _FB is connected to the inverting input terminal 1312 of the operational amplifier 131 , and the lower plate is connected to the output terminal 1313 of the operational amplifier 131 . The voltage of the feedback capacitor C _FB according to the formula

The calculation is obtained, wherein, V _OUT is the output voltage representing the output terminal 1313 of the operational amplifier 131 , and V _REF is the first reference voltage. The charge of the feedback capacitor C _FB is calculated according to the formula

Calculated.

計算得到。根據電荷守恆定律，回饋電容C_FB 的電荷根據公式：

計算得到。Since the charge of the feedback capacitor C _FB does not change in the initial stage and the scanning stage, the output voltage of the output terminal 1313 of the operational amplifier 131 is based on the formula

Calculated. According to the law of conservation of charge, the charge of the feedback capacitor C _FB is based on the formula:

Calculated.

計算得到，其中，C_finger 為第一寄生電容C_finger 的電容，Q1為第一金屬層1211的電荷。(c) In the precharging stage, the third timing control signal Φ1 is at a high level, and the first sub-switch Φ11 , the second sub-switch Φ12 , and the third sub-switch Φ13 of the first switch group are turned on at the same time. The fourth timing control signal Φ2 is at a low level, the first sub-switch Φ21, the second sub-switch Φ22, and the third sub-switch Φ23 of the second switch group are turned off at the same time, the first capacitor 21, the second capacitor 22, the first parasitic The capacitor C _finger is connected to the power supply voltage V _DD , the first metal layer 1211 is disconnected from the operational amplifier 131 , and the charge of the first metal layer 1211 is determined by the formula

The calculation is obtained, wherein, C _finger is the capacitance of the first parasitic capacitance C _finger , and Q1 is the charge of the first metal layer 1211 .

，其中C₂ 為第一電容21的電容。總寄生電容的電荷量根據公式

計算得到。第三子開關Φ23導通之前，運算放大器131的反相輸入端1312的電荷量根據公式

計算得到。第三子開關Φ23導通後，總寄生電容的電荷量

。根據電荷守恆定律，

，則計算得到運算放大器131的輸出端1313的輸出電壓

。(d) In the charge transfer stage, the third timing control signal Φ1 changes from a high level to a low level, and the first sub-switch Φ11 , the second sub-switch Φ12 , and the third sub-switch Φ13 of the first switch group are turned off at the same time. The fourth timing control signal Φ2 changes from a low level to a high level, and the first sub-switch Φ21 , the second sub-switch Φ22 , and the third sub-switch Φ23 of the second switch group are turned on at the same time. When the third sub-switch Φ23 is turned on, the inverting input terminal 1312 of the operational amplifier 131 is connected to the first metal layer 1211 through the third sub-switch Φ23, and the output terminal 1313 and the inverting input terminal 1312 of the operational amplifier 131 are connected by the feedback capacitor C _FB is connected to form a feedback structure. The voltage of the inverting input terminal 1312 of the operational amplifier 131 is equal to the voltage of the non-inverting input terminal 1311 , that is, the voltage of the first metal layer 1211 is the first reference voltage V _REF . The second sub-switch Φ22 is switched from off to on, and the voltage of the third metal layer 1213 is the first reference voltage V _REF , because the voltages of the first metal layer 1211 and the third metal layer 1213 are both V _{REF , and} the first metal layer 1213 has a voltage of V REF . The second capacitor 22 formed by the layer 1211 and the third metal layer 1213 has no charge transfer. The first sub-switch Φ21 of the second switch group changes from off to on state, the second metal layer 1212 is connected to the ground terminal GND, and the total parasitic capacitance from the first metal layer 1211 to the ground terminal GND is

, where C ₂ is the capacitance of the first capacitor 21 . The amount of charge of the total parasitic capacitance according to the formula

Calculated. Before the third sub-switch Φ23 is turned on, the amount of charge at the inverting input terminal 1312 of the operational amplifier 131 is based on the formula

Calculated. After the third sub-switch Φ23 is turned on, the charge amount of the total parasitic capacitance

. According to the law of conservation of charge,

, then the output voltage of the output terminal 1313 of the operational amplifier 131 is calculated

.

本實施方式中，圖元陣列感應電路12在空掃時，需要保持

V_OUT 不隨積分次數N的變化而變化，輸出端1313的輸出電壓則為固定值

，與第一寄生電容C_finger 無關。After N times of integration, the amount of fingerprint signal is amplified, which effectively improves the sensitivity of signal acquisition. The output voltage of the output terminal 1313 of the operational amplifier 131 is:

In this embodiment, the image element array sensing circuit 12 needs to keep the

V _OUT does not change with the change of the number of integrations N, and the output voltage of the output terminal 1313 is a fixed value

, independent of the first parasitic capacitance C _finger .

若空掃時的V_OUT 低於V_OUT __VIR ，則說明V_REF 項（正數項）小於V_DD 項（負數項），需將V_REF 增大。若空掃時的V_OUT 高於Vout_vir，則說明V_REF 項（正數項）大於V_DD 項（負數項），需將V_REF 減小。因此，本實施方式中，可以藉由調整第一參考電壓V_REF 及第二參考電壓V_{DC_OS} 來調整輸出端1313的輸出電壓V_OUT ，防止指紋信號C_finger 過小，後端的模數轉換電路15無法處理的問題。第一參考電壓V_REF 可調節，適應不同的應用場景，提高了應用的靈活性。Assume that the output voltage of the output terminal 1313 of the operational amplifier 131 during the free sweep

If V _OUT during free sweep is lower than V _OUT _ _VIR , it means that the V _REF term (positive term) is less than the V _DD term (negative term), and V _REF needs to be increased. If V _OUT during free sweep is higher than Vout_vir, it means that the V _REF term (positive term) is greater than the V _DD term (negative term), and V _REF needs to be reduced. Therefore, in this embodiment, the output voltage V _OUT of the output terminal 1313 can be adjusted by adjusting the first reference voltage V _REF and the second reference voltage V _{DC_OS} to prevent the fingerprint signal C _finger from being too small and the analog-to-digital conversion circuit 15 at the back end cannot deal with the problem. The first reference voltage V _REF is adjustable to adapt to different application scenarios and improve application flexibility.

The entire picture element array sensing circuit 12 and the amplifying circuit 13 in this embodiment have simple structures, the required power supply voltage V _DD and ground GND do not need special treatment, and the V _DD and GND of other modules of the compatible chip do not need to be used. The special process can be realized by ordinary CMOS process.

The sensitivity of the fingerprint signal sensed in this embodiment is high, and it is not necessary to increase the sensitivity by increasing the area of the sensing circuit of the image element array. Compared with the general acquisition circuit, the area of the sensing circuit of the image element array in this embodiment can be reduced. Save wafer cost.

In other embodiments, the feedback capacitor C _FB of the amplifier 131 in the present application can be set in a variety of ways in accordance with the application of different external conditions.

In other embodiments, after the graphic element array sensing circuit 12 of the fingerprint acquisition circuit 1 performs one fingerprint sampling, the analog-to-digital conversion circuit 15 performs multiple analog-to-digital conversions; or after the graphic element array sensing circuit 12 performs multiple fingerprint sampling, The analog-to-digital conversion circuit 15 performs one analog-to-digital conversion; or after the primitive array sensing circuit 12 performs multiple fingerprint sampling, the analog-to-digital conversion circuit 15 performs multiple analog-to-digital conversions and other different working modes to effectively increase the signal volume of the fingerprint .

The embodiment of the present application also provides a fingerprint chip, and the fingerprint chip includes a fingerprint collection circuit 1 . The fingerprint collection circuit 1 is provided as in the above-mentioned embodiment. For the specific content of the fingerprint collection circuit, reference may be made to the content in the foregoing embodiments, and details are not repeated here.

The embodiments of the present application also provide an electronic device, the electronic device includes the fingerprint chip provided in the foregoing embodiments.

To sum up, the present invention complies with the requirements of an invention patent, and a patent application can be filed in accordance with the law. However, the above descriptions are only the preferred embodiments of the present invention, and for those who are familiar with the techniques of this case, equivalent modifications or changes made in accordance with the creative spirit of this case shall be included in the scope of the following patent application.

1: fingerprint acquisition circuit 11: digital-to-analog conversion circuit 12: primitive array sensing circuit 13: amplifier circuit 14: buffer 15: analog-to-digital conversion circuit V _REF : first reference voltage V _{DC_OS} : second reference voltage 121 : primitive Circuit 1211: first metal layer 1212: second metal layer 1213: third metal layer 1214: substrate layer GND: ground terminal C _finger : first parasitic capacitance C _pex : second parasitic capacitance 1218: resistance Φ11: first sub-switch Φ12: second sub-switch Φ13: third sub-switch Φ21: first sub-switch Φ22: second sub-switch Φ23: third sub-switch 22: second capacitor V _DD : power supply voltage 131: operational amplifier 132: feedback loop 1311 : non-inverting input terminal 1312 : reverse input terminal 1313 : output terminal V _REF : first reference voltage C _FB : feedback capacitor rst_a1 : first sub-switch rst_a2 : second sub-switch rst_a3 : third sub-switch rst_b1 : first sub-switch rst_b2: second sub-switch V _{DC_OS} : second reference voltage reset_a: first timing control signal reset_b: second timing control signal Φ1: third timing control signal Φ2: fourth timing control signal

FIG. 1 is a system frame of a fingerprint collection circuit in an embodiment of the present application.

FIG. 2 is a circuit structure diagram of a primitive circuit in an embodiment of the present invention.

FIG. 3 is a schematic diagram of a specific connection between the sensing circuit of the primitive array and the amplifying circuit in an embodiment of the present application.

FIG. 4 is a sequence diagram of fingerprint collection performed by a fingerprint collection circuit according to an embodiment of the present application.

1: Fingerprint acquisition circuit

11: Digital-to-analog conversion circuit

12: Element Array Induction Circuit

13: Amplifier circuit

14: Buffer

15: Analog-to-digital conversion circuit

Claims (11)

A fingerprint collection circuit, comprising a picture element array induction circuit and an amplifying circuit connected to each other, wherein the picture element array induction circuit includes a plurality of picture element circuits, and each picture element circuit includes a first metal layer, a second metal layer, a third a metal layer and a substrate layer, the first metal layer is used for detecting fingerprints of a finger, the second metal layer and the third metal layer are arranged between the first metal layer and the substrate layer, the first metal layer is The projection of the second metal layer and the third metal layer on the substrate layer covers the projection of the first metal layer on the substrate layer, thereby isolating the first metal layer from the substrate layer, and the first metal layer is touched by fingers Then, a fingerprint signal is generated, and the amplifying circuit is used for amplifying the fingerprint signal. The fingerprint collection circuit according to claim 1, wherein the image element array sensing circuit includes a first switch group and a second switch group, and the first switch group includes a first sub-switch, a second sub-switch, a third sub-switch, and a third sub-switch. a sub-switch, the second switch group includes a first sub-switch, a second sub-switch, and a third sub-switch, the first metal layer is connected to the second metal layer, and the second metal layer is connected by the The first sub-switch of the first switch group is connected to the power supply voltage and is connected to the ground terminal through the first sub-switch of the second switch group, the first metal layer is connected to the third metal layer, and the first metal layer is connected to the third metal layer. The three metal layers are connected to the power supply voltage through the second sub-switch of the first switch group and to the first reference voltage through the second sub-switch of the second switch group. The third sub-switch of the first switch group is connected to the power supply voltage and the third sub-switch of the second switch group is connected to the amplifier circuit. The fingerprint collection circuit according to claim 2, wherein the amplifying circuit includes an operational amplifier and a feedback loop, the operational amplifier includes a non-inverting input terminal, an inverting input terminal and an output terminal, and the non-inverting input terminal is connected to the The first reference voltage is connected, and the output voltage of the output terminal is adjusted by adjusting the first reference voltage. The fingerprint collection circuit according to claim 3, wherein the first metal layer is connected to the reverse input terminal through the third sub-switch of the second switch group, and the output terminal is connected to the feedback terminal through the feedback A loop is connected to the inverting input. The fingerprint collection circuit according to claim 4, wherein the feedback loop comprises a feedback capacitor, a third switch group and a fourth switch group, and the upper plate of the feedback capacitor is connected by the third switch group of the third switch group. A sub-switch is connected to the second reference voltage, the lower plate of the feedback capacitor is connected to the power supply voltage through the second sub-switch of the third switch group, and the upper plate of the feedback capacitor is connected to the power supply voltage through the second sub-switch of the third switch group The first sub-switch of the fourth switch group is connected to the reverse input terminal, the lower plate of the feedback capacitor is connected to the output terminal through the second sub-switch of the fourth switch group, and the reverse The input terminal is connected to the output terminal through the third sub-switch of the third switch group. The fingerprint collection circuit according to claim 5, wherein the fingerprint collection circuit further comprises a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit provides the first reference voltage and the second reference voltage. The fingerprint acquisition circuit according to claim 5, wherein the fingerprint acquisition circuit provides a first timing control signal, a second timing control signal, a third timing control signal and a fourth timing control signal, the first timing control signal The control signal and the second timing control signal are clock signals with a phase difference of 180 ^° , the third timing control signal Φ1 and the fourth timing control signal Φ2 are non-overlapping clock signals with a phase difference of 180 ^° , and the The first timing control signal is used to control the opening and closing and closing of the first sub-switch, the second sub-switch and the third sub-switch of the third switch group, and the second timing control signal is used to control the fourth sub-switch. The first sub-switch and the second sub-switch of the switch group are turned on and off, and the third timing control signal is used to control the first sub-switch, the second sub-switch and the third sub-switch of the first switch group. On and off, the fourth timing control signal is used to control the on-off and off of the first sub-switch, the second sub-switch, and the third sub-switch of the second switch group. The fingerprint collection circuit according to claim 7, wherein the working steps of the fingerprint collection circuit are: (a) Initial stage; the first timing control signal is at a high level, the second timing control signal is at a low level, and the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are at the same time is turned on, the first sub-switch and the second sub-switch of the fourth switch group are simultaneously disconnected; (b) Scanning stage: the first timing control signal is at a low level, the second timing control signal is at a high level, and the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group The sub-switches are turned off at the same time, and the first sub-switch and the second sub-switch of the fourth switch group are turned on at the same time; (c) Precharge stage: the third timing control signal is high, the first sub-switch, the second sub-switch, and the third sub-switch of the first switch group are turned on at the same time, and the fourth timing control signal is low level, the first sub-switch, the second sub-switch, and the third sub-switch of the second switch group are turned off simultaneously; (d) In the charge transfer stage, the third timing control signal changes from a high level to a low level, and the first sub-switch, the second sub-switch, and the third sub-switch of the first switch group are turned off at the same time, so the The fourth timing control signal changes from a low level to a high level, and the first sub-switch, the second sub-switch and the third sub-switch of the second switch group are turned on at the same time. The fingerprint acquisition circuit of claim 1, wherein the fingerprint acquisition circuit further comprises an analog-to-digital conversion circuit, the primitive array sensing circuit performs one fingerprint sampling, and the analog-to-digital conversion circuit performs multiple analog-to-digital conversions; Or the picture element array induction circuit performs multiple sampling, and the analog-to-digital conversion circuit performs one analog-to-digital conversion; or the picture element array induction circuit performs multiple sampling, and the analog-to-digital conversion circuit performs multiple analog-to-digital conversions . A fingerprint chip, wherein the fingerprint chip integrates the fingerprint collection circuit of any one of claim 1 to 9. An electronic device, wherein the electronic device adopts the fingerprint chip provided in claim 10.

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